iPXE
3c509.h
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00001 /*
00002  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions are
00006  * met: 1. Redistributions of source code must retain the above copyright
00007  * notice, this list of conditions and the following disclaimer. 2. The name
00008  * of the author may not be used to endorse or promote products derived from
00009  * this software withough specific prior written permission
00010  *
00011  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
00012  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
00014  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
00015  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
00016  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
00017  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00018  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
00019  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00020  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00021  *
00022  * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
00023  *
00024  October 2, 1994
00025 
00026  Modified by: Andres Vega Garcia
00027 
00028  INRIA - Sophia Antipolis, France
00029  e-mail: avega@sophia.inria.fr
00030  finger: avega@pax.inria.fr
00031 
00032  */
00033 
00034 FILE_LICENCE ( BSD3 );
00035 
00036 #include "nic.h"
00037 
00038 /*
00039  * Ethernet software status per interface.
00040  */
00041 /*
00042  * Some global constants
00043  */
00044 
00045 #define TX_INIT_RATE            16
00046 #define TX_INIT_MAX_RATE        64
00047 #define RX_INIT_LATENCY         64
00048 #define RX_INIT_EARLY_THRESH    64
00049 #define MIN_RX_EARLY_THRESHF    16      /* not less than ether_header */
00050 #define MIN_RX_EARLY_THRESHL    4
00051 
00052 #define EEPROMSIZE      0x40
00053 #define MAX_EEPROMBUSY  1000
00054 #define EP_ID_PORT_START 0x110  /* avoid 0x100 to avoid conflict with SB16 */
00055 #define EP_ID_PORT_INC 0x10
00056 #define EP_ID_PORT_END 0x200
00057 #define EP_TAG_MAX              0x7 /* must be 2^n - 1 */
00058 
00059 /*
00060  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
00061  * Offset 0xa)
00062  */
00063 #define EEPROM_CMD_RD   0x0080  /* Read:  Address required (5 bits) */
00064 #define EEPROM_CMD_WR   0x0040  /* Write: Address required (5 bits) */
00065 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
00066 #define EEPROM_CMD_EWEN 0x0030  /* Erase/Write Enable: No data required */
00067 
00068 #define EEPROM_BUSY             (1<<15)
00069 #define EEPROM_TST_MODE         (1<<14)
00070 
00071 /*
00072  * Some short functions, worth to let them be a macro
00073  */
00074 #define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
00075 #define GO_WINDOW(b,x)  outw(WINDOW_SELECT|(x), (b)+EP_COMMAND)
00076 
00077 /**************************************************************************
00078  *
00079  * These define the EEPROM data structure.  They are used in the probe
00080  * function to verify the existence of the adapter after having sent
00081  * the ID_Sequence.
00082  *
00083  * There are others but only the ones we use are defined here.
00084  *
00085  **************************************************************************/
00086 
00087 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
00088 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
00089 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
00090 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
00091 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
00092 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
00093 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
00094 
00095 /**************************************************************************
00096  *
00097  * These are the registers for the 3Com 3c509 and their bit patterns when
00098  * applicable.  They have been taken out the the "EtherLink III Parallel
00099  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
00100  * from 3com.
00101  *
00102  * Getting this document out of 3Com is almost impossible.  However,
00103  * archived copies are available at
00104  * http://www.osdever.net/cottontail/downloads/docs/3c5x9b.zip and
00105  * several other places on the web (search for 3c5x9b.pdf).
00106  *
00107  **************************************************************************/
00108 
00109 #define EP_COMMAND              0x0e    /* Write. BASE+0x0e is always a
00110                                          * command reg. */
00111 #define EP_STATUS               0x0e    /* Read. BASE+0x0e is always status
00112                                          * reg. */
00113 #define EP_WINDOW               0x0f    /* Read. BASE+0x0f is always window
00114                                          * reg. */
00115 /*
00116  * Window 0 registers. Setup.
00117  */
00118 /* Write */
00119 #define EP_W0_EEPROM_DATA       0x0c
00120 #define EP_W0_EEPROM_COMMAND    0x0a
00121 #define EP_W0_RESOURCE_CFG      0x08
00122 #define EP_W0_ADDRESS_CFG       0x06
00123 #define EP_W0_CONFIG_CTRL       0x04
00124 /* Read */
00125 #define EP_W0_PRODUCT_ID        0x02
00126 #define EP_W0_MFG_ID            0x00
00127 
00128 /*
00129  * Window 1 registers. Operating Set.
00130  */
00131 /* Write */
00132 #define EP_W1_TX_PIO_WR_2       0x02
00133 #define EP_W1_TX_PIO_WR_1       0x00
00134 /* Read */
00135 #define EP_W1_FREE_TX           0x0c
00136 #define EP_W1_TX_STATUS         0x0b    /* byte */
00137 #define EP_W1_TIMER             0x0a    /* byte */
00138 #define EP_W1_RX_STATUS         0x08
00139 #define EP_W1_RX_PIO_RD_2       0x02
00140 #define EP_W1_RX_PIO_RD_1       0x00
00141 
00142 /*
00143  * Window 2 registers. Station Address Setup/Read
00144  */
00145 /* Read/Write */
00146 #define EP_W2_ADDR_5            0x05
00147 #define EP_W2_ADDR_4            0x04
00148 #define EP_W2_ADDR_3            0x03
00149 #define EP_W2_ADDR_2            0x02
00150 #define EP_W2_ADDR_1            0x01
00151 #define EP_W2_ADDR_0            0x00
00152 
00153 /*
00154  * Window 3 registers.  FIFO Management.
00155  */
00156 /* Read */
00157 #define EP_W3_FREE_TX           0x0c
00158 #define EP_W3_FREE_RX           0x0a
00159 
00160 /*
00161  * Window 4 registers. Diagnostics.
00162  */
00163 /* Read/Write */
00164 #define EP_W4_MEDIA_TYPE        0x0a
00165 #define EP_W4_CTRLR_STATUS      0x08
00166 #define EP_W4_NET_DIAG          0x06
00167 #define EP_W4_FIFO_DIAG         0x04
00168 #define EP_W4_HOST_DIAG         0x02
00169 #define EP_W4_TX_DIAG           0x00
00170 
00171 /*
00172  * Window 5 Registers.  Results and Internal status.
00173  */
00174 /* Read */
00175 #define EP_W5_READ_0_MASK       0x0c
00176 #define EP_W5_INTR_MASK         0x0a
00177 #define EP_W5_RX_FILTER         0x08
00178 #define EP_W5_RX_EARLY_THRESH   0x06
00179 #define EP_W5_TX_AVAIL_THRESH   0x02
00180 #define EP_W5_TX_START_THRESH   0x00
00181 
00182 /*
00183  * Window 6 registers. Statistics.
00184  */
00185 /* Read/Write */
00186 #define TX_TOTAL_OK             0x0c
00187 #define RX_TOTAL_OK             0x0a
00188 #define TX_DEFERRALS            0x08
00189 #define RX_FRAMES_OK            0x07
00190 #define TX_FRAMES_OK            0x06
00191 #define RX_OVERRUNS             0x05
00192 #define TX_COLLISIONS           0x04
00193 #define TX_AFTER_1_COLLISION    0x03
00194 #define TX_AFTER_X_COLLISIONS   0x02
00195 #define TX_NO_SQE               0x01
00196 #define TX_CD_LOST              0x00
00197 
00198 /****************************************
00199  *
00200  * Register definitions.
00201  *
00202  ****************************************/
00203 
00204 /*
00205  * Command register. All windows.
00206  *
00207  * 16 bit register.
00208  *     15-11:  5-bit code for command to be executed.
00209  *     10-0:   11-bit arg if any. For commands with no args;
00210  *            this can be set to anything.
00211  */
00212 #define GLOBAL_RESET            (unsigned short) 0x0000 /* Wait at least 1ms
00213                                                          * after issuing */
00214 #define WINDOW_SELECT           (unsigned short) (0x1<<11)
00215 #define START_TRANSCEIVER       (unsigned short) (0x2<<11)      /* Read ADDR_CFG reg to
00216                                                          * determine whether
00217                                                          * this is needed. If
00218                                                          * so; wait 800 uSec
00219                                                          * before using trans-
00220                                                          * ceiver. */
00221 #define RX_DISABLE              (unsigned short) (0x3<<11)      /* state disabled on
00222                                                          * power-up */
00223 #define RX_ENABLE               (unsigned short) (0x4<<11)
00224 #define RX_RESET                (unsigned short) (0x5<<11)
00225 #define RX_DISCARD_TOP_PACK     (unsigned short) (0x8<<11)
00226 #define TX_ENABLE               (unsigned short) (0x9<<11)
00227 #define TX_DISABLE              (unsigned short) (0xa<<11)
00228 #define TX_RESET                (unsigned short) (0xb<<11)
00229 #define REQ_INTR                (unsigned short) (0xc<<11)
00230 #define SET_INTR_MASK           (unsigned short) (0xe<<11)
00231 #define SET_RD_0_MASK           (unsigned short) (0xf<<11)
00232 #define SET_RX_FILTER           (unsigned short) (0x10<<11)
00233 #define FIL_INDIVIDUAL  (unsigned short) (0x1)
00234 #define FIL_GROUP               (unsigned short) (0x2)
00235 #define FIL_BRDCST      (unsigned short) (0x4)
00236 #define FIL_ALL         (unsigned short) (0x8)
00237 #define SET_RX_EARLY_THRESH     (unsigned short) (0x11<<11)
00238 #define SET_TX_AVAIL_THRESH     (unsigned short) (0x12<<11)
00239 #define SET_TX_START_THRESH     (unsigned short) (0x13<<11)
00240 #define STATS_ENABLE            (unsigned short) (0x15<<11)
00241 #define STATS_DISABLE           (unsigned short) (0x16<<11)
00242 #define STOP_TRANSCEIVER        (unsigned short) (0x17<<11)
00243 /*
00244  * The following C_* acknowledge the various interrupts. Some of them don't
00245  * do anything.  See the manual.
00246  */
00247 #define ACK_INTR                (unsigned short) (0x6800)
00248 #define C_INTR_LATCH    (unsigned short) (ACK_INTR|0x1)
00249 #define C_CARD_FAILURE  (unsigned short) (ACK_INTR|0x2)
00250 #define C_TX_COMPLETE   (unsigned short) (ACK_INTR|0x4)
00251 #define C_TX_AVAIL      (unsigned short) (ACK_INTR|0x8)
00252 #define C_RX_COMPLETE   (unsigned short) (ACK_INTR|0x10)
00253 #define C_RX_EARLY      (unsigned short) (ACK_INTR|0x20)
00254 #define C_INT_RQD               (unsigned short) (ACK_INTR|0x40)
00255 #define C_UPD_STATS     (unsigned short) (ACK_INTR|0x80)
00256 
00257 /*
00258  * Status register. All windows.
00259  *
00260  *     15-13:  Window number(0-7).
00261  *     12:     Command_in_progress.
00262  *     11:     reserved.
00263  *     10:     reserved.
00264  *     9:      reserved.
00265  *     8:      reserved.
00266  *     7:      Update Statistics.
00267  *     6:      Interrupt Requested.
00268  *     5:      RX Early.
00269  *     4:      RX Complete.
00270  *     3:      TX Available.
00271  *     2:      TX Complete.
00272  *     1:      Adapter Failure.
00273  *     0:      Interrupt Latch.
00274  */
00275 #define S_INTR_LATCH            (unsigned short) (0x1)
00276 #define S_CARD_FAILURE          (unsigned short) (0x2)
00277 #define S_TX_COMPLETE           (unsigned short) (0x4)
00278 #define S_TX_AVAIL              (unsigned short) (0x8)
00279 #define S_RX_COMPLETE           (unsigned short) (0x10)
00280 #define S_RX_EARLY              (unsigned short) (0x20)
00281 #define S_INT_RQD               (unsigned short) (0x40)
00282 #define S_UPD_STATS             (unsigned short) (0x80)
00283 #define S_5_INTS                (S_CARD_FAILURE|S_TX_COMPLETE|\
00284                                  S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
00285 #define S_COMMAND_IN_PROGRESS   (unsigned short) (0x1000)
00286 
00287 /*
00288  * FIFO Registers.
00289  * RX Status. Window 1/Port 08
00290  *
00291  *     15:     Incomplete or FIFO empty.
00292  *     14:     1: Error in RX Packet   0: Incomplete or no error.
00293  *     13-11:  Type of error.
00294  *            1000 = Overrun.
00295  *            1011 = Run Packet Error.
00296  *            1100 = Alignment Error.
00297  *            1101 = CRC Error.
00298  *            1001 = Oversize Packet Error (>1514 bytes)
00299  *            0010 = Dribble Bits.
00300  *            (all other error codes, no errors.)
00301  *
00302  *     10-0:   RX Bytes (0-1514)
00303  */
00304 #define ERR_RX_INCOMPLETE       (unsigned short) (0x1<<15)
00305 #define ERR_RX                  (unsigned short) (0x1<<14)
00306 #define ERR_RX_OVERRUN          (unsigned short) (0x8<<11)
00307 #define ERR_RX_RUN_PKT          (unsigned short) (0xb<<11)
00308 #define ERR_RX_ALIGN            (unsigned short) (0xc<<11)
00309 #define ERR_RX_CRC              (unsigned short) (0xd<<11)
00310 #define ERR_RX_OVERSIZE         (unsigned short) (0x9<<11)
00311 #define ERR_RX_DRIBBLE          (unsigned short) (0x2<<11)
00312 
00313 /*
00314  * FIFO Registers.
00315  * TX Status. Window 1/Port 0B
00316  *
00317  *   Reports the transmit status of a completed transmission. Writing this
00318  *   register pops the transmit completion stack.
00319  *
00320  *   Window 1/Port 0x0b.
00321  *
00322  *     7:      Complete
00323  *     6:      Interrupt on successful transmission requested.
00324  *     5:      Jabber Error (TP Only, TX Reset required. )
00325  *     4:      Underrun (TX Reset required. )
00326  *     3:      Maximum Collisions.
00327  *     2:      TX Status Overflow.
00328  *     1-0:    Undefined.
00329  *
00330  */
00331 #define TXS_COMPLETE            0x80
00332 #define TXS_SUCCES_INTR_REQ             0x40
00333 #define TXS_JABBER              0x20
00334 #define TXS_UNDERRUN            0x10
00335 #define TXS_MAX_COLLISION       0x8
00336 #define TXS_STATUS_OVERFLOW     0x4
00337 
00338 /*
00339  * Configuration control register.
00340  * Window 0/Port 04
00341  */
00342 /* Read */
00343 #define IS_AUI                          (1<<13)
00344 #define IS_BNC                          (1<<12)
00345 #define IS_UTP                          (1<<9)
00346 /* Write */
00347 #define ENABLE_DRQ_IRQ                  0x0001
00348 #define W0_P4_CMD_RESET_ADAPTER         0x4
00349 #define W0_P4_CMD_ENABLE_ADAPTER        0x1
00350 /*
00351  * Media type and status.
00352  * Window 4/Port 0A
00353  */
00354 #define ENABLE_UTP                      0xc0
00355 #define DISABLE_UTP                     0x0
00356 
00357 /*
00358  * Resource control register
00359  */
00360 
00361 #define SET_IRQ(i)      ( ((i)<<12) | 0xF00) /* set IRQ i */
00362 
00363 /*
00364  * Receive status register
00365  */
00366 
00367 #define RX_BYTES_MASK                   (unsigned short) (0x07ff)
00368 #define RX_ERROR        0x4000
00369 #define RX_INCOMPLETE   0x8000
00370 
00371 /*
00372  * Misc defines for various things.
00373  */
00374 #define MFG_ID                          0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
00375 #define PROD_ID                         0x9150
00376 
00377 #define AUI                             0x1
00378 #define BNC                             0x2
00379 #define UTP                             0x4
00380 
00381 #define RX_BYTES_MASK                   (unsigned short) (0x07ff)
00382 
00383 /*
00384  * Function shared between 3c509.c and 3c529.c
00385  */
00386 extern int t5x9_probe ( struct nic *nic,
00387                         uint16_t prod_id_check, uint16_t prod_id_mask );
00388 extern void t5x9_disable ( struct nic *nic );
00389 
00390 /*
00391  * Local variables:
00392  *  c-basic-offset: 8
00393  * End:
00394  */