iPXE
3c595.h
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00001 /*
00002  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions are
00006  * met: 1. Redistributions of source code must retain the above copyright
00007  * notice, this list of conditions and the following disclaimer. 2. The name
00008  * of the author may not be used to endorse or promote products derived from
00009  * this software without specific prior written permission
00010  *
00011  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
00012  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
00014  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
00015  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
00016  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
00017  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00018  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
00019  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00020  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00021  *
00022  October 2, 1994
00023 
00024  Modified by: Andres Vega Garcia
00025 
00026  INRIA - Sophia Antipolis, France
00027  e-mail: avega@sophia.inria.fr
00028  finger: avega@pax.inria.fr
00029 
00030  */
00031 
00032 FILE_LICENCE ( BSD3 );
00033 
00034 /*
00035  * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
00036  * 3c590 family.
00037  */
00038 
00039 /*
00040  * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp>
00041  * for etherboot
00042  * Mar. 14, 2000
00043 */
00044 
00045 /*
00046  * Ethernet software status per interface.
00047  */
00048 
00049 /*
00050  * Some global constants
00051  */
00052 
00053 #define TX_INIT_RATE         16
00054 #define TX_INIT_MAX_RATE     64
00055 #define RX_INIT_LATENCY      64
00056 #define RX_INIT_EARLY_THRESH 64
00057 #define MIN_RX_EARLY_THRESHF   16 /* not less than ether_header */
00058 #define MIN_RX_EARLY_THRESHL   4
00059 
00060 #define EEPROMSIZE      0x40
00061 #define MAX_EEPROMBUSY  1000
00062 #define VX_LAST_TAG     0xd7
00063 #define VX_MAX_BOARDS   16
00064 #define VX_ID_PORT      0x100
00065 
00066 /*
00067  * some macros to acces long named fields
00068  */
00069 #define BASE    (eth_nic_base)
00070 
00071 /*
00072  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
00073  * Offset 0xa)
00074  */
00075 #define EEPROM_CMD_RD    0x0080 /* Read:  Address required (5 bits) */
00076 #define EEPROM_CMD_WR    0x0040 /* Write: Address required (5 bits) */
00077 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
00078 #define EEPROM_CMD_EWEN  0x0030 /* Erase/Write Enable: No data required */
00079 
00080 #define EEPROM_BUSY             (1<<15)
00081 
00082 /*
00083  * Some short functions, worth to let them be a macro
00084  */
00085 
00086 /**************************************************************************
00087  *                                                                        *
00088  * These define the EEPROM data structure.  They are used in the probe
00089  * function to verify the existence of the adapter after having sent
00090  * the ID_Sequence.
00091  *
00092  * There are others but only the ones we use are defined here.
00093  *
00094  **************************************************************************/
00095 
00096 #define EEPROM_NODE_ADDR_0      0x0     /* Word */
00097 #define EEPROM_NODE_ADDR_1      0x1     /* Word */
00098 #define EEPROM_NODE_ADDR_2      0x2     /* Word */
00099 #define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
00100 #define EEPROM_MFG_ID           0x7     /* 0x6d50 */
00101 #define EEPROM_ADDR_CFG         0x8     /* Base addr */
00102 #define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
00103 #define EEPROM_OEM_ADDR_0       0xa     /* Word */
00104 #define EEPROM_OEM_ADDR_1       0xb     /* Word */
00105 #define EEPROM_OEM_ADDR_2       0xc     /* Word */
00106 #define EEPROM_SOFT_INFO_2      0xf     /* Software information 2 */
00107 
00108 #define NO_RX_OVN_ANOMALY       (1<<5)
00109 
00110 /**************************************************************************
00111  *                                                                                *
00112  * These are the registers for the 3Com 3c509 and their bit patterns when *
00113  * applicable.  They have been taken out the the "EtherLink III Parallel  *
00114  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
00115  * from 3com.                                                             *
00116  *                                                                                *
00117  **************************************************************************/
00118 
00119 #define VX_COMMAND              0x0e    /* Write. BASE+0x0e is always a
00120                                          * command reg. */
00121 #define VX_STATUS               0x0e    /* Read. BASE+0x0e is always status
00122                                          * reg. */
00123 #define VX_WINDOW               0x0f    /* Read. BASE+0x0f is always window
00124                                          * reg. */
00125 /*
00126  * Window 0 registers. Setup.
00127  */
00128 /* Write */
00129 #define VX_W0_EEPROM_DATA       0x0c
00130 #define VX_W0_EEPROM_COMMAND    0x0a
00131 #define VX_W0_RESOURCE_CFG      0x08
00132 #define VX_W0_ADDRESS_CFG       0x06 
00133 #define VX_W0_CONFIG_CTRL       0x04
00134         /* Read */
00135 #define VX_W0_PRODUCT_ID        0x02
00136 #define VX_W0_MFG_ID            0x00
00137 
00138 
00139 /*
00140  * Window 1 registers. Operating Set.
00141  */
00142 /* Write */
00143 #define VX_W1_TX_PIO_WR_2       0x02
00144 #define VX_W1_TX_PIO_WR_1       0x00
00145 /* Read */
00146 #define VX_W1_FREE_TX           0x0c
00147 #define VX_W1_TX_STATUS         0x0b    /* byte */
00148 #define VX_W1_TIMER             0x0a    /* byte */
00149 #define VX_W1_RX_STATUS         0x08
00150 #define VX_W1_RX_PIO_RD_2       0x02
00151 #define VX_W1_RX_PIO_RD_1       0x00
00152 
00153 /*
00154  * Window 2 registers. Station Address Setup/Read
00155  */
00156 /* Read/Write */
00157 #define VX_W2_ADDR_5            0x05
00158 #define VX_W2_ADDR_4            0x04
00159 #define VX_W2_ADDR_3            0x03
00160 #define VX_W2_ADDR_2            0x02
00161 #define VX_W2_ADDR_1            0x01
00162 #define VX_W2_ADDR_0            0x00
00163 
00164 /*
00165  * Window 3 registers. FIFO Management.
00166  */
00167 /* Read */
00168 #define VX_W3_INTERNAL_CFG      0x00
00169 #define VX_W3_RESET_OPT         0x08
00170 #define VX_W3_FREE_TX           0x0c
00171 #define VX_W3_FREE_RX           0x0a
00172 
00173 /*
00174  * Window 4 registers. Diagnostics.
00175  */
00176 /* Read/Write */
00177 #define VX_W4_MEDIA_TYPE        0x0a
00178 #define VX_W4_CTRLR_STATUS      0x08
00179 #define VX_W4_NET_DIAG          0x06
00180 #define VX_W4_FIFO_DIAG         0x04
00181 #define VX_W4_HOST_DIAG         0x02
00182 #define VX_W4_TX_DIAG           0x00
00183 
00184 /*
00185  * Window 5 Registers.  Results and Internal status.
00186  */
00187 /* Read */
00188 #define VX_W5_READ_0_MASK       0x0c
00189 #define VX_W5_INTR_MASK         0x0a
00190 #define VX_W5_RX_FILTER         0x08
00191 #define VX_W5_RX_EARLY_THRESH   0x06
00192 #define VX_W5_TX_AVAIL_THRESH   0x02
00193 #define VX_W5_TX_START_THRESH   0x00
00194 
00195 /*
00196  * Window 6 registers. Statistics.
00197  */
00198 /* Read/Write */
00199 #define TX_TOTAL_OK             0x0c
00200 #define RX_TOTAL_OK             0x0a
00201 #define TX_DEFERRALS            0x08
00202 #define RX_FRAMES_OK            0x07
00203 #define TX_FRAMES_OK            0x06
00204 #define RX_OVERRUNS             0x05
00205 #define TX_COLLISIONS           0x04
00206 #define TX_AFTER_1_COLLISION    0x03
00207 #define TX_AFTER_X_COLLISIONS   0x02
00208 #define TX_NO_SQE               0x01
00209 #define TX_CD_LOST              0x00
00210 
00211 /****************************************
00212  *
00213  * Register definitions.
00214  *
00215  ****************************************/
00216 
00217 /*
00218  * Command register. All windows.
00219  *
00220  * 16 bit register.
00221  *     15-11:  5-bit code for command to be executed.
00222  *     10-0:   11-bit arg if any. For commands with no args;
00223  *            this can be set to anything.
00224  */
00225 #define GLOBAL_RESET            (unsigned short) 0x0000 /* Wait at least 1ms
00226                                                          * after issuing */
00227 #define WINDOW_SELECT           (unsigned short) (0x1<<11)
00228 #define START_TRANSCEIVER       (unsigned short) (0x2<<11)      /* Read ADDR_CFG reg to
00229                                                          * determine whether
00230                                                          * this is needed. If
00231                                                          * so; wait 800 uSec
00232                                                          * before using trans-
00233                                                          * ceiver. */
00234 #define RX_DISABLE              (unsigned short) (0x3<<11)      /* state disabled on
00235                                                          * power-up */
00236 #define RX_ENABLE               (unsigned short) (0x4<<11)
00237 #define RX_RESET                (unsigned short) (0x5<<11)
00238 #define RX_DISCARD_TOP_PACK     (unsigned short) (0x8<<11)
00239 #define TX_ENABLE               (unsigned short) (0x9<<11)
00240 #define TX_DISABLE              (unsigned short) (0xa<<11)
00241 #define TX_RESET                (unsigned short) (0xb<<11)
00242 #define REQ_INTR                (unsigned short) (0xc<<11)
00243 /*
00244  * The following C_* acknowledge the various interrupts. Some of them don't
00245  * do anything.  See the manual.
00246  */
00247 #define ACK_INTR                (unsigned short) (0x6800)
00248 #       define C_INTR_LATCH     (unsigned short) (ACK_INTR|0x1)
00249 #       define C_CARD_FAILURE   (unsigned short) (ACK_INTR|0x2)
00250 #       define C_TX_COMPLETE    (unsigned short) (ACK_INTR|0x4)
00251 #       define C_TX_AVAIL       (unsigned short) (ACK_INTR|0x8)
00252 #       define C_RX_COMPLETE    (unsigned short) (ACK_INTR|0x10)
00253 #       define C_RX_EARLY       (unsigned short) (ACK_INTR|0x20)
00254 #       define C_INT_RQD                (unsigned short) (ACK_INTR|0x40)
00255 #       define C_UPD_STATS      (unsigned short) (ACK_INTR|0x80)
00256 #define SET_INTR_MASK           (unsigned short) (0xe<<11)
00257 #define SET_RD_0_MASK           (unsigned short) (0xf<<11)
00258 #define SET_RX_FILTER           (unsigned short) (0x10<<11)
00259 #       define FIL_INDIVIDUAL   (unsigned short) (0x1)
00260 #       define FIL_MULTICAST     (unsigned short) (0x02)
00261 #       define FIL_BRDCST        (unsigned short) (0x04)
00262 #       define FIL_PROMISC       (unsigned short) (0x08)
00263 #define SET_RX_EARLY_THRESH     (unsigned short) (0x11<<11)
00264 #define SET_TX_AVAIL_THRESH     (unsigned short) (0x12<<11)
00265 #define SET_TX_START_THRESH     (unsigned short) (0x13<<11)
00266 #define STATS_ENABLE            (unsigned short) (0x15<<11)
00267 #define STATS_DISABLE           (unsigned short) (0x16<<11)
00268 #define STOP_TRANSCEIVER        (unsigned short) (0x17<<11)
00269 
00270 /*
00271  * Status register. All windows.
00272  *
00273  *     15-13:  Window number(0-7).
00274  *     12:     Command_in_progress.
00275  *     11:     reserved.
00276  *     10:     reserved.
00277  *     9:      reserved.
00278  *     8:      reserved.
00279  *     7:      Update Statistics.
00280  *     6:      Interrupt Requested.
00281  *     5:      RX Early.
00282  *     4:      RX Complete.
00283  *     3:      TX Available.
00284  *     2:      TX Complete.
00285  *     1:      Adapter Failure.
00286  *     0:      Interrupt Latch.
00287  */
00288 #define S_INTR_LATCH            (unsigned short) (0x1)
00289 #define S_CARD_FAILURE          (unsigned short) (0x2)
00290 #define S_TX_COMPLETE           (unsigned short) (0x4)
00291 #define S_TX_AVAIL              (unsigned short) (0x8)
00292 #define S_RX_COMPLETE           (unsigned short) (0x10)
00293 #define S_RX_EARLY              (unsigned short) (0x20)
00294 #define S_INT_RQD               (unsigned short) (0x40)
00295 #define S_UPD_STATS             (unsigned short) (0x80)
00296 #define S_COMMAND_IN_PROGRESS   (unsigned short) (0x1000)
00297 
00298 #define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
00299 
00300 /* Address Config. Register.    
00301  * Window 0/Port 06
00302  */
00303 
00304 #define ACF_CONNECTOR_BITS      14  
00305 #define ACF_CONNECTOR_UTP       0
00306 #define ACF_CONNECTOR_AUI       1
00307 #define ACF_CONNECTOR_BNC       3
00308    
00309 #define INTERNAL_CONNECTOR_BITS 20
00310 #define INTERNAL_CONNECTOR_MASK 0x01700000
00311 
00312 /*
00313  * FIFO Registers. RX Status.
00314  *
00315  *     15:     Incomplete or FIFO empty.
00316  *     14:     1: Error in RX Packet   0: Incomplete or no error.
00317  *     13-11:  Type of error.
00318  *            1000 = Overrun.
00319  *            1011 = Run Packet Error.
00320  *            1100 = Alignment Error.
00321  *            1101 = CRC Error.
00322  *            1001 = Oversize Packet Error (>1514 bytes)
00323  *            0010 = Dribble Bits.
00324  *            (all other error codes, no errors.)
00325  *
00326  *     10-0:   RX Bytes (0-1514)
00327  */
00328 #define ERR_INCOMPLETE  (unsigned short) (0x8000)
00329 #define ERR_RX          (unsigned short) (0x4000)
00330 #define ERR_MASK        (unsigned short) (0x7800)
00331 #define ERR_OVERRUN     (unsigned short) (0x4000)
00332 #define ERR_RUNT        (unsigned short) (0x5800)
00333 #define ERR_ALIGNMENT   (unsigned short) (0x6000)
00334 #define ERR_CRC         (unsigned short) (0x6800)
00335 #define ERR_OVERSIZE    (unsigned short) (0x4800)
00336 #define ERR_DRIBBLE     (unsigned short) (0x1000)
00337 
00338 /*
00339  * TX Status. 
00340  *
00341  *   Reports the transmit status of a completed transmission. Writing this
00342  *   register pops the transmit completion stack.
00343  *
00344  *   Window 1/Port 0x0b.
00345  *
00346  *     7:      Complete
00347  *     6:      Interrupt on successful transmission requested.
00348  *     5:      Jabber Error (TP Only, TX Reset required. )
00349  *     4:      Underrun (TX Reset required. )
00350  *     3:      Maximum Collisions.
00351  *     2:      TX Status Overflow.
00352  *     1-0:    Undefined.
00353  *
00354  */
00355 #define TXS_COMPLETE            0x80
00356 #define TXS_INTR_REQ            0x40
00357 #define TXS_JABBER              0x20
00358 #define TXS_UNDERRUN            0x10
00359 #define TXS_MAX_COLLISION       0x8
00360 #define TXS_STATUS_OVERFLOW     0x4
00361 
00362 #define RS_AUI                  (1<<5)
00363 #define RS_BNC                  (1<<4)
00364 #define RS_UTP                  (1<<3)
00365 #define RS_T4                   (1<<0)
00366 #define RS_TX                   (1<<1)
00367 #define RS_FX                   (1<<2)
00368 #define RS_MII                  (1<<6)
00369 
00370 
00371 /*
00372  * FIFO Status (Window 4)
00373  *
00374  *   Supports FIFO diagnostics
00375  *
00376  *   Window 4/Port 0x04.1
00377  *
00378  *     15:      1=RX receiving (RO). Set when a packet is being received
00379  *              into the RX FIFO.
00380  *     14:      Reserved
00381  *     13:      1=RX underrun (RO). Generates Adapter Failure interrupt.
00382  *              Requires RX Reset or Global Reset command to recover.
00383  *              It is generated when you read past the end of a packet -
00384  *              reading past what has been received so far will give bad
00385  *              data.
00386  *     12:      1=RX status overrun (RO). Set when there are already 8
00387  *              packets in the RX FIFO. While this bit is set, no additional
00388  *              packets are received. Requires no action on the part of
00389  *              the host. The condition is cleared once a packet has been
00390  *              read out of the RX FIFO.
00391  *     11:      1=RX overrun (RO). Set when the RX FIFO is full (there
00392  *              may not be an overrun packet yet). While this bit is set,
00393  *              no additional packets will be received (some additional
00394  *              bytes can still be pending between the wire and the RX
00395  *              FIFO). Requires no action on the part of the host. The
00396  *              condition is cleared once a few bytes have been read out
00397  *              from the RX FIFO.
00398  *     10:      1=TX overrun (RO). Generates adapter failure interrupt.
00399  *              Requires TX Reset or Global Reset command to recover.
00400  *              Disables Transmitter.
00401  *     9-8:     Unassigned.
00402  *     7-0:     Built in self test bits for the RX and TX FIFO's.
00403  */
00404 #define FIFOS_RX_RECEIVING      (unsigned short) 0x8000
00405 #define FIFOS_RX_UNDERRUN       (unsigned short) 0x2000
00406 #define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000
00407 #define FIFOS_RX_OVERRUN        (unsigned short) 0x0800
00408 #define FIFOS_TX_OVERRUN        (unsigned short) 0x0400
00409 
00410 /*
00411  * Misc defines for various things.
00412  */
00413 #define TAG_ADAPTER                     0xd0
00414 #define ACTIVATE_ADAPTER_TO_CONFIG      0xff
00415 #define ENABLE_DRQ_IRQ                  0x0001
00416 #define MFG_ID                          0x506d  /* `TCM' */
00417 #define PROD_ID                         0x5090
00418 #define GO_WINDOW(x)            outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
00419 #define JABBER_GUARD_ENABLE     0x40
00420 #define LINKBEAT_ENABLE         0x80
00421 #define ENABLE_UTP              (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
00422 #define DISABLE_UTP             0x0
00423 #define RX_BYTES_MASK           (unsigned short) (0x07ff)
00424 #define RX_ERROR        0x4000
00425 #define RX_INCOMPLETE   0x8000
00426 #define TX_INDICATE             1<<15
00427 #define is_eeprom_busy(b)       (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY)
00428 
00429 #define VX_IOSIZE       0x20
00430 
00431 #define VX_CONNECTORS 8
00432 
00433 /*
00434  * Local variables:
00435  *  c-basic-offset: 8
00436  * End:
00437  */