iPXE
MT25218_PRM.h
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00001 /*
00002   This software is available to you under a choice of one of two
00003   licenses.  You may choose to be licensed under the terms of the GNU
00004   General Public License (GPL) Version 2, available at
00005   <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
00006   license, available in the LICENSE.TXT file accompanying this
00007   software.  These details are also available at
00008   <http://openib.org/license.html>.
00009 
00010   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
00011   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00012   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
00013   NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
00014   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
00015   ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
00016   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
00017   SOFTWARE.
00018 
00019   Copyright (c) 2004 Mellanox Technologies Ltd.  All rights reserved.
00020 */
00021 
00022 FILE_LICENCE ( GPL2_ONLY );
00023 
00024 /***
00025  *** This file was generated at "Tue Nov 22 15:21:23 2005"
00026  *** by:
00027  ***    % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp
00028  ***/
00029 
00030 #ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
00031 #define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
00032 
00033 /* UD Address Vector */
00034 
00035 struct arbelprm_ud_address_vector_st {  /* Little Endian */
00036     pseudo_bit_t        pd[0x00018];           /* Protection Domain */
00037     pseudo_bit_t        port_number[0x00002];  /* Port number
00038                                                  1 - Port 1
00039                                                  2 - Port 2
00040                                                  other - reserved */
00041     pseudo_bit_t        reserved0[0x00006];
00042 /* -------------- */
00043     pseudo_bit_t        rlid[0x00010];         /* Remote (Destination) LID */
00044     pseudo_bit_t        my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
00045     pseudo_bit_t        g[0x00001];            /* Global address enable - if set, GRH will be formed for packet header */
00046     pseudo_bit_t        reserved1[0x00008];
00047 /* -------------- */
00048     pseudo_bit_t        hop_limit[0x00008];    /* IPv6 hop limit */
00049     pseudo_bit_t        max_stat_rate[0x00003];/* Maximum static rate control. 
00050                                                  0 - 4X injection rate
00051                                                  1 - 1X injection rate
00052                                                  other - reserved
00053                                                   */
00054     pseudo_bit_t        reserved2[0x00001];
00055     pseudo_bit_t        msg[0x00002];          /* Max Message size, size is 256*2^MSG bytes */
00056     pseudo_bit_t        reserved3[0x00002];
00057     pseudo_bit_t        mgid_index[0x00006];   /* Index to port GID table
00058                                                  mgid_index = (port_number-1) * 2^log_max_gid + gid_index
00059                                                  Where:
00060                                                  1. log_max_gid is taken from QUERY_DEV_LIM command
00061                                                  2. gid_index is the index to the GID table */
00062     pseudo_bit_t        reserved4[0x0000a];
00063 /* -------------- */
00064     pseudo_bit_t        flow_label[0x00014];   /* IPv6 flow label */
00065     pseudo_bit_t        tclass[0x00008];       /* IPv6 TClass */
00066     pseudo_bit_t        sl[0x00004];           /* InfiniBand Service Level (SL) */
00067 /* -------------- */
00068     pseudo_bit_t        rgid_127_96[0x00020];  /* Remote GID[127:96] */
00069 /* -------------- */
00070     pseudo_bit_t        rgid_95_64[0x00020];   /* Remote GID[95:64] */
00071 /* -------------- */
00072     pseudo_bit_t        rgid_63_32[0x00020];   /* Remote GID[63:32] */
00073 /* -------------- */
00074     pseudo_bit_t        rgid_31_0[0x00020];    /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
00075 /* -------------- */
00076 }; 
00077 
00078 /* Send doorbell */
00079 
00080 struct arbelprm_send_doorbell_st {      /* Little Endian */
00081     pseudo_bit_t        nopcode[0x00005];      /* Opcode of descriptor to be executed */
00082     pseudo_bit_t        f[0x00001];            /* Fence bit. If set, descriptor is fenced */
00083     pseudo_bit_t        reserved0[0x00002];
00084     pseudo_bit_t        wqe_counter[0x00010];  /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
00085     pseudo_bit_t        wqe_cnt[0x00008];      /* Number of WQEs posted with this doorbell. Must be grater then zero. */
00086 /* -------------- */
00087     pseudo_bit_t        nds[0x00006];          /* Next descriptor size (in 16-byte chunks) */
00088     pseudo_bit_t        reserved1[0x00002];
00089     pseudo_bit_t        qpn[0x00018];          /* QP number this doorbell is rung on */
00090 /* -------------- */
00091 }; 
00092 
00093 /* ACCESS_LAM_inject_errors_input_modifier */
00094 
00095 struct arbelprm_access_lam_inject_errors_input_modifier_st {    /* Little Endian */
00096     pseudo_bit_t        index3[0x00007];
00097     pseudo_bit_t        q3[0x00001];
00098     pseudo_bit_t        index2[0x00007];
00099     pseudo_bit_t        q2[0x00001];
00100     pseudo_bit_t        index1[0x00007];
00101     pseudo_bit_t        q1[0x00001];
00102     pseudo_bit_t        index0[0x00007];
00103     pseudo_bit_t        q0[0x00001];
00104 /* -------------- */
00105 }; 
00106 
00107 /* ACCESS_LAM_inject_errors_input_parameter */
00108 
00109 struct arbelprm_access_lam_inject_errors_input_parameter_st {   /* Little Endian */
00110     pseudo_bit_t        ba[0x00002];           /* Bank Address */
00111     pseudo_bit_t        da[0x00002];           /* Dimm Address */
00112     pseudo_bit_t        reserved0[0x0001c];
00113 /* -------------- */
00114     pseudo_bit_t        ra[0x00010];           /* Row Address */
00115     pseudo_bit_t        ca[0x00010];           /* Column Address */
00116 /* -------------- */
00117 }; 
00118 
00119 /*  */
00120 
00121 struct arbelprm_recv_wqe_segment_next_st {      /* Little Endian */
00122     pseudo_bit_t        reserved0[0x00006];
00123     pseudo_bit_t        nda_31_6[0x0001a];     /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
00124 /* -------------- */
00125     pseudo_bit_t        nds[0x00006];          /* Next WQE size in OctoWords (16 bytes). 
00126                                                  Zero value in NDS field signals end of WQEs? chain.
00127                                                   */
00128     pseudo_bit_t        reserved1[0x0001a];
00129 /* -------------- */
00130 }; 
00131 
00132 /* Send wqe segment data inline */
00133 
00134 struct arbelprm_wqe_segment_data_inline_st {    /* Little Endian */
00135     pseudo_bit_t        byte_count[0x0000a];   /* Not including padding for 16Byte chunks */
00136     pseudo_bit_t        reserved0[0x00015];
00137     pseudo_bit_t        always1[0x00001];
00138 /* -------------- */
00139     pseudo_bit_t        data[0x00018];         /* Data may be more this segment size - in 16Byte chunks */
00140     pseudo_bit_t        reserved1[0x00008];
00141 /* -------------- */
00142     pseudo_bit_t        reserved2[0x00040];
00143 /* -------------- */
00144 }; 
00145 
00146 /* Send wqe segment data ptr */
00147 
00148 struct arbelprm_wqe_segment_data_ptr_st {       /* Little Endian */
00149     pseudo_bit_t        byte_count[0x0001f];
00150     pseudo_bit_t        always0[0x00001];
00151 /* -------------- */
00152     pseudo_bit_t        l_key[0x00020];
00153 /* -------------- */
00154     pseudo_bit_t        local_address_h[0x00020];
00155 /* -------------- */
00156     pseudo_bit_t        local_address_l[0x00020];
00157 /* -------------- */
00158 }; 
00159 
00160 /* Send wqe segment rd */
00161 
00162 struct arbelprm_local_invalidate_segment_st {   /* Little Endian */
00163     pseudo_bit_t        reserved0[0x00040];
00164 /* -------------- */
00165     pseudo_bit_t        mem_key[0x00018];
00166     pseudo_bit_t        reserved1[0x00008];
00167 /* -------------- */
00168     pseudo_bit_t        reserved2[0x000a0];
00169 /* -------------- */
00170 }; 
00171 
00172 /* Fast_Registration_Segment */
00173 
00174 struct arbelprm_fast_registration_segment_st {  /* Little Endian */
00175     pseudo_bit_t        reserved0[0x0001b];
00176     pseudo_bit_t        lr[0x00001];           /* If set - Local Read access will be enabled */
00177     pseudo_bit_t        lw[0x00001];           /* If set - Local Write access will be enabled */
00178     pseudo_bit_t        rr[0x00001];           /* If set - Remote Read access will be enabled */
00179     pseudo_bit_t        rw[0x00001];           /* If set - Remote Write access will be enabled */
00180     pseudo_bit_t        a[0x00001];            /* If set - Remote Atomic access will be enabled */
00181 /* -------------- */
00182     pseudo_bit_t        pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */
00183 /* -------------- */
00184     pseudo_bit_t        mem_key[0x00020];      /* Memory Key on which the fast registration is executed on. */
00185 /* -------------- */
00186     pseudo_bit_t        page_size[0x00005];    /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
00187                                                  page_size should be less than 20. */
00188     pseudo_bit_t        reserved1[0x00002];
00189     pseudo_bit_t        zb[0x00001];           /* Zero Based Region */
00190     pseudo_bit_t        pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */
00191 /* -------------- */
00192     pseudo_bit_t        start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
00193 /* -------------- */
00194     pseudo_bit_t        start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
00195 /* -------------- */
00196     pseudo_bit_t        reg_len_h[0x00020];    /* Region Length[63:32] */
00197 /* -------------- */
00198     pseudo_bit_t        reg_len_l[0x00020];    /* Region Length[31:0] */
00199 /* -------------- */
00200 }; 
00201 
00202 /* Send wqe segment atomic */
00203 
00204 struct arbelprm_wqe_segment_atomic_st { /* Little Endian */
00205     pseudo_bit_t        swap_add_h[0x00020];
00206 /* -------------- */
00207     pseudo_bit_t        swap_add_l[0x00020];
00208 /* -------------- */
00209     pseudo_bit_t        compare_h[0x00020];
00210 /* -------------- */
00211     pseudo_bit_t        compare_l[0x00020];
00212 /* -------------- */
00213 }; 
00214 
00215 /* Send wqe segment remote address */
00216 
00217 struct arbelprm_wqe_segment_remote_address_st { /* Little Endian */
00218     pseudo_bit_t        remote_virt_addr_h[0x00020];
00219 /* -------------- */
00220     pseudo_bit_t        remote_virt_addr_l[0x00020];
00221 /* -------------- */
00222     pseudo_bit_t        rkey[0x00020];
00223 /* -------------- */
00224     pseudo_bit_t        reserved0[0x00020];
00225 /* -------------- */
00226 }; 
00227 
00228 /* end wqe segment bind */
00229 
00230 struct arbelprm_wqe_segment_bind_st {   /* Little Endian */
00231     pseudo_bit_t        reserved0[0x0001d];
00232     pseudo_bit_t        rr[0x00001];           /* If set, Remote Read Enable for bound window. */
00233     pseudo_bit_t        rw[0x00001];           /* If set, Remote Write Enable for bound window.
00234                                                   */
00235     pseudo_bit_t        a[0x00001];            /* If set, Atomic Enable for bound window. */
00236 /* -------------- */
00237     pseudo_bit_t        reserved1[0x0001e];
00238     pseudo_bit_t        zb[0x00001];           /* If set, Window is Zero Based. */
00239     pseudo_bit_t        type[0x00001];         /* Window type.
00240                                                  0 - Type one window
00241                                                  1 - Type two window
00242                                                   */
00243 /* -------------- */
00244     pseudo_bit_t        new_rkey[0x00020];     /* The new RKey of window to bind */
00245 /* -------------- */
00246     pseudo_bit_t        region_lkey[0x00020];  /* Local key of region, which window will be bound to */
00247 /* -------------- */
00248     pseudo_bit_t        start_address_h[0x00020];
00249 /* -------------- */
00250     pseudo_bit_t        start_address_l[0x00020];
00251 /* -------------- */
00252     pseudo_bit_t        length_h[0x00020];
00253 /* -------------- */
00254     pseudo_bit_t        length_l[0x00020];
00255 /* -------------- */
00256 }; 
00257 
00258 /* Send wqe segment ud */
00259 
00260 struct arbelprm_wqe_segment_ud_st {     /* Little Endian */
00261     struct arbelprm_ud_address_vector_st        ud_address_vector;/* UD Address Vector */
00262 /* -------------- */
00263     pseudo_bit_t        destination_qp[0x00018];
00264     pseudo_bit_t        reserved0[0x00008];
00265 /* -------------- */
00266     pseudo_bit_t        q_key[0x00020];
00267 /* -------------- */
00268     pseudo_bit_t        reserved1[0x00040];
00269 /* -------------- */
00270 }; 
00271 
00272 /* Send wqe segment rd */
00273 
00274 struct arbelprm_wqe_segment_rd_st {     /* Little Endian */
00275     pseudo_bit_t        destination_qp[0x00018];
00276     pseudo_bit_t        reserved0[0x00008];
00277 /* -------------- */
00278     pseudo_bit_t        q_key[0x00020];
00279 /* -------------- */
00280     pseudo_bit_t        reserved1[0x00040];
00281 /* -------------- */
00282 }; 
00283 
00284 /* Send wqe segment ctrl */
00285 
00286 struct arbelprm_wqe_segment_ctrl_send_st {      /* Little Endian */
00287     pseudo_bit_t        always1[0x00001];
00288     pseudo_bit_t        s[0x00001];            /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */
00289     pseudo_bit_t        e[0x00001];            /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */
00290     pseudo_bit_t        c[0x00001];            /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */
00291     pseudo_bit_t        ip[0x00001];           /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
00292     pseudo_bit_t        tcp_udp[0x00001];      /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
00293     pseudo_bit_t        reserved0[0x00001];
00294     pseudo_bit_t        so[0x00001];           /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
00295     pseudo_bit_t        reserved1[0x00018];
00296 /* -------------- */
00297     pseudo_bit_t        immediate[0x00020];    /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
00298 /* -------------- */
00299 }; 
00300 
00301 /* Send wqe segment next */
00302 
00303 struct arbelprm_wqe_segment_next_st {   /* Little Endian */
00304     pseudo_bit_t        nopcode[0x00005];      /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP:
00305                                                  ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else
00306                                                  ?01000? - RDMA-write
00307                                                  ?01001? - RDMA-Write with Immediate 
00308                                                  ?10000? - RDMA-read  
00309                                                  ?10001? - Atomic Compare & swap
00310                                                  ?10010? - Atomic Fetch & Add
00311                                                  ?11000? - Bind memory window
00312                                                  
00313                                                  The encoding for the following operations depends on the QP type:
00314                                                  For RC, UC and RD QP:
00315                                                  ?01010? - SEND
00316                                                  ?01011? - SEND with Immediate
00317                                                  
00318                                                  For UD QP: 
00319                                                  the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of
00320                                                  both  the current WQE and the next WQE, as follows:
00321                                                  
00322                                                  If  the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set :
00323                                                  ?01000? - SEND
00324                                                  ?01001? - SEND with Immediate
00325                                                  
00326                                                  otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set):
00327                                                  ?01010? - SEND
00328                                                  ?01011? - SEND with Immediate
00329                                                  
00330                                                  All other opcode values are RESERVED, and will result in invalid operation execution. */
00331     pseudo_bit_t        reserved0[0x00001];
00332     pseudo_bit_t        nda_31_6[0x0001a];     /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
00333 /* -------------- */
00334     pseudo_bit_t        nds[0x00006];          /* Next WQE size in OctoWords (16 bytes). 
00335                                                  Zero value in NDS field signals end of WQEs? chain.
00336                                                   */
00337     pseudo_bit_t        f[0x00001];            /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */
00338     pseudo_bit_t        always1[0x00001];
00339     pseudo_bit_t        reserved1[0x00018];
00340 /* -------------- */
00341 }; 
00342 
00343 /* Address Path */
00344 
00345 struct arbelprm_address_path_st {       /* Little Endian */
00346     pseudo_bit_t        pkey_index[0x00007];   /* PKey table index */
00347     pseudo_bit_t        reserved0[0x00011];
00348     pseudo_bit_t        port_number[0x00002];  /* Specific port associated with this QP/EE.
00349                                                  1 - Port 1
00350                                                  2 - Port 2
00351                                                  other - reserved */
00352     pseudo_bit_t        reserved1[0x00006];
00353 /* -------------- */
00354     pseudo_bit_t        rlid[0x00010];         /* Remote (Destination) LID */
00355     pseudo_bit_t        my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
00356     pseudo_bit_t        g[0x00001];            /* Global address enable - if set, GRH will be formed for packet header */
00357     pseudo_bit_t        reserved2[0x00005];
00358     pseudo_bit_t        rnr_retry[0x00003];    /* RNR retry count (see C9-132 in IB spec Vol 1)
00359                                                  0-6 - number of retries
00360                                                  7    - infinite */
00361 /* -------------- */
00362     pseudo_bit_t        hop_limit[0x00008];    /* IPv6 hop limit */
00363     pseudo_bit_t        max_stat_rate[0x00003];/* Maximum static rate control. 
00364                                                  0 - 100% injection rate 
00365                                                  1 - 25% injection rate
00366                                                  2 - 12.5% injection rate
00367                                                  3 - 50% injection rate
00368                                                  other - reserved */
00369     pseudo_bit_t        reserved3[0x00005];
00370     pseudo_bit_t        mgid_index[0x00006];   /* Index to port GID table */
00371     pseudo_bit_t        reserved4[0x00005];
00372     pseudo_bit_t        ack_timeout[0x00005];  /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
00373                                                  The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
00374 /* -------------- */
00375     pseudo_bit_t        flow_label[0x00014];   /* IPv6 flow label */
00376     pseudo_bit_t        tclass[0x00008];       /* IPv6 TClass */
00377     pseudo_bit_t        sl[0x00004];           /* InfiniBand Service Level (SL) */
00378 /* -------------- */
00379     pseudo_bit_t        rgid_127_96[0x00020];  /* Remote GID[127:96] */
00380 /* -------------- */
00381     pseudo_bit_t        rgid_95_64[0x00020];   /* Remote GID[95:64] */
00382 /* -------------- */
00383     pseudo_bit_t        rgid_63_32[0x00020];   /* Remote GID[63:32] */
00384 /* -------------- */
00385     pseudo_bit_t        rgid_31_0[0x00020];    /* Remote GID[31:0] */
00386 /* -------------- */
00387 }; 
00388 
00389 /* HCA Command Register (HCR) */
00390 
00391 struct arbelprm_hca_command_register_st {       /* Little Endian */
00392     pseudo_bit_t        in_param_h[0x00020];   /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
00393 /* -------------- */
00394     pseudo_bit_t        in_param_l[0x00020];   /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
00395 /* -------------- */
00396     pseudo_bit_t        input_modifier[0x00020];/* Input Parameter Modifier */
00397 /* -------------- */
00398     pseudo_bit_t        out_param_h[0x00020];  /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
00399 /* -------------- */
00400     pseudo_bit_t        out_param_l[0x00020];  /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
00401 /* -------------- */
00402     pseudo_bit_t        reserved0[0x00010];
00403     pseudo_bit_t        token[0x00010];        /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
00404 /* -------------- */
00405     pseudo_bit_t        opcode[0x0000c];       /* Command opcode */
00406     pseudo_bit_t        opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
00407     pseudo_bit_t        reserved1[0x00006];
00408     pseudo_bit_t        e[0x00001];            /* Event Request
00409                                                  0 - Don't report event (software will poll the GO bit)
00410                                                  1 - Report event to EQ when the command completes */
00411     pseudo_bit_t        go[0x00001];           /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
00412                                                  Software can write to the HCR only if Go bit is cleared.
00413                                                  Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
00414     pseudo_bit_t        status[0x00008];       /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
00415                                                  0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
00416 /* -------------- */
00417 }; 
00418 
00419 /* CQ Doorbell */
00420 
00421 struct arbelprm_cq_cmd_doorbell_st {    /* Little Endian */
00422     pseudo_bit_t        cqn[0x00018];          /* CQ number accessed */
00423     pseudo_bit_t        cmd[0x00003];          /* Command to be executed on CQ
00424                                                  0x0 - Reserved
00425                                                  0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
00426                                                  0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
00427                                                  0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
00428                                                  Other - Reserved */
00429     pseudo_bit_t        reserved0[0x00001];
00430     pseudo_bit_t        cmd_sn[0x00002];       /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
00431                                                  This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited 
00432                                                  completion or Request notification for multiple completions doorbells after receiving completion notification.
00433                                                  This field is initialized to Zero */
00434     pseudo_bit_t        reserved1[0x00002];
00435 /* -------------- */
00436     pseudo_bit_t        cq_param[0x00020];     /* parameter to be used by CQ command */
00437 /* -------------- */
00438 }; 
00439 
00440 /* RD-send doorbell */
00441 
00442 struct arbelprm_rd_send_doorbell_st {   /* Little Endian */
00443     pseudo_bit_t        reserved0[0x00008];
00444     pseudo_bit_t        een[0x00018];          /* End-to-end context number (reliable datagram)
00445                                                  Must be zero for Nop and Bind operations */
00446 /* -------------- */
00447     pseudo_bit_t        reserved1[0x00008];
00448     pseudo_bit_t        qpn[0x00018];          /* QP number this doorbell is rung on */
00449 /* -------------- */
00450     struct arbelprm_send_doorbell_st    send_doorbell;/* Send Parameters */
00451 /* -------------- */
00452 }; 
00453 
00454 /* Multicast Group Member QP */
00455 
00456 struct arbelprm_mgmqp_st {      /* Little Endian */
00457     pseudo_bit_t        qpn_i[0x00018];        /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
00458     pseudo_bit_t        reserved0[0x00007];
00459     pseudo_bit_t        qi[0x00001];           /* Qi: QPN_i is valid */
00460 /* -------------- */
00461 }; 
00462 
00463 /* vsd */
00464 
00465 struct arbelprm_vsd_st {        /* Little Endian */
00466     pseudo_bit_t        vsd_dw0[0x00020];
00467 /* -------------- */
00468     pseudo_bit_t        vsd_dw1[0x00020];
00469 /* -------------- */
00470     pseudo_bit_t        vsd_dw2[0x00020];
00471 /* -------------- */
00472     pseudo_bit_t        vsd_dw3[0x00020];
00473 /* -------------- */
00474     pseudo_bit_t        vsd_dw4[0x00020];
00475 /* -------------- */
00476     pseudo_bit_t        vsd_dw5[0x00020];
00477 /* -------------- */
00478     pseudo_bit_t        vsd_dw6[0x00020];
00479 /* -------------- */
00480     pseudo_bit_t        vsd_dw7[0x00020];
00481 /* -------------- */
00482     pseudo_bit_t        vsd_dw8[0x00020];
00483 /* -------------- */
00484     pseudo_bit_t        vsd_dw9[0x00020];
00485 /* -------------- */
00486     pseudo_bit_t        vsd_dw10[0x00020];
00487 /* -------------- */
00488     pseudo_bit_t        vsd_dw11[0x00020];
00489 /* -------------- */
00490     pseudo_bit_t        vsd_dw12[0x00020];
00491 /* -------------- */
00492     pseudo_bit_t        vsd_dw13[0x00020];
00493 /* -------------- */
00494     pseudo_bit_t        vsd_dw14[0x00020];
00495 /* -------------- */
00496     pseudo_bit_t        vsd_dw15[0x00020];
00497 /* -------------- */
00498     pseudo_bit_t        vsd_dw16[0x00020];
00499 /* -------------- */
00500     pseudo_bit_t        vsd_dw17[0x00020];
00501 /* -------------- */
00502     pseudo_bit_t        vsd_dw18[0x00020];
00503 /* -------------- */
00504     pseudo_bit_t        vsd_dw19[0x00020];
00505 /* -------------- */
00506     pseudo_bit_t        vsd_dw20[0x00020];
00507 /* -------------- */
00508     pseudo_bit_t        vsd_dw21[0x00020];
00509 /* -------------- */
00510     pseudo_bit_t        vsd_dw22[0x00020];
00511 /* -------------- */
00512     pseudo_bit_t        vsd_dw23[0x00020];
00513 /* -------------- */
00514     pseudo_bit_t        vsd_dw24[0x00020];
00515 /* -------------- */
00516     pseudo_bit_t        vsd_dw25[0x00020];
00517 /* -------------- */
00518     pseudo_bit_t        vsd_dw26[0x00020];
00519 /* -------------- */
00520     pseudo_bit_t        vsd_dw27[0x00020];
00521 /* -------------- */
00522     pseudo_bit_t        vsd_dw28[0x00020];
00523 /* -------------- */
00524     pseudo_bit_t        vsd_dw29[0x00020];
00525 /* -------------- */
00526     pseudo_bit_t        vsd_dw30[0x00020];
00527 /* -------------- */
00528     pseudo_bit_t        vsd_dw31[0x00020];
00529 /* -------------- */
00530     pseudo_bit_t        vsd_dw32[0x00020];
00531 /* -------------- */
00532     pseudo_bit_t        vsd_dw33[0x00020];
00533 /* -------------- */
00534     pseudo_bit_t        vsd_dw34[0x00020];
00535 /* -------------- */
00536     pseudo_bit_t        vsd_dw35[0x00020];
00537 /* -------------- */
00538     pseudo_bit_t        vsd_dw36[0x00020];
00539 /* -------------- */
00540     pseudo_bit_t        vsd_dw37[0x00020];
00541 /* -------------- */
00542     pseudo_bit_t        vsd_dw38[0x00020];
00543 /* -------------- */
00544     pseudo_bit_t        vsd_dw39[0x00020];
00545 /* -------------- */
00546     pseudo_bit_t        vsd_dw40[0x00020];
00547 /* -------------- */
00548     pseudo_bit_t        vsd_dw41[0x00020];
00549 /* -------------- */
00550     pseudo_bit_t        vsd_dw42[0x00020];
00551 /* -------------- */
00552     pseudo_bit_t        vsd_dw43[0x00020];
00553 /* -------------- */
00554     pseudo_bit_t        vsd_dw44[0x00020];
00555 /* -------------- */
00556     pseudo_bit_t        vsd_dw45[0x00020];
00557 /* -------------- */
00558     pseudo_bit_t        vsd_dw46[0x00020];
00559 /* -------------- */
00560     pseudo_bit_t        vsd_dw47[0x00020];
00561 /* -------------- */
00562     pseudo_bit_t        vsd_dw48[0x00020];
00563 /* -------------- */
00564     pseudo_bit_t        vsd_dw49[0x00020];
00565 /* -------------- */
00566     pseudo_bit_t        vsd_dw50[0x00020];
00567 /* -------------- */
00568     pseudo_bit_t        vsd_dw51[0x00020];
00569 /* -------------- */
00570     pseudo_bit_t        vsd_dw52[0x00020];
00571 /* -------------- */
00572     pseudo_bit_t        vsd_dw53[0x00020];
00573 /* -------------- */
00574     pseudo_bit_t        vsd_dw54[0x00020];
00575 /* -------------- */
00576     pseudo_bit_t        vsd_dw55[0x00020];
00577 /* -------------- */
00578 }; 
00579 
00580 /* ACCESS_LAM_inject_errors */
00581 
00582 struct arbelprm_access_lam_inject_errors_st {   /* Little Endian */
00583     struct arbelprm_access_lam_inject_errors_input_parameter_st access_lam_inject_errors_input_parameter;
00584 /* -------------- */
00585     struct arbelprm_access_lam_inject_errors_input_modifier_st  access_lam_inject_errors_input_modifier;
00586 /* -------------- */
00587     pseudo_bit_t        reserved0[0x00020];
00588 /* -------------- */
00589 }; 
00590 
00591 /* Logical DIMM Information */
00592 
00593 struct arbelprm_dimminfo_st {   /* Little Endian */
00594     pseudo_bit_t        dimmsize[0x00010];     /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */
00595     pseudo_bit_t        reserved0[0x00008];
00596     pseudo_bit_t        dimmstatus[0x00001];   /* DIMM Status
00597                                                  0 - Enabled
00598                                                  1 - Disabled
00599                                                   */
00600     pseudo_bit_t        dh[0x00001];           /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */
00601     pseudo_bit_t        wo[0x00001];           /* When set, the DIMM is write only.
00602                                                  If data integrity is configured (other than none), the DIMM must be
00603                                                  only targeted by write transactions where the address and size are multiples of 16 bytes. */
00604     pseudo_bit_t        reserved1[0x00005];
00605 /* -------------- */
00606     pseudo_bit_t        spd[0x00001];          /* 0 - DIMM SPD was read from DIMM
00607                                                  1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */
00608     pseudo_bit_t        sladr[0x00003];        /* SPD Slave Address 3 LSBits. 
00609                                                  Valid only if spd bit is 0. */
00610     pseudo_bit_t        sock_num[0x00002];     /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */
00611     pseudo_bit_t        syn[0x00004];          /* Error syndrome (valid regardless of status value)
00612                                                  0 - DIMM has no error
00613                                                  1 - SPD error (e.g. checksum error, no response, error while reading)
00614                                                  2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)
00615                                                  3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)
00616                                                  5 - DIMM size trimmed due to configuration (size exceeds)
00617                                                  other - Error, reserved
00618                                                   */
00619     pseudo_bit_t        reserved2[0x00016];
00620 /* -------------- */
00621     pseudo_bit_t        reserved3[0x00040];
00622 /* -------------- */
00623     pseudo_bit_t        dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */
00624 /* -------------- */
00625     pseudo_bit_t        dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */
00626 /* -------------- */
00627     pseudo_bit_t        reserved4[0x00040];
00628 /* -------------- */
00629 }; 
00630 
00631 /* UAR Parameters */
00632 
00633 struct arbelprm_uar_params_st { /* Little Endian */
00634     pseudo_bit_t        uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */
00635 /* -------------- */
00636     pseudo_bit_t        reserved0[0x00014];
00637     pseudo_bit_t        uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */
00638 /* -------------- */
00639     pseudo_bit_t        uar_page_sz[0x00008];  /* This field defines the size of each UAR page.
00640                                                  Size of UAR Page is 4KB*2^UAR_Page_Size */
00641     pseudo_bit_t        log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */
00642     pseudo_bit_t        reserved1[0x00004];
00643     pseudo_bit_t        log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */
00644     pseudo_bit_t        reserved2[0x0000a];
00645 /* -------------- */
00646     pseudo_bit_t        reserved3[0x00020];
00647 /* -------------- */
00648     pseudo_bit_t        uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32].
00649                                                  Number of entries in table is 2^log_max_uars.
00650                                                  Table must be aligned to its size */
00651 /* -------------- */
00652     pseudo_bit_t        uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0].
00653                                                  Number of entries in table is 2^log_max_uars. 
00654                                                  Table must be aligned to its size. */
00655 /* -------------- */
00656     pseudo_bit_t        uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32].
00657                                                  Number of entries in table is 2^log_max_uars.
00658                                                  Table must be aligned to its size. */
00659 /* -------------- */
00660     pseudo_bit_t        uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0].
00661                                                  Number of entries in table is 2^log_max_uars. 
00662                                                  Table must be aligned to its size. */
00663 /* -------------- */
00664 }; 
00665 
00666 /* Translation and Protection Tables Parameters */
00667 
00668 struct arbelprm_tptparams_st {  /* Little Endian */
00669     pseudo_bit_t        mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32].
00670                                                  Entry size is 64 bytes.
00671                                                  Table must be aligned to its size.
00672                                                  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
00673 /* -------------- */
00674     pseudo_bit_t        mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0].
00675                                                  Entry size is 64 bytes.
00676                                                  Table must be aligned to its size.
00677                                                  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
00678 /* -------------- */
00679     pseudo_bit_t        log_mpt_sz[0x00006];   /* Log (base 2) of the number of region/windows entries in the MPT table. */
00680     pseudo_bit_t        reserved0[0x00002];
00681     pseudo_bit_t        pfto[0x00005];         /* Page Fault RNR Timeout - 
00682                                                  The field returned in RNR Naks generated when a page fault is detected.
00683                                                  It has no effect when on-demand-paging is not used. */
00684     pseudo_bit_t        reserved1[0x00013];
00685 /* -------------- */
00686     pseudo_bit_t        reserved2[0x00020];
00687 /* -------------- */
00688     pseudo_bit_t        mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
00689                                                  Table must be aligned to its size.
00690                                                  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
00691 /* -------------- */
00692     pseudo_bit_t        mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
00693                                                  Table must be aligned to its size.
00694                                                  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
00695 /* -------------- */
00696     pseudo_bit_t        reserved3[0x00040];
00697 /* -------------- */
00698 }; 
00699 
00700 /* Multicast Support Parameters */
00701 
00702 struct arbelprm_multicastparam_st {     /* Little Endian */
00703     pseudo_bit_t        mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
00704                                                  The base address must be aligned to the entry size.
00705                                                  Address may be set to 0xFFFFFFFF if multicast is not supported. */
00706 /* -------------- */
00707     pseudo_bit_t        mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. 
00708                                                  The base address must be aligned to the entry size.
00709                                                  Address may be set to 0xFFFFFFFF if multicast is not supported. */
00710 /* -------------- */
00711     pseudo_bit_t        reserved0[0x00040];
00712 /* -------------- */
00713     pseudo_bit_t        log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry.
00714                                                  Must be greater than 5 (to allow CTRL and GID sections). 
00715                                                  That implies the number of QPs per MC table entry. */
00716     pseudo_bit_t        reserved1[0x00010];
00717 /* -------------- */
00718     pseudo_bit_t        mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2)
00719                                                  INIT_HCA - the required number of entries
00720                                                  QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
00721     pseudo_bit_t        reserved2[0x0000f];
00722 /* -------------- */
00723     pseudo_bit_t        log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
00724     pseudo_bit_t        reserved3[0x00013];
00725     pseudo_bit_t        mc_hash_fn[0x00003];   /* Multicast hash function
00726                                                  0 - Default hash function
00727                                                  other - reserved */
00728     pseudo_bit_t        reserved4[0x00005];
00729 /* -------------- */
00730     pseudo_bit_t        reserved5[0x00020];
00731 /* -------------- */
00732 }; 
00733 
00734 /* QPC/EEC/CQC/EQC/RDB Parameters */
00735 
00736 struct arbelprm_qpcbaseaddr_st {        /* Little Endian */
00737     pseudo_bit_t        reserved0[0x00080];
00738 /* -------------- */
00739     pseudo_bit_t        qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
00740                                                  Table must be aligned on its size */
00741 /* -------------- */
00742     pseudo_bit_t        log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
00743     pseudo_bit_t        reserved1[0x00002];
00744     pseudo_bit_t        qpc_base_addr_l[0x00019];/* QPC Base Address [31:7]
00745                                                  Table must be aligned on its size */
00746 /* -------------- */
00747     pseudo_bit_t        reserved2[0x00040];
00748 /* -------------- */
00749     pseudo_bit_t        eec_base_addr_h[0x00020];/* EEC Base Address [63:32]
00750                                                  Table must be aligned on its size.
00751                                                  Address may be set to 0xFFFFFFFF if RD is not supported. */
00752 /* -------------- */
00753     pseudo_bit_t        log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */
00754     pseudo_bit_t        reserved3[0x00002];
00755     pseudo_bit_t        eec_base_addr_l[0x00019];/* EEC Base Address [31:7]
00756                                                  Table must be aligned on its size
00757                                                  Address may be set to 0xFFFFFFFF if RD is not supported. */
00758 /* -------------- */
00759     pseudo_bit_t        srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
00760                                                  Table must be aligned on its size
00761                                                  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
00762 /* -------------- */
00763     pseudo_bit_t        log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
00764     pseudo_bit_t        srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
00765                                                  Table must be aligned on its size
00766                                                  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
00767 /* -------------- */
00768     pseudo_bit_t        cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
00769                                                  Table must be aligned on its size */
00770 /* -------------- */
00771     pseudo_bit_t        log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
00772     pseudo_bit_t        reserved4[0x00001];
00773     pseudo_bit_t        cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6]
00774                                                  Table must be aligned on its size */
00775 /* -------------- */
00776     pseudo_bit_t        reserved5[0x00040];
00777 /* -------------- */
00778     pseudo_bit_t        eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32]
00779                                                  Table has same number of entries as QPC table.
00780                                                  Table must be aligned to entry size. */
00781 /* -------------- */
00782     pseudo_bit_t        eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0]
00783                                                  Table has same number of entries as QPC table.
00784                                                  Table must be aligned to entry size. */
00785 /* -------------- */
00786     pseudo_bit_t        reserved6[0x00040];
00787 /* -------------- */
00788     pseudo_bit_t        eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32]
00789                                                  Table has same number of entries as EEC table.
00790                                                  Table must be aligned to entry size.
00791                                                  Address may be set to 0xFFFFFFFF if RD is not supported. */
00792 /* -------------- */
00793     pseudo_bit_t        eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0]
00794                                                  Table has same number of entries as EEC table.
00795                                                  Table must be aligned to entry size.
00796                                                  Address may be set to 0xFFFFFFFF if RD is not supported. */
00797 /* -------------- */
00798     pseudo_bit_t        reserved7[0x00040];
00799 /* -------------- */
00800     pseudo_bit_t        eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
00801                                                  Address may be set to 0xFFFFFFFF if EQs are not supported.
00802                                                  Table must be aligned to entry size. */
00803 /* -------------- */
00804     pseudo_bit_t        log_num_eq[0x00004];   /* Log base 2 of number of supported EQs.
00805                                                  Must be 6 or less in InfiniHost-III-EX. */
00806     pseudo_bit_t        reserved8[0x00002];
00807     pseudo_bit_t        eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6]
00808                                                  Address may be set to 0xFFFFFFFF if EQs are not supported.
00809                                                  Table must be aligned to entry size. */
00810 /* -------------- */
00811     pseudo_bit_t        reserved9[0x00040];
00812 /* -------------- */
00813     pseudo_bit_t        rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32]. 
00814                                                  Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported.
00815                                                  Please refer to QP and EE chapter for further explanation on RDB allocation. */
00816 /* -------------- */
00817     pseudo_bit_t        rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0]. 
00818                                                  Table must be aligned to RDB entry size (32 bytes).
00819                                                  Address may be set to zero if remote RDMA reads are not supported.
00820                                                  Please refer to QP and EE chapter for further explanation on RDB allocation. */
00821 /* -------------- */
00822     pseudo_bit_t        reserved10[0x00040];
00823 /* -------------- */
00824 }; 
00825 
00826 /* Header_Log_Register */
00827 
00828 struct arbelprm_header_log_register_st {        /* Little Endian */
00829     pseudo_bit_t        place_holder[0x00020];
00830 /* -------------- */
00831     pseudo_bit_t        reserved0[0x00060];
00832 /* -------------- */
00833 }; 
00834 
00835 /* Performance Monitors */
00836 
00837 struct arbelprm_performance_monitors_st {       /* Little Endian */
00838     pseudo_bit_t        e0[0x00001];           /* Enables counting of respective performance counter */
00839     pseudo_bit_t        e1[0x00001];           /* Enables counting of respective performance counter */
00840     pseudo_bit_t        e2[0x00001];           /* Enables counting of respective performance counter */
00841     pseudo_bit_t        reserved0[0x00001];
00842     pseudo_bit_t        r0[0x00001];           /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
00843     pseudo_bit_t        r1[0x00001];           /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
00844     pseudo_bit_t        r2[0x00001];           /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
00845     pseudo_bit_t        reserved1[0x00001];
00846     pseudo_bit_t        i0[0x00001];           /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
00847     pseudo_bit_t        i1[0x00001];           /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
00848     pseudo_bit_t        i2[0x00001];           /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
00849     pseudo_bit_t        reserved2[0x00001];
00850     pseudo_bit_t        f0[0x00001];           /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
00851     pseudo_bit_t        f1[0x00001];           /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
00852     pseudo_bit_t        f2[0x00001];           /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
00853     pseudo_bit_t        reserved3[0x00001];
00854     pseudo_bit_t        ev_cnt1[0x00005];      /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
00855     pseudo_bit_t        reserved4[0x00003];
00856     pseudo_bit_t        ev_cnt2[0x00005];      /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
00857     pseudo_bit_t        reserved5[0x00003];
00858 /* -------------- */
00859     pseudo_bit_t        clock_counter[0x00020];
00860 /* -------------- */
00861     pseudo_bit_t        event_counter1[0x00020];
00862 /* -------------- */
00863     pseudo_bit_t        event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
00864 /* -------------- */
00865 }; 
00866 
00867 /* Receive segment format */
00868 
00869 struct arbelprm_wqe_segment_ctrl_recv_st {      /* Little Endian */
00870     struct arbelprm_recv_wqe_segment_next_st    wqe_segment_next;
00871 /* -------------- */
00872     pseudo_bit_t        reserved0[0x00002];
00873     pseudo_bit_t        reserved1[0x00001];
00874     pseudo_bit_t        reserved2[0x00001];
00875     pseudo_bit_t        reserved3[0x0001c];
00876 /* -------------- */
00877     pseudo_bit_t        reserved4[0x00020];
00878 /* -------------- */
00879 }; 
00880 
00881 /* MLX WQE segment format */
00882 
00883 struct arbelprm_wqe_segment_ctrl_mlx_st {       /* Little Endian */
00884     pseudo_bit_t        reserved0[0x00002];
00885     pseudo_bit_t        e[0x00001];            /* WQE event */
00886     pseudo_bit_t        c[0x00001];            /* Create CQE (for "requested signalling" QP) */
00887     pseudo_bit_t        icrc[0x00002];         /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved.  3 - Leave last dword as is. Last dword must not be 0x0. */
00888     pseudo_bit_t        reserved1[0x00002];
00889     pseudo_bit_t        sl[0x00004];
00890     pseudo_bit_t        max_statrate[0x00004];
00891     pseudo_bit_t        slr[0x00001];          /* 0= take slid from port. 1= take slid from given headers */
00892     pseudo_bit_t        v15[0x00001];          /* Send packet over VL15 */
00893     pseudo_bit_t        reserved2[0x0000e];
00894 /* -------------- */
00895     pseudo_bit_t        vcrc[0x00010];         /* Packet's VCRC (if not 0 - otherwise computed by HW) */
00896     pseudo_bit_t        rlid[0x00010];         /* Destination LID (must match given headers) */
00897 /* -------------- */
00898 }; 
00899 
00900 /* Send WQE segment format */
00901 
00902 struct arbelprm_send_wqe_segment_st {   /* Little Endian */
00903     struct arbelprm_wqe_segment_next_st wqe_segment_next;/* Send wqe segment next */
00904 /* -------------- */
00905     struct arbelprm_wqe_segment_ctrl_send_st    wqe_segment_ctrl_send;/* Send wqe segment ctrl */
00906 /* -------------- */
00907     struct arbelprm_wqe_segment_rd_st   wqe_segment_rd;/* Send wqe segment rd */
00908 /* -------------- */
00909     struct arbelprm_wqe_segment_ud_st   wqe_segment_ud;/* Send wqe segment ud */
00910 /* -------------- */
00911     struct arbelprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */
00912 /* -------------- */
00913     pseudo_bit_t        reserved0[0x00180];
00914 /* -------------- */
00915     struct arbelprm_wqe_segment_remote_address_st       wqe_segment_remote_address;/* Send wqe segment remote address */
00916 /* -------------- */
00917     struct arbelprm_wqe_segment_atomic_st       wqe_segment_atomic;/* Send wqe segment atomic */
00918 /* -------------- */
00919     struct arbelprm_fast_registration_segment_st        fast_registration_segment;/* Fast Registration Segment */
00920 /* -------------- */
00921     struct arbelprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */
00922 /* -------------- */
00923     struct arbelprm_wqe_segment_data_ptr_st     wqe_segment_data_ptr;/* Send wqe segment data ptr */
00924 /* -------------- */
00925     struct arbelprm_wqe_segment_data_inline_st  wqe_segment_data_inline;/* Send wqe segment data inline */
00926 /* -------------- */
00927     pseudo_bit_t        reserved1[0x00200];
00928 /* -------------- */
00929 }; 
00930 
00931 /* QP and EE Context Entry */
00932 
00933 struct arbelprm_queue_pair_ee_context_entry_st {        /* Little Endian */
00934     pseudo_bit_t        reserved0[0x00008];
00935     pseudo_bit_t        de[0x00001];           /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */
00936     pseudo_bit_t        reserved1[0x00002];
00937     pseudo_bit_t        pm_state[0x00002];     /* Path migration state (Migrated, Armed or Rearm)
00938                                                  11-Migrated
00939                                                  00-Armed
00940                                                  01-Rearm
00941                                                  10-Reserved
00942                                                  Should be set to 11 for UD QPs and for QPs which do not support APM */
00943     pseudo_bit_t        reserved2[0x00003];
00944     pseudo_bit_t        st[0x00003];           /* Service type (invalid in EE context):
00945                                                  000-Reliable Connection
00946                                                  001-Unreliable Connection
00947                                                  010-Reliable Datagram 
00948                                                  011-Unreliable Datagram
00949                                                  111-MLX transport (raw bits injection). Used for management QPs and RAW */
00950     pseudo_bit_t        reserved3[0x00009];
00951     pseudo_bit_t        state[0x00004];        /* QP/EE state:
00952                                                  0 - RST
00953                                                  1 - INIT
00954                                                  2 - RTR
00955                                                  3 - RTS
00956                                                  4 - SQEr
00957                                                  5 - SQD (Send Queue Drained)
00958                                                  6 - ERR
00959                                                  7 - Send Queue Draining
00960                                                  8 - Reserved
00961                                                  9 - Suspended
00962                                                  A- F - Reserved
00963                                                  (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
00964 /* -------------- */
00965     pseudo_bit_t        reserved4[0x00020];
00966 /* -------------- */
00967     pseudo_bit_t        sched_queue[0x00004];  /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */
00968     pseudo_bit_t        rlky[0x00001];         /* When set this QP can use the Reserved L_Key */
00969     pseudo_bit_t        reserved5[0x00003];
00970     pseudo_bit_t        log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
00971                                                  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
00972     pseudo_bit_t        log_sq_size[0x00004];  /* Log2 of the Number of WQEs in the Send Queue. */
00973     pseudo_bit_t        reserved6[0x00001];
00974     pseudo_bit_t        log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
00975                                                  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
00976     pseudo_bit_t        log_rq_size[0x00004];  /* Log2 of the Number of WQEs in the Receive Queue. */
00977     pseudo_bit_t        reserved7[0x00001];
00978     pseudo_bit_t        msg_max[0x00005];      /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
00979                                                  Must be equal to MTU for UD and MLX QPs. */
00980     pseudo_bit_t        mtu[0x00003];          /* MTU of the QP (Must be the same for both paths: primary and alternative):
00981                                                  0x1 - 256 bytes
00982                                                  0x2 - 512
00983                                                  0x3 - 1024
00984                                                  0x4 - 2048
00985                                                  other - reserved
00986                                                  
00987                                                  Should be configured to 0x4 for UD and MLX QPs. */
00988 /* -------------- */
00989     pseudo_bit_t        usr_page[0x00018];     /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
00990     pseudo_bit_t        reserved8[0x00008];
00991 /* -------------- */
00992     pseudo_bit_t        local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
00993                                                  This field is valid for QUERY and ERR2RST commands only. */
00994     pseudo_bit_t        reserved9[0x00008];
00995 /* -------------- */
00996     pseudo_bit_t        remote_qpn_een[0x00018];/* Remote QP/EE number */
00997     pseudo_bit_t        reserved10[0x00008];
00998 /* -------------- */
00999     pseudo_bit_t        reserved11[0x00040];
01000 /* -------------- */
01001     struct arbelprm_address_path_st     primary_address_path;/* Primary address path for the QP/EE */
01002 /* -------------- */
01003     struct arbelprm_address_path_st     alternative_address_path;/* Alternate address path for the QP/EE */
01004 /* -------------- */
01005     pseudo_bit_t        rdd[0x00018];          /* Reliable Datagram Domain */
01006     pseudo_bit_t        reserved12[0x00008];
01007 /* -------------- */
01008     pseudo_bit_t        pd[0x00018];           /* QP protection domain. Not valid (reserved) in EE context. */
01009     pseudo_bit_t        reserved13[0x00008];
01010 /* -------------- */
01011     pseudo_bit_t        wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ. 
01012                                                  Reserved for EE context. */
01013 /* -------------- */
01014     pseudo_bit_t        wqe_lkey[0x00020];     /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */
01015 /* -------------- */
01016     pseudo_bit_t        reserved14[0x00003];
01017     pseudo_bit_t        ssc[0x00001];          /* Send Signaled Completion
01018                                                  1 - all send WQEs generate CQEs. 
01019                                                  0 - only send WQEs with C bit set generate completion. 
01020                                                  Not valid (reserved) in EE context. */
01021     pseudo_bit_t        sic[0x00001];          /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */
01022     pseudo_bit_t        cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
01023                                                  The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
01024     pseudo_bit_t        cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
01025                                                  The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
01026     pseudo_bit_t        fre[0x00001];          /* Fast Registration Work Request Enabled. (Reserved for EE) */
01027     pseudo_bit_t        reserved15[0x00001];
01028     pseudo_bit_t        sae[0x00001];          /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */
01029     pseudo_bit_t        swe[0x00001];          /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */
01030     pseudo_bit_t        sre[0x00001];          /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */
01031     pseudo_bit_t        retry_count[0x00003];  /* Transport timeout Retry count */
01032     pseudo_bit_t        reserved16[0x00002];
01033     pseudo_bit_t        sra_max[0x00003];      /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
01034     pseudo_bit_t        flight_lim[0x00004];   /* Number of outstanding (in-flight) messages on the wire allowed for this send queue. 
01035                                                  Number of outstanding messages is 2^Flight_Lim. 
01036                                                  Use 0xF for unlimited number of outstanding messages. */
01037     pseudo_bit_t        ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
01038 /* -------------- */
01039     pseudo_bit_t        reserved17[0x00020];
01040 /* -------------- */
01041     pseudo_bit_t        next_send_psn[0x00018];/* Next PSN to be sent */
01042     pseudo_bit_t        reserved18[0x00008];
01043 /* -------------- */
01044     pseudo_bit_t        cqn_snd[0x00018];      /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
01045     pseudo_bit_t        reserved19[0x00008];
01046 /* -------------- */
01047     pseudo_bit_t        reserved20[0x00006];
01048     pseudo_bit_t        snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
01049 /* -------------- */
01050     pseudo_bit_t        snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry.
01051                                                  HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record.
01052                                                  The entry is obtained via the usr_page field.
01053                                                  Not valid for EE. */
01054 /* -------------- */
01055     pseudo_bit_t        last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
01056     pseudo_bit_t        reserved21[0x00008];
01057 /* -------------- */
01058     pseudo_bit_t        ssn[0x00018];          /* Requester Send Sequence Number (QUERY_QPEE only) */
01059     pseudo_bit_t        reserved22[0x00008];
01060 /* -------------- */
01061     pseudo_bit_t        reserved23[0x00003];
01062     pseudo_bit_t        rsc[0x00001];          /* 1 - all receive WQEs generate CQEs. 
01063                                                  0 - only receive WQEs with C bit set generate completion. 
01064                                                  Not valid (reserved) in EE context.
01065                                                   */
01066     pseudo_bit_t        ric[0x00001];          /* Invalid Credits. 
01067                                                  1 - place "Invalid Credits" to ACKs sent from this queue.
01068                                                  0 - ACKs report the actual number of end to end credits on the connection.
01069                                                  Not valid (reserved) in EE context.
01070                                                  Must be set to 1 on QPs which are attached to SRQ. */
01071     pseudo_bit_t        reserved24[0x00008];
01072     pseudo_bit_t        rae[0x00001];          /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
01073     pseudo_bit_t        rwe[0x00001];          /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
01074     pseudo_bit_t        rre[0x00001];          /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
01075     pseudo_bit_t        reserved25[0x00005];
01076     pseudo_bit_t        rra_max[0x00003];      /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. 
01077                                                  Must be 0 for EE context. */
01078     pseudo_bit_t        reserved26[0x00008];
01079 /* -------------- */
01080     pseudo_bit_t        next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
01081     pseudo_bit_t        min_rnr_nak[0x00005];  /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). 
01082                                                  Not valid (reserved) in EE context. */
01083     pseudo_bit_t        reserved27[0x00003];
01084 /* -------------- */
01085     pseudo_bit_t        reserved28[0x00005];
01086     pseudo_bit_t        ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer. 
01087                                                  This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */
01088 /* -------------- */
01089     pseudo_bit_t        cqn_rcv[0x00018];      /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
01090     pseudo_bit_t        reserved29[0x00008];
01091 /* -------------- */
01092     pseudo_bit_t        reserved30[0x00006];
01093     pseudo_bit_t        rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
01094 /* -------------- */
01095     pseudo_bit_t        rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. 
01096                                                  HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record.
01097                                                  The entry is obtained via the usr_page field.
01098                                                  Not valid for EE. */
01099 /* -------------- */
01100     pseudo_bit_t        q_key[0x00020];        /* Q_Key to be validated against received datagrams.
01101                                                  On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
01102                                                  Not valid (reserved) in EE context. */
01103 /* -------------- */
01104     pseudo_bit_t        srqn[0x00018];         /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. 
01105                                                  SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
01106     pseudo_bit_t        srq[0x00001];          /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
01107     pseudo_bit_t        reserved31[0x00007];
01108 /* -------------- */
01109     pseudo_bit_t        rmsn[0x00018];         /* Responder current message sequence number (QUERY_QPEE only) */
01110     pseudo_bit_t        reserved32[0x00008];
01111 /* -------------- */
01112     pseudo_bit_t        sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
01113                                                  Must be 0x0 in SQ initialization.
01114                                                  (QUERY_QPEE only). */
01115     pseudo_bit_t        rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
01116                                                  Must be 0x0 in RQ initialization.
01117                                                  (QUERY_QPEE only). */
01118 /* -------------- */
01119     pseudo_bit_t        reserved33[0x00040];
01120 /* -------------- */
01121 }; 
01122 
01123 /* Clear Interrupt [63:0] */
01124 
01125 struct arbelprm_clr_int_st {    /* Little Endian */
01126     pseudo_bit_t        clr_int_h[0x00020];    /* Clear Interrupt [63:32]
01127                                                  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 
01128                                                  This register is write-only. Reading from this register will cause undefined result
01129                                                   */
01130 /* -------------- */
01131     pseudo_bit_t        clr_int_l[0x00020];    /* Clear Interrupt [31:0]
01132                                                  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 
01133                                                  This register is write-only. Reading from this register will cause undefined result */
01134 /* -------------- */
01135 }; 
01136 
01137 /* EQ_Arm_DB_Region */
01138 
01139 struct arbelprm_eq_arm_db_region_st {   /* Little Endian */
01140     pseudo_bit_t        eq_x_arm_h[0x00020];   /* EQ[63:32]  X state.
01141                                                  This register is used to Arm EQs when setting the appropriate bits. */
01142 /* -------------- */
01143     pseudo_bit_t        eq_x_arm_l[0x00020];   /* EQ[31:0]  X state.
01144                                                  This register is used to Arm EQs when setting the appropriate bits. */
01145 /* -------------- */
01146 }; 
01147 
01148 /* EQ Set CI DBs Table */
01149 
01150 struct arbelprm_eq_set_ci_table_st {    /* Little Endian */
01151     pseudo_bit_t        eq0_set_ci[0x00020];   /* EQ0_Set_CI */
01152 /* -------------- */
01153     pseudo_bit_t        reserved0[0x00020];
01154 /* -------------- */
01155     pseudo_bit_t        eq1_set_ci[0x00020];   /* EQ1_Set_CI */
01156 /* -------------- */
01157     pseudo_bit_t        reserved1[0x00020];
01158 /* -------------- */
01159     pseudo_bit_t        eq2_set_ci[0x00020];   /* EQ2_Set_CI */
01160 /* -------------- */
01161     pseudo_bit_t        reserved2[0x00020];
01162 /* -------------- */
01163     pseudo_bit_t        eq3_set_ci[0x00020];   /* EQ3_Set_CI */
01164 /* -------------- */
01165     pseudo_bit_t        reserved3[0x00020];
01166 /* -------------- */
01167     pseudo_bit_t        eq4_set_ci[0x00020];   /* EQ4_Set_CI */
01168 /* -------------- */
01169     pseudo_bit_t        reserved4[0x00020];
01170 /* -------------- */
01171     pseudo_bit_t        eq5_set_ci[0x00020];   /* EQ5_Set_CI */
01172 /* -------------- */
01173     pseudo_bit_t        reserved5[0x00020];
01174 /* -------------- */
01175     pseudo_bit_t        eq6_set_ci[0x00020];   /* EQ6_Set_CI */
01176 /* -------------- */
01177     pseudo_bit_t        reserved6[0x00020];
01178 /* -------------- */
01179     pseudo_bit_t        eq7_set_ci[0x00020];   /* EQ7_Set_CI */
01180 /* -------------- */
01181     pseudo_bit_t        reserved7[0x00020];
01182 /* -------------- */
01183     pseudo_bit_t        eq8_set_ci[0x00020];   /* EQ8_Set_CI */
01184 /* -------------- */
01185     pseudo_bit_t        reserved8[0x00020];
01186 /* -------------- */
01187     pseudo_bit_t        eq9_set_ci[0x00020];   /* EQ9_Set_CI */
01188 /* -------------- */
01189     pseudo_bit_t        reserved9[0x00020];
01190 /* -------------- */
01191     pseudo_bit_t        eq10_set_ci[0x00020];  /* EQ10_Set_CI */
01192 /* -------------- */
01193     pseudo_bit_t        reserved10[0x00020];
01194 /* -------------- */
01195     pseudo_bit_t        eq11_set_ci[0x00020];  /* EQ11_Set_CI */
01196 /* -------------- */
01197     pseudo_bit_t        reserved11[0x00020];
01198 /* -------------- */
01199     pseudo_bit_t        eq12_set_ci[0x00020];  /* EQ12_Set_CI */
01200 /* -------------- */
01201     pseudo_bit_t        reserved12[0x00020];
01202 /* -------------- */
01203     pseudo_bit_t        eq13_set_ci[0x00020];  /* EQ13_Set_CI */
01204 /* -------------- */
01205     pseudo_bit_t        reserved13[0x00020];
01206 /* -------------- */
01207     pseudo_bit_t        eq14_set_ci[0x00020];  /* EQ14_Set_CI */
01208 /* -------------- */
01209     pseudo_bit_t        reserved14[0x00020];
01210 /* -------------- */
01211     pseudo_bit_t        eq15_set_ci[0x00020];  /* EQ15_Set_CI */
01212 /* -------------- */
01213     pseudo_bit_t        reserved15[0x00020];
01214 /* -------------- */
01215     pseudo_bit_t        eq16_set_ci[0x00020];  /* EQ16_Set_CI */
01216 /* -------------- */
01217     pseudo_bit_t        reserved16[0x00020];
01218 /* -------------- */
01219     pseudo_bit_t        eq17_set_ci[0x00020];  /* EQ17_Set_CI */
01220 /* -------------- */
01221     pseudo_bit_t        reserved17[0x00020];
01222 /* -------------- */
01223     pseudo_bit_t        eq18_set_ci[0x00020];  /* EQ18_Set_CI */
01224 /* -------------- */
01225     pseudo_bit_t        reserved18[0x00020];
01226 /* -------------- */
01227     pseudo_bit_t        eq19_set_ci[0x00020];  /* EQ19_Set_CI */
01228 /* -------------- */
01229     pseudo_bit_t        reserved19[0x00020];
01230 /* -------------- */
01231     pseudo_bit_t        eq20_set_ci[0x00020];  /* EQ20_Set_CI */
01232 /* -------------- */
01233     pseudo_bit_t        reserved20[0x00020];
01234 /* -------------- */
01235     pseudo_bit_t        eq21_set_ci[0x00020];  /* EQ21_Set_CI */
01236 /* -------------- */
01237     pseudo_bit_t        reserved21[0x00020];
01238 /* -------------- */
01239     pseudo_bit_t        eq22_set_ci[0x00020];  /* EQ22_Set_CI */
01240 /* -------------- */
01241     pseudo_bit_t        reserved22[0x00020];
01242 /* -------------- */
01243     pseudo_bit_t        eq23_set_ci[0x00020];  /* EQ23_Set_CI */
01244 /* -------------- */
01245     pseudo_bit_t        reserved23[0x00020];
01246 /* -------------- */
01247     pseudo_bit_t        eq24_set_ci[0x00020];  /* EQ24_Set_CI */
01248 /* -------------- */
01249     pseudo_bit_t        reserved24[0x00020];
01250 /* -------------- */
01251     pseudo_bit_t        eq25_set_ci[0x00020];  /* EQ25_Set_CI */
01252 /* -------------- */
01253     pseudo_bit_t        reserved25[0x00020];
01254 /* -------------- */
01255     pseudo_bit_t        eq26_set_ci[0x00020];  /* EQ26_Set_CI */
01256 /* -------------- */
01257     pseudo_bit_t        reserved26[0x00020];
01258 /* -------------- */
01259     pseudo_bit_t        eq27_set_ci[0x00020];  /* EQ27_Set_CI */
01260 /* -------------- */
01261     pseudo_bit_t        reserved27[0x00020];
01262 /* -------------- */
01263     pseudo_bit_t        eq28_set_ci[0x00020];  /* EQ28_Set_CI */
01264 /* -------------- */
01265     pseudo_bit_t        reserved28[0x00020];
01266 /* -------------- */
01267     pseudo_bit_t        eq29_set_ci[0x00020];  /* EQ29_Set_CI */
01268 /* -------------- */
01269     pseudo_bit_t        reserved29[0x00020];
01270 /* -------------- */
01271     pseudo_bit_t        eq30_set_ci[0x00020];  /* EQ30_Set_CI */
01272 /* -------------- */
01273     pseudo_bit_t        reserved30[0x00020];
01274 /* -------------- */
01275     pseudo_bit_t        eq31_set_ci[0x00020];  /* EQ31_Set_CI */
01276 /* -------------- */
01277     pseudo_bit_t        reserved31[0x00020];
01278 /* -------------- */
01279     pseudo_bit_t        eq32_set_ci[0x00020];  /* EQ32_Set_CI */
01280 /* -------------- */
01281     pseudo_bit_t        reserved32[0x00020];
01282 /* -------------- */
01283     pseudo_bit_t        eq33_set_ci[0x00020];  /* EQ33_Set_CI */
01284 /* -------------- */
01285     pseudo_bit_t        reserved33[0x00020];
01286 /* -------------- */
01287     pseudo_bit_t        eq34_set_ci[0x00020];  /* EQ34_Set_CI */
01288 /* -------------- */
01289     pseudo_bit_t        reserved34[0x00020];
01290 /* -------------- */
01291     pseudo_bit_t        eq35_set_ci[0x00020];  /* EQ35_Set_CI */
01292 /* -------------- */
01293     pseudo_bit_t        reserved35[0x00020];
01294 /* -------------- */
01295     pseudo_bit_t        eq36_set_ci[0x00020];  /* EQ36_Set_CI */
01296 /* -------------- */
01297     pseudo_bit_t        reserved36[0x00020];
01298 /* -------------- */
01299     pseudo_bit_t        eq37_set_ci[0x00020];  /* EQ37_Set_CI */
01300 /* -------------- */
01301     pseudo_bit_t        reserved37[0x00020];
01302 /* -------------- */
01303     pseudo_bit_t        eq38_set_ci[0x00020];  /* EQ38_Set_CI */
01304 /* -------------- */
01305     pseudo_bit_t        reserved38[0x00020];
01306 /* -------------- */
01307     pseudo_bit_t        eq39_set_ci[0x00020];  /* EQ39_Set_CI */
01308 /* -------------- */
01309     pseudo_bit_t        reserved39[0x00020];
01310 /* -------------- */
01311     pseudo_bit_t        eq40_set_ci[0x00020];  /* EQ40_Set_CI */
01312 /* -------------- */
01313     pseudo_bit_t        reserved40[0x00020];
01314 /* -------------- */
01315     pseudo_bit_t        eq41_set_ci[0x00020];  /* EQ41_Set_CI */
01316 /* -------------- */
01317     pseudo_bit_t        reserved41[0x00020];
01318 /* -------------- */
01319     pseudo_bit_t        eq42_set_ci[0x00020];  /* EQ42_Set_CI */
01320 /* -------------- */
01321     pseudo_bit_t        reserved42[0x00020];
01322 /* -------------- */
01323     pseudo_bit_t        eq43_set_ci[0x00020];  /* EQ43_Set_CI */
01324 /* -------------- */
01325     pseudo_bit_t        reserved43[0x00020];
01326 /* -------------- */
01327     pseudo_bit_t        eq44_set_ci[0x00020];  /* EQ44_Set_CI */
01328 /* -------------- */
01329     pseudo_bit_t        reserved44[0x00020];
01330 /* -------------- */
01331     pseudo_bit_t        eq45_set_ci[0x00020];  /* EQ45_Set_CI */
01332 /* -------------- */
01333     pseudo_bit_t        reserved45[0x00020];
01334 /* -------------- */
01335     pseudo_bit_t        eq46_set_ci[0x00020];  /* EQ46_Set_CI */
01336 /* -------------- */
01337     pseudo_bit_t        reserved46[0x00020];
01338 /* -------------- */
01339     pseudo_bit_t        eq47_set_ci[0x00020];  /* EQ47_Set_CI */
01340 /* -------------- */
01341     pseudo_bit_t        reserved47[0x00020];
01342 /* -------------- */
01343     pseudo_bit_t        eq48_set_ci[0x00020];  /* EQ48_Set_CI */
01344 /* -------------- */
01345     pseudo_bit_t        reserved48[0x00020];
01346 /* -------------- */
01347     pseudo_bit_t        eq49_set_ci[0x00020];  /* EQ49_Set_CI */
01348 /* -------------- */
01349     pseudo_bit_t        reserved49[0x00020];
01350 /* -------------- */
01351     pseudo_bit_t        eq50_set_ci[0x00020];  /* EQ50_Set_CI */
01352 /* -------------- */
01353     pseudo_bit_t        reserved50[0x00020];
01354 /* -------------- */
01355     pseudo_bit_t        eq51_set_ci[0x00020];  /* EQ51_Set_CI */
01356 /* -------------- */
01357     pseudo_bit_t        reserved51[0x00020];
01358 /* -------------- */
01359     pseudo_bit_t        eq52_set_ci[0x00020];  /* EQ52_Set_CI */
01360 /* -------------- */
01361     pseudo_bit_t        reserved52[0x00020];
01362 /* -------------- */
01363     pseudo_bit_t        eq53_set_ci[0x00020];  /* EQ53_Set_CI */
01364 /* -------------- */
01365     pseudo_bit_t        reserved53[0x00020];
01366 /* -------------- */
01367     pseudo_bit_t        eq54_set_ci[0x00020];  /* EQ54_Set_CI */
01368 /* -------------- */
01369     pseudo_bit_t        reserved54[0x00020];
01370 /* -------------- */
01371     pseudo_bit_t        eq55_set_ci[0x00020];  /* EQ55_Set_CI */
01372 /* -------------- */
01373     pseudo_bit_t        reserved55[0x00020];
01374 /* -------------- */
01375     pseudo_bit_t        eq56_set_ci[0x00020];  /* EQ56_Set_CI */
01376 /* -------------- */
01377     pseudo_bit_t        reserved56[0x00020];
01378 /* -------------- */
01379     pseudo_bit_t        eq57_set_ci[0x00020];  /* EQ57_Set_CI */
01380 /* -------------- */
01381     pseudo_bit_t        reserved57[0x00020];
01382 /* -------------- */
01383     pseudo_bit_t        eq58_set_ci[0x00020];  /* EQ58_Set_CI */
01384 /* -------------- */
01385     pseudo_bit_t        reserved58[0x00020];
01386 /* -------------- */
01387     pseudo_bit_t        eq59_set_ci[0x00020];  /* EQ59_Set_CI */
01388 /* -------------- */
01389     pseudo_bit_t        reserved59[0x00020];
01390 /* -------------- */
01391     pseudo_bit_t        eq60_set_ci[0x00020];  /* EQ60_Set_CI */
01392 /* -------------- */
01393     pseudo_bit_t        reserved60[0x00020];
01394 /* -------------- */
01395     pseudo_bit_t        eq61_set_ci[0x00020];  /* EQ61_Set_CI */
01396 /* -------------- */
01397     pseudo_bit_t        reserved61[0x00020];
01398 /* -------------- */
01399     pseudo_bit_t        eq62_set_ci[0x00020];  /* EQ62_Set_CI */
01400 /* -------------- */
01401     pseudo_bit_t        reserved62[0x00020];
01402 /* -------------- */
01403     pseudo_bit_t        eq63_set_ci[0x00020];  /* EQ63_Set_CI */
01404 /* -------------- */
01405     pseudo_bit_t        reserved63[0x00020];
01406 /* -------------- */
01407 }; 
01408 
01409 /* InfiniHost-III-EX Configuration Registers */
01410 
01411 struct arbelprm_configuration_registers_st {    /* Little Endian */
01412     pseudo_bit_t        reserved0[0x403400];
01413 /* -------------- */
01414     struct arbelprm_hca_command_register_st     hca_command_interface_register;/* HCA Command Register */
01415 /* -------------- */
01416     pseudo_bit_t        reserved1[0x3fcb20];
01417 /* -------------- */
01418 }; 
01419 
01420 /* QP_DB_Record */
01421 
01422 struct arbelprm_qp_db_record_st {       /* Little Endian */
01423     pseudo_bit_t        counter[0x00010];      /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */
01424     pseudo_bit_t        reserved0[0x00010];
01425 /* -------------- */
01426     pseudo_bit_t        reserved1[0x00005];
01427     pseudo_bit_t        res[0x00003];          /* 0x3 for SQ
01428                                                  0x4 for RQ 
01429                                                  0x5 for SRQ */
01430     pseudo_bit_t        qp_number[0x00018];    /* QP number */
01431 /* -------------- */
01432 }; 
01433 
01434 /* CQ_ARM_DB_Record */
01435 
01436 struct arbelprm_cq_arm_db_record_st {   /* Little Endian */
01437     pseudo_bit_t        counter[0x00020];      /* CQ counter for the arming request */
01438 /* -------------- */
01439     pseudo_bit_t        cmd[0x00003];          /* 0x0 - No command
01440                                                  0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
01441                                                  0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
01442                                                  0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
01443                                                  Other - Reserved */
01444     pseudo_bit_t        cmd_sn[0x00002];       /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
01445     pseudo_bit_t        res[0x00003];          /* Must be 0x2 */
01446     pseudo_bit_t        cq_number[0x00018];    /* CQ number */
01447 /* -------------- */
01448 }; 
01449 
01450 /* CQ_CI_DB_Record */
01451 
01452 struct arbelprm_cq_ci_db_record_st {    /* Little Endian */
01453     pseudo_bit_t        counter[0x00020];      /* CQ counter */
01454 /* -------------- */
01455     pseudo_bit_t        reserved0[0x00005];
01456     pseudo_bit_t        res[0x00003];          /* Must be 0x1 */
01457     pseudo_bit_t        cq_number[0x00018];    /* CQ number */
01458 /* -------------- */
01459 }; 
01460 
01461 /* Virtual_Physical_Mapping */
01462 
01463 struct arbelprm_virtual_physical_mapping_st {   /* Little Endian */
01464     pseudo_bit_t        va_h[0x00020];         /* Virtual Address[63:32]. Valid only for MAP_ICM command. */
01465 /* -------------- */
01466     pseudo_bit_t        reserved0[0x0000c];
01467     pseudo_bit_t        va_l[0x00014];         /* Virtual Address[31:12]. Valid only for MAP_ICM command. */
01468 /* -------------- */
01469     pseudo_bit_t        pa_h[0x00020];         /* Physical Address[63:32] */
01470 /* -------------- */
01471     pseudo_bit_t        log2size[0x00006];     /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */
01472     pseudo_bit_t        reserved1[0x00006];
01473     pseudo_bit_t        pa_l[0x00014];         /* Physical Address[31:12] */
01474 /* -------------- */
01475 }; 
01476 
01477 /* MOD_STAT_CFG */
01478 
01479 struct arbelprm_mod_stat_cfg_st {       /* Little Endian */
01480     pseudo_bit_t        log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */
01481     pseudo_bit_t        reserved0[0x00001];
01482     pseudo_bit_t        srq[0x00001];          /* When set SRQs are supported */
01483     pseudo_bit_t        srq_m[0x00001];        /* Modify SRQ parameters */
01484     pseudo_bit_t        reserved1[0x00018];
01485 /* -------------- */
01486     pseudo_bit_t        reserved2[0x007e0];
01487 /* -------------- */
01488 }; 
01489 
01490 /* SRQ Context */
01491 
01492 struct arbelprm_srq_context_st {        /* Little Endian */
01493     pseudo_bit_t        srqn[0x00018];         /* SRQ number */
01494     pseudo_bit_t        log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue.
01495                                                  Maximum value is 0x10, i.e. 16M WQEs. */
01496     pseudo_bit_t        state[0x00004];        /* SRQ State:
01497                                                  1111 - SW Ownership
01498                                                  0000 - HW Ownership
01499                                                  0001 - Error
01500                                                  Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
01501 /* -------------- */
01502     pseudo_bit_t        l_key[0x00020];        /* memory key (L-Key) to be used to access WQEs. */
01503 /* -------------- */
01504     pseudo_bit_t        srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. 
01505                                                  HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record.
01506                                                  The entry is obtained via the usr_page field. */
01507 /* -------------- */
01508     pseudo_bit_t        usr_page[0x00018];     /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
01509     pseudo_bit_t        reserved0[0x00005];
01510     pseudo_bit_t        log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
01511 /* -------------- */
01512     pseudo_bit_t        wqe_addr_h[0x00020];   /* Bits 63:32 of WQE address (WQE base address) */
01513 /* -------------- */
01514     pseudo_bit_t        reserved1[0x00006];
01515     pseudo_bit_t        srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */
01516 /* -------------- */
01517     pseudo_bit_t        pd[0x00018];           /* SRQ protection domain. */
01518     pseudo_bit_t        reserved2[0x00008];
01519 /* -------------- */
01520     pseudo_bit_t        wqe_cnt[0x00010];      /* WQE count on the SRQ.
01521                                                  Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
01522     pseudo_bit_t        lwm[0x00010];          /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */
01523 /* -------------- */
01524     pseudo_bit_t        srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
01525                                                  Must be 0x0 in SRQ initialization.
01526                                                  (QUERY_SRQ only). */
01527     pseudo_bit_t        reserved3[0x00010];
01528 /* -------------- */
01529     pseudo_bit_t        reserved4[0x00060];
01530 /* -------------- */
01531 }; 
01532 
01533 /* PBL */
01534 
01535 struct arbelprm_pbl_st {        /* Little Endian */
01536     pseudo_bit_t        mtt_0_h[0x00020];      /* First MTT[63:32] */
01537 /* -------------- */
01538     pseudo_bit_t        mtt_0_l[0x00020];      /* First MTT[31:0] */
01539 /* -------------- */
01540     pseudo_bit_t        mtt_1_h[0x00020];      /* Second MTT[63:32] */
01541 /* -------------- */
01542     pseudo_bit_t        mtt_1_l[0x00020];      /* Second MTT[31:0] */
01543 /* -------------- */
01544     pseudo_bit_t        mtt_2_h[0x00020];      /* Third MTT[63:32] */
01545 /* -------------- */
01546     pseudo_bit_t        mtt_2_l[0x00020];      /* Third MTT[31:0] */
01547 /* -------------- */
01548     pseudo_bit_t        mtt_3_h[0x00020];      /* Fourth MTT[63:32] */
01549 /* -------------- */
01550     pseudo_bit_t        mtt_3_l[0x00020];      /* Fourth MTT[31:0] */
01551 /* -------------- */
01552 }; 
01553 
01554 /* Performance Counters */
01555 
01556 struct arbelprm_performance_counters_st {       /* Little Endian */
01557     pseudo_bit_t        sqpc_access_cnt[0x00020];/* SQPC cache access count */
01558 /* -------------- */
01559     pseudo_bit_t        sqpc_miss_cnt[0x00020];/* SQPC cache miss count */
01560 /* -------------- */
01561     pseudo_bit_t        reserved0[0x00040];
01562 /* -------------- */
01563     pseudo_bit_t        rqpc_access_cnt[0x00020];/* RQPC cache access count */
01564 /* -------------- */
01565     pseudo_bit_t        rqpc_miss_cnt[0x00020];/* RQPC cache miss count */
01566 /* -------------- */
01567     pseudo_bit_t        reserved1[0x00040];
01568 /* -------------- */
01569     pseudo_bit_t        cqc_access_cnt[0x00020];/* CQC cache access count */
01570 /* -------------- */
01571     pseudo_bit_t        cqc_miss_cnt[0x00020]; /* CQC cache miss count */
01572 /* -------------- */
01573     pseudo_bit_t        reserved2[0x00040];
01574 /* -------------- */
01575     pseudo_bit_t        tpt_access_cnt[0x00020];/* TPT cache access count */
01576 /* -------------- */
01577     pseudo_bit_t        mpt_miss_cnt[0x00020]; /* MPT cache miss count */
01578 /* -------------- */
01579     pseudo_bit_t        mtt_miss_cnt[0x00020]; /* MTT cache miss count */
01580 /* -------------- */
01581     pseudo_bit_t        reserved3[0x00620];
01582 /* -------------- */
01583 }; 
01584 
01585 /* Transport and CI Error Counters */
01586 
01587 struct arbelprm_transport_and_ci_error_counters_st {    /* Little Endian */
01588     pseudo_bit_t        rq_num_lle[0x00020];   /* Responder - number of local length errors */
01589 /* -------------- */
01590     pseudo_bit_t        sq_num_lle[0x00020];   /* Requester - number of local length errors */
01591 /* -------------- */
01592     pseudo_bit_t        rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */
01593 /* -------------- */
01594     pseudo_bit_t        sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */
01595 /* -------------- */
01596     pseudo_bit_t        rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */
01597 /* -------------- */
01598     pseudo_bit_t        sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */
01599 /* -------------- */
01600     pseudo_bit_t        rq_num_lpe[0x00020];   /* Responder - number of local protection errors */
01601 /* -------------- */
01602     pseudo_bit_t        sq_num_lpe[0x00020];   /* Requester - number of local protection errors */
01603 /* -------------- */
01604     pseudo_bit_t        rq_num_wrfe[0x00020];  /* Responder - number of CQEs with error. 
01605                                                  Incremented each time a CQE with error is generated */
01606 /* -------------- */
01607     pseudo_bit_t        sq_num_wrfe[0x00020];  /* Requester - number of CQEs with error. 
01608                                                  Incremented each time a CQE with error is generated */
01609 /* -------------- */
01610     pseudo_bit_t        reserved0[0x00020];
01611 /* -------------- */
01612     pseudo_bit_t        sq_num_mwbe[0x00020];  /* Requester - number of memory window bind errors */
01613 /* -------------- */
01614     pseudo_bit_t        reserved1[0x00020];
01615 /* -------------- */
01616     pseudo_bit_t        sq_num_bre[0x00020];   /* Requester - number of bad response errors */
01617 /* -------------- */
01618     pseudo_bit_t        rq_num_lae[0x00020];   /* Responder - number of local access errors */
01619 /* -------------- */
01620     pseudo_bit_t        reserved2[0x00040];
01621 /* -------------- */
01622     pseudo_bit_t        sq_num_rire[0x00020];  /* Requester - number of remote invalid request errors
01623                                                  NAK-Invalid Request on:
01624                                                  1. Unsupported OpCode: Responder detected an unsupported OpCode.
01625                                                  2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such
01626                                                  as a missing "Last" packet.
01627                                                  Note: there is no PSN error, thus this does not indicate a dropped packet. */
01628 /* -------------- */
01629     pseudo_bit_t        rq_num_rire[0x00020];  /* Responder - number of remote invalid request errors.
01630                                                  NAK may or may not be sent.
01631                                                  1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only):
01632                                                  Inbound request OpCode was either reserved, or was for a function not supported by this
01633                                                  QP. (E.g. RDMA or ATOMIC on QP not set up for this).
01634                                                  2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion.
01635                                                  3. Too many RDMA READ or ATOMIC Requests: There were more requests received
01636                                                  and not ACKed than allowed for the connection.
01637                                                  4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder
01638                                                  detected an error in the sequence of OpCodes; a missing "Last" packet
01639                                                  5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder
01640                                                  detected an error in the sequence of OpCodes; a missing "First" packet
01641                                                  6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able
01642                                                  buffer space.
01643                                                  7. Length error: RDMA WRITE request message contained too much or too little pay-load
01644                                                  data compared to the DMA length advertised in the first or only packet.
01645                                                  8. Length error: Payload length was not consistent with the opcode:
01646                                                  a: 0 byte <= "only" <= PMTU bytes
01647                                                  b: ("first" or "middle") == PMTU bytes
01648                                                  c: 1byte <= "last" <= PMTU bytes
01649                                                  9. Length error: Inbound message exceeded the size supported by the CA port. */
01650 /* -------------- */
01651     pseudo_bit_t        sq_num_rae[0x00020];   /* Requester - number of remote access errors.
01652                                                  NAK-Remote Access Error on:
01653                                                  R_Key Violation: Responder detected an invalid R_Key while executing an RDMA
01654                                                  Request. */
01655 /* -------------- */
01656     pseudo_bit_t        rq_num_rae[0x00020];   /* Responder - number of remote access errors.
01657                                                  R_Key Violation Responder detected an R_Key violation while executing an RDMA
01658                                                  request.
01659                                                  NAK may or may not be sent. */
01660 /* -------------- */
01661     pseudo_bit_t        sq_num_roe[0x00020];   /* Requester - number of remote operation errors.
01662                                                  NAK-Remote Operation Error on:
01663                                                  Remote Operation Error: Responder encountered an error, (local to the responder),
01664                                                  which prevented it from completing the request. */
01665 /* -------------- */
01666     pseudo_bit_t        rq_num_roe[0x00020];   /* Responder - number of remote operation errors.
01667                                                  NAK-Remote Operation Error on:
01668                                                  1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing
01669                                                  the packet.
01670                                                  2. Remote Operation Error: Responder encountered an error, (local to the responder),
01671                                                  which prevented it from completing the request. */
01672 /* -------------- */
01673     pseudo_bit_t        sq_num_tree[0x00020];  /* Requester - number of transport retries exceeded errors */
01674 /* -------------- */
01675     pseudo_bit_t        reserved3[0x00020];
01676 /* -------------- */
01677     pseudo_bit_t        sq_num_rree[0x00020];  /* Requester - number of RNR nak retries exceeded errors */
01678 /* -------------- */
01679     pseudo_bit_t        reserved4[0x00020];
01680 /* -------------- */
01681     pseudo_bit_t        sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */
01682 /* -------------- */
01683     pseudo_bit_t        rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */
01684 /* -------------- */
01685     pseudo_bit_t        reserved5[0x00040];
01686 /* -------------- */
01687     pseudo_bit_t        sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */
01688 /* -------------- */
01689     pseudo_bit_t        reserved6[0x00020];
01690 /* -------------- */
01691     pseudo_bit_t        sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */
01692 /* -------------- */
01693     pseudo_bit_t        reserved7[0x00020];
01694 /* -------------- */
01695     pseudo_bit_t        sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */
01696 /* -------------- */
01697     pseudo_bit_t        reserved8[0x00380];
01698 /* -------------- */
01699     pseudo_bit_t        rq_num_oos[0x00020];   /* Responder - number of out of sequence requests received */
01700 /* -------------- */
01701     pseudo_bit_t        sq_num_oos[0x00020];   /* Requester - number of out of sequence Naks received */
01702 /* -------------- */
01703     pseudo_bit_t        rq_num_mce[0x00020];   /* Responder - number of bad multicast packets received */
01704 /* -------------- */
01705     pseudo_bit_t        reserved9[0x00020];
01706 /* -------------- */
01707     pseudo_bit_t        rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */
01708 /* -------------- */
01709     pseudo_bit_t        sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */
01710 /* -------------- */
01711     pseudo_bit_t        rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */
01712 /* -------------- */
01713     pseudo_bit_t        reserved10[0x00020];
01714 /* -------------- */
01715     pseudo_bit_t        rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */
01716 /* -------------- */
01717     pseudo_bit_t        reserved11[0x003e0];
01718 /* -------------- */
01719     pseudo_bit_t        num_cqovf[0x00020];    /* Number of CQ overflows */
01720 /* -------------- */
01721     pseudo_bit_t        num_eqovf[0x00020];    /* Number of EQ overflows */
01722 /* -------------- */
01723     pseudo_bit_t        num_baddb[0x00020];    /* Number of bad doorbells */
01724 /* -------------- */
01725     pseudo_bit_t        reserved12[0x002a0];
01726 /* -------------- */
01727 }; 
01728 
01729 /* Event_data Field - HCR Completion Event */
01730 
01731 struct arbelprm_hcr_completion_event_st {       /* Little Endian */
01732     pseudo_bit_t        token[0x00010];        /* HCR Token */
01733     pseudo_bit_t        reserved0[0x00010];
01734 /* -------------- */
01735     pseudo_bit_t        reserved1[0x00020];
01736 /* -------------- */
01737     pseudo_bit_t        status[0x00008];       /* HCR Status */
01738     pseudo_bit_t        reserved2[0x00018];
01739 /* -------------- */
01740     pseudo_bit_t        out_param_h[0x00020];  /* HCR Output Parameter [63:32] */
01741 /* -------------- */
01742     pseudo_bit_t        out_param_l[0x00020];  /* HCR Output Parameter [31:0] */
01743 /* -------------- */
01744     pseudo_bit_t        reserved3[0x00020];
01745 /* -------------- */
01746 }; 
01747 
01748 /* Completion with Error CQE */
01749 
01750 struct arbelprm_completion_with_error_st {      /* Little Endian */
01751     pseudo_bit_t        myqpn[0x00018];        /* Indicates the QP for which completion is being reported */
01752     pseudo_bit_t        reserved0[0x00008];
01753 /* -------------- */
01754     pseudo_bit_t        reserved1[0x00060];
01755 /* -------------- */
01756     pseudo_bit_t        reserved2[0x00010];
01757     pseudo_bit_t        vendor_code[0x00008];
01758     pseudo_bit_t        syndrome[0x00008];     /* Completion with error syndrome:
01759                                                          0x01 - Local Length Error
01760                                                          0x02 - Local QP Operation Error
01761                                                          0x03 - Local EE Context Operation Error
01762                                                          0x04 - Local Protection Error
01763                                                          0x05 - Work Request Flushed Error 
01764                                                          0x06 - Memory Window Bind Error
01765                                                          0x10 - Bad Response Error
01766                                                          0x11 - Local Access Error
01767                                                          0x12 - Remote Invalid Request Error
01768                                                          0x13 - Remote Access Error
01769                                                          0x14 - Remote Operation Error
01770                                                          0x15 - Transport Retry Counter Exceeded
01771                                                          0x16 - RNR Retry Counter Exceeded
01772                                                          0x20 - Local RDD Violation Error
01773                                                          0x21 - Remote Invalid RD Request
01774                                                          0x22 - Remote Aborted Error
01775                                                          0x23 - Invalid EE Context Number
01776                                                          0x24 - Invalid EE Context State
01777                                                          other - Reserved
01778                                                  Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
01779 /* -------------- */
01780     pseudo_bit_t        reserved3[0x00020];
01781 /* -------------- */
01782     pseudo_bit_t        reserved4[0x00006];
01783     pseudo_bit_t        wqe_addr[0x0001a];     /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
01784 /* -------------- */
01785     pseudo_bit_t        reserved5[0x00007];
01786     pseudo_bit_t        owner[0x00001];        /* Owner field. Zero value of this field means SW ownership of CQE. */
01787     pseudo_bit_t        reserved6[0x00010];
01788     pseudo_bit_t        opcode[0x00008];       /* The opcode of WQE completion is reported for.
01789                                                  
01790                                                  The following values are reported in case of completion with error:
01791                                                  0xFE - For completion with error on Receive Queues
01792                                                  0xFF - For completion with error on Send Queues */
01793 /* -------------- */
01794 }; 
01795 
01796 /* Resize CQ Input Mailbox */
01797 
01798 struct arbelprm_resize_cq_st {  /* Little Endian */
01799     pseudo_bit_t        reserved0[0x00020];
01800 /* -------------- */
01801     pseudo_bit_t        start_addr_h[0x00020]; /* Start address of CQ[63:32]. 
01802                                                  Must be aligned on CQE size (32 bytes) */
01803 /* -------------- */
01804     pseudo_bit_t        start_addr_l[0x00020]; /* Start address of CQ[31:0]. 
01805                                                  Must be aligned on CQE size (32 bytes) */
01806 /* -------------- */
01807     pseudo_bit_t        reserved1[0x00018];
01808     pseudo_bit_t        log_cq_size[0x00005];  /* Log (base 2) of the CQ size (in entries) */
01809     pseudo_bit_t        reserved2[0x00003];
01810 /* -------------- */
01811     pseudo_bit_t        reserved3[0x00060];
01812 /* -------------- */
01813     pseudo_bit_t        l_key[0x00020];        /* Memory key (L_Key) to be used to access CQ */
01814 /* -------------- */
01815     pseudo_bit_t        reserved4[0x00100];
01816 /* -------------- */
01817 }; 
01818 
01819 /* MAD_IFC Input Modifier */
01820 
01821 struct arbelprm_mad_ifc_input_modifier_st {     /* Little Endian */
01822     pseudo_bit_t        port_number[0x00008];  /* The packet reception port number (1 or 2). */
01823     pseudo_bit_t        mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
01824                                                  Required for trap generation when BKey check is enabled and for global routed packets. */
01825     pseudo_bit_t        reserved0[0x00007];
01826     pseudo_bit_t        rlid[0x00010];         /* Remote (source) LID  from the received MAD.
01827                                                  This field is required for trap generation upon MKey/BKey validation. */
01828 /* -------------- */
01829 }; 
01830 
01831 /* MAD_IFC Input Mailbox */
01832 
01833 struct arbelprm_mad_ifc_st {    /* Little Endian */
01834     pseudo_bit_t        request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
01835 /* -------------- */
01836     pseudo_bit_t        my_qpn[0x00018];       /* Destination QP number from the received MAD. 
01837                                                  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
01838     pseudo_bit_t        reserved0[0x00008];
01839 /* -------------- */
01840     pseudo_bit_t        rqpn[0x00018];         /* Remote (source) QP number  from the received MAD.
01841                                                  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
01842     pseudo_bit_t        reserved1[0x00008];
01843 /* -------------- */
01844     pseudo_bit_t        rlid[0x00010];         /* Remote (source) LID  from the received MAD.
01845                                                  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
01846     pseudo_bit_t        ml_path[0x00007];      /* My (destination) LID path bits  from the received MAD.
01847                                                  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
01848     pseudo_bit_t        g[0x00001];            /* If set, the GRH field in valid. 
01849                                                  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
01850     pseudo_bit_t        reserved2[0x00004];
01851     pseudo_bit_t        sl[0x00004];           /* Service Level of the received MAD.
01852                                                  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
01853 /* -------------- */
01854     pseudo_bit_t        pkey_indx[0x00010];    /* Index in PKey table that matches PKey of the received MAD. 
01855                                                  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
01856     pseudo_bit_t        reserved3[0x00010];
01857 /* -------------- */
01858     pseudo_bit_t        reserved4[0x00180];
01859 /* -------------- */
01860     pseudo_bit_t        grh[10][0x00020];      /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. 
01861                                                  Valid if Mad_extended_info bit (in the input modifier) and g bit are set. 
01862                                                  Otherwise this field is reserved. */
01863 /* -------------- */
01864     pseudo_bit_t        reserved5[0x004c0];
01865 /* -------------- */
01866 }; 
01867 
01868 /* Query Debug Message */
01869 
01870 struct arbelprm_query_debug_msg_st {    /* Little Endian */
01871     pseudo_bit_t        phy_addr_h[0x00020];   /* Translation of the address in firmware area. High 32 bits. */
01872 /* -------------- */
01873     pseudo_bit_t        v[0x00001];            /* Physical translation is valid */
01874     pseudo_bit_t        reserved0[0x0000b];
01875     pseudo_bit_t        phy_addr_l[0x00014];   /* Translation of the address in firmware area. Low 32 bits. */
01876 /* -------------- */
01877     pseudo_bit_t        fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
01878 /* -------------- */
01879     pseudo_bit_t        fw_area_size[0x00020]; /* Firmware area size */
01880 /* -------------- */
01881     pseudo_bit_t        trc_hdr_sz[0x00020];   /* Trace message header size in dwords. */
01882 /* -------------- */
01883     pseudo_bit_t        trc_arg_num[0x00020];  /* The number of arguments per trace message. */
01884 /* -------------- */
01885     pseudo_bit_t        reserved1[0x000c0];
01886 /* -------------- */
01887     pseudo_bit_t        dbg_msk_h[0x00020];    /* Debug messages mask [63:32] */
01888 /* -------------- */
01889     pseudo_bit_t        dbg_msk_l[0x00020];    /* Debug messages mask [31:0] */
01890 /* -------------- */
01891     pseudo_bit_t        reserved2[0x00040];
01892 /* -------------- */
01893     pseudo_bit_t        buff0_addr[0x00020];   /* Address in firmware area of Trace Buffer 0 */
01894 /* -------------- */
01895     pseudo_bit_t        buff0_size[0x00020];   /* Size of Trace Buffer 0 */
01896 /* -------------- */
01897     pseudo_bit_t        buff1_addr[0x00020];   /* Address in firmware area of Trace Buffer 1 */
01898 /* -------------- */
01899     pseudo_bit_t        buff1_size[0x00020];   /* Size of Trace Buffer 1 */
01900 /* -------------- */
01901     pseudo_bit_t        buff2_addr[0x00020];   /* Address in firmware area of Trace Buffer 2 */
01902 /* -------------- */
01903     pseudo_bit_t        buff2_size[0x00020];   /* Size of Trace Buffer 2 */
01904 /* -------------- */
01905     pseudo_bit_t        buff3_addr[0x00020];   /* Address in firmware area of Trace Buffer 3 */
01906 /* -------------- */
01907     pseudo_bit_t        buff3_size[0x00020];   /* Size of Trace Buffer 3 */
01908 /* -------------- */
01909     pseudo_bit_t        buff4_addr[0x00020];   /* Address in firmware area of Trace Buffer 4 */
01910 /* -------------- */
01911     pseudo_bit_t        buff4_size[0x00020];   /* Size of Trace Buffer 4 */
01912 /* -------------- */
01913     pseudo_bit_t        buff5_addr[0x00020];   /* Address in firmware area of Trace Buffer 5 */
01914 /* -------------- */
01915     pseudo_bit_t        buff5_size[0x00020];   /* Size of Trace Buffer 5 */
01916 /* -------------- */
01917     pseudo_bit_t        buff6_addr[0x00020];   /* Address in firmware area of Trace Buffer 6 */
01918 /* -------------- */
01919     pseudo_bit_t        buff6_size[0x00020];   /* Size of Trace Buffer 6 */
01920 /* -------------- */
01921     pseudo_bit_t        buff7_addr[0x00020];   /* Address in firmware area of Trace Buffer 7 */
01922 /* -------------- */
01923     pseudo_bit_t        buff7_size[0x00020];   /* Size of Trace Buffer 7 */
01924 /* -------------- */
01925     pseudo_bit_t        reserved3[0x00400];
01926 /* -------------- */
01927 }; 
01928 
01929 /* User Access Region */
01930 
01931 struct arbelprm_uar_st {        /* Little Endian */
01932     struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */
01933 /* -------------- */
01934     struct arbelprm_send_doorbell_st    send_doorbell;/* Send doorbell */
01935 /* -------------- */
01936     pseudo_bit_t        reserved0[0x00040];
01937 /* -------------- */
01938     struct arbelprm_cq_cmd_doorbell_st  cq_command_doorbell;/* CQ Doorbell */
01939 /* -------------- */
01940     pseudo_bit_t        reserved1[0x03ec0];
01941 /* -------------- */
01942 }; 
01943 
01944 /* Receive doorbell */
01945 
01946 struct arbelprm_receive_doorbell_st {   /* Little Endian */
01947     pseudo_bit_t        reserved0[0x00008];
01948     pseudo_bit_t        wqe_counter[0x00010];  /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
01949     pseudo_bit_t        reserved1[0x00008];
01950 /* -------------- */
01951     pseudo_bit_t        reserved2[0x00005];
01952     pseudo_bit_t        srq[0x00001];          /* If set, this is a Shared Receive Queue */
01953     pseudo_bit_t        reserved3[0x00002];
01954     pseudo_bit_t        qpn[0x00018];          /* QP number or SRQ number this doorbell is rung on */
01955 /* -------------- */
01956 }; 
01957 
01958 /* SET_IB Parameters */
01959 
01960 struct arbelprm_set_ib_st {     /* Little Endian */
01961     pseudo_bit_t        rqk[0x00001];          /* Reset QKey Violation Counter */
01962     pseudo_bit_t        reserved0[0x00011];
01963     pseudo_bit_t        sig[0x00001];          /* Set System Image GUID to system_image_guid specified.
01964                                                  system_image_guid and sig must be the same for all ports. */
01965     pseudo_bit_t        reserved1[0x0000d];
01966 /* -------------- */
01967     pseudo_bit_t        capability_mask[0x00020];/* PortInfo Capability Mask */
01968 /* -------------- */
01969     pseudo_bit_t        system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
01970                                                  Must be the same for both ports. */
01971 /* -------------- */
01972     pseudo_bit_t        system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
01973                                                  Must be the same for both ports. */
01974 /* -------------- */
01975     pseudo_bit_t        reserved2[0x00180];
01976 /* -------------- */
01977 }; 
01978 
01979 /* Multicast Group Member */
01980 
01981 struct arbelprm_mgm_entry_st {  /* Little Endian */
01982     pseudo_bit_t        reserved0[0x00006];
01983     pseudo_bit_t        next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
01984                                                  The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
01985                                                  next_gid_index=0 means end of the chain. */
01986 /* -------------- */
01987     pseudo_bit_t        reserved1[0x00060];
01988 /* -------------- */
01989     pseudo_bit_t        mgid_128_96[0x00020];  /* Multicast group GID[128:96] in big endian format.
01990                                                  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
01991 /* -------------- */
01992     pseudo_bit_t        mgid_95_64[0x00020];   /* Multicast group GID[95:64] in big endian format.
01993                                                  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
01994 /* -------------- */
01995     pseudo_bit_t        mgid_63_32[0x00020];   /* Multicast group GID[63:32] in big endian format.
01996                                                  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
01997 /* -------------- */
01998     pseudo_bit_t        mgid_31_0[0x00020];    /* Multicast group GID[31:0] in big endian format.
01999                                                  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
02000 /* -------------- */
02001     struct arbelprm_mgmqp_st    mgmqp_0;   /* Multicast Group Member QP */
02002 /* -------------- */
02003     struct arbelprm_mgmqp_st    mgmqp_1;   /* Multicast Group Member QP */
02004 /* -------------- */
02005     struct arbelprm_mgmqp_st    mgmqp_2;   /* Multicast Group Member QP */
02006 /* -------------- */
02007     struct arbelprm_mgmqp_st    mgmqp_3;   /* Multicast Group Member QP */
02008 /* -------------- */
02009     struct arbelprm_mgmqp_st    mgmqp_4;   /* Multicast Group Member QP */
02010 /* -------------- */
02011     struct arbelprm_mgmqp_st    mgmqp_5;   /* Multicast Group Member QP */
02012 /* -------------- */
02013     struct arbelprm_mgmqp_st    mgmqp_6;   /* Multicast Group Member QP */
02014 /* -------------- */
02015     struct arbelprm_mgmqp_st    mgmqp_7;   /* Multicast Group Member QP */
02016 /* -------------- */
02017 }; 
02018 
02019 /* INIT_IB Parameters */
02020 
02021 struct arbelprm_init_ib_st {    /* Little Endian */
02022     pseudo_bit_t        reserved0[0x00004];
02023     pseudo_bit_t        vl_cap[0x00004];       /* Maximum VLs supported on the port, excluding VL15.
02024                                                  Legal values are 1,2,4 and 8. */
02025     pseudo_bit_t        port_width_cap[0x00004];/* IB Port Width
02026                                                  1   - 1x
02027                                                  3   - 1x, 4x
02028                                                  11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208)
02029                                                  else - Reserved */
02030     pseudo_bit_t        mtu_cap[0x00004];      /* Maximum MTU Supported
02031                                                  0x0 - Reserved
02032                                                  0x1 - 256
02033                                                  0x2 - 512
02034                                                  0x3 - 1024
02035                                                  0x4 - 2048
02036                                                  0x5 - 0xF Reserved */
02037     pseudo_bit_t        g0[0x00001];           /* Set port GUID0 to GUID0 specified */
02038     pseudo_bit_t        ng[0x00001];           /* Set node GUID to node_guid specified.
02039                                                  node_guid and ng must be the same for all ports. */
02040     pseudo_bit_t        sig[0x00001];          /* Set System Image GUID to system_image_guid specified.
02041                                                  system_image_guid and sig must be the same for all ports. */
02042     pseudo_bit_t        reserved1[0x0000d];
02043 /* -------------- */
02044     pseudo_bit_t        max_gid[0x00010];      /* Maximum number of GIDs for the port */
02045     pseudo_bit_t        reserved2[0x00010];
02046 /* -------------- */
02047     pseudo_bit_t        max_pkey[0x00010];     /* Maximum pkeys for the port.
02048                                                  Must be the same for both ports. */
02049     pseudo_bit_t        reserved3[0x00010];
02050 /* -------------- */
02051     pseudo_bit_t        reserved4[0x00020];
02052 /* -------------- */
02053     pseudo_bit_t        guid0_h[0x00020];      /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
02054 /* -------------- */
02055     pseudo_bit_t        guid0_l[0x00020];      /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
02056 /* -------------- */
02057     pseudo_bit_t        node_guid_h[0x00020];  /* Node GUID[63:32], takes effect only if the NG bit is set
02058                                                  Must be the same for both ports. */
02059 /* -------------- */
02060     pseudo_bit_t        node_guid_l[0x00020];  /* Node GUID[31:0], takes effect only if the NG bit is set
02061                                                  Must be the same for both ports. */
02062 /* -------------- */
02063     pseudo_bit_t        system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
02064                                                  Must be the same for both ports. */
02065 /* -------------- */
02066     pseudo_bit_t        system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
02067                                                  Must be the same for both ports. */
02068 /* -------------- */
02069     pseudo_bit_t        reserved5[0x006c0];
02070 /* -------------- */
02071 }; 
02072 
02073 /* Query Device Limitations */
02074 
02075 struct arbelprm_query_dev_lim_st {      /* Little Endian */
02076     pseudo_bit_t        reserved0[0x00080];
02077 /* -------------- */
02078     pseudo_bit_t        log_max_qp[0x00005];   /* Log2 of the Maximum number of QPs supported */
02079     pseudo_bit_t        reserved1[0x00003];
02080     pseudo_bit_t        log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
02081                                                  The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
02082     pseudo_bit_t        reserved2[0x00004];
02083     pseudo_bit_t        log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
02084     pseudo_bit_t        log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
02085 /* -------------- */
02086     pseudo_bit_t        log_max_ee[0x00005];   /* Log2 of the Maximum number of EE contexts supported */
02087     pseudo_bit_t        reserved3[0x00003];
02088     pseudo_bit_t        log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use
02089                                                  The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */
02090     pseudo_bit_t        reserved4[0x00004];
02091     pseudo_bit_t        log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.
02092                                                   */
02093     pseudo_bit_t        reserved5[0x00007];
02094     pseudo_bit_t        log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use
02095                                                  The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1
02096                                                  This parameter is valid only if the SRQ bit is set. */
02097 /* -------------- */
02098     pseudo_bit_t        log_max_cq[0x00005];   /* Log2 of the Maximum number of CQs supported */
02099     pseudo_bit_t        reserved6[0x00003];
02100     pseudo_bit_t        log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
02101                                                  The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
02102     pseudo_bit_t        reserved7[0x00004];
02103     pseudo_bit_t        log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
02104     pseudo_bit_t        reserved8[0x00008];
02105 /* -------------- */
02106     pseudo_bit_t        log_max_eq[0x00003];   /* Log2 of the Maximum number of EQs */
02107     pseudo_bit_t        reserved9[0x00005];
02108     pseudo_bit_t        num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
02109                                                  The reserved resources are numbered from 0 to num_rsvd_eqs-1
02110                                                  If 0 - no resources are reserved. */
02111     pseudo_bit_t        reserved10[0x00004];
02112     pseudo_bit_t        log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */
02113     pseudo_bit_t        reserved11[0x00002];
02114     pseudo_bit_t        log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
02115 /* -------------- */
02116     pseudo_bit_t        log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */
02117     pseudo_bit_t        reserved12[0x00002];
02118     pseudo_bit_t        log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
02119                                                  The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
02120     pseudo_bit_t        reserved13[0x00004];
02121     pseudo_bit_t        log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */
02122     pseudo_bit_t        reserved14[0x00004];
02123     pseudo_bit_t        log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
02124                                                  The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
02125                                                   */
02126 /* -------------- */
02127     pseudo_bit_t        reserved15[0x00020];
02128 /* -------------- */
02129     pseudo_bit_t        log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
02130     pseudo_bit_t        reserved16[0x0000a];
02131     pseudo_bit_t        log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
02132     pseudo_bit_t        reserved17[0x0000a];
02133 /* -------------- */
02134     pseudo_bit_t        log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
02135     pseudo_bit_t        reserved18[0x00016];
02136     pseudo_bit_t        log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use
02137                                                  The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */
02138 /* -------------- */
02139     pseudo_bit_t        rsz_srq[0x00001];      /* Ability to modify the maximum number of WRs per SRQ. */
02140     pseudo_bit_t        reserved19[0x0001f];
02141 /* -------------- */
02142     pseudo_bit_t        num_ports[0x00004];    /* Number of IB ports. */
02143     pseudo_bit_t        max_vl[0x00004];       /* Maximum VLs supported on each port, excluding VL15 */
02144     pseudo_bit_t        max_port_width[0x00004];/* IB Port Width
02145                                                  1   - 1x
02146                                                  3   - 1x, 4x
02147                                                  11 - 1x, 4x or 12x
02148                                                  else - Reserved */
02149     pseudo_bit_t        max_mtu[0x00004];      /* Maximum MTU Supported
02150                                                  0x0 - Reserved
02151                                                  0x1 - 256
02152                                                  0x2 - 512
02153                                                  0x3 - 1024
02154                                                  0x4 - 2048
02155                                                  0x5 - 0xF Reserved */
02156     pseudo_bit_t        local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
02157                                                  The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
02158     pseudo_bit_t        reserved20[0x0000b];
02159 /* -------------- */
02160     pseudo_bit_t        log_max_gid[0x00004];  /* Log2 of the maximum number of GIDs per port */
02161     pseudo_bit_t        reserved21[0x0001c];
02162 /* -------------- */
02163     pseudo_bit_t        log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
02164     pseudo_bit_t        reserved22[0x0000c];
02165     pseudo_bit_t        stat_rate_support[0x00010];/* bit mask of stat rate supported
02166                                                  bit 0 - full bw
02167                                                  bit 1 - 1/4 bw
02168                                                  bit 2 - 1/8 bw
02169                                                  bit 3 - 1/2 bw; */
02170 /* -------------- */
02171     pseudo_bit_t        reserved23[0x00020];
02172 /* -------------- */
02173     pseudo_bit_t        rc[0x00001];           /* RC Transport supported */
02174     pseudo_bit_t        uc[0x00001];           /* UC Transport Supported */
02175     pseudo_bit_t        ud[0x00001];           /* UD Transport Supported */
02176     pseudo_bit_t        rd[0x00001];           /* RD Transport Supported */
02177     pseudo_bit_t        raw_ipv6[0x00001];     /* Raw IPv6 Transport Supported */
02178     pseudo_bit_t        raw_ether[0x00001];    /* Raw Ethertype Transport Supported */
02179     pseudo_bit_t        srq[0x00001];          /* SRQ is supported
02180                                                   */
02181     pseudo_bit_t        ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */
02182     pseudo_bit_t        pkv[0x00001];          /* PKey Violation Counter Supported */
02183     pseudo_bit_t        qkv[0x00001];          /* QKey Violation Coutner Supported */
02184     pseudo_bit_t        reserved24[0x00006];
02185     pseudo_bit_t        mw[0x00001];           /* Memory windows supported */
02186     pseudo_bit_t        apm[0x00001];          /* Automatic Path Migration Supported */
02187     pseudo_bit_t        atm[0x00001];          /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
02188     pseudo_bit_t        rm[0x00001];           /* Raw Multicast Supported */
02189     pseudo_bit_t        avp[0x00001];          /* Address Vector Port checking supported */
02190     pseudo_bit_t        udm[0x00001];          /* UD Multicast Supported */
02191     pseudo_bit_t        reserved25[0x00002];
02192     pseudo_bit_t        pg[0x00001];           /* Paging on demand supported */
02193     pseudo_bit_t        r[0x00001];            /* Router mode supported */
02194     pseudo_bit_t        reserved26[0x00006];
02195 /* -------------- */
02196     pseudo_bit_t        log_pg_sz[0x00008];    /* Minimum system page size supported (log2).
02197                                                  For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
02198     pseudo_bit_t        reserved27[0x00008];
02199     pseudo_bit_t        uar_sz[0x00006];       /* UAR Area Size = 1MB * 2^uar_sz */
02200     pseudo_bit_t        reserved28[0x00006];
02201     pseudo_bit_t        num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
02202                                                  The reserved resources are numbered from 0 to num_reserved_uars-1
02203                                                  Note that UAR number num_reserved_uars is always for the kernel. */
02204 /* -------------- */
02205     pseudo_bit_t        reserved29[0x00020];
02206 /* -------------- */
02207     pseudo_bit_t        max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
02208     pseudo_bit_t        max_sg_sq[0x00008];    /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
02209     pseudo_bit_t        reserved30[0x00008];
02210 /* -------------- */
02211     pseudo_bit_t        max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
02212     pseudo_bit_t        max_sg_rq[0x00008];    /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
02213     pseudo_bit_t        reserved31[0x00008];
02214 /* -------------- */
02215     pseudo_bit_t        reserved32[0x00040];
02216 /* -------------- */
02217     pseudo_bit_t        log_max_mcg[0x00008];  /* Log2 of the maximum number of multicast groups */
02218     pseudo_bit_t        num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
02219                                                  The reserved resources are numbered from 0 to num_reserved_mcgs-1
02220                                                  If 0 - no resources are reserved. */
02221     pseudo_bit_t        reserved33[0x00004];
02222     pseudo_bit_t        log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
02223     pseudo_bit_t        reserved34[0x00008];
02224 /* -------------- */
02225     pseudo_bit_t        log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */
02226     pseudo_bit_t        reserved35[0x00006];
02227     pseudo_bit_t        num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use
02228                                                  The reserved resources are numbered from 0 to num_reserved_rdds-1.
02229                                                  If 0 - no resources are reserved. */
02230     pseudo_bit_t        log_max_pd[0x00006];   /* Log2 of the maximum number of PDs */
02231     pseudo_bit_t        reserved36[0x00006];
02232     pseudo_bit_t        num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
02233                                                  The reserved resources are numbered from 0 to num_reserved_pds-1
02234                                                  If 0 - no resources are reserved. */
02235 /* -------------- */
02236     pseudo_bit_t        reserved37[0x000c0];
02237 /* -------------- */
02238     pseudo_bit_t        qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
02239                                                  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
02240     pseudo_bit_t        eec_entry_sz[0x00010]; /* EEC Entry Size for the device
02241                                                  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
02242 /* -------------- */
02243     pseudo_bit_t        eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device
02244                                                  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
02245     pseudo_bit_t        eeec_entry_sz[0x00010];/* Extended EEC entry size for the device
02246                                                  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
02247 /* -------------- */
02248     pseudo_bit_t        cqc_entry_sz[0x00010]; /* CQC entry size for the device
02249                                                  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
02250     pseudo_bit_t        eqc_entry_sz[0x00010]; /* EQ context entry size for the device
02251                                                  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
02252 /* -------------- */
02253     pseudo_bit_t        uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size
02254                                                  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
02255     pseudo_bit_t        srq_entry_sz[0x00010]; /* SRQ context entry size for the device
02256                                                  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
02257 /* -------------- */
02258     pseudo_bit_t        mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device.
02259                                                  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
02260     pseudo_bit_t        mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device.
02261                                                  For the InfiniHost-III-EX MT25208 entry size is 8 bytes */
02262 /* -------------- */
02263     pseudo_bit_t        bmme[0x00001];         /* Base Memory Management Extension Support */
02264     pseudo_bit_t        win_type[0x00001];     /* Bound Type 2 Memory Window Association mechanism:
02265                                                  0 - Type 2A - QP Number Association; or
02266                                                  1 - Type 2B - QP Number and PD Association. */
02267     pseudo_bit_t        mps[0x00001];          /* Ability of this HCA to support multiple page sizes per Memory Region. */
02268     pseudo_bit_t        bl[0x00001];           /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */
02269     pseudo_bit_t        zb[0x00001];           /* Zero Based region/windows supported */
02270     pseudo_bit_t        lif[0x00001];          /* Ability of this HCA to support Local Invalidate Fencing. */
02271     pseudo_bit_t        reserved38[0x00002];
02272     pseudo_bit_t        log_pbl_sz[0x00006];   /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb.
02273                                                   */
02274     pseudo_bit_t        reserved39[0x00012];
02275 /* -------------- */
02276     pseudo_bit_t        resd_lkey[0x00020];    /* The value of the reserved Lkey for Base Memory Management Extension */
02277 /* -------------- */
02278     pseudo_bit_t        lamr[0x00001];         /* When set the device requires local attached memory in order to operate.
02279                                                  When set,  ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */
02280     pseudo_bit_t        reserved40[0x0001f];
02281 /* -------------- */
02282     pseudo_bit_t        max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
02283 /* -------------- */
02284     pseudo_bit_t        max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
02285 /* -------------- */
02286     pseudo_bit_t        reserved41[0x002c0];
02287 /* -------------- */
02288 }; 
02289 
02290 /* QUERY_ADAPTER Parameters Block */
02291 
02292 struct arbelprm_query_adapter_st {      /* Little Endian */
02293     pseudo_bit_t        reserved0[0x00080];
02294 /* -------------- */
02295     pseudo_bit_t        reserved1[0x00018];
02296     pseudo_bit_t        intapin[0x00008];      /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
02297 /* -------------- */
02298     pseudo_bit_t        reserved2[0x00060];
02299 /* -------------- */
02300     struct arbelprm_vsd_st      vsd;
02301 /* -------------- */
02302 }; 
02303 
02304 /* QUERY_FW Parameters Block */
02305 
02306 struct arbelprm_query_fw_st {   /* Little Endian */
02307     pseudo_bit_t        fw_rev_major[0x00010]; /* Firmware Revision - Major */
02308     pseudo_bit_t        fw_pages[0x00010];     /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
02309 /* -------------- */
02310     pseudo_bit_t        fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
02311     pseudo_bit_t        fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
02312 /* -------------- */
02313     pseudo_bit_t        cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
02314     pseudo_bit_t        reserved0[0x0000e];
02315     pseudo_bit_t        wqe_h_mode[0x00001];   /* Hermon mode. If '1', then WQE and AV format is the advanced format */
02316     pseudo_bit_t        zb_wq_cq[0x00001];     /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */
02317 /* -------------- */
02318     pseudo_bit_t        log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
02319     pseudo_bit_t        reserved1[0x00017];
02320     pseudo_bit_t        dt[0x00001];           /* Debug Trace Support
02321                                                  0 - Debug trace is not supported 
02322                                                  1 - Debug trace is supported */
02323 /* -------------- */
02324     pseudo_bit_t        cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */
02325     pseudo_bit_t        reserved2[0x0001f];
02326 /* -------------- */
02327     pseudo_bit_t        reserved3[0x00060];
02328 /* -------------- */
02329     pseudo_bit_t        clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address. 
02330                                                  Points to 64 bit register. */
02331 /* -------------- */
02332     pseudo_bit_t        clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address. 
02333                                                  Points to 64 bit register. */
02334 /* -------------- */
02335     pseudo_bit_t        reserved4[0x00040];
02336 /* -------------- */
02337     pseudo_bit_t        error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
02338 /* -------------- */
02339     pseudo_bit_t        error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
02340 /* -------------- */
02341     pseudo_bit_t        error_buf_size[0x00020];/* Size in words */
02342 /* -------------- */
02343     pseudo_bit_t        reserved5[0x00020];
02344 /* -------------- */
02345     pseudo_bit_t        eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address. 
02346                                                  Points to 64 bit register.
02347                                                  Setting bit x in the offset, arms EQ number x.
02348                                                   */
02349 /* -------------- */
02350     pseudo_bit_t        eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address. 
02351                                                  Points to 64 bit register.
02352                                                  Setting bit x in the offset, arms EQ number x. */
02353 /* -------------- */
02354     pseudo_bit_t        eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address.
02355                                                  Points to a the EQ Set CI DBs Table base address. */
02356 /* -------------- */
02357     pseudo_bit_t        eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address.
02358                                                  Points to a the EQ Set CI DBs Table base address. */
02359 /* -------------- */
02360     pseudo_bit_t        cmd_db_dw1[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02361     pseudo_bit_t        cmd_db_dw0[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02362 /* -------------- */
02363     pseudo_bit_t        cmd_db_dw3[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02364     pseudo_bit_t        cmd_db_dw2[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02365 /* -------------- */
02366     pseudo_bit_t        cmd_db_dw5[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02367     pseudo_bit_t        cmd_db_dw4[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02368 /* -------------- */
02369     pseudo_bit_t        cmd_db_dw7[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02370     pseudo_bit_t        cmd_db_dw6[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
02371 /* -------------- */
02372     pseudo_bit_t        cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
02373 /* -------------- */
02374     pseudo_bit_t        cmd_db_addr_base_l[0x00020];/* Low  bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
02375 /* -------------- */
02376     pseudo_bit_t        reserved6[0x004c0];
02377 /* -------------- */
02378 }; 
02379 
02380 /* ACCESS_LAM */
02381 
02382 struct arbelprm_access_lam_st { /* Little Endian */
02383     struct arbelprm_access_lam_inject_errors_st access_lam_inject_errors;
02384 /* -------------- */
02385     pseudo_bit_t        reserved0[0x00080];
02386 /* -------------- */
02387 }; 
02388 
02389 /* ENABLE_LAM Parameters Block */
02390 
02391 struct arbelprm_enable_lam_st { /* Little Endian */
02392     pseudo_bit_t        lam_start_adr_h[0x00020];/* LAM start address [63:32] */
02393 /* -------------- */
02394     pseudo_bit_t        lam_start_adr_l[0x00020];/* LAM start address [31:0] */
02395 /* -------------- */
02396     pseudo_bit_t        lam_end_adr_h[0x00020];/* LAM end address [63:32] */
02397 /* -------------- */
02398     pseudo_bit_t        lam_end_adr_l[0x00020];/* LAM end address [31:0] */
02399 /* -------------- */
02400     pseudo_bit_t        di[0x00002];           /* Data Integrity Configuration:
02401                                                  00 - none
02402                                                  01 - Parity
02403                                                  10 - ECC Detection Only
02404                                                  11 - ECC With Correction */
02405     pseudo_bit_t        ap[0x00002];           /* Auto Precharge Mode
02406                                                  00 - No auto precharge
02407                                                  01 - Auto precharge per transaction
02408                                                  10 - Auto precharge per 64 bytes
02409                                                  11 - reserved */
02410     pseudo_bit_t        dh[0x00001];           /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */
02411     pseudo_bit_t        reserved0[0x0001b];
02412 /* -------------- */
02413     pseudo_bit_t        reserved1[0x00160];
02414 /* -------------- */
02415     struct arbelprm_dimminfo_st dimm0;  /* Logical DIMM 0 Parameters */
02416 /* -------------- */
02417     struct arbelprm_dimminfo_st dimm1;  /* Logical DIMM 1 Parameters */
02418 /* -------------- */
02419     pseudo_bit_t        reserved2[0x00400];
02420 /* -------------- */
02421 }; 
02422 
02423 /* Memory Access Parameters for UD Address Vector Table */
02424 
02425 struct arbelprm_udavtable_memory_parameters_st {        /* Little Endian */
02426     pseudo_bit_t        l_key[0x00020];        /* L_Key used to access TPT */
02427 /* -------------- */
02428     pseudo_bit_t        pd[0x00018];           /* PD used by TPT for matching against PD of region entry being accessed. */
02429     pseudo_bit_t        reserved0[0x00005];
02430     pseudo_bit_t        xlation_en[0x00001];   /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
02431     pseudo_bit_t        reserved1[0x00002];
02432 /* -------------- */
02433 }; 
02434 
02435 /* INIT_HCA & QUERY_HCA Parameters Block */
02436 
02437 struct arbelprm_init_hca_st {   /* Little Endian */
02438     pseudo_bit_t        reserved0[0x00060];
02439 /* -------------- */
02440     pseudo_bit_t        reserved1[0x00010];
02441     pseudo_bit_t        time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented.
02442                                                  The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond)
02443                                                  When sets to Zero, timestamp reporting in the CQE is disabled.
02444                                                  This feature is currently not supported.
02445                                                   */
02446     pseudo_bit_t        hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */
02447 /* -------------- */
02448     pseudo_bit_t        reserved2[0x00008];
02449     pseudo_bit_t        router_qp[0x00010];    /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.
02450                                                  Valid only if RE bit is set */
02451     pseudo_bit_t        reserved3[0x00007];
02452     pseudo_bit_t        re[0x00001];           /* Router Mode Enable
02453                                                  If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */
02454 /* -------------- */
02455     pseudo_bit_t        udp[0x00001];          /* UD Port Check Enable
02456                                                  0 - Port field in Address Vector is ignored
02457                                                  1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
02458     pseudo_bit_t        he[0x00001];           /* Host Endianess - Used for Atomic Operations
02459                                                  0 - Host is Little Endian
02460                                                  1 - Host is Big endian
02461                                                   */
02462     pseudo_bit_t        reserved4[0x00001];
02463     pseudo_bit_t        ce[0x00001];           /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
02464     pseudo_bit_t        sph[0x00001];          /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet
02465                                                  1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet
02466                                                   */
02467     pseudo_bit_t        rph[0x00001];          /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet
02468                                                  1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet
02469                                                   */
02470     pseudo_bit_t        reserved5[0x00002];
02471     pseudo_bit_t        responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester .
02472                                                  responder_exu/16 = (number of responder exu engines)/(total number of engines)
02473                                                  Legal values are 0x0-0xF. 0 is "auto".
02474                                                  
02475                                                   */
02476     pseudo_bit_t        reserved6[0x00004];
02477     pseudo_bit_t        wqe_quota[0x0000f];    /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */
02478     pseudo_bit_t        wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */
02479 /* -------------- */
02480     pseudo_bit_t        reserved7[0x00040];
02481 /* -------------- */
02482     struct arbelprm_qpcbaseaddr_st      qpc_eec_cqc_eqc_rdb_parameters;
02483 /* -------------- */
02484     pseudo_bit_t        reserved8[0x00100];
02485 /* -------------- */
02486     struct arbelprm_multicastparam_st   multicast_parameters;
02487 /* -------------- */
02488     pseudo_bit_t        reserved9[0x00080];
02489 /* -------------- */
02490     struct arbelprm_tptparams_st        tpt_parameters;
02491 /* -------------- */
02492     pseudo_bit_t        reserved10[0x00080];
02493 /* -------------- */
02494     struct arbelprm_uar_params_st       uar_parameters;/* UAR Parameters */
02495 /* -------------- */
02496     pseudo_bit_t        reserved11[0x00600];
02497 /* -------------- */
02498 }; 
02499 
02500 /* Event Queue Context Table Entry */
02501 
02502 struct arbelprm_eqc_st {        /* Little Endian */
02503     pseudo_bit_t        reserved0[0x00008];
02504     pseudo_bit_t        st[0x00004];           /* Event delivery state machine
02505                                                  0x9 - Armed
02506                                                  0xA - Fired
02507                                                  0xB - Always_Armed (auto-rearm)
02508                                                  other - reserved */
02509     pseudo_bit_t        reserved1[0x00005];
02510     pseudo_bit_t        oi[0x00001];           /* Oerrun ignore.
02511                                                  If set, HW will not check EQ full condition when writing new EQEs. */
02512     pseudo_bit_t        tr[0x00001];           /* Translation Required. If set - EQ access undergo address translation. */
02513     pseudo_bit_t        reserved2[0x00005];
02514     pseudo_bit_t        owner[0x00004];        /* 0 - SW ownership
02515                                                  1 - HW ownership
02516                                                  Valid for the QUERY_EQ and HW2SW_EQ commands only */
02517     pseudo_bit_t        status[0x00004];       /* EQ status:
02518                                                  0000 - OK
02519                                                  1010 - EQ write failure
02520                                                  Valid for the QUERY_EQ and HW2SW_EQ commands only */
02521 /* -------------- */
02522     pseudo_bit_t        start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */
02523 /* -------------- */
02524     pseudo_bit_t        start_address_l[0x00020];/* Start Address of Event Queue[31:0]. 
02525                                                  Must be aligned on 32-byte boundary */
02526 /* -------------- */
02527     pseudo_bit_t        reserved3[0x00018];
02528     pseudo_bit_t        log_eq_size[0x00005];  /* Amount of entries in this EQ is 2^log_eq_size.
02529                                                  Log_eq_size must be bigger than 1.
02530                                                  Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */
02531     pseudo_bit_t        reserved4[0x00003];
02532 /* -------------- */
02533     pseudo_bit_t        reserved5[0x00020];
02534 /* -------------- */
02535     pseudo_bit_t        intr[0x00008];         /* Interrupt (message) to be generated to report event to INT layer.
02536                                                  00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express.
02537                                                  10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).
02538                                                  All other values are reserved and should not be used.
02539                                                  
02540                                                  If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */
02541     pseudo_bit_t        reserved6[0x00018];
02542 /* -------------- */
02543     pseudo_bit_t        pd[0x00018];           /* PD to be used to access EQ */
02544     pseudo_bit_t        reserved7[0x00008];
02545 /* -------------- */
02546     pseudo_bit_t        lkey[0x00020];         /* Memory key (L-Key) to be used to access EQ */
02547 /* -------------- */
02548     pseudo_bit_t        reserved8[0x00040];
02549 /* -------------- */
02550     pseudo_bit_t        consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.
02551                                                  Must be initalized to zero while opening EQ */
02552 /* -------------- */
02553     pseudo_bit_t        producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.
02554                                                  Must be initalized to zero while opening EQ. */
02555 /* -------------- */
02556     pseudo_bit_t        reserved9[0x00080];
02557 /* -------------- */
02558 }; 
02559 
02560 /* Memory Translation Table (MTT) Entry */
02561 
02562 struct arbelprm_mtt_st {        /* Little Endian */
02563     pseudo_bit_t        ptag_h[0x00020];       /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
02564 /* -------------- */
02565     pseudo_bit_t        p[0x00001];            /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
02566     pseudo_bit_t        reserved0[0x0000b];
02567     pseudo_bit_t        ptag_l[0x00014];       /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
02568 /* -------------- */
02569 }; 
02570 
02571 /* Memory Protection Table (MPT) Entry */
02572 
02573 struct arbelprm_mpt_st {        /* Little Endian */
02574     pseudo_bit_t        reserved0[0x00008];
02575     pseudo_bit_t        r_w[0x00001];          /* Defines whether this entry is Region (1) or Window (0) */
02576     pseudo_bit_t        pa[0x00001];           /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */
02577     pseudo_bit_t        lr[0x00001];           /* If set - local read access enabled */
02578     pseudo_bit_t        lw[0x00001];           /* If set - local write access enabled */
02579     pseudo_bit_t        rr[0x00001];           /* If set - remote read access enabled. */
02580     pseudo_bit_t        rw[0x00001];           /* If set - remote write access enabled */
02581     pseudo_bit_t        a[0x00001];            /* If set - remote Atomic access is enabled */
02582     pseudo_bit_t        eb[0x00001];           /* If set - Bind is enabled. Valid for region entry only. */
02583     pseudo_bit_t        reserved1[0x0000c];
02584     pseudo_bit_t        status[0x00004];       /* Region/Window Status
02585                                                  0xF - not valid (SW ownership)
02586                                                  0x3 - FREE state
02587                                                  else - HW ownership
02588                                                  Unbound Type I windows are doneted reg_wnd_len field equals zero.
02589                                                  Unbound Type II windows are donated by Status=FREE. */
02590 /* -------------- */
02591     pseudo_bit_t        page_size[0x00005];    /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
02592                                                  page_size should be less than 20. */
02593     pseudo_bit_t        reserved2[0x00002];
02594     pseudo_bit_t        type[0x00001];         /* Applicable for windows only, must be zero for regions
02595                                                  0 - Type one window
02596                                                  1 - Type two window */
02597     pseudo_bit_t        qpn[0x00018];          /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
02598 /* -------------- */
02599     pseudo_bit_t        mem_key[0x00020];      /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}.
02600                                                   */
02601 /* -------------- */
02602     pseudo_bit_t        pd[0x00018];           /* Protection Domain */
02603     pseudo_bit_t        reserved3[0x00001];
02604     pseudo_bit_t        ei[0x00001];           /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. 
02605                                                  Must be set for type2 windows and non-shared physical memory regions.
02606                                                  Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
02607     pseudo_bit_t        zb[0x00001];           /* When set, this region is Zero Based Region */
02608     pseudo_bit_t        fre[0x00001];          /* When set, Fast Registration Operations can be executed on this region */
02609     pseudo_bit_t        rae[0x00001];          /* When set, remote access can be enabled on this region.
02610                                                  Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. 
02611                                                  If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail.
02612                                                   */
02613     pseudo_bit_t        reserved4[0x00003];
02614 /* -------------- */
02615     pseudo_bit_t        start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */
02616 /* -------------- */
02617     pseudo_bit_t        start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */
02618 /* -------------- */
02619     pseudo_bit_t        reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */
02620 /* -------------- */
02621     pseudo_bit_t        reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */
02622 /* -------------- */
02623     pseudo_bit_t        lkey[0x00020];         /* Must be 0 for SW2HW_MPT.
02624                                                  On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.
02625                                                  The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
02626 /* -------------- */
02627     pseudo_bit_t        win_cnt[0x00020];      /* Number of windows bound to this region. Valid for regions only.
02628                                                  The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
02629 /* -------------- */
02630     pseudo_bit_t        reserved5[0x00020];
02631 /* -------------- */
02632     pseudo_bit_t        mtt_adr_h[0x00006];    /* Base (first) address of the MTT relative to MTT base in the ICM */
02633     pseudo_bit_t        reserved6[0x0001a];
02634 /* -------------- */
02635     pseudo_bit_t        reserved7[0x00003];
02636     pseudo_bit_t        mtt_adr_l[0x0001d];    /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */
02637 /* -------------- */
02638     pseudo_bit_t        mtt_sz[0x00020];       /* Number of MTT entries allocated for this MR.
02639                                                  When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved.
02640                                                  When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value  is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */
02641 /* -------------- */
02642     pseudo_bit_t        reserved8[0x00040];
02643 /* -------------- */
02644 }; 
02645 
02646 /* Completion Queue Context Table Entry */
02647 
02648 struct arbelprm_completion_queue_context_st {   /* Little Endian */
02649     pseudo_bit_t        reserved0[0x00008];
02650     pseudo_bit_t        st[0x00004];           /* Event delivery state machine
02651                                                  0x0 - reserved
02652                                                  0x9 - ARMED (Request for Notification)
02653                                                  0x6 - ARMED SOLICITED (Request Solicited Notification)
02654                                                  0xA - FIRED
02655                                                  other - reserved
02656                                                  
02657                                                  Must be 0x0 in CQ initialization.
02658                                                  Valid for the QUERY_CQ and HW2SW_CQ commands only. */
02659     pseudo_bit_t        reserved1[0x00005];
02660     pseudo_bit_t        oi[0x00001];           /* When set, overrun ignore is enabled.
02661                                                  When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
02662     pseudo_bit_t        reserved2[0x0000a];
02663     pseudo_bit_t        status[0x00004];       /* CQ status
02664                                                  0000 - OK
02665                                                  1001 - CQ overflow
02666                                                  1010 - CQ write failure
02667                                                  Valid for the QUERY_CQ and HW2SW_CQ commands only */
02668 /* -------------- */
02669     pseudo_bit_t        start_address_h[0x00020];/* Start address of CQ[63:32]. 
02670                                                  Must be aligned on CQE size (32 bytes) */
02671 /* -------------- */
02672     pseudo_bit_t        start_address_l[0x00020];/* Start address of CQ[31:0]. 
02673                                                  Must be aligned on CQE size (32 bytes) */
02674 /* -------------- */
02675     pseudo_bit_t        usr_page[0x00018];     /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
02676     pseudo_bit_t        log_cq_size[0x00005];  /* Log (base 2) of the CQ size (in entries).
02677                                                  Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
02678     pseudo_bit_t        reserved3[0x00003];
02679 /* -------------- */
02680     pseudo_bit_t        reserved4[0x00020];
02681 /* -------------- */
02682     pseudo_bit_t        c_eqn[0x00008];        /* Event Queue this CQ reports completion events to.
02683                                                  Valid values are 0 to 63
02684                                                  If configured to value other than 0-63, completion events will not be reported on the CQ. */
02685     pseudo_bit_t        reserved5[0x00018];
02686 /* -------------- */
02687     pseudo_bit_t        pd[0x00018];           /* Protection Domain to be used to access CQ.
02688                                                  Must be the same PD of the CQ L_Key. */
02689     pseudo_bit_t        reserved6[0x00008];
02690 /* -------------- */
02691     pseudo_bit_t        l_key[0x00020];        /* Memory key (L_Key) to be used to access CQ */
02692 /* -------------- */
02693     pseudo_bit_t        last_notified_indx[0x00020];/* Maintained by HW.
02694                                                  Valid for QUERY_CQ and HW2SW_CQ commands only. */
02695 /* -------------- */
02696     pseudo_bit_t        solicit_producer_indx[0x00020];/* Maintained by HW.
02697                                                  Valid for QUERY_CQ and HW2SW_CQ commands only. 
02698                                                   */
02699 /* -------------- */
02700     pseudo_bit_t        consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
02701                                                  Must be 0x0 in CQ initialization.
02702                                                  Valid for the QUERY_CQ and HW2SW_CQ commands only. */
02703 /* -------------- */
02704     pseudo_bit_t        producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
02705                                                  CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
02706                                                  Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
02707 /* -------------- */
02708     pseudo_bit_t        cqn[0x00018];          /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table
02709                                                  Valid for the QUERY_CQ and HW2SW_CQ commands only */
02710     pseudo_bit_t        reserved7[0x00008];
02711 /* -------------- */
02712     pseudo_bit_t        cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry.
02713                                                  HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record.
02714                                                  This value can be retrieved from the HW in the QUERY_CQ command. */
02715 /* -------------- */
02716     pseudo_bit_t        cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry.
02717                                                  HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record.
02718                                                  This value can be retrieved from the HW in the QUERY_CQ command. */
02719 /* -------------- */
02720     pseudo_bit_t        reserved8[0x00020];
02721 /* -------------- */
02722 }; 
02723 
02724 /* GPIO_event_data */
02725 
02726 struct arbelprm_gpio_event_data_st {    /* Little Endian */
02727     pseudo_bit_t        reserved0[0x00060];
02728 /* -------------- */
02729     pseudo_bit_t        gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
02730 /* -------------- */
02731     pseudo_bit_t        gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
02732 /* -------------- */
02733     pseudo_bit_t        reserved1[0x00020];
02734 /* -------------- */
02735 }; 
02736 
02737 /* Event_data Field - QP/EE Events */
02738 
02739 struct arbelprm_qp_ee_event_st {        /* Little Endian */
02740     pseudo_bit_t        qpn_een[0x00018];      /* QP/EE/SRQ number event is reported for */
02741     pseudo_bit_t        reserved0[0x00008];
02742 /* -------------- */
02743     pseudo_bit_t        reserved1[0x00020];
02744 /* -------------- */
02745     pseudo_bit_t        reserved2[0x0001c];
02746     pseudo_bit_t        e_q[0x00001];          /* If set - EEN if cleared - QP in the QPN/EEN field
02747                                                  Not valid on SRQ events */
02748     pseudo_bit_t        reserved3[0x00003];
02749 /* -------------- */
02750     pseudo_bit_t        reserved4[0x00060];
02751 /* -------------- */
02752 }; 
02753 
02754 /* InfiniHost-III-EX Type0 Configuration Header */
02755 
02756 struct arbelprm_mt25208_type0_st {      /* Little Endian */
02757     pseudo_bit_t        vendor_id[0x00010];    /* Hardwired to 0x15B3 */
02758     pseudo_bit_t        device_id[0x00010];    /* 25208 (decimal) - InfiniHost-III compatible mode
02759                                                  25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual)
02760                                                  25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode
02761                                                   */
02762 /* -------------- */
02763     pseudo_bit_t        command[0x00010];      /* PCI Command Register */
02764     pseudo_bit_t        status[0x00010];       /* PCI Status Register */
02765 /* -------------- */
02766     pseudo_bit_t        revision_id[0x00008];
02767     pseudo_bit_t        class_code_hca_class_code[0x00018];
02768 /* -------------- */
02769     pseudo_bit_t        cache_line_size[0x00008];/* Cache Line Size */
02770     pseudo_bit_t        latency_timer[0x00008];
02771     pseudo_bit_t        header_type[0x00008];  /* hardwired to zero */
02772     pseudo_bit_t        bist[0x00008];
02773 /* -------------- */
02774     pseudo_bit_t        bar0_ctrl[0x00004];    /* hard-wired to 0100 */
02775     pseudo_bit_t        reserved0[0x00010];
02776     pseudo_bit_t        bar0_l[0x0000c];       /* Lower bits of BAR0 (Device Configuration Space) */
02777 /* -------------- */
02778     pseudo_bit_t        bar0_h[0x00020];       /* Upper 32 bits of BAR0 (Device Configuration Space) */
02779 /* -------------- */
02780     pseudo_bit_t        bar1_ctrl[0x00004];    /* Hardwired to 1100 */
02781     pseudo_bit_t        reserved1[0x00010];
02782     pseudo_bit_t        bar1_l[0x0000c];       /* Lower bits of BAR1 (User Access Region - UAR - space) */
02783 /* -------------- */
02784     pseudo_bit_t        bar1_h[0x00020];       /* upper 32 bits of BAR1 (User Access Region - UAR - space) */
02785 /* -------------- */
02786     pseudo_bit_t        bar2_ctrl[0x00004];    /* Hardwired to 1100 */
02787     pseudo_bit_t        reserved2[0x00010];
02788     pseudo_bit_t        bar2_l[0x0000c];       /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
02789 /* -------------- */
02790     pseudo_bit_t        bar2_h[0x00020];       /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
02791 /* -------------- */
02792     pseudo_bit_t        cardbus_cis_pointer[0x00020];
02793 /* -------------- */
02794     pseudo_bit_t        subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
02795     pseudo_bit_t        subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
02796 /* -------------- */
02797     pseudo_bit_t        expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
02798     pseudo_bit_t        reserved3[0x0000a];
02799     pseudo_bit_t        expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
02800 /* -------------- */
02801     pseudo_bit_t        capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
02802     pseudo_bit_t        reserved4[0x00018];
02803 /* -------------- */
02804     pseudo_bit_t        reserved5[0x00020];
02805 /* -------------- */
02806     pseudo_bit_t        interrupt_line[0x00008];
02807     pseudo_bit_t        interrupt_pin[0x00008];
02808     pseudo_bit_t        min_gnt[0x00008];
02809     pseudo_bit_t        max_latency[0x00008];
02810 /* -------------- */
02811     pseudo_bit_t        reserved6[0x00100];
02812 /* -------------- */
02813     pseudo_bit_t        msi_cap_id[0x00008];
02814     pseudo_bit_t        msi_next_cap_ptr[0x00008];
02815     pseudo_bit_t        msi_en[0x00001];
02816     pseudo_bit_t        multiple_msg_cap[0x00003];
02817     pseudo_bit_t        multiple_msg_en[0x00003];
02818     pseudo_bit_t        cap_64_bit_addr[0x00001];
02819     pseudo_bit_t        reserved7[0x00008];
02820 /* -------------- */
02821     pseudo_bit_t        msg_addr_l[0x00020];
02822 /* -------------- */
02823     pseudo_bit_t        msg_addr_h[0x00020];
02824 /* -------------- */
02825     pseudo_bit_t        msg_data[0x00010];
02826     pseudo_bit_t        reserved8[0x00010];
02827 /* -------------- */
02828     pseudo_bit_t        reserved9[0x00080];
02829 /* -------------- */
02830     pseudo_bit_t        pm_cap_id[0x00008];    /* Power management capability ID - 01h */
02831     pseudo_bit_t        pm_next_cap_ptr[0x00008];
02832     pseudo_bit_t        pm_cap[0x00010];       /* [2:0] Version - 02h
02833                                                  [3] PME clock - 0h
02834                                                  [4] RsvP
02835                                                  [5] Device specific initialization - 0h
02836                                                  [8:6] AUX current - 0h
02837                                                  [9] D1 support - 0h
02838                                                  [10] D2 support - 0h
02839                                                  [15:11] PME support - 0h */
02840 /* -------------- */
02841     pseudo_bit_t        pm_status_control[0x00010];/* [14:13] - Data scale - 0h */
02842     pseudo_bit_t        pm_control_status_brdg_ext[0x00008];
02843     pseudo_bit_t        data[0x00008];
02844 /* -------------- */
02845     pseudo_bit_t        reserved10[0x00040];
02846 /* -------------- */
02847     pseudo_bit_t        vpd_cap_id[0x00008];   /* 03h */
02848     pseudo_bit_t        vpd_next_cap_id[0x00008];
02849     pseudo_bit_t        vpd_address[0x0000f];
02850     pseudo_bit_t        f[0x00001];
02851 /* -------------- */
02852     pseudo_bit_t        vpd_data[0x00020];
02853 /* -------------- */
02854     pseudo_bit_t        reserved11[0x00040];
02855 /* -------------- */
02856     pseudo_bit_t        pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */
02857     pseudo_bit_t        pciex_next_cap_ptr[0x00008];
02858     pseudo_bit_t        pciex_cap[0x00010];    /* [3:0] Capability version - 1h
02859                                                  [7:4] Device/Port Type - 0h
02860                                                  [8] Slot implemented - 0h
02861                                                  [13:9] Interrupt message number
02862                                                   */
02863 /* -------------- */
02864     pseudo_bit_t        device_cap[0x00020];   /* [2:0] Max_Payload_Size supported - 2h
02865                                                  [4:3] Phantom Function supported - 0h
02866                                                  [5] Extended Tag Filed supported - 0h
02867                                                  [8:6] Endpoint L0s Acceptable Latency - TBD
02868                                                  [11:9] Endpoint L1 Acceptable Latency - TBD
02869                                                  [12] Attention Button Present - configured through InfiniBurn
02870                                                  [13] Attention Indicator Present - configured through InfiniBurn
02871                                                  [14] Power Indicator Present - configured through InfiniBurn
02872                                                  [25:18] Captured Slot Power Limit Value
02873                                                  [27:26] Captured Slot Power Limit Scale */
02874 /* -------------- */
02875     pseudo_bit_t        device_control[0x00010];
02876     pseudo_bit_t        device_status[0x00010];
02877 /* -------------- */
02878     pseudo_bit_t        link_cap[0x00020];     /* [3:0] Maximum Link Speed - 1h
02879                                                  [9:4] Maximum Link Width - 8h
02880                                                  [11:10] Active State Power Management Support - 3h
02881                                                  [14:12] L0s Exit Latency - TBD
02882                                                  [17:15] L1 Exit Latency - TBD
02883                                                  [31:24] Port Number - 0h */
02884 /* -------------- */
02885     pseudo_bit_t        link_control[0x00010];
02886     pseudo_bit_t        link_status[0x00010];  /* [3:0] Link Speed - 1h
02887                                                  [9:4] Negotiated Link Width
02888                                                  [12] Slot clock configuration - 1h */
02889 /* -------------- */
02890     pseudo_bit_t        reserved12[0x00260];
02891 /* -------------- */
02892     pseudo_bit_t        advanced_error_reporting_cap_id[0x00010];/* 0001h. */
02893     pseudo_bit_t        capability_version[0x00004];/* 1h */
02894     pseudo_bit_t        next_capability_offset[0x0000c];/* 0h */
02895 /* -------------- */
02896     pseudo_bit_t        uncorrectable_error_status_register[0x00020];/* 0 Training Error Status
02897                                                  4 Data Link Protocol Error Status
02898                                                  12 Poisoned TLP Status 
02899                                                  13 Flow Control Protocol Error Status 
02900                                                  14 Completion Timeout Status 
02901                                                  15 Completer Abort Status 
02902                                                  16 Unexpected Completion Status 
02903                                                  17 Receiver Overflow Status 
02904                                                  18 Malformed TLP Status 
02905                                                  19 ECRC Error Status 
02906                                                  20 Unsupported Request Error Status */
02907 /* -------------- */
02908     pseudo_bit_t        uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask
02909                                                  4 Data Link Protocol Error Mask
02910                                                  12 Poisoned TLP Mask 
02911                                                  13 Flow Control Protocol Error Mask
02912                                                  14 Completion Timeout Mask
02913                                                  15 Completer Abort Mask
02914                                                  16 Unexpected Completion Mask
02915                                                  17 Receiver Overflow Mask
02916                                                  18 Malformed TLP Mask
02917                                                  19 ECRC Error Mask
02918                                                  20 Unsupported Request Error Mask */
02919 /* -------------- */
02920     pseudo_bit_t        uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity
02921                                                  4 Data Link Protocol Error Severity
02922                                                  12 Poisoned TLP Severity
02923                                                  13 Flow Control Protocol Error Severity
02924                                                  14 Completion Timeout Severity
02925                                                  15 Completer Abort Severity
02926                                                  16 Unexpected Completion Severity
02927                                                  17 Receiver Overflow Severity
02928                                                  18 Malformed TLP Severity
02929                                                  19 ECRC Error Severity
02930                                                  20 Unsupported Request Error Severity */
02931 /* -------------- */
02932     pseudo_bit_t        correctable_error_status_register[0x00020];/* 0 Receiver Error Status
02933                                                  6 Bad TLP Status
02934                                                  7 Bad DLLP Status
02935                                                  8 REPLAY_NUM Rollover Status
02936                                                  12 Replay Timer Timeout Status */
02937 /* -------------- */
02938     pseudo_bit_t        correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask
02939                                                  6 Bad TLP Mask
02940                                                  7 Bad DLLP Mask
02941                                                  8 REPLAY_NUM Rollover Mask
02942                                                  12 Replay Timer Timeout Mask */
02943 /* -------------- */
02944     pseudo_bit_t        advance_error_capabilities_and_control_register[0x00020];
02945 /* -------------- */
02946     struct arbelprm_header_log_register_st      header_log_register;
02947 /* -------------- */
02948     pseudo_bit_t        reserved13[0x006a0];
02949 /* -------------- */
02950 }; 
02951 
02952 /* Event Data Field - Performance Monitor */
02953 
02954 struct arbelprm_performance_monitor_event_st {  /* Little Endian */
02955     struct arbelprm_performance_monitors_st     performance_monitor_snapshot;/* Performance monitor snapshot */
02956 /* -------------- */
02957     pseudo_bit_t        monitor_number[0x00008];/* 0x01 - SQPC
02958                                                  0x02 - RQPC
02959                                                  0x03 - CQC
02960                                                  0x04 - Rkey
02961                                                  0x05 - TLB
02962                                                  0x06 - port0
02963                                                  0x07 - port1 */
02964     pseudo_bit_t        reserved0[0x00018];
02965 /* -------------- */
02966     pseudo_bit_t        reserved1[0x00040];
02967 /* -------------- */
02968 }; 
02969 
02970 /* Event_data Field - Page Faults */
02971 
02972 struct arbelprm_page_fault_event_data_st {      /* Little Endian */
02973     pseudo_bit_t        va_h[0x00020];         /* Virtual Address[63:32] this page fault is reported on */
02974 /* -------------- */
02975     pseudo_bit_t        va_l[0x00020];         /* Virtual Address[63:32] this page fault is reported on */
02976 /* -------------- */
02977     pseudo_bit_t        mem_key[0x00020];      /* Memory Key this page fault is reported on */
02978 /* -------------- */
02979     pseudo_bit_t        qp[0x00018];           /* QP this page fault is reported on */
02980     pseudo_bit_t        reserved0[0x00003];
02981     pseudo_bit_t        a[0x00001];            /* If set the memory access that caused the page fault was atomic */
02982     pseudo_bit_t        lw[0x00001];           /* If set the memory access that caused the page fault was local write */
02983     pseudo_bit_t        lr[0x00001];           /* If set the memory access that caused the page fault was local read */
02984     pseudo_bit_t        rw[0x00001];           /* If set the memory access that caused the page fault was remote write */
02985     pseudo_bit_t        rr[0x00001];           /* If set the memory access that caused the page fault was remote read */
02986 /* -------------- */
02987     pseudo_bit_t        pd[0x00018];           /* PD this page fault is reported on */
02988     pseudo_bit_t        reserved1[0x00008];
02989 /* -------------- */
02990     pseudo_bit_t        prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
02991 /* -------------- */
02992 }; 
02993 
02994 /* WQE segments format */
02995 
02996 struct arbelprm_wqe_segment_st {        /* Little Endian */
02997     struct arbelprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */
02998 /* -------------- */
02999     pseudo_bit_t        reserved0[0x00280];
03000 /* -------------- */
03001     struct arbelprm_wqe_segment_ctrl_mlx_st     mlx_wqe_segment_ctrl;/* MLX WQE segment format */
03002 /* -------------- */
03003     pseudo_bit_t        reserved1[0x00100];
03004 /* -------------- */
03005     struct arbelprm_wqe_segment_ctrl_recv_st    recv_wqe_segment_ctrl;/* Receive segment format */
03006 /* -------------- */
03007     pseudo_bit_t        reserved2[0x00080];
03008 /* -------------- */
03009 }; 
03010 
03011 /* Event_data Field - Port State Change */
03012 
03013 struct arbelprm_port_state_change_st {  /* Little Endian */
03014     pseudo_bit_t        reserved0[0x00040];
03015 /* -------------- */
03016     pseudo_bit_t        reserved1[0x0001c];
03017     pseudo_bit_t        p[0x00002];            /* Port number (1 or 2) */
03018     pseudo_bit_t        reserved2[0x00002];
03019 /* -------------- */
03020     pseudo_bit_t        reserved3[0x00060];
03021 /* -------------- */
03022 }; 
03023 
03024 /* Event_data Field - Completion Queue Error */
03025 
03026 struct arbelprm_completion_queue_error_st {     /* Little Endian */
03027     pseudo_bit_t        cqn[0x00018];          /* CQ number event is reported for */
03028     pseudo_bit_t        reserved0[0x00008];
03029 /* -------------- */
03030     pseudo_bit_t        reserved1[0x00020];
03031 /* -------------- */
03032     pseudo_bit_t        syndrome[0x00008];     /* Error syndrome
03033                                                  0x01 - CQ overrun
03034                                                  0x02 - CQ access violation error */
03035     pseudo_bit_t        reserved2[0x00018];
03036 /* -------------- */
03037     pseudo_bit_t        reserved3[0x00060];
03038 /* -------------- */
03039 }; 
03040 
03041 /* Event_data Field - Completion Event */
03042 
03043 struct arbelprm_completion_event_st {   /* Little Endian */
03044     pseudo_bit_t        cqn[0x00018];          /* CQ number event is reported for */
03045     pseudo_bit_t        reserved0[0x00008];
03046 /* -------------- */
03047     pseudo_bit_t        reserved1[0x000a0];
03048 /* -------------- */
03049 }; 
03050 
03051 /* Event Queue Entry */
03052 
03053 struct arbelprm_event_queue_entry_st {  /* Little Endian */
03054     pseudo_bit_t        event_sub_type[0x00008];/* Event Sub Type. 
03055                                                  Defined for events which have sub types, zero elsewhere. */
03056     pseudo_bit_t        reserved0[0x00008];
03057     pseudo_bit_t        event_type[0x00008];   /* Event Type */
03058     pseudo_bit_t        reserved1[0x00008];
03059 /* -------------- */
03060     pseudo_bit_t        event_data[6][0x00020];/* Delivers auxilary data to handle event. */
03061 /* -------------- */
03062     pseudo_bit_t        reserved2[0x00007];
03063     pseudo_bit_t        owner[0x00001];        /* Owner of the entry 
03064                                                  0 SW 
03065                                                  1 HW */
03066     pseudo_bit_t        reserved3[0x00018];
03067 /* -------------- */
03068 }; 
03069 
03070 /* QP/EE State Transitions Command Parameters */
03071 
03072 struct arbelprm_qp_ee_state_transitions_st {    /* Little Endian */
03073     pseudo_bit_t        opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
03074 /* -------------- */
03075     pseudo_bit_t        reserved0[0x00020];
03076 /* -------------- */
03077     struct arbelprm_queue_pair_ee_context_entry_st      qpc_eec_data;/* QPC/EEC data */
03078 /* -------------- */
03079     pseudo_bit_t        reserved1[0x009c0];
03080 /* -------------- */
03081 }; 
03082 
03083 /* Completion Queue Entry Format */
03084 
03085 struct arbelprm_completion_queue_entry_st {     /* Little Endian */
03086     pseudo_bit_t        my_qpn[0x00018];       /* Indicates the QP for which completion is being reported */
03087     pseudo_bit_t        reserved0[0x00004];
03088     pseudo_bit_t        ver[0x00004];          /* CQE version. 
03089                                                  0 for InfiniHost-III-EX */
03090 /* -------------- */
03091     pseudo_bit_t        my_ee[0x00018];        /* EE context (for RD only).
03092                                                  Invalid for Bind and Nop operation on RD.
03093                                                  For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported.
03094                                                   */
03095     pseudo_bit_t        checksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */
03096 /* -------------- */
03097     pseudo_bit_t        rqpn[0x00018];         /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */
03098     pseudo_bit_t        checksum_7_0[0x00008]; /* Checksum[7:0] - See IPoverIB checksum offloading chapter */
03099 /* -------------- */
03100     pseudo_bit_t        rlid[0x00010];         /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */
03101     pseudo_bit_t        ml_path[0x00007];      /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW.
03102                                                  Valid in responder of UD QP CQE only.
03103                                                  Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */
03104     pseudo_bit_t        g[0x00001];            /* GRH present indicator. Valid in Responder of UD QP CQE only. */
03105     pseudo_bit_t        ipok[0x00001];         /* IP OK - See IPoverIB checksum offloading chapter */
03106     pseudo_bit_t        reserved1[0x00003];
03107     pseudo_bit_t        sl[0x00004];           /* Service Level of the message. Valid in Responder of UD QP CQE only. */
03108 /* -------------- */
03109     pseudo_bit_t        immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only. 
03110                                                  If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet. 
03111                                                  If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet. 
03112                                                  If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived. 
03113                                                  If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated.
03114                                                  For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */
03115 /* -------------- */
03116     pseudo_bit_t        byte_cnt[0x00020];     /* Byte count of data actually transferred (valid for receive queue completions only) */
03117 /* -------------- */
03118     pseudo_bit_t        reserved2[0x00006];
03119     pseudo_bit_t        wqe_adr[0x0001a];      /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
03120 /* -------------- */
03121     pseudo_bit_t        reserved3[0x00007];
03122     pseudo_bit_t        owner[0x00001];        /* Owner field. Zero value of this field means SW ownership of CQE. */
03123     pseudo_bit_t        reserved4[0x0000f];
03124     pseudo_bit_t        s[0x00001];            /* If set, completion is reported for Send queue, if cleared - receive queue. */
03125     pseudo_bit_t        opcode[0x00008];       /* The opcode of WQE completion is reported for.
03126                                                  For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field.
03127                                                  For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field.
03128                                                  For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only)
03129                                                  
03130                                                  The following values are reported in case of completion with error:
03131                                                  0xFE - For completion with error on Receive Queues
03132                                                  0xFF - For completion with error on Send Queues */
03133 /* -------------- */
03134 }; 
03135 
03136 /*  */
03137 
03138 struct arbelprm_ecc_detect_event_data_st {      /* Little Endian */
03139     pseudo_bit_t        reserved0[0x00080];
03140 /* -------------- */
03141     pseudo_bit_t        cause_lsb[0x00001];
03142     pseudo_bit_t        reserved1[0x00002];
03143     pseudo_bit_t        cause_msb[0x00001];
03144     pseudo_bit_t        reserved2[0x00002];
03145     pseudo_bit_t        err_rmw[0x00001];
03146     pseudo_bit_t        err_src_id[0x00003];
03147     pseudo_bit_t        err_da[0x00002];
03148     pseudo_bit_t        err_ba[0x00002];
03149     pseudo_bit_t        reserved3[0x00011];
03150     pseudo_bit_t        overflow[0x00001];
03151 /* -------------- */
03152     pseudo_bit_t        err_ra[0x00010];
03153     pseudo_bit_t        err_ca[0x00010];
03154 /* -------------- */
03155 }; 
03156 
03157 /* Event_data Field - ECC Detection Event */
03158 
03159 struct arbelprm_scrubbing_event_st {    /* Little Endian */
03160     pseudo_bit_t        reserved0[0x00080];
03161 /* -------------- */
03162     pseudo_bit_t        cause_lsb[0x00001];    /* data integrity error cause:
03163                                                  single ECC error in the 64bit lsb data, on the rise edge of the clock */
03164     pseudo_bit_t        reserved1[0x00002];
03165     pseudo_bit_t        cause_msb[0x00001];    /* data integrity error cause:
03166                                                  single ECC error in the 64bit msb data, on the fall edge of the clock */
03167     pseudo_bit_t        reserved2[0x00002];
03168     pseudo_bit_t        err_rmw[0x00001];      /* transaction type:
03169                                                  0 - read
03170                                                  1 - read/modify/write */
03171     pseudo_bit_t        err_src_id[0x00003];   /* source of the transaction: 0x4 - PCI, other - internal or IB */
03172     pseudo_bit_t        err_da[0x00002];       /* Error DIMM address */
03173     pseudo_bit_t        err_ba[0x00002];       /* Error bank address */
03174     pseudo_bit_t        reserved3[0x00011];
03175     pseudo_bit_t        overflow[0x00001];     /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
03176 /* -------------- */
03177     pseudo_bit_t        err_ra[0x00010];       /* Error row address */
03178     pseudo_bit_t        err_ca[0x00010];       /* Error column address */
03179 /* -------------- */
03180 }; 
03181 
03182 /* Miscellaneous Counters */
03183 
03184 struct arbelprm_misc_counters_st {      /* Little Endian */
03185     pseudo_bit_t        ddr_scan_cnt[0x00020]; /* Number of times whole of LAM was scanned */
03186 /* -------------- */
03187     pseudo_bit_t        reserved0[0x007e0];
03188 /* -------------- */
03189 }; 
03190 
03191 /* LAM_EN Output Parameter */
03192 
03193 struct arbelprm_lam_en_out_param_st {   /* Little Endian */
03194     pseudo_bit_t        reserved0[0x00040];
03195 /* -------------- */
03196 }; 
03197 
03198 /* Extended_Completion_Queue_Entry */
03199 
03200 struct arbelprm_extended_completion_queue_entry_st {    /* Little Endian */
03201     pseudo_bit_t        reserved0[0x00020];
03202 /* -------------- */
03203 }; 
03204 
03205 /*  */
03206 
03207 struct arbelprm_eq_cmd_doorbell_st {    /* Little Endian */
03208     pseudo_bit_t        reserved0[0x00020];
03209 /* -------------- */
03210 }; 
03211 
03212 /* 0 */
03213 
03214 struct arbelprm_arbel_prm_st {  /* Little Endian */
03215     struct arbelprm_completion_queue_entry_st   completion_queue_entry;/* Completion Queue Entry Format */
03216 /* -------------- */
03217     pseudo_bit_t        reserved0[0x7ff00];
03218 /* -------------- */
03219     struct arbelprm_qp_ee_state_transitions_st  qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */
03220 /* -------------- */
03221     pseudo_bit_t        reserved1[0x7f000];
03222 /* -------------- */
03223     struct arbelprm_event_queue_entry_st        event_queue_entry;/* Event Queue Entry */
03224 /* -------------- */
03225     pseudo_bit_t        reserved2[0x7ff00];
03226 /* -------------- */
03227     struct arbelprm_completion_event_st completion_event;/* Event_data Field - Completion Event */
03228 /* -------------- */
03229     pseudo_bit_t        reserved3[0x7ff40];
03230 /* -------------- */
03231     struct arbelprm_completion_queue_error_st   completion_queue_error;/* Event_data Field - Completion Queue Error */
03232 /* -------------- */
03233     pseudo_bit_t        reserved4[0x7ff40];
03234 /* -------------- */
03235     struct arbelprm_port_state_change_st        port_state_change;/* Event_data Field - Port State Change */
03236 /* -------------- */
03237     pseudo_bit_t        reserved5[0x7ff40];
03238 /* -------------- */
03239     struct arbelprm_wqe_segment_st      wqe_segment;/* WQE segments format */
03240 /* -------------- */
03241     pseudo_bit_t        reserved6[0x7f000];
03242 /* -------------- */
03243     struct arbelprm_page_fault_event_data_st    page_fault_event_data;/* Event_data Field - Page Faults */
03244 /* -------------- */
03245     pseudo_bit_t        reserved7[0x7ff40];
03246 /* -------------- */
03247     struct arbelprm_performance_monitor_event_st        performance_monitor_event;/* Event Data Field - Performance Monitor */
03248 /* -------------- */
03249     pseudo_bit_t        reserved8[0xfff20];
03250 /* -------------- */
03251     struct arbelprm_mt25208_type0_st    mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */
03252 /* -------------- */
03253     pseudo_bit_t        reserved9[0x7f000];
03254 /* -------------- */
03255     struct arbelprm_qp_ee_event_st      qp_ee_event;/* Event_data Field - QP/EE Events */
03256 /* -------------- */
03257     pseudo_bit_t        reserved10[0x00040];
03258 /* -------------- */
03259     struct arbelprm_gpio_event_data_st  gpio_event_data;
03260 /* -------------- */
03261     pseudo_bit_t        reserved11[0x7fe40];
03262 /* -------------- */
03263     struct arbelprm_ud_address_vector_st        ud_address_vector;/* UD Address Vector */
03264 /* -------------- */
03265     pseudo_bit_t        reserved12[0x7ff00];
03266 /* -------------- */
03267     struct arbelprm_queue_pair_ee_context_entry_st      queue_pair_ee_context_entry;/* QP and EE Context Entry */
03268 /* -------------- */
03269     pseudo_bit_t        reserved13[0x7fa00];
03270 /* -------------- */
03271     struct arbelprm_address_path_st     address_path;/* Address Path */
03272 /* -------------- */
03273     pseudo_bit_t        reserved14[0x7ff00];
03274 /* -------------- */
03275     struct arbelprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */
03276 /* -------------- */
03277     pseudo_bit_t        reserved15[0x7fe00];
03278 /* -------------- */
03279     struct arbelprm_mpt_st      mpt;         /* Memory Protection Table (MPT) Entry */
03280 /* -------------- */
03281     pseudo_bit_t        reserved16[0x7fe00];
03282 /* -------------- */
03283     struct arbelprm_mtt_st      mtt;         /* Memory Translation Table (MTT) Entry */
03284 /* -------------- */
03285     pseudo_bit_t        reserved17[0x7ffc0];
03286 /* -------------- */
03287     struct arbelprm_eqc_st      eqc;         /* Event Queue Context Table Entry */
03288 /* -------------- */
03289     pseudo_bit_t        reserved18[0x7fe00];
03290 /* -------------- */
03291     struct arbelprm_performance_monitors_st     performance_monitors;/* Performance Monitors */
03292 /* -------------- */
03293     pseudo_bit_t        reserved19[0x7ff80];
03294 /* -------------- */
03295     struct arbelprm_hca_command_register_st     hca_command_register;/* HCA Command Register (HCR) */
03296 /* -------------- */
03297     pseudo_bit_t        reserved20[0xfff20];
03298 /* -------------- */
03299     struct arbelprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */
03300 /* -------------- */
03301     pseudo_bit_t        reserved21[0x7f000];
03302 /* -------------- */
03303     struct arbelprm_qpcbaseaddr_st      qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */
03304 /* -------------- */
03305     pseudo_bit_t        reserved22[0x7fc00];
03306 /* -------------- */
03307     struct arbelprm_udavtable_memory_parameters_st      udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */
03308 /* -------------- */
03309     pseudo_bit_t        reserved23[0x7ffc0];
03310 /* -------------- */
03311     struct arbelprm_multicastparam_st   multicastparam;/* Multicast Support Parameters */
03312 /* -------------- */
03313     pseudo_bit_t        reserved24[0x7ff00];
03314 /* -------------- */
03315     struct arbelprm_tptparams_st        tptparams;/* Translation and Protection Tables Parameters */
03316 /* -------------- */
03317     pseudo_bit_t        reserved25[0x7ff00];
03318 /* -------------- */
03319     struct arbelprm_enable_lam_st       enable_lam;/* ENABLE_LAM Parameters Block */
03320 /* -------------- */
03321     struct arbelprm_access_lam_st       access_lam;
03322 /* -------------- */
03323     pseudo_bit_t        reserved26[0x7f700];
03324 /* -------------- */
03325     struct arbelprm_dimminfo_st dimminfo;/* Logical DIMM Information */
03326 /* -------------- */
03327     pseudo_bit_t        reserved27[0x7ff00];
03328 /* -------------- */
03329     struct arbelprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */
03330 /* -------------- */
03331     pseudo_bit_t        reserved28[0x7f800];
03332 /* -------------- */
03333     struct arbelprm_query_adapter_st    query_adapter;/* QUERY_ADAPTER Parameters Block */
03334 /* -------------- */
03335     pseudo_bit_t        reserved29[0x7f800];
03336 /* -------------- */
03337     struct arbelprm_query_dev_lim_st    query_dev_lim;/* Query Device Limitations */
03338 /* -------------- */
03339     pseudo_bit_t        reserved30[0x7f800];
03340 /* -------------- */
03341     struct arbelprm_uar_params_st       uar_params;/* UAR Parameters */
03342 /* -------------- */
03343     pseudo_bit_t        reserved31[0x7ff00];
03344 /* -------------- */
03345     struct arbelprm_init_ib_st  init_ib; /* INIT_IB Parameters */
03346 /* -------------- */
03347     pseudo_bit_t        reserved32[0x7f800];
03348 /* -------------- */
03349     struct arbelprm_mgm_entry_st        mgm_entry;/* Multicast Group Member */
03350 /* -------------- */
03351     pseudo_bit_t        reserved33[0x7fe00];
03352 /* -------------- */
03353     struct arbelprm_set_ib_st   set_ib;   /* SET_IB Parameters */
03354 /* -------------- */
03355     pseudo_bit_t        reserved34[0x7fe00];
03356 /* -------------- */
03357     struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */
03358 /* -------------- */
03359     pseudo_bit_t        reserved35[0x7ff80];
03360 /* -------------- */
03361     struct arbelprm_send_doorbell_st    send_doorbell;/* Send doorbell */
03362 /* -------------- */
03363     pseudo_bit_t        reserved36[0x7ffc0];
03364 /* -------------- */
03365     struct arbelprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */
03366 /* -------------- */
03367     pseudo_bit_t        reserved37[0x7ffc0];
03368 /* -------------- */
03369     struct arbelprm_cq_cmd_doorbell_st  cq_cmd_doorbell;/* CQ Doorbell */
03370 /* -------------- */
03371     pseudo_bit_t        reserved38[0xfffc0];
03372 /* -------------- */
03373     struct arbelprm_uar_st      uar;         /* User Access Region */
03374 /* -------------- */
03375     pseudo_bit_t        reserved39[0x7c000];
03376 /* -------------- */
03377     struct arbelprm_mgmqp_st    mgmqp;     /* Multicast Group Member QP */
03378 /* -------------- */
03379     pseudo_bit_t        reserved40[0x7ffe0];
03380 /* -------------- */
03381     struct arbelprm_query_debug_msg_st  query_debug_msg;/* Query Debug Message */
03382 /* -------------- */
03383     pseudo_bit_t        reserved41[0x7f800];
03384 /* -------------- */
03385     struct arbelprm_mad_ifc_st  mad_ifc; /* MAD_IFC Input Mailbox */
03386 /* -------------- */
03387     pseudo_bit_t        reserved42[0x00900];
03388 /* -------------- */
03389     struct arbelprm_mad_ifc_input_modifier_st   mad_ifc_input_modifier;/* MAD_IFC Input Modifier */
03390 /* -------------- */
03391     pseudo_bit_t        reserved43[0x7e6e0];
03392 /* -------------- */
03393     struct arbelprm_resize_cq_st        resize_cq;/* Resize CQ Input Mailbox */
03394 /* -------------- */
03395     pseudo_bit_t        reserved44[0x7fe00];
03396 /* -------------- */
03397     struct arbelprm_completion_with_error_st    completion_with_error;/* Completion with Error CQE */
03398 /* -------------- */
03399     pseudo_bit_t        reserved45[0x7ff00];
03400 /* -------------- */
03401     struct arbelprm_hcr_completion_event_st     hcr_completion_event;/* Event_data Field - HCR Completion Event */
03402 /* -------------- */
03403     pseudo_bit_t        reserved46[0x7ff40];
03404 /* -------------- */
03405     struct arbelprm_transport_and_ci_error_counters_st  transport_and_ci_error_counters;/* Transport and CI Error Counters */
03406 /* -------------- */
03407     pseudo_bit_t        reserved47[0x7f000];
03408 /* -------------- */
03409     struct arbelprm_performance_counters_st     performance_counters;/* Performance Counters */
03410 /* -------------- */
03411     pseudo_bit_t        reserved48[0x9ff800];
03412 /* -------------- */
03413     struct arbelprm_fast_registration_segment_st        fast_registration_segment;/* Fast Registration Segment */
03414 /* -------------- */
03415     pseudo_bit_t        reserved49[0x7ff00];
03416 /* -------------- */
03417     struct arbelprm_pbl_st      pbl;         /* Physical Buffer List */
03418 /* -------------- */
03419     pseudo_bit_t        reserved50[0x7ff00];
03420 /* -------------- */
03421     struct arbelprm_srq_context_st      srq_context;/* SRQ Context */
03422 /* -------------- */
03423     pseudo_bit_t        reserved51[0x7fe80];
03424 /* -------------- */
03425     struct arbelprm_mod_stat_cfg_st     mod_stat_cfg;/* MOD_STAT_CFG */
03426 /* -------------- */
03427     pseudo_bit_t        reserved52[0x7f800];
03428 /* -------------- */
03429     struct arbelprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */
03430 /* -------------- */
03431     pseudo_bit_t        reserved53[0x7ff80];
03432 /* -------------- */
03433     struct arbelprm_cq_ci_db_record_st  cq_ci_db_record;/* CQ_CI_DB_Record */
03434 /* -------------- */
03435     pseudo_bit_t        reserved54[0x7ffc0];
03436 /* -------------- */
03437     struct arbelprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */
03438 /* -------------- */
03439     pseudo_bit_t        reserved55[0x7ffc0];
03440 /* -------------- */
03441     struct arbelprm_qp_db_record_st     qp_db_record;/* QP_DB_Record */
03442 /* -------------- */
03443     pseudo_bit_t        reserved56[0x1fffc0];
03444 /* -------------- */
03445     struct arbelprm_configuration_registers_st  configuration_registers;/* InfiniHost III EX Configuration Registers */
03446 /* -------------- */
03447     struct arbelprm_eq_set_ci_table_st  eq_set_ci_table;/* EQ Set CI DBs Table */
03448 /* -------------- */
03449     pseudo_bit_t        reserved57[0x01000];
03450 /* -------------- */
03451     struct arbelprm_eq_arm_db_region_st eq_arm_db_region;/* EQ Arm Doorbell Region */
03452 /* -------------- */
03453     pseudo_bit_t        reserved58[0x00fc0];
03454 /* -------------- */
03455     struct arbelprm_clr_int_st  clr_int; /* Clear Interrupt Register */
03456 /* -------------- */
03457     pseudo_bit_t        reserved59[0xffcfc0];
03458 /* -------------- */
03459 }; 
03460 #endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */