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iPXE
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00001 /* 00002 This software is available to you under a choice of one of two 00003 licenses. You may choose to be licensed under the terms of the GNU 00004 General Public License (GPL) Version 2, available at 00005 <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD 00006 license, available in the LICENSE.TXT file accompanying this 00007 software. These details are also available at 00008 <http://openib.org/license.html>. 00009 00010 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 00011 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00012 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 00013 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 00014 BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 00015 ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 00016 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 00017 SOFTWARE. 00018 00019 Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. 00020 */ 00021 00022 FILE_LICENCE ( GPL2_ONLY ); 00023 00024 /*** 00025 *** This file was generated at "Mon Apr 16 23:22:02 2007" 00026 *** by: 00027 *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix hermonprm_ -bits -fixnames MT25408_PRM.csp 00028 ***/ 00029 00030 #ifndef H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 00031 #define H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 00032 00033 /* UD Address Vector */ 00034 00035 struct hermonprm_ud_address_vector_st { /* Little Endian */ 00036 pseudo_bit_t pd[0x00018]; /* Protection Domain */ 00037 pseudo_bit_t port_number[0x00002]; /* Port number 00038 1 - Port 1 00039 2 - Port 2 00040 other - reserved */ 00041 pseudo_bit_t reserved0[0x00005]; 00042 pseudo_bit_t fl[0x00001]; /* force loopback */ 00043 /* -------------- */ 00044 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 00045 pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 00046 pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 00047 pseudo_bit_t reserved1[0x00008]; 00048 /* -------------- */ 00049 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 00050 pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 00051 0 - 4X injection rate 00052 1 - 1X injection rate 00053 other - reserved 00054 */ 00055 pseudo_bit_t reserved2[0x00004]; 00056 pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table 00057 mgid_index = (port_number-1) * 2^log_max_gid + gid_index 00058 Where: 00059 1. log_max_gid is taken from QUERY_DEV_CAP command 00060 2. gid_index is the index to the GID table */ 00061 pseudo_bit_t reserved3[0x00009]; 00062 /* -------------- */ 00063 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 00064 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 00065 pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 00066 /* -------------- */ 00067 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 00068 /* -------------- */ 00069 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 00070 /* -------------- */ 00071 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 00072 /* -------------- */ 00073 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ 00074 /* -------------- */ 00075 }; 00076 00077 /* Send doorbell */ 00078 00079 struct hermonprm_send_doorbell_st { /* Little Endian */ 00080 pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ 00081 pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ 00082 pseudo_bit_t reserved0[0x00002]; 00083 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ 00084 pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ 00085 /* -------------- */ 00086 pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ 00087 pseudo_bit_t reserved1[0x00002]; 00088 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 00089 /* -------------- */ 00090 }; 00091 00092 /* Send wqe segment data inline */ 00093 00094 struct hermonprm_wqe_segment_data_inline_st { /* Little Endian */ 00095 pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ 00096 pseudo_bit_t reserved0[0x00015]; 00097 pseudo_bit_t always1[0x00001]; 00098 /* -------------- */ 00099 pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ 00100 pseudo_bit_t reserved1[0x00008]; 00101 /* -------------- */ 00102 pseudo_bit_t reserved2[0x00040]; 00103 /* -------------- */ 00104 }; 00105 00106 /* Send wqe segment data ptr */ 00107 00108 struct hermonprm_wqe_segment_data_ptr_st { /* Little Endian */ 00109 pseudo_bit_t byte_count[0x0001f]; 00110 pseudo_bit_t always0[0x00001]; 00111 /* -------------- */ 00112 pseudo_bit_t l_key[0x00020]; 00113 /* -------------- */ 00114 pseudo_bit_t local_address_h[0x00020]; 00115 /* -------------- */ 00116 pseudo_bit_t local_address_l[0x00020]; 00117 /* -------------- */ 00118 }; 00119 00120 /* Send wqe segment rd */ 00121 00122 struct hermonprm_local_invalidate_segment_st { /* Little Endian */ 00123 pseudo_bit_t reserved0[0x00040]; 00124 /* -------------- */ 00125 pseudo_bit_t mem_key[0x00018]; 00126 pseudo_bit_t reserved1[0x00008]; 00127 /* -------------- */ 00128 pseudo_bit_t reserved2[0x000a0]; 00129 /* -------------- */ 00130 }; 00131 00132 /* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */ 00133 00134 struct hermonprm_fast_registration_segment_st { /* Little Endian */ 00135 pseudo_bit_t reserved0[0x0001b]; 00136 pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ 00137 pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ 00138 pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ 00139 pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ 00140 pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ 00141 /* -------------- */ 00142 pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */ 00143 /* -------------- */ 00144 pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */ 00145 /* -------------- */ 00146 pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 00147 page_size should be less than 20. ###michal - field doesn't exsist (see replacement above) */ 00148 pseudo_bit_t reserved1[0x00002]; 00149 pseudo_bit_t zb[0x00001]; /* Zero Based Region ###michal - field doesn't exsist (see replacement above) */ 00150 pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */ 00151 /* -------------- */ 00152 pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ 00153 /* -------------- */ 00154 pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ 00155 /* -------------- */ 00156 pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ 00157 /* -------------- */ 00158 pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ 00159 /* -------------- */ 00160 }; 00161 00162 /* Send wqe segment atomic */ 00163 00164 struct hermonprm_wqe_segment_atomic_st { /* Little Endian */ 00165 pseudo_bit_t swap_add_h[0x00020]; 00166 /* -------------- */ 00167 pseudo_bit_t swap_add_l[0x00020]; 00168 /* -------------- */ 00169 pseudo_bit_t compare_h[0x00020]; 00170 /* -------------- */ 00171 pseudo_bit_t compare_l[0x00020]; 00172 /* -------------- */ 00173 }; 00174 00175 /* Send wqe segment remote address */ 00176 00177 struct hermonprm_wqe_segment_remote_address_st { /* Little Endian */ 00178 pseudo_bit_t remote_virt_addr_h[0x00020]; 00179 /* -------------- */ 00180 pseudo_bit_t remote_virt_addr_l[0x00020]; 00181 /* -------------- */ 00182 pseudo_bit_t rkey[0x00020]; 00183 /* -------------- */ 00184 pseudo_bit_t reserved0[0x00020]; 00185 /* -------------- */ 00186 }; 00187 00188 /* end wqe segment bind */ 00189 00190 struct hermonprm_wqe_segment_bind_st { /* Little Endian */ 00191 pseudo_bit_t reserved0[0x0001d]; 00192 pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ 00193 pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. 00194 */ 00195 pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ 00196 /* -------------- */ 00197 pseudo_bit_t reserved1[0x0001e]; 00198 pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ 00199 pseudo_bit_t type[0x00001]; /* Window type. 00200 0 - Type one window 00201 1 - Type two window 00202 */ 00203 /* -------------- */ 00204 pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ 00205 /* -------------- */ 00206 pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ 00207 /* -------------- */ 00208 pseudo_bit_t start_address_h[0x00020]; 00209 /* -------------- */ 00210 pseudo_bit_t start_address_l[0x00020]; 00211 /* -------------- */ 00212 pseudo_bit_t length_h[0x00020]; 00213 /* -------------- */ 00214 pseudo_bit_t length_l[0x00020]; 00215 /* -------------- */ 00216 }; 00217 00218 /* Send wqe segment ud */ 00219 00220 struct hermonprm_wqe_segment_ud_st { /* Little Endian */ 00221 struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 00222 /* -------------- */ 00223 pseudo_bit_t destination_qp[0x00018]; 00224 pseudo_bit_t reserved0[0x00008]; 00225 /* -------------- */ 00226 pseudo_bit_t q_key[0x00020]; 00227 /* -------------- */ 00228 pseudo_bit_t reserved1[0x00040]; 00229 /* -------------- */ 00230 }; 00231 00232 /* Send wqe segment rd */ 00233 00234 struct hermonprm_wqe_segment_rd_st { /* Little Endian */ 00235 pseudo_bit_t destination_qp[0x00018]; 00236 pseudo_bit_t reserved0[0x00008]; 00237 /* -------------- */ 00238 pseudo_bit_t q_key[0x00020]; 00239 /* -------------- */ 00240 pseudo_bit_t reserved1[0x00040]; 00241 /* -------------- */ 00242 }; 00243 00244 /* Send wqe segment ctrl */ 00245 00246 struct hermonprm_wqe_segment_ctrl_send_st { /* Little Endian */ 00247 pseudo_bit_t opcode[0x00005]; 00248 pseudo_bit_t reserved0[0x0001a]; 00249 pseudo_bit_t owner[0x00001]; 00250 /* -------------- */ 00251 pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */ 00252 pseudo_bit_t f[0x00001]; /* fence */ 00253 pseudo_bit_t reserved1[0x00019]; 00254 /* -------------- */ 00255 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 00256 pseudo_bit_t s[0x00001]; /* Remote Solicited Event */ 00257 pseudo_bit_t c[0x00002]; /* completion required: 0b00 - no 0b11 - yes */ 00258 pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ 00259 pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ 00260 pseudo_bit_t reserved2[0x00001]; 00261 pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ 00262 pseudo_bit_t src_remote_buf[0x00018]; 00263 /* -------------- */ 00264 pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ 00265 /* -------------- */ 00266 }; 00267 00268 /* Address Path # ###michal - match to PRM */ 00269 00270 struct hermonprm_address_path_st { /* Little Endian */ 00271 pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ 00272 pseudo_bit_t reserved0[0x00016]; 00273 pseudo_bit_t sv[0x00001]; /* Service VLAN on QP */ 00274 pseudo_bit_t cv[0x00001]; /* Customer VLAN in QP */ 00275 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 00276 /* -------------- */ 00277 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 00278 pseudo_bit_t my_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 00279 pseudo_bit_t grh_ip[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 00280 pseudo_bit_t reserved1[0x00008]; 00281 /* -------------- */ 00282 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 00283 pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 00284 0 - 100% injection rate 00285 1 - 25% injection rate 00286 2 - 12.5% injection rate 00287 3 - 50% injection rate 00288 7: 2.5 Gb/s. 00289 8: 10 Gb/s. 00290 9: 30 Gb/s. 00291 10: 5 Gb/s. 00292 11: 20 Gb/s. 00293 12: 40 Gb/s. 00294 13: 60 Gb/s. 00295 14: 80 Gb/s. 00296 15: 120 Gb/s. */ 00297 pseudo_bit_t reserved2[0x00004]; 00298 pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table */ 00299 pseudo_bit_t reserved3[0x00004]; 00300 pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. 00301 The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ 00302 /* -------------- */ 00303 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 00304 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 00305 pseudo_bit_t reserved4[0x00004]; 00306 /* -------------- */ 00307 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 00308 /* -------------- */ 00309 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 00310 /* -------------- */ 00311 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 00312 /* -------------- */ 00313 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ 00314 /* -------------- */ 00315 pseudo_bit_t reserved5[0x00008]; 00316 pseudo_bit_t sp[0x00001]; /* if set, spoofing protection is enforced on this QP and Ethertype headers are restricted */ 00317 pseudo_bit_t reserved6[0x00002]; 00318 pseudo_bit_t fvl[0x00001]; /* force VLAN */ 00319 pseudo_bit_t fsip[0x00001]; /* force source IP */ 00320 pseudo_bit_t fsm[0x00001]; /* force source MAC */ 00321 pseudo_bit_t reserved7[0x0000a]; 00322 pseudo_bit_t sched_queue[0x00008]; 00323 /* -------------- */ 00324 pseudo_bit_t dmac_47_32[0x00010]; 00325 pseudo_bit_t vlan_index[0x00007]; 00326 pseudo_bit_t reserved8[0x00001]; 00327 pseudo_bit_t counter_index[0x00008];/* Index to a table of counters that counts egress packets and bytes, 0xFF not valid */ 00328 /* -------------- */ 00329 pseudo_bit_t dmac_31_0[0x00020]; 00330 /* -------------- */ 00331 }; 00332 00333 /* HCA Command Register (HCR) #### michal - match PRM */ 00334 00335 struct hermonprm_hca_command_register_st { /* Little Endian */ 00336 pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ 00337 /* -------------- */ 00338 pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ 00339 /* -------------- */ 00340 pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ 00341 /* -------------- */ 00342 pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ 00343 /* -------------- */ 00344 pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ 00345 /* -------------- */ 00346 pseudo_bit_t reserved0[0x00010]; 00347 pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ 00348 /* -------------- */ 00349 pseudo_bit_t opcode[0x0000c]; /* Command opcode */ 00350 pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ 00351 pseudo_bit_t reserved1[0x00005]; 00352 pseudo_bit_t t[0x00001]; /* Toggle */ 00353 pseudo_bit_t e[0x00001]; /* Event Request 00354 0 - Don't report event (software will poll the GO bit) 00355 1 - Report event to EQ when the command completes */ 00356 pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) 00357 Software can write to the HCR only if Go bit is cleared. 00358 Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ 00359 pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) 00360 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ 00361 /* -------------- */ 00362 }; 00363 00364 /* CQ Doorbell */ 00365 00366 struct hermonprm_cq_cmd_doorbell_st { /* Little Endian */ 00367 pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ 00368 pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ 00369 0x0 - Reserved 00370 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. 00371 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. 00372 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated 00373 Other - Reserved */ 00374 pseudo_bit_t reserved0[0x00001]; 00375 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. 00376 This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited 00377 completion or Request notification for multiple completions doorbells after receiving completion notification. 00378 This field is initialized to Zero */ 00379 pseudo_bit_t reserved1[0x00002]; 00380 /* -------------- */ 00381 pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ 00382 /* -------------- */ 00383 }; 00384 00385 /* RD-send doorbell */ 00386 00387 struct hermonprm_rd_send_doorbell_st { /* Little Endian */ 00388 pseudo_bit_t reserved0[0x00008]; 00389 pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) 00390 Must be zero for Nop and Bind operations */ 00391 /* -------------- */ 00392 pseudo_bit_t reserved1[0x00008]; 00393 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 00394 /* -------------- */ 00395 struct hermonprm_send_doorbell_st send_doorbell;/* Send Parameters */ 00396 /* -------------- */ 00397 }; 00398 00399 /* Multicast Group Member QP #### michal - match PRM */ 00400 00401 struct hermonprm_mgmqp_st { /* Little Endian */ 00402 pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ 00403 pseudo_bit_t reserved0[0x00006]; 00404 pseudo_bit_t blck_lb[0x00001]; /* Block self-loopback messages arriving to this qp */ 00405 pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ 00406 /* -------------- */ 00407 }; 00408 00409 /* vsd */ 00410 00411 struct hermonprm_vsd_st { /* Little Endian */ 00412 pseudo_bit_t vsd_dw0[0x00020]; 00413 /* -------------- */ 00414 pseudo_bit_t vsd_dw1[0x00020]; 00415 /* -------------- */ 00416 pseudo_bit_t vsd_dw2[0x00020]; 00417 /* -------------- */ 00418 pseudo_bit_t vsd_dw3[0x00020]; 00419 /* -------------- */ 00420 pseudo_bit_t vsd_dw4[0x00020]; 00421 /* -------------- */ 00422 pseudo_bit_t vsd_dw5[0x00020]; 00423 /* -------------- */ 00424 pseudo_bit_t vsd_dw6[0x00020]; 00425 /* -------------- */ 00426 pseudo_bit_t vsd_dw7[0x00020]; 00427 /* -------------- */ 00428 pseudo_bit_t vsd_dw8[0x00020]; 00429 /* -------------- */ 00430 pseudo_bit_t vsd_dw9[0x00020]; 00431 /* -------------- */ 00432 pseudo_bit_t vsd_dw10[0x00020]; 00433 /* -------------- */ 00434 pseudo_bit_t vsd_dw11[0x00020]; 00435 /* -------------- */ 00436 pseudo_bit_t vsd_dw12[0x00020]; 00437 /* -------------- */ 00438 pseudo_bit_t vsd_dw13[0x00020]; 00439 /* -------------- */ 00440 pseudo_bit_t vsd_dw14[0x00020]; 00441 /* -------------- */ 00442 pseudo_bit_t vsd_dw15[0x00020]; 00443 /* -------------- */ 00444 pseudo_bit_t vsd_dw16[0x00020]; 00445 /* -------------- */ 00446 pseudo_bit_t vsd_dw17[0x00020]; 00447 /* -------------- */ 00448 pseudo_bit_t vsd_dw18[0x00020]; 00449 /* -------------- */ 00450 pseudo_bit_t vsd_dw19[0x00020]; 00451 /* -------------- */ 00452 pseudo_bit_t vsd_dw20[0x00020]; 00453 /* -------------- */ 00454 pseudo_bit_t vsd_dw21[0x00020]; 00455 /* -------------- */ 00456 pseudo_bit_t vsd_dw22[0x00020]; 00457 /* -------------- */ 00458 pseudo_bit_t vsd_dw23[0x00020]; 00459 /* -------------- */ 00460 pseudo_bit_t vsd_dw24[0x00020]; 00461 /* -------------- */ 00462 pseudo_bit_t vsd_dw25[0x00020]; 00463 /* -------------- */ 00464 pseudo_bit_t vsd_dw26[0x00020]; 00465 /* -------------- */ 00466 pseudo_bit_t vsd_dw27[0x00020]; 00467 /* -------------- */ 00468 pseudo_bit_t vsd_dw28[0x00020]; 00469 /* -------------- */ 00470 pseudo_bit_t vsd_dw29[0x00020]; 00471 /* -------------- */ 00472 pseudo_bit_t vsd_dw30[0x00020]; 00473 /* -------------- */ 00474 pseudo_bit_t vsd_dw31[0x00020]; 00475 /* -------------- */ 00476 pseudo_bit_t vsd_dw32[0x00020]; 00477 /* -------------- */ 00478 pseudo_bit_t vsd_dw33[0x00020]; 00479 /* -------------- */ 00480 pseudo_bit_t vsd_dw34[0x00020]; 00481 /* -------------- */ 00482 pseudo_bit_t vsd_dw35[0x00020]; 00483 /* -------------- */ 00484 pseudo_bit_t vsd_dw36[0x00020]; 00485 /* -------------- */ 00486 pseudo_bit_t vsd_dw37[0x00020]; 00487 /* -------------- */ 00488 pseudo_bit_t vsd_dw38[0x00020]; 00489 /* -------------- */ 00490 pseudo_bit_t vsd_dw39[0x00020]; 00491 /* -------------- */ 00492 pseudo_bit_t vsd_dw40[0x00020]; 00493 /* -------------- */ 00494 pseudo_bit_t vsd_dw41[0x00020]; 00495 /* -------------- */ 00496 pseudo_bit_t vsd_dw42[0x00020]; 00497 /* -------------- */ 00498 pseudo_bit_t vsd_dw43[0x00020]; 00499 /* -------------- */ 00500 pseudo_bit_t vsd_dw44[0x00020]; 00501 /* -------------- */ 00502 pseudo_bit_t vsd_dw45[0x00020]; 00503 /* -------------- */ 00504 pseudo_bit_t vsd_dw46[0x00020]; 00505 /* -------------- */ 00506 pseudo_bit_t vsd_dw47[0x00020]; 00507 /* -------------- */ 00508 pseudo_bit_t vsd_dw48[0x00020]; 00509 /* -------------- */ 00510 pseudo_bit_t vsd_dw49[0x00020]; 00511 /* -------------- */ 00512 pseudo_bit_t vsd_dw50[0x00020]; 00513 /* -------------- */ 00514 pseudo_bit_t vsd_dw51[0x00020]; 00515 /* -------------- */ 00516 pseudo_bit_t vsd_dw52[0x00020]; 00517 /* -------------- */ 00518 pseudo_bit_t vsd_dw53[0x00020]; 00519 /* -------------- */ 00520 pseudo_bit_t vsd_dw54[0x00020]; 00521 /* -------------- */ 00522 pseudo_bit_t vsd_dw55[0x00020]; 00523 /* -------------- */ 00524 }; 00525 00526 /* UAR Parameters */ 00527 00528 struct hermonprm_uar_params_st { /* Little Endian */ 00529 pseudo_bit_t reserved0[0x00040]; 00530 /* -------------- */ 00531 pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. 00532 Size of UAR Page is 4KB*2^UAR_Page_Size */ 00533 pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ 00534 pseudo_bit_t reserved1[0x00014]; 00535 /* -------------- */ 00536 pseudo_bit_t reserved2[0x000a0]; 00537 /* -------------- */ 00538 }; 00539 00540 /* Translation and Protection Tables Parameters */ 00541 00542 struct hermonprm_tptparams_st { /* Little Endian */ 00543 pseudo_bit_t dmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32]. 00544 Entry size is 64 bytes. 00545 Table must be aligned to its size. 00546 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00547 /* -------------- */ 00548 pseudo_bit_t dmpt_base_adr_l[0x00020];/* dMPT - Memory Protection Table base physical address [31:0]. 00549 Entry size is 64 bytes. 00550 Table must be aligned to its size. 00551 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00552 /* -------------- */ 00553 pseudo_bit_t log_dmpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the dMPT table. */ 00554 pseudo_bit_t reserved0[0x00002]; 00555 pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - 00556 The field returned in RNR Naks generated when a page fault is detected. 00557 It has no effect when on-demand-paging is not used. */ 00558 pseudo_bit_t reserved1[0x00013]; 00559 /* -------------- */ 00560 pseudo_bit_t reserved2[0x00020]; 00561 /* -------------- */ 00562 pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. 00563 Table must be aligned to its size. 00564 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00565 /* -------------- */ 00566 pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. 00567 Table must be aligned to its size. 00568 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00569 /* -------------- */ 00570 pseudo_bit_t cmpt_base_adr_h[0x00020];/* cMPT - Memory Protection Table base physical address [63:32]. 00571 Entry size is 64 bytes. 00572 Table must be aligned to its size. */ 00573 /* -------------- */ 00574 pseudo_bit_t cmpt_base_adr_l[0x00020];/* cMPT - Memory Protection Table base physical address [31:0]. 00575 Entry size is 64 bytes. 00576 Table must be aligned to its size. */ 00577 /* -------------- */ 00578 }; 00579 00580 /* Multicast Support Parameters #### michal - match PRM */ 00581 00582 struct hermonprm_multicastparam_st { /* Little Endian */ 00583 pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. 00584 The base address must be aligned to the entry size. 00585 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 00586 /* -------------- */ 00587 pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. 00588 The base address must be aligned to the entry size. 00589 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 00590 /* -------------- */ 00591 pseudo_bit_t reserved0[0x00040]; 00592 /* -------------- */ 00593 pseudo_bit_t log_mc_table_entry_sz[0x00005];/* Log2 of the Size of multicast group member (MGM) entry. 00594 Must be greater than 5 (to allow CTRL and GID sections). 00595 That implies the number of QPs per MC table entry. */ 00596 pseudo_bit_t reserved1[0x0000b]; 00597 pseudo_bit_t reserved2[0x00010]; 00598 /* -------------- */ 00599 pseudo_bit_t log_mc_table_hash_sz[0x00005];/* Number of entries in multicast DGID hash table (must be power of 2) 00600 INIT_HCA - the required number of entries 00601 QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ 00602 pseudo_bit_t reserved3[0x0001b]; 00603 /* -------------- */ 00604 pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ 00605 pseudo_bit_t reserved4[0x00013]; 00606 pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function 00607 0 - Default hash function 00608 other - reserved */ 00609 pseudo_bit_t uc_group_steering[0x00001]; 00610 pseudo_bit_t reserved5[0x00004]; 00611 /* -------------- */ 00612 pseudo_bit_t reserved6[0x00020]; 00613 /* -------------- */ 00614 }; 00615 00616 /* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */ 00617 00618 struct hermonprm_qpcbaseaddr_st { /* Little Endian */ 00619 pseudo_bit_t reserved0[0x00080]; 00620 /* -------------- */ 00621 pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] 00622 Table must be aligned on its size */ 00623 /* -------------- */ 00624 pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ 00625 pseudo_bit_t qpc_base_addr_l[0x0001b];/* QPC Base Address [31:7] 00626 Table must be aligned on its size */ 00627 /* -------------- */ 00628 pseudo_bit_t reserved1[0x00040]; 00629 /* -------------- */ 00630 pseudo_bit_t reserved2[0x00040]; 00631 /* -------------- */ 00632 pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] 00633 Table must be aligned on its size 00634 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 00635 /* -------------- */ 00636 pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ 00637 pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] 00638 Table must be aligned on its size 00639 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 00640 /* -------------- */ 00641 pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] 00642 Table must be aligned on its size */ 00643 /* -------------- */ 00644 pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ 00645 pseudo_bit_t cqc_base_addr_l[0x0001b];/* CQC Base Address [31:6] 00646 Table must be aligned on its size */ 00647 /* -------------- */ 00648 pseudo_bit_t reserved3[0x00040]; 00649 /* -------------- */ 00650 pseudo_bit_t altc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32] 00651 Table has same number of entries as QPC table. 00652 Table must be aligned to entry size. */ 00653 /* -------------- */ 00654 pseudo_bit_t altc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0] 00655 Table has same number of entries as QPC table. 00656 Table must be aligned to entry size. */ 00657 /* -------------- */ 00658 pseudo_bit_t reserved4[0x00040]; 00659 /* -------------- */ 00660 pseudo_bit_t auxc_base_addr_h[0x00020]; 00661 /* -------------- */ 00662 pseudo_bit_t auxc_base_addr_l[0x00020]; 00663 /* -------------- */ 00664 pseudo_bit_t reserved5[0x00040]; 00665 /* -------------- */ 00666 pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] 00667 Address may be set to 0xFFFFFFFF if EQs are not supported. 00668 Table must be aligned to entry size. */ 00669 /* -------------- */ 00670 pseudo_bit_t log_num_of_eq[0x00005];/* Log base 2 of number of supported EQs. 00671 Must be 6 or less in InfiniHost-III-EX. */ 00672 pseudo_bit_t eqc_base_addr_l[0x0001b];/* EQC Base Address [31:6] 00673 Address may be set to 0xFFFFFFFF if EQs are not supported. 00674 Table must be aligned to entry size. */ 00675 /* -------------- */ 00676 pseudo_bit_t reserved6[0x00040]; 00677 /* -------------- */ 00678 pseudo_bit_t rdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */ 00679 /* -------------- */ 00680 pseudo_bit_t log_num_rd[0x00003]; /* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */ 00681 pseudo_bit_t reserved7[0x00002]; 00682 pseudo_bit_t rdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0]. 00683 Table must be aligned to RDB entry size (32 bytes). */ 00684 /* -------------- */ 00685 pseudo_bit_t reserved8[0x00040]; 00686 /* -------------- */ 00687 }; 00688 00689 /* Header_Log_Register */ 00690 00691 struct hermonprm_header_log_register_st { /* Little Endian */ 00692 pseudo_bit_t place_holder[0x00020]; 00693 /* -------------- */ 00694 pseudo_bit_t reserved0[0x00060]; 00695 /* -------------- */ 00696 }; 00697 00698 /* Performance Monitors */ 00699 00700 struct hermonprm_performance_monitors_st { /* Little Endian */ 00701 pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ 00702 pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ 00703 pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ 00704 pseudo_bit_t reserved0[0x00001]; 00705 pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00706 pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00707 pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00708 pseudo_bit_t reserved1[0x00001]; 00709 pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00710 pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00711 pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00712 pseudo_bit_t reserved2[0x00001]; 00713 pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00714 pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00715 pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00716 pseudo_bit_t reserved3[0x00001]; 00717 pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ 00718 pseudo_bit_t reserved4[0x00003]; 00719 pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ 00720 pseudo_bit_t reserved5[0x00003]; 00721 /* -------------- */ 00722 pseudo_bit_t clock_counter[0x00020]; 00723 /* -------------- */ 00724 pseudo_bit_t event_counter1[0x00020]; 00725 /* -------------- */ 00726 pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ 00727 /* -------------- */ 00728 }; 00729 00730 /* MLX WQE segment format */ 00731 00732 struct hermonprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ 00733 pseudo_bit_t opcode[0x00005]; /* must be 0xA = SEND */ 00734 pseudo_bit_t reserved0[0x0001a]; 00735 pseudo_bit_t owner[0x00001]; 00736 /* -------------- */ 00737 pseudo_bit_t ds[0x00006]; /* Descriptor Size */ 00738 pseudo_bit_t reserved1[0x0001a]; 00739 /* -------------- */ 00740 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 00741 pseudo_bit_t reserved2[0x00001]; 00742 pseudo_bit_t c[0x00002]; /* Create CQE (for "requested signalling" QP) */ 00743 pseudo_bit_t icrc[0x00001]; /* last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. 1 - Leave last dword as is. */ 00744 pseudo_bit_t reserved3[0x00003]; 00745 pseudo_bit_t sl[0x00004]; 00746 pseudo_bit_t max_statrate[0x00004]; 00747 pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ 00748 pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ 00749 pseudo_bit_t reserved4[0x0000e]; 00750 /* -------------- */ 00751 pseudo_bit_t reserved5[0x00010]; 00752 pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ 00753 /* -------------- */ 00754 }; 00755 00756 /* Send WQE segment format */ 00757 00758 struct hermonprm_send_wqe_segment_st { /* Little Endian */ 00759 struct hermonprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ 00760 /* -------------- */ 00761 struct hermonprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ 00762 /* -------------- */ 00763 struct hermonprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ 00764 /* -------------- */ 00765 struct hermonprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ 00766 /* -------------- */ 00767 pseudo_bit_t reserved0[0x00180]; 00768 /* -------------- */ 00769 struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ 00770 /* -------------- */ 00771 struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ 00772 /* -------------- */ 00773 struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 00774 /* -------------- */ 00775 struct hermonprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ 00776 /* -------------- */ 00777 struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ 00778 /* -------------- */ 00779 struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ 00780 /* -------------- */ 00781 pseudo_bit_t reserved1[0x00200]; 00782 /* -------------- */ 00783 }; 00784 00785 /* QP and EE Context Entry */ 00786 00787 struct hermonprm_queue_pair_ee_context_entry_st { /* Little Endian */ 00788 pseudo_bit_t reserved0[0x00008]; 00789 pseudo_bit_t reserved1[0x00001]; 00790 pseudo_bit_t reserved2[0x00002]; 00791 pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) 00792 11-Migrated 00793 00-Armed 00794 01-Rearm 00795 10-Reserved 00796 Should be set to 11 for UD QPs and for QPs which do not support APM */ 00797 pseudo_bit_t reserved3[0x00003]; 00798 pseudo_bit_t st[0x00004]; /* Transport Service Type: RC: 0, UC: 1, RD: 2, UD: 3, FCMND:4, FEXCH:5, SRC:6, MLX 7, Raw Eth 11 */ 00799 pseudo_bit_t reserved4[0x00008]; 00800 pseudo_bit_t state[0x00004]; /* QP/EE state: 00801 0 - RST 00802 1 - INIT 00803 2 - RTR 00804 3 - RTS 00805 4 - SQEr 00806 5 - SQD (Send Queue Drained) 00807 6 - ERR 00808 7 - Send Queue Draining 00809 8 - Reserved 00810 9 - Suspended 00811 A- F - Reserved 00812 (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ 00813 /* -------------- */ 00814 pseudo_bit_t pd[0x00018]; 00815 pseudo_bit_t reserved5[0x00008]; 00816 /* -------------- */ 00817 pseudo_bit_t reserved6[0x00004]; 00818 pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ 00819 pseudo_bit_t reserved7[0x00003]; 00820 pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. 00821 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 00822 pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ 00823 pseudo_bit_t reserved8[0x00001]; 00824 pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. 00825 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 00826 pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ 00827 pseudo_bit_t reserved9[0x00001]; 00828 pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. 00829 Must be equal to MTU for UD and MLX QPs. */ 00830 pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): 00831 0x1 - 256 bytes 00832 0x2 - 512 00833 0x3 - 1024 00834 0x4 - 2048 00835 other - reserved 00836 00837 Should be configured to 0x4 for UD and MLX QPs. */ 00838 /* -------------- */ 00839 pseudo_bit_t usr_page[0x00018]; /* UAR number to ring doorbells for this QP (aliased to doorbell and Blue Flame pages) */ 00840 pseudo_bit_t reserved10[0x00008]; 00841 /* -------------- */ 00842 pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained 00843 This field is valid for QUERY and ERR2RST commands only. */ 00844 pseudo_bit_t reserved11[0x00008]; 00845 /* -------------- */ 00846 pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ 00847 pseudo_bit_t reserved12[0x00008]; 00848 /* -------------- */ 00849 struct hermonprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ 00850 /* -------------- */ 00851 struct hermonprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ 00852 /* -------------- */ 00853 pseudo_bit_t reserved13[0x00003]; 00854 pseudo_bit_t reserved14[0x00001]; 00855 pseudo_bit_t reserved15[0x00001]; 00856 pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). 00857 The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ 00858 pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). 00859 The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ 00860 pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ 00861 pseudo_bit_t reserved16[0x00001]; 00862 pseudo_bit_t rnr_retry[0x00003]; 00863 pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ 00864 pseudo_bit_t reserved17[0x00002]; 00865 pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ 00866 pseudo_bit_t reserved18[0x00004]; 00867 pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ 00868 /* -------------- */ 00869 pseudo_bit_t reserved19[0x00020]; 00870 /* -------------- */ 00871 pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ 00872 pseudo_bit_t reserved20[0x00008]; 00873 /* -------------- */ 00874 pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ 00875 pseudo_bit_t reserved21[0x00008]; 00876 /* -------------- */ 00877 pseudo_bit_t reserved22[0x00040]; 00878 /* -------------- */ 00879 pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ 00880 pseudo_bit_t reserved23[0x00008]; 00881 /* -------------- */ 00882 pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ 00883 pseudo_bit_t reserved24[0x00008]; 00884 /* -------------- */ 00885 pseudo_bit_t reserved25[0x00004]; 00886 pseudo_bit_t ric[0x00001]; /* Invalid Credits. 00887 1 - place "Invalid Credits" to ACKs sent from this queue. 00888 0 - ACKs report the actual number of end to end credits on the connection. 00889 Not valid (reserved) in EE context. 00890 Must be set to 1 on QPs which are attached to SRQ. */ 00891 pseudo_bit_t reserved26[0x00001]; 00892 pseudo_bit_t page_offset[0x00006]; /* start address of wqes in first page (11:6), bits [5:0] reserved */ 00893 pseudo_bit_t reserved27[0x00001]; 00894 pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ 00895 pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ 00896 pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ 00897 pseudo_bit_t reserved28[0x00005]; 00898 pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. 00899 Must be 0 for EE context. */ 00900 pseudo_bit_t physical_function[0x00008]; 00901 /* -------------- */ 00902 pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ 00903 pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). 00904 Not valid (reserved) in EE context. */ 00905 pseudo_bit_t reserved30[0x00003]; 00906 /* -------------- */ 00907 pseudo_bit_t srcd[0x00010]; /* Scalable Reliable Connection Domain. Valid for SRC transport service */ 00908 pseudo_bit_t reserved31[0x00010]; 00909 /* -------------- */ 00910 pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ 00911 pseudo_bit_t reserved32[0x00008]; 00912 /* -------------- */ 00913 pseudo_bit_t db_record_addr_h[0x00020];/* QP DB Record physical address */ 00914 /* -------------- */ 00915 pseudo_bit_t reserved33[0x00002]; 00916 pseudo_bit_t db_record_addr_l[0x0001e];/* QP DB Record physical address */ 00917 /* -------------- */ 00918 pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. 00919 On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. 00920 Not valid (reserved) in EE context. */ 00921 /* -------------- */ 00922 pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. 00923 SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ 00924 pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ 00925 pseudo_bit_t reserved34[0x00007]; 00926 /* -------------- */ 00927 pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ 00928 pseudo_bit_t reserved35[0x00008]; 00929 /* -------------- */ 00930 pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 00931 Must be 0x0 in SQ initialization. 00932 (QUERY_QPEE only). */ 00933 pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. 00934 Must be 0x0 in RQ initialization. 00935 (QUERY_QPEE only). */ 00936 /* -------------- */ 00937 pseudo_bit_t reserved36[0x00040]; 00938 /* -------------- */ 00939 pseudo_bit_t rmc_parent_qpn[0x00018];/* reliable multicast parent queue number */ 00940 pseudo_bit_t hs[0x00001]; /* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */ 00941 pseudo_bit_t is[0x00001]; /* when set - inline scatter is enabled for this RQ */ 00942 pseudo_bit_t reserved37[0x00001]; 00943 pseudo_bit_t rme[0x00002]; /* Reliable Multicast 00944 00 - disabled 00945 01 - parent QP (requester) 00946 10 - child QP (requester) 00947 11 - responder QP 00948 Note that Reliable Multicast is a preliminary definition which can be subject to change. */ 00949 pseudo_bit_t reserved38[0x00002]; 00950 pseudo_bit_t mkey_rmp[0x00001]; /* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */ 00951 /* -------------- */ 00952 pseudo_bit_t base_mkey[0x00018]; /* Base Mkey bits [31:8]. Lower 8 bits must be zero. */ 00953 pseudo_bit_t num_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */ 00954 /* -------------- */ 00955 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 00956 pseudo_bit_t reserved39[0x00010]; 00957 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 00958 pseudo_bit_t reserved40[0x00002]; 00959 /* -------------- */ 00960 pseudo_bit_t reserved41[0x00003]; 00961 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 00962 /* -------------- */ 00963 pseudo_bit_t vft_lan[0x0000c]; 00964 pseudo_bit_t vft_prio[0x00003]; /* The Priority filed in the VFT header for FCP */ 00965 pseudo_bit_t reserved42[0x00001]; 00966 pseudo_bit_t cs_ctl[0x00009]; /* The Priority filed in the VFT header for FCP */ 00967 pseudo_bit_t reserved43[0x00006]; 00968 pseudo_bit_t ve[0x00001]; /* Should we add/check the VFT header */ 00969 /* -------------- */ 00970 pseudo_bit_t exch_base[0x00010]; /* For init QP only - The base exchanges */ 00971 pseudo_bit_t reserved44[0x00008]; 00972 pseudo_bit_t exch_size[0x00004]; /* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */ 00973 pseudo_bit_t reserved45[0x00003]; 00974 pseudo_bit_t fc[0x00001]; /* When set it mean that this QP is used for FIBRE CHANNEL. */ 00975 /* -------------- */ 00976 pseudo_bit_t remote_id[0x00018]; /* Peer NX port ID */ 00977 pseudo_bit_t reserved46[0x00008]; 00978 /* -------------- */ 00979 pseudo_bit_t fcp_mtu[0x0000a]; /* In 4*Bytes units. The MTU Size */ 00980 pseudo_bit_t reserved47[0x00006]; 00981 pseudo_bit_t my_id_indx[0x00008]; /* Index to My NX port ID table */ 00982 pseudo_bit_t vft_hop_count[0x00008];/* HopCnt value for the VFT header */ 00983 /* -------------- */ 00984 pseudo_bit_t reserved48[0x000c0]; 00985 /* -------------- */ 00986 }; 00987 00988 /* */ 00989 00990 struct hermonprm_mcg_qp_dw_st { /* Little Endian */ 00991 pseudo_bit_t qpn[0x00018]; 00992 pseudo_bit_t reserved0[0x00006]; 00993 pseudo_bit_t blck_lb[0x00001]; 00994 pseudo_bit_t reserved1[0x00001]; 00995 /* -------------- */ 00996 }; 00997 00998 /* Clear Interrupt [63:0] #### michal - match to PRM */ 00999 01000 struct hermonprm_clr_int_st { /* Little Endian */ 01001 pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] 01002 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 01003 This register is write-only. Reading from this register will cause undefined result 01004 */ 01005 /* -------------- */ 01006 pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] 01007 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 01008 This register is write-only. Reading from this register will cause undefined result */ 01009 /* -------------- */ 01010 }; 01011 01012 /* EQ Set CI DBs Table */ 01013 01014 struct hermonprm_eq_set_ci_table_st { /* Little Endian */ 01015 pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ 01016 /* -------------- */ 01017 pseudo_bit_t reserved0[0x00020]; 01018 /* -------------- */ 01019 pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ 01020 /* -------------- */ 01021 pseudo_bit_t reserved1[0x00020]; 01022 /* -------------- */ 01023 pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ 01024 /* -------------- */ 01025 pseudo_bit_t reserved2[0x00020]; 01026 /* -------------- */ 01027 pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ 01028 /* -------------- */ 01029 pseudo_bit_t reserved3[0x00020]; 01030 /* -------------- */ 01031 pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ 01032 /* -------------- */ 01033 pseudo_bit_t reserved4[0x00020]; 01034 /* -------------- */ 01035 pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ 01036 /* -------------- */ 01037 pseudo_bit_t reserved5[0x00020]; 01038 /* -------------- */ 01039 pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ 01040 /* -------------- */ 01041 pseudo_bit_t reserved6[0x00020]; 01042 /* -------------- */ 01043 pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ 01044 /* -------------- */ 01045 pseudo_bit_t reserved7[0x00020]; 01046 /* -------------- */ 01047 pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ 01048 /* -------------- */ 01049 pseudo_bit_t reserved8[0x00020]; 01050 /* -------------- */ 01051 pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ 01052 /* -------------- */ 01053 pseudo_bit_t reserved9[0x00020]; 01054 /* -------------- */ 01055 pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ 01056 /* -------------- */ 01057 pseudo_bit_t reserved10[0x00020]; 01058 /* -------------- */ 01059 pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ 01060 /* -------------- */ 01061 pseudo_bit_t reserved11[0x00020]; 01062 /* -------------- */ 01063 pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ 01064 /* -------------- */ 01065 pseudo_bit_t reserved12[0x00020]; 01066 /* -------------- */ 01067 pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ 01068 /* -------------- */ 01069 pseudo_bit_t reserved13[0x00020]; 01070 /* -------------- */ 01071 pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ 01072 /* -------------- */ 01073 pseudo_bit_t reserved14[0x00020]; 01074 /* -------------- */ 01075 pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ 01076 /* -------------- */ 01077 pseudo_bit_t reserved15[0x00020]; 01078 /* -------------- */ 01079 pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ 01080 /* -------------- */ 01081 pseudo_bit_t reserved16[0x00020]; 01082 /* -------------- */ 01083 pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ 01084 /* -------------- */ 01085 pseudo_bit_t reserved17[0x00020]; 01086 /* -------------- */ 01087 pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ 01088 /* -------------- */ 01089 pseudo_bit_t reserved18[0x00020]; 01090 /* -------------- */ 01091 pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ 01092 /* -------------- */ 01093 pseudo_bit_t reserved19[0x00020]; 01094 /* -------------- */ 01095 pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ 01096 /* -------------- */ 01097 pseudo_bit_t reserved20[0x00020]; 01098 /* -------------- */ 01099 pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ 01100 /* -------------- */ 01101 pseudo_bit_t reserved21[0x00020]; 01102 /* -------------- */ 01103 pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ 01104 /* -------------- */ 01105 pseudo_bit_t reserved22[0x00020]; 01106 /* -------------- */ 01107 pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ 01108 /* -------------- */ 01109 pseudo_bit_t reserved23[0x00020]; 01110 /* -------------- */ 01111 pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ 01112 /* -------------- */ 01113 pseudo_bit_t reserved24[0x00020]; 01114 /* -------------- */ 01115 pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ 01116 /* -------------- */ 01117 pseudo_bit_t reserved25[0x00020]; 01118 /* -------------- */ 01119 pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ 01120 /* -------------- */ 01121 pseudo_bit_t reserved26[0x00020]; 01122 /* -------------- */ 01123 pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ 01124 /* -------------- */ 01125 pseudo_bit_t reserved27[0x00020]; 01126 /* -------------- */ 01127 pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ 01128 /* -------------- */ 01129 pseudo_bit_t reserved28[0x00020]; 01130 /* -------------- */ 01131 pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ 01132 /* -------------- */ 01133 pseudo_bit_t reserved29[0x00020]; 01134 /* -------------- */ 01135 pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ 01136 /* -------------- */ 01137 pseudo_bit_t reserved30[0x00020]; 01138 /* -------------- */ 01139 pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ 01140 /* -------------- */ 01141 pseudo_bit_t reserved31[0x00020]; 01142 /* -------------- */ 01143 pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ 01144 /* -------------- */ 01145 pseudo_bit_t reserved32[0x00020]; 01146 /* -------------- */ 01147 pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ 01148 /* -------------- */ 01149 pseudo_bit_t reserved33[0x00020]; 01150 /* -------------- */ 01151 pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ 01152 /* -------------- */ 01153 pseudo_bit_t reserved34[0x00020]; 01154 /* -------------- */ 01155 pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ 01156 /* -------------- */ 01157 pseudo_bit_t reserved35[0x00020]; 01158 /* -------------- */ 01159 pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ 01160 /* -------------- */ 01161 pseudo_bit_t reserved36[0x00020]; 01162 /* -------------- */ 01163 pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ 01164 /* -------------- */ 01165 pseudo_bit_t reserved37[0x00020]; 01166 /* -------------- */ 01167 pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ 01168 /* -------------- */ 01169 pseudo_bit_t reserved38[0x00020]; 01170 /* -------------- */ 01171 pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ 01172 /* -------------- */ 01173 pseudo_bit_t reserved39[0x00020]; 01174 /* -------------- */ 01175 pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ 01176 /* -------------- */ 01177 pseudo_bit_t reserved40[0x00020]; 01178 /* -------------- */ 01179 pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ 01180 /* -------------- */ 01181 pseudo_bit_t reserved41[0x00020]; 01182 /* -------------- */ 01183 pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ 01184 /* -------------- */ 01185 pseudo_bit_t reserved42[0x00020]; 01186 /* -------------- */ 01187 pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ 01188 /* -------------- */ 01189 pseudo_bit_t reserved43[0x00020]; 01190 /* -------------- */ 01191 pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ 01192 /* -------------- */ 01193 pseudo_bit_t reserved44[0x00020]; 01194 /* -------------- */ 01195 pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ 01196 /* -------------- */ 01197 pseudo_bit_t reserved45[0x00020]; 01198 /* -------------- */ 01199 pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ 01200 /* -------------- */ 01201 pseudo_bit_t reserved46[0x00020]; 01202 /* -------------- */ 01203 pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ 01204 /* -------------- */ 01205 pseudo_bit_t reserved47[0x00020]; 01206 /* -------------- */ 01207 pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ 01208 /* -------------- */ 01209 pseudo_bit_t reserved48[0x00020]; 01210 /* -------------- */ 01211 pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ 01212 /* -------------- */ 01213 pseudo_bit_t reserved49[0x00020]; 01214 /* -------------- */ 01215 pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ 01216 /* -------------- */ 01217 pseudo_bit_t reserved50[0x00020]; 01218 /* -------------- */ 01219 pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ 01220 /* -------------- */ 01221 pseudo_bit_t reserved51[0x00020]; 01222 /* -------------- */ 01223 pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ 01224 /* -------------- */ 01225 pseudo_bit_t reserved52[0x00020]; 01226 /* -------------- */ 01227 pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ 01228 /* -------------- */ 01229 pseudo_bit_t reserved53[0x00020]; 01230 /* -------------- */ 01231 pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ 01232 /* -------------- */ 01233 pseudo_bit_t reserved54[0x00020]; 01234 /* -------------- */ 01235 pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ 01236 /* -------------- */ 01237 pseudo_bit_t reserved55[0x00020]; 01238 /* -------------- */ 01239 pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ 01240 /* -------------- */ 01241 pseudo_bit_t reserved56[0x00020]; 01242 /* -------------- */ 01243 pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ 01244 /* -------------- */ 01245 pseudo_bit_t reserved57[0x00020]; 01246 /* -------------- */ 01247 pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ 01248 /* -------------- */ 01249 pseudo_bit_t reserved58[0x00020]; 01250 /* -------------- */ 01251 pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ 01252 /* -------------- */ 01253 pseudo_bit_t reserved59[0x00020]; 01254 /* -------------- */ 01255 pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ 01256 /* -------------- */ 01257 pseudo_bit_t reserved60[0x00020]; 01258 /* -------------- */ 01259 pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ 01260 /* -------------- */ 01261 pseudo_bit_t reserved61[0x00020]; 01262 /* -------------- */ 01263 pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ 01264 /* -------------- */ 01265 pseudo_bit_t reserved62[0x00020]; 01266 /* -------------- */ 01267 pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ 01268 /* -------------- */ 01269 pseudo_bit_t reserved63[0x00020]; 01270 /* -------------- */ 01271 }; 01272 01273 /* InfiniHost-III-EX Configuration Registers #### michal - match to PRM */ 01274 01275 struct hermonprm_configuration_registers_st { /* Little Endian */ 01276 pseudo_bit_t reserved0[0x403400]; 01277 /* -------------- */ 01278 struct hermonprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ 01279 /* -------------- */ 01280 pseudo_bit_t reserved1[0x3fcb20]; 01281 /* -------------- */ 01282 }; 01283 01284 /* QP_DB_Record ### michal = gdror fixed */ 01285 01286 struct hermonprm_qp_db_record_st { /* Little Endian */ 01287 pseudo_bit_t receive_wqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ 01288 pseudo_bit_t reserved0[0x00010]; 01289 /* -------------- */ 01290 }; 01291 01292 /* CQ_ARM_DB_Record */ 01293 01294 struct hermonprm_cq_arm_db_record_st { /* Little Endian */ 01295 pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ 01296 /* -------------- */ 01297 pseudo_bit_t cmd[0x00003]; /* 0x0 - No command 01298 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. 01299 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. 01300 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated 01301 Other - Reserved */ 01302 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ 01303 pseudo_bit_t res[0x00003]; /* Must be 0x2 */ 01304 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 01305 /* -------------- */ 01306 }; 01307 01308 /* CQ_CI_DB_Record */ 01309 01310 struct hermonprm_cq_ci_db_record_st { /* Little Endian */ 01311 pseudo_bit_t counter[0x00020]; /* CQ counter */ 01312 /* -------------- */ 01313 pseudo_bit_t reserved0[0x00005]; 01314 pseudo_bit_t res[0x00003]; /* Must be 0x1 */ 01315 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 01316 /* -------------- */ 01317 }; 01318 01319 /* Virtual_Physical_Mapping */ 01320 01321 struct hermonprm_virtual_physical_mapping_st { /* Little Endian */ 01322 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ 01323 /* -------------- */ 01324 pseudo_bit_t reserved0[0x0000c]; 01325 pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ 01326 /* -------------- */ 01327 pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ 01328 /* -------------- */ 01329 pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ 01330 pseudo_bit_t reserved1[0x00006]; 01331 pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ 01332 /* -------------- */ 01333 }; 01334 01335 /* MOD_STAT_CFG #### michal - gdror fix */ 01336 01337 struct hermonprm_mod_stat_cfg_st { /* Little Endian */ 01338 pseudo_bit_t log_pg_sz[0x00008]; 01339 pseudo_bit_t log_pg_sz_m[0x00001]; 01340 pseudo_bit_t reserved0[0x00005]; 01341 pseudo_bit_t dife[0x00001]; 01342 pseudo_bit_t dife_m[0x00001]; 01343 pseudo_bit_t rx_options[0x00004]; /* number of RX options to sweep when doing SerDes parameters AutoNegotiation. */ 01344 pseudo_bit_t reserved1[0x00003]; 01345 pseudo_bit_t rx_options_m[0x00001]; /* Modify rx_options */ 01346 pseudo_bit_t tx_options[0x00004]; /* number of TX options to sweep when doing SerDes parameters AutoNegotiation. */ 01347 pseudo_bit_t reserved2[0x00003]; 01348 pseudo_bit_t tx_options_m[0x00001]; /* Modify tx_options */ 01349 /* -------------- */ 01350 pseudo_bit_t reserved3[0x00010]; 01351 pseudo_bit_t qdr_rx_options[0x00004]; 01352 pseudo_bit_t reserved4[0x00003]; 01353 pseudo_bit_t qdr_rx_options_m[0x00001]; 01354 pseudo_bit_t qdr_tx_options[0x00004]; 01355 pseudo_bit_t reserved5[0x00003]; 01356 pseudo_bit_t qdr_tx_options_m[0x00001]; 01357 /* -------------- */ 01358 pseudo_bit_t reserved6[0x00020]; 01359 /* -------------- */ 01360 pseudo_bit_t lid[0x00010]; /* default LID */ 01361 pseudo_bit_t lid_m[0x00001]; /* Modify default LID */ 01362 pseudo_bit_t reserved7[0x00003]; 01363 pseudo_bit_t port_en[0x00001]; /* enable port (E_Key) */ 01364 pseudo_bit_t port_en_m[0x00001]; /* Modify port_en */ 01365 pseudo_bit_t reserved8[0x00002]; 01366 pseudo_bit_t port_pause_mode[0x00002]; 01367 pseudo_bit_t reserved9[0x00001]; 01368 pseudo_bit_t port_pause_mode_m[0x00001]; 01369 pseudo_bit_t reserved10[0x00004]; 01370 /* -------------- */ 01371 pseudo_bit_t reserved11[0x0001f]; 01372 pseudo_bit_t guid_hi_m[0x00001]; /* Modify guid_hi */ 01373 /* -------------- */ 01374 pseudo_bit_t guid_hi[0x00020]; 01375 /* -------------- */ 01376 pseudo_bit_t reserved12[0x0001f]; 01377 pseudo_bit_t guid_lo_m[0x00001]; /* Modify guid_lo */ 01378 /* -------------- */ 01379 pseudo_bit_t guid_lo[0x00020]; 01380 /* -------------- */ 01381 pseudo_bit_t reserved13[0x0001f]; 01382 pseudo_bit_t nodeguid_hi_m[0x00001]; 01383 /* -------------- */ 01384 pseudo_bit_t nodeguid_hi[0x00020]; 01385 /* -------------- */ 01386 pseudo_bit_t reserved14[0x0001f]; 01387 pseudo_bit_t nodeguid_lo_m[0x00001]; 01388 /* -------------- */ 01389 pseudo_bit_t nodeguid_lo[0x00020]; 01390 /* -------------- */ 01391 pseudo_bit_t ob_preemp_pre[0x00005]; 01392 pseudo_bit_t reserved15[0x00003]; 01393 pseudo_bit_t ob_preemp_post[0x00005]; 01394 pseudo_bit_t reserved16[0x00003]; 01395 pseudo_bit_t ob_preemp_main[0x00005]; 01396 pseudo_bit_t reserved17[0x00003]; 01397 pseudo_bit_t ob_preemp[0x00005]; 01398 pseudo_bit_t reserved18[0x00002]; 01399 pseudo_bit_t serdes_m[0x00001]; 01400 /* -------------- */ 01401 pseudo_bit_t inbuf_ind_en[0x00003]; 01402 pseudo_bit_t reserved19[0x00001]; 01403 pseudo_bit_t sd_main[0x00004]; 01404 pseudo_bit_t reserved20[0x00004]; 01405 pseudo_bit_t sd_equal[0x00004]; 01406 pseudo_bit_t reserved21[0x00004]; 01407 pseudo_bit_t sd_mux_main[0x00002]; 01408 pseudo_bit_t reserved22[0x00002]; 01409 pseudo_bit_t mux_eq[0x00002]; 01410 pseudo_bit_t reserved23[0x00002]; 01411 pseudo_bit_t sigdet_th[0x00003]; 01412 pseudo_bit_t reserved24[0x00001]; 01413 /* -------------- */ 01414 pseudo_bit_t reserved25[0x00040]; 01415 /* -------------- */ 01416 pseudo_bit_t port_protocol[0x00008]; 01417 pseudo_bit_t port_dual[0x00001]; 01418 pseudo_bit_t reserved26[0x00006]; 01419 pseudo_bit_t port_protocol_m[0x00001]; 01420 pseudo_bit_t num_port[0x00008]; 01421 pseudo_bit_t reserved27[0x00008]; 01422 /* -------------- */ 01423 pseudo_bit_t port_protocol_vpi[0x00008]; 01424 pseudo_bit_t reserved28[0x00018]; 01425 /* -------------- */ 01426 pseudo_bit_t reserved29[0x00180]; 01427 /* -------------- */ 01428 pseudo_bit_t fw_rev_major[0x00010]; 01429 pseudo_bit_t reserved30[0x0000f]; 01430 pseudo_bit_t fw_rev_support[0x00001]; 01431 /* -------------- */ 01432 pseudo_bit_t fw_rev_minor[0x00010]; 01433 pseudo_bit_t fw_rev_subminor[0x00010]; 01434 /* -------------- */ 01435 pseudo_bit_t cmd_interface_rev[0x00010]; 01436 pseudo_bit_t reserved31[0x00010]; 01437 /* -------------- */ 01438 pseudo_bit_t reserved32[0x00060]; 01439 /* -------------- */ 01440 pseudo_bit_t mac_high[0x00010]; 01441 pseudo_bit_t reserved33[0x0000f]; 01442 pseudo_bit_t mac_m[0x00001]; 01443 /* -------------- */ 01444 pseudo_bit_t mac_low[0x00020]; 01445 /* -------------- */ 01446 pseudo_bit_t reserved34[0x00010]; 01447 pseudo_bit_t num_veps[0x00008]; 01448 pseudo_bit_t num_vep_groups[0x00008]; 01449 /* -------------- */ 01450 pseudo_bit_t reserved35[0x00020]; 01451 /* -------------- */ 01452 pseudo_bit_t reserved36[0x00018]; 01453 pseudo_bit_t outer_vlan_en[0x00001]; 01454 pseudo_bit_t reserved37[0x00002]; 01455 pseudo_bit_t outer_vlan_en_m[0x00001]; 01456 pseudo_bit_t port_net_boot[0x00001]; 01457 pseudo_bit_t reserved38[0x00002]; 01458 pseudo_bit_t port_net_boot_m[0x00001]; 01459 /* -------------- */ 01460 pseudo_bit_t reserved39[0x00060]; 01461 /* -------------- */ 01462 pseudo_bit_t port_eth_mode_capability[0x0001f]; 01463 pseudo_bit_t reserved40[0x00001]; 01464 /* -------------- */ 01465 pseudo_bit_t port_eth_mode_enabled[0x0001f]; 01466 pseudo_bit_t port_eth_mod_m[0x00001]; 01467 /* -------------- */ 01468 pseudo_bit_t port_eth_mode_current[0x0001f]; 01469 pseudo_bit_t reserved41[0x00001]; 01470 /* -------------- */ 01471 pseudo_bit_t reserved42[0x00220]; 01472 }; 01473 01474 /* SRQ Context */ 01475 01476 struct hermonprm_srq_context_st { /* Little Endian */ 01477 pseudo_bit_t srqn[0x00018]; /* SRQ number */ 01478 pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. 01479 Maximum value is 0x10, i.e. 16M WQEs. */ 01480 pseudo_bit_t state[0x00004]; /* SRQ State: 01481 1111 - SW Ownership 01482 0000 - HW Ownership 01483 0001 - Error 01484 Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 01485 /* -------------- */ 01486 pseudo_bit_t src_domain[0x00010]; /* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */ 01487 pseudo_bit_t reserved0[0x00008]; 01488 pseudo_bit_t log_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ 01489 pseudo_bit_t reserved1[0x00005]; 01490 /* -------------- */ 01491 pseudo_bit_t cqn[0x00018]; /* Completion Queue to report SRC messages directed to this SRQ. */ 01492 pseudo_bit_t page_offset[0x00006]; /* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,“Work Queue Buffer Structure”) */ 01493 pseudo_bit_t reserved2[0x00002]; 01494 /* -------------- */ 01495 pseudo_bit_t reserved3[0x00020]; 01496 /* -------------- */ 01497 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 01498 pseudo_bit_t reserved4[0x00010]; 01499 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 01500 pseudo_bit_t reserved5[0x00002]; 01501 /* -------------- */ 01502 pseudo_bit_t reserved6[0x00003]; 01503 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 01504 /* -------------- */ 01505 pseudo_bit_t pd[0x00018]; /* SRQ protection domain */ 01506 pseudo_bit_t reserved7[0x00008]; 01507 /* -------------- */ 01508 pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 01509 pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 01510 /* -------------- */ 01511 pseudo_bit_t srq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */ 01512 pseudo_bit_t reserved8[0x00010]; 01513 /* -------------- */ 01514 pseudo_bit_t reserved9[0x00020]; 01515 /* -------------- */ 01516 pseudo_bit_t db_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */ 01517 /* -------------- */ 01518 pseudo_bit_t reserved10[0x00002]; 01519 pseudo_bit_t db_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */ 01520 /* -------------- */ 01521 }; 01522 01523 /* PBL */ 01524 01525 struct hermonprm_pbl_st { /* Little Endian */ 01526 pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ 01527 /* -------------- */ 01528 pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ 01529 /* -------------- */ 01530 pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ 01531 /* -------------- */ 01532 pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ 01533 /* -------------- */ 01534 pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ 01535 /* -------------- */ 01536 pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ 01537 /* -------------- */ 01538 pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ 01539 /* -------------- */ 01540 pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ 01541 /* -------------- */ 01542 }; 01543 01544 /* Performance Counters #### michal - gdror fixed */ 01545 01546 struct hermonprm_performance_counters_st { /* Little Endian */ 01547 pseudo_bit_t reserved0[0x00080]; 01548 /* -------------- */ 01549 pseudo_bit_t reserved1[0x00080]; 01550 /* -------------- */ 01551 pseudo_bit_t reserved2[0x00080]; 01552 /* -------------- */ 01553 pseudo_bit_t reserved3[0x00060]; 01554 /* -------------- */ 01555 pseudo_bit_t reserved4[0x00620]; 01556 /* -------------- */ 01557 }; 01558 01559 /* Transport and CI Error Counters */ 01560 01561 struct hermonprm_transport_and_ci_error_counters_st { /* Little Endian */ 01562 pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ 01563 /* -------------- */ 01564 pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ 01565 /* -------------- */ 01566 pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ 01567 /* -------------- */ 01568 pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ 01569 /* -------------- */ 01570 pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ 01571 /* -------------- */ 01572 pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ 01573 /* -------------- */ 01574 pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ 01575 /* -------------- */ 01576 pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ 01577 /* -------------- */ 01578 pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. 01579 Incremented each time a CQE with error is generated */ 01580 /* -------------- */ 01581 pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. 01582 Incremented each time a CQE with error is generated */ 01583 /* -------------- */ 01584 pseudo_bit_t reserved0[0x00020]; 01585 /* -------------- */ 01586 pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ 01587 /* -------------- */ 01588 pseudo_bit_t reserved1[0x00020]; 01589 /* -------------- */ 01590 pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ 01591 /* -------------- */ 01592 pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ 01593 /* -------------- */ 01594 pseudo_bit_t reserved2[0x00040]; 01595 /* -------------- */ 01596 pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors 01597 NAK-Invalid Request on: 01598 1. Unsupported OpCode: Responder detected an unsupported OpCode. 01599 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such 01600 as a missing "Last" packet. 01601 Note: there is no PSN error, thus this does not indicate a dropped packet. */ 01602 /* -------------- */ 01603 pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. 01604 NAK may or may not be sent. 01605 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): 01606 Inbound request OpCode was either reserved, or was for a function not supported by this 01607 QP. (E.g. RDMA or ATOMIC on QP not set up for this). 01608 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. 01609 3. Too many RDMA READ or ATOMIC Requests: There were more requests received 01610 and not ACKed than allowed for the connection. 01611 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder 01612 detected an error in the sequence of OpCodes; a missing "Last" packet 01613 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder 01614 detected an error in the sequence of OpCodes; a missing "First" packet 01615 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able 01616 buffer space. 01617 7. Length error: RDMA WRITE request message contained too much or too little pay-load 01618 data compared to the DMA length advertised in the first or only packet. 01619 8. Length error: Payload length was not consistent with the opcode: 01620 a: 0 byte <= "only" <= PMTU bytes 01621 b: ("first" or "middle") == PMTU bytes 01622 c: 1byte <= "last" <= PMTU bytes 01623 9. Length error: Inbound message exceeded the size supported by the CA port. */ 01624 /* -------------- */ 01625 pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. 01626 NAK-Remote Access Error on: 01627 R_Key Violation: Responder detected an invalid R_Key while executing an RDMA 01628 Request. */ 01629 /* -------------- */ 01630 pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. 01631 R_Key Violation Responder detected an R_Key violation while executing an RDMA 01632 request. 01633 NAK may or may not be sent. */ 01634 /* -------------- */ 01635 pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. 01636 NAK-Remote Operation Error on: 01637 Remote Operation Error: Responder encountered an error, (local to the responder), 01638 which prevented it from completing the request. */ 01639 /* -------------- */ 01640 pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. 01641 NAK-Remote Operation Error on: 01642 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing 01643 the packet. 01644 2. Remote Operation Error: Responder encountered an error, (local to the responder), 01645 which prevented it from completing the request. */ 01646 /* -------------- */ 01647 pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ 01648 /* -------------- */ 01649 pseudo_bit_t reserved3[0x00020]; 01650 /* -------------- */ 01651 pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ 01652 /* -------------- */ 01653 pseudo_bit_t rq_num_rnr[0x00020]; /* Responder - the number of RNR Naks sent */ 01654 /* -------------- */ 01655 pseudo_bit_t sq_num_rnr[0x00020]; /* Requester - the number of RNR Naks received */ 01656 /* -------------- */ 01657 pseudo_bit_t reserved4[0x00040]; 01658 /* -------------- */ 01659 pseudo_bit_t reserved5[0x00020]; 01660 /* -------------- */ 01661 pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ 01662 /* -------------- */ 01663 pseudo_bit_t reserved6[0x00020]; 01664 /* -------------- */ 01665 pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ 01666 /* -------------- */ 01667 pseudo_bit_t reserved7[0x00020]; 01668 /* -------------- */ 01669 pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ 01670 /* -------------- */ 01671 pseudo_bit_t reserved8[0x00380]; 01672 /* -------------- */ 01673 pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ 01674 /* -------------- */ 01675 pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ 01676 /* -------------- */ 01677 pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ 01678 /* -------------- */ 01679 pseudo_bit_t reserved9[0x00020]; 01680 /* -------------- */ 01681 pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ 01682 /* -------------- */ 01683 pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ 01684 /* -------------- */ 01685 pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ 01686 /* -------------- */ 01687 pseudo_bit_t reserved10[0x00020]; 01688 /* -------------- */ 01689 pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ 01690 /* -------------- */ 01691 pseudo_bit_t reserved11[0x003e0]; 01692 /* -------------- */ 01693 pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ 01694 /* -------------- */ 01695 pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ 01696 /* -------------- */ 01697 pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ 01698 /* -------------- */ 01699 pseudo_bit_t reserved12[0x002a0]; 01700 /* -------------- */ 01701 }; 01702 01703 /* Event_data Field - HCR Completion Event #### michal - match PRM */ 01704 01705 struct hermonprm_hcr_completion_event_st { /* Little Endian */ 01706 pseudo_bit_t token[0x00010]; /* HCR Token */ 01707 pseudo_bit_t reserved0[0x00010]; 01708 /* -------------- */ 01709 pseudo_bit_t reserved1[0x00020]; 01710 /* -------------- */ 01711 pseudo_bit_t status[0x00008]; /* HCR Status */ 01712 pseudo_bit_t reserved2[0x00018]; 01713 /* -------------- */ 01714 pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ 01715 /* -------------- */ 01716 pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ 01717 /* -------------- */ 01718 pseudo_bit_t reserved3[0x00020]; 01719 /* -------------- */ 01720 }; 01721 01722 /* Completion with Error CQE #### michal - gdror fixed */ 01723 01724 struct hermonprm_completion_with_error_st { /* Little Endian */ 01725 pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 01726 pseudo_bit_t reserved0[0x00008]; 01727 /* -------------- */ 01728 pseudo_bit_t reserved1[0x000a0]; 01729 /* -------------- */ 01730 pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: 01731 0x01 - Local Length Error 01732 0x02 - Local QP Operation Error 01733 0x03 - Local EE Context Operation Error 01734 0x04 - Local Protection Error 01735 0x05 - Work Request Flushed Error 01736 0x06 - Memory Window Bind Error 01737 0x10 - Bad Response Error 01738 0x11 - Local Access Error 01739 0x12 - Remote Invalid Request Error 01740 0x13 - Remote Access Error 01741 0x14 - Remote Operation Error 01742 0x15 - Transport Retry Counter Exceeded 01743 0x16 - RNR Retry Counter Exceeded 01744 0x20 - Local RDD Violation Error 01745 0x21 - Remote Invalid RD Request 01746 0x22 - Remote Aborted Error 01747 0x23 - Invalid EE Context Number 01748 0x24 - Invalid EE Context State 01749 other - Reserved 01750 Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ 01751 pseudo_bit_t vendor_error_syndrome[0x00008]; 01752 pseudo_bit_t wqe_counter[0x00010]; 01753 /* -------------- */ 01754 pseudo_bit_t opcode[0x00005]; /* The opcode of WQE completion is reported for. 01755 01756 The following values are reported in case of completion with error: 01757 0xFE - For completion with error on Receive Queues 01758 0xFF - For completion with error on Send Queues */ 01759 pseudo_bit_t reserved2[0x00001]; 01760 pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 01761 pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 01762 pseudo_bit_t reserved3[0x00018]; 01763 /* -------------- */ 01764 }; 01765 01766 /* Resize CQ Input Mailbox */ 01767 01768 struct hermonprm_resize_cq_st { /* Little Endian */ 01769 pseudo_bit_t reserved0[0x00040]; 01770 /* -------------- */ 01771 pseudo_bit_t reserved1[0x00006]; 01772 pseudo_bit_t page_offset[0x00006]; 01773 pseudo_bit_t reserved2[0x00014]; 01774 /* -------------- */ 01775 pseudo_bit_t reserved3[0x00018]; 01776 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ 01777 pseudo_bit_t reserved4[0x00003]; 01778 /* -------------- */ 01779 pseudo_bit_t reserved5[0x00020]; 01780 /* -------------- */ 01781 pseudo_bit_t mtt_base_addr_h[0x00008]; 01782 pseudo_bit_t reserved6[0x00010]; 01783 pseudo_bit_t log2_page_size[0x00006]; 01784 pseudo_bit_t reserved7[0x00002]; 01785 /* -------------- */ 01786 pseudo_bit_t reserved8[0x00003]; 01787 pseudo_bit_t mtt_base_addr_l[0x0001d]; 01788 /* -------------- */ 01789 pseudo_bit_t reserved9[0x00020]; 01790 /* -------------- */ 01791 pseudo_bit_t reserved10[0x00100]; 01792 /* -------------- */ 01793 }; 01794 01795 /* MAD_IFC Input Modifier */ 01796 01797 struct hermonprm_mad_ifc_input_modifier_st { /* Little Endian */ 01798 pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ 01799 pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. 01800 Required for trap generation when BKey check is enabled and for global routed packets. */ 01801 pseudo_bit_t reserved0[0x00007]; 01802 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 01803 This field is required for trap generation upon MKey/BKey validation. */ 01804 /* -------------- */ 01805 }; 01806 01807 /* MAD_IFC Input Mailbox ###michal -gdror fixed */ 01808 01809 struct hermonprm_mad_ifc_st { /* Little Endian */ 01810 pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ 01811 /* -------------- */ 01812 pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. 01813 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01814 pseudo_bit_t reserved0[0x00008]; 01815 /* -------------- */ 01816 pseudo_bit_t reserved1[0x00020]; 01817 /* -------------- */ 01818 pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. 01819 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01820 pseudo_bit_t reserved2[0x00008]; 01821 /* -------------- */ 01822 pseudo_bit_t reserved3[0x00010]; 01823 pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. 01824 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01825 pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. 01826 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01827 pseudo_bit_t reserved4[0x00004]; 01828 pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. 01829 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01830 /* -------------- */ 01831 pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. 01832 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01833 pseudo_bit_t reserved5[0x00010]; 01834 /* -------------- */ 01835 pseudo_bit_t reserved6[0x00160]; 01836 /* -------------- */ 01837 pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. 01838 Valid if Mad_extended_info bit (in the input modifier) and g bit are set. 01839 Otherwise this field is reserved. */ 01840 /* -------------- */ 01841 pseudo_bit_t reserved7[0x004c0]; 01842 /* -------------- */ 01843 }; 01844 01845 /* Query Debug Message #### michal - gdror fixed */ 01846 01847 struct hermonprm_query_debug_msg_st { /* Little Endian */ 01848 pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ 01849 /* -------------- */ 01850 pseudo_bit_t v[0x00001]; /* Physical translation is valid */ 01851 pseudo_bit_t reserved0[0x0000b]; 01852 pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ 01853 /* -------------- */ 01854 pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ 01855 /* -------------- */ 01856 pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ 01857 /* -------------- */ 01858 pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ 01859 /* -------------- */ 01860 pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ 01861 /* -------------- */ 01862 pseudo_bit_t reserved1[0x000c0]; 01863 /* -------------- */ 01864 pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ 01865 /* -------------- */ 01866 pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ 01867 /* -------------- */ 01868 pseudo_bit_t reserved2[0x00040]; 01869 /* -------------- */ 01870 pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ 01871 /* -------------- */ 01872 pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ 01873 /* -------------- */ 01874 pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ 01875 /* -------------- */ 01876 pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ 01877 /* -------------- */ 01878 pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ 01879 /* -------------- */ 01880 pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ 01881 /* -------------- */ 01882 pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ 01883 /* -------------- */ 01884 pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ 01885 /* -------------- */ 01886 pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ 01887 /* -------------- */ 01888 pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ 01889 /* -------------- */ 01890 pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ 01891 /* -------------- */ 01892 pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ 01893 /* -------------- */ 01894 pseudo_bit_t reserved3[0x00080]; 01895 /* -------------- */ 01896 pseudo_bit_t hw_buff_addr[0x00020]; /* Dror Mux Bohrer tracer */ 01897 /* -------------- */ 01898 pseudo_bit_t hw_buff_size[0x00020]; 01899 /* -------------- */ 01900 pseudo_bit_t reserved4[0x003c0]; 01901 /* -------------- */ 01902 }; 01903 01904 /* User Access Region */ 01905 01906 struct hermonprm_uar_st { /* Little Endian */ 01907 struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ 01908 /* -------------- */ 01909 struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 01910 /* -------------- */ 01911 pseudo_bit_t reserved0[0x00040]; 01912 /* -------------- */ 01913 struct hermonprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ 01914 /* -------------- */ 01915 pseudo_bit_t reserved1[0x03ec0]; 01916 /* -------------- */ 01917 }; 01918 01919 /* Receive doorbell */ 01920 01921 struct hermonprm_receive_doorbell_st { /* Little Endian */ 01922 pseudo_bit_t reserved0[0x00008]; 01923 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ 01924 pseudo_bit_t reserved1[0x00008]; 01925 /* -------------- */ 01926 pseudo_bit_t reserved2[0x00005]; 01927 pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ 01928 pseudo_bit_t reserved3[0x00002]; 01929 pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ 01930 /* -------------- */ 01931 }; 01932 01933 /* SET_IB Parameters */ 01934 01935 struct hermonprm_set_ib_st { /* Little Endian */ 01936 pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ 01937 pseudo_bit_t reserved0[0x00011]; 01938 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 01939 system_image_guid and sig must be the same for all ports. */ 01940 pseudo_bit_t reserved1[0x0000d]; 01941 /* -------------- */ 01942 pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ 01943 /* -------------- */ 01944 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 01945 Must be the same for both ports. */ 01946 /* -------------- */ 01947 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 01948 Must be the same for both ports. */ 01949 /* -------------- */ 01950 pseudo_bit_t reserved2[0x00180]; 01951 /* -------------- */ 01952 }; 01953 01954 /* Multicast Group Member #### michal - gdror fixed */ 01955 01956 struct hermonprm_mgm_entry_st { /* Little Endian */ 01957 pseudo_bit_t reserved0[0x00006]; 01958 pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. 01959 The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. 01960 next_gid_index=0 means end of the chain. */ 01961 /* -------------- */ 01962 pseudo_bit_t reserved1[0x00060]; 01963 /* -------------- */ 01964 pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. 01965 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01966 /* -------------- */ 01967 pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. 01968 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01969 /* -------------- */ 01970 pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. 01971 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01972 /* -------------- */ 01973 pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. 01974 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01975 /* -------------- */ 01976 struct hermonprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ 01977 /* -------------- */ 01978 struct hermonprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ 01979 /* -------------- */ 01980 struct hermonprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ 01981 /* -------------- */ 01982 struct hermonprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ 01983 /* -------------- */ 01984 struct hermonprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ 01985 /* -------------- */ 01986 struct hermonprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ 01987 /* -------------- */ 01988 struct hermonprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ 01989 /* -------------- */ 01990 struct hermonprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ 01991 /* -------------- */ 01992 }; 01993 01994 /* INIT_PORT Parameters #### michal - match PRM */ 01995 01996 struct hermonprm_init_port_st { /* Little Endian */ 01997 pseudo_bit_t reserved0[0x00004]; 01998 pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. 01999 Legal values are 1,2,4 and 8. */ 02000 pseudo_bit_t port_width_cap[0x00004];/* IB Port Width 02001 1 - 1x 02002 3 - 1x, 4x 02003 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) 02004 else - Reserved */ 02005 pseudo_bit_t reserved1[0x00004]; 02006 pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ 02007 pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. 02008 node_guid and ng must be the same for all ports. */ 02009 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 02010 system_image_guid and sig must be the same for all ports. */ 02011 pseudo_bit_t reserved2[0x0000d]; 02012 /* -------------- */ 02013 pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ 02014 pseudo_bit_t mtu[0x00010]; /* Maximum MTU Supported in bytes 02015 must be: 256, 512, 1024, 2048 or 4096 02016 For Eth port, can be any 02017 Field must not cross device capabilities as reported 02018 */ 02019 /* -------------- */ 02020 pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. 02021 Must be the same for both ports. */ 02022 pseudo_bit_t reserved3[0x00010]; 02023 /* -------------- */ 02024 pseudo_bit_t reserved4[0x00020]; 02025 /* -------------- */ 02026 pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ 02027 /* -------------- */ 02028 pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ 02029 /* -------------- */ 02030 pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set 02031 Must be the same for both ports. */ 02032 /* -------------- */ 02033 pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set 02034 Must be the same for both ports. */ 02035 /* -------------- */ 02036 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 02037 Must be the same for both ports. */ 02038 /* -------------- */ 02039 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 02040 Must be the same for both ports. */ 02041 /* -------------- */ 02042 pseudo_bit_t reserved5[0x006c0]; 02043 /* -------------- */ 02044 }; 02045 02046 /* Query Device Capablities #### michal - gdror fixed */ 02047 02048 struct hermonprm_query_dev_cap_st { /* Little Endian */ 02049 pseudo_bit_t reserved0[0x00080]; 02050 /* -------------- */ 02051 pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ 02052 pseudo_bit_t reserved1[0x00003]; 02053 pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use 02054 The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ 02055 pseudo_bit_t reserved2[0x00004]; 02056 pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ 02057 pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ 02058 /* -------------- */ 02059 pseudo_bit_t log_max_scqs[0x00004]; /* log base 2 of number of supported schedule queues */ 02060 pseudo_bit_t reserved3[0x00004]; 02061 pseudo_bit_t num_rsvd_scqs[0x00006]; 02062 pseudo_bit_t reserved4[0x00002]; 02063 pseudo_bit_t log_max_srqs[0x00005]; 02064 pseudo_bit_t reserved5[0x00007]; 02065 pseudo_bit_t log2_rsvd_srqs[0x00004]; 02066 /* -------------- */ 02067 pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ 02068 pseudo_bit_t reserved6[0x00003]; 02069 pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use 02070 The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ 02071 pseudo_bit_t reserved7[0x00004]; 02072 pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ 02073 pseudo_bit_t num_rsvd_eqs[0x00008]; /* The number of EQs reserved for firmware use 02074 The reserved resources are numbered from 0 to num_rsvd_eqs-1 02075 If 0 - no resources are reserved. */ 02076 /* -------------- */ 02077 pseudo_bit_t log_max_eq[0x00004]; /* Log2 of the Maximum number of EQs */ 02078 pseudo_bit_t reserved9[0x00004]; 02079 pseudo_bit_t log2_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use 02080 The reserved resources are numbered from 0 to num_rsvd_eqs-1 02081 If 0 - no resources are reserved. */ 02082 pseudo_bit_t reserved10[0x00004]; 02083 pseudo_bit_t log_max_d_mpts[0x00006];/* Log (base 2) of the maximum number of data MPT entries (the number of Regions/Windows) */ 02084 pseudo_bit_t reserved11[0x00002]; 02085 pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ 02086 /* -------------- */ 02087 pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ 02088 pseudo_bit_t reserved12[0x00002]; 02089 pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use 02090 The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ 02091 pseudo_bit_t reserved13[0x00004]; 02092 pseudo_bit_t log_max_mrw_sz[0x00007];/* Log2 of the Maximum Size of Memory Region/Window. is it in PRM layout? */ 02093 pseudo_bit_t reserved14[0x00005]; 02094 pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use 02095 The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 02096 */ 02097 /* -------------- */ 02098 pseudo_bit_t reserved15[0x00020]; 02099 /* -------------- */ 02100 pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ 02101 pseudo_bit_t reserved16[0x0000a]; 02102 pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ 02103 pseudo_bit_t reserved17[0x0000a]; 02104 /* -------------- */ 02105 pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ 02106 pseudo_bit_t reserved18[0x0001a]; 02107 /* -------------- */ 02108 pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ 02109 pseudo_bit_t reserved19[0x0001f]; 02110 /* -------------- */ 02111 pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ 02112 pseudo_bit_t reserved47[0x00004]; 02113 pseudo_bit_t pci_pf_num[0x00008]; /* Number of supported physical functions */ 02114 pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. 02115 The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ 02116 pseudo_bit_t port_type[0x00004]; /* Hermon New. bit per port. bit0 is first port. value '1' is ehternet. '0' is IB */ 02117 pseudo_bit_t reserved20[0x00004]; 02118 pseudo_bit_t w[0x00001]; /* Hermon New. 10GB eth support */ 02119 pseudo_bit_t j[0x00001]; /* Hermon New. Jumbo frame support */ 02120 pseudo_bit_t reserved21[0x00001]; 02121 /* -------------- */ 02122 pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ 02123 pseudo_bit_t reserved22[0x00004]; 02124 pseudo_bit_t log_ethtype[0x00004]; /* Hermon New. log2 eth type table size */ 02125 pseudo_bit_t reserved23[0x00004]; 02126 pseudo_bit_t log_drain_size[0x00008];/* Log (base 2) of minimum size of the NoDropVLDrain buffer, specified in 4Kpages units */ 02127 pseudo_bit_t log_max_msg[0x00005]; /* Log (base 2) of the maximum message size supported by the device */ 02128 pseudo_bit_t reserved24[0x00003]; 02129 /* -------------- */ 02130 pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ 02131 pseudo_bit_t reserved25[0x0000c]; 02132 pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported 02133 bit 0 - full bw 02134 bit 1 - 1/4 bw 02135 bit 2 - 1/8 bw 02136 bit 3 - 1/2 bw; */ 02137 /* -------------- */ 02138 pseudo_bit_t reserved26[0x00008]; 02139 pseudo_bit_t rss_udp[0x00001]; 02140 pseudo_bit_t vep_uc_steering[0x00001]; 02141 pseudo_bit_t vep_mc_steering[0x00001]; 02142 pseudo_bit_t reserved27[0x00015]; 02143 02144 /* -------------- */ 02145 pseudo_bit_t rc[0x00001]; /* RC Transport supported */ 02146 pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ 02147 pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ 02148 pseudo_bit_t src[0x00001]; /* SRC Transport Supported. Hermon New instead of RD. */ 02149 pseudo_bit_t rcm[0x00001]; /* Reliable Multicast support. Hermon New instead of IPv6 Transport Supported */ 02150 pseudo_bit_t fcoib[0x00001]; /* Hermon New */ 02151 pseudo_bit_t srq[0x00001]; /* SRQ is supported 02152 */ 02153 pseudo_bit_t checksum[0x00001]; /* IP over IB checksum is supported */ 02154 pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ 02155 pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ 02156 pseudo_bit_t vmm[0x00001]; /* Hermon New */ 02157 pseudo_bit_t fcoe[0x00001]; 02158 pseudo_bit_t dpdp[0x00001]; /* Dual Port Different Protocols */ 02159 pseudo_bit_t raw_ethertype[0x00001]; 02160 pseudo_bit_t raw_ipv6[0x00001]; 02161 pseudo_bit_t blh[0x00001]; 02162 pseudo_bit_t mw[0x00001]; /* Memory windows supported */ 02163 pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ 02164 pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ 02165 pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ 02166 pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ 02167 pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ 02168 pseudo_bit_t reserved28[0x00002]; 02169 pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ 02170 pseudo_bit_t r[0x00001]; /* Router mode supported */ 02171 pseudo_bit_t reserved29[0x00006]; 02172 /* -------------- */ 02173 pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). 02174 For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ 02175 pseudo_bit_t reserved30[0x00008]; 02176 pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ 02177 pseudo_bit_t reserved31[0x00006]; 02178 pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use 02179 The reserved resources are numbered from 0 to num_reserved_uars-1 02180 Note that UAR number num_reserved_uars is always for the kernel. */ 02181 /* -------------- */ 02182 pseudo_bit_t log_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */ 02183 pseudo_bit_t reserved32[0x00002]; 02184 pseudo_bit_t log_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */ 02185 pseudo_bit_t reserved33[0x00002]; 02186 pseudo_bit_t log_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */ 02187 pseudo_bit_t reserved34[0x0000a]; 02188 pseudo_bit_t bf[0x00001]; /* If set to "1" then BlueFlame may be used. */ 02189 /* -------------- */ 02190 pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ 02191 pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ 02192 pseudo_bit_t reserved35[0x00008]; 02193 /* -------------- */ 02194 pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ 02195 pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ 02196 pseudo_bit_t reserved36[0x00008]; 02197 /* -------------- */ 02198 pseudo_bit_t reserved37[0x00001]; 02199 pseudo_bit_t fexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */ 02200 pseudo_bit_t fcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */ 02201 pseudo_bit_t fexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */ 02202 /* -------------- */ 02203 pseudo_bit_t reserved38[0x00020]; 02204 /* -------------- */ 02205 pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ 02206 pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. 02207 The reserved resources are numbered from 0 to num_reserved_mcgs-1 02208 If 0 - no resources are reserved. */ 02209 pseudo_bit_t reserved39[0x00004]; 02210 pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ 02211 pseudo_bit_t reserved40[0x00008]; 02212 /* -------------- */ 02213 pseudo_bit_t log_max_srcds[0x00004];/* Log2 of the maximum number of SRC Domains */ 02214 pseudo_bit_t reserved41[0x00008]; 02215 pseudo_bit_t num_rsvd_scrds[0x00004];/* The number of SRCDs reserved for firmware use 02216 The reserved resources are numbered from 0 to num_reserved_rdds-1. 02217 If 0 - no resources are reserved. */ 02218 pseudo_bit_t log_max_pd[0x00005]; /* Log2 of the maximum number of PDs */ 02219 pseudo_bit_t reserved42[0x00007]; 02220 pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use 02221 The reserved resources are numbered from 0 to num_reserved_pds-1 02222 If 0 - no resources are reserved. */ 02223 /* -------------- */ 02224 pseudo_bit_t reserved43[0x000c0]; 02225 /* -------------- */ 02226 pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device 02227 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 02228 pseudo_bit_t rdmardc_entry_sz[0x00010];/* RdmaRdC Entry Size for the device 02229 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 02230 /* -------------- */ 02231 pseudo_bit_t altc_entry_sz[0x00010];/* Extended QPC entry size for the device 02232 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02233 pseudo_bit_t aux_entry_sz[0x00010]; /* Auxilary context entry size */ 02234 /* -------------- */ 02235 pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device 02236 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02237 pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device 02238 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02239 /* -------------- */ 02240 pseudo_bit_t c_mpt_entry_sz[0x00010];/* cMPT entry size in Bytes for the device. 02241 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02242 pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device 02243 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02244 /* -------------- */ 02245 pseudo_bit_t d_mpt_entry_sz[0x00010];/* dMPT entry size in Bytes for the device. 02246 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02247 pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. 02248 For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ 02249 /* -------------- */ 02250 pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ 02251 pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: 02252 0 - Type 2A - QP Number Association; or 02253 1 - Type 2B - QP Number and PD Association. */ 02254 pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ 02255 pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. */ 02256 pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ 02257 pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ 02258 pseudo_bit_t reserved44[0x0001a]; 02259 /* -------------- */ 02260 pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ 02261 /* -------------- */ 02262 pseudo_bit_t reserved45[0x00020]; 02263 /* -------------- */ 02264 pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ 02265 /* -------------- */ 02266 pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ 02267 /* -------------- */ 02268 pseudo_bit_t reserved46[0x002c0]; 02269 /* -------------- */ 02270 }; 02271 02272 /* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */ 02273 02274 struct hermonprm_query_adapter_st { /* Little Endian */ 02275 pseudo_bit_t reserved0[0x00080]; 02276 /* -------------- */ 02277 pseudo_bit_t reserved1[0x00018]; 02278 pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ 02279 /* -------------- */ 02280 pseudo_bit_t reserved2[0x00060]; 02281 /* -------------- */ 02282 struct hermonprm_vsd_st vsd; /* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */ 02283 /* -------------- */ 02284 }; 02285 02286 /* QUERY_FW Parameters Block #### michal - doesn't match PRM */ 02287 02288 struct hermonprm_query_fw_st { /* Little Endian */ 02289 pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ 02290 pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ 02291 /* -------------- */ 02292 pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ 02293 pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ 02294 /* -------------- */ 02295 pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ 02296 pseudo_bit_t reserved0[0x00010]; 02297 /* -------------- */ 02298 pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ 02299 pseudo_bit_t reserved1[0x00017]; 02300 pseudo_bit_t dt[0x00001]; /* Debug Trace Support 02301 0 - Debug trace is not supported 02302 1 - Debug trace is supported */ 02303 /* -------------- */ 02304 pseudo_bit_t reserved2[0x00001]; 02305 pseudo_bit_t ccq[0x00001]; /* CCQ support */ 02306 pseudo_bit_t reserved3[0x00006]; 02307 pseudo_bit_t fw_seconds[0x00008]; /* FW timestamp - seconds. Dispalyed as Hexadecimal number */ 02308 pseudo_bit_t fw_minutes[0x00008]; /* FW timestamp - minutes. Dispalyed as Hexadecimal number */ 02309 pseudo_bit_t fw_hour[0x00008]; /* FW timestamp - hour. Dispalyed as Hexadecimal number */ 02310 /* -------------- */ 02311 pseudo_bit_t fw_day[0x00008]; /* FW timestamp - day. Dispalyed as Hexadecimal number */ 02312 pseudo_bit_t fw_month[0x00008]; /* FW timestamp - month. Dispalyed as Hexadecimal number */ 02313 pseudo_bit_t fw_year[0x00010]; /* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */ 02314 /* -------------- */ 02315 pseudo_bit_t reserved4[0x00040]; 02316 /* -------------- */ 02317 pseudo_bit_t clr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 02318 /* -------------- */ 02319 pseudo_bit_t clr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 02320 /* -------------- */ 02321 pseudo_bit_t reserved5[0x0001e]; 02322 pseudo_bit_t clr_int_bar[0x00002]; /* PCI base address register (BAR) where clr_int register is located. 02323 00 - BAR 0-1 02324 01 - BAR 2-3 02325 10 - BAR 4-5 02326 11 - Reserved 02327 The PCI BARs of ConnectX are 64 bit BARs. 02328 In ConnectX, clr_int register is located on BAR 0-1. */ 02329 /* -------------- */ 02330 pseudo_bit_t reserved6[0x00020]; 02331 /* -------------- */ 02332 pseudo_bit_t error_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */ 02333 /* -------------- */ 02334 pseudo_bit_t error_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */ 02335 /* -------------- */ 02336 pseudo_bit_t error_buf_size[0x00020];/* Size in words */ 02337 /* -------------- */ 02338 pseudo_bit_t reserved7[0x0001e]; 02339 pseudo_bit_t error_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located. 02340 00 - BAR 0-1 02341 01 - BAR 2-3 02342 10 - BAR 4-5 02343 11 - Reserved 02344 The PCI BARs of ConnectX are 64 bit BARs. 02345 In ConnectX, error_buf register is located on BAR 0-1. */ 02346 /* -------------- */ 02347 pseudo_bit_t reserved8[0x00600]; 02348 /* -------------- */ 02349 }; 02350 02351 /* Memory Access Parameters for UD Address Vector Table */ 02352 02353 struct hermonprm_udavtable_memory_parameters_st { /* Little Endian */ 02354 pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ 02355 /* -------------- */ 02356 pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ 02357 pseudo_bit_t reserved0[0x00005]; 02358 pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ 02359 pseudo_bit_t reserved1[0x00002]; 02360 /* -------------- */ 02361 }; 02362 02363 /* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */ 02364 02365 struct hermonprm_init_hca_st { /* Little Endian */ 02366 pseudo_bit_t reserved0[0x00018]; 02367 pseudo_bit_t version[0x00008]; 02368 /* -------------- */ 02369 pseudo_bit_t reserved1[0x00040]; 02370 /* -------------- */ 02371 pseudo_bit_t reserved2[0x00010]; 02372 pseudo_bit_t hca_core_clock[0x00010];/* Internal Clock freq in MHz */ 02373 /* -------------- */ 02374 pseudo_bit_t router_qp[0x00018]; /* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet. 02375 Valid only if RE bit is set */ 02376 pseudo_bit_t reserved3[0x00005]; 02377 pseudo_bit_t ipr2[0x00001]; /* Hermon New. IP router on port 2 */ 02378 pseudo_bit_t ipr1[0x00001]; /* Hermon New. IP router on port 1 */ 02379 pseudo_bit_t ibr[0x00001]; /* InfiniBand Router Mode */ 02380 /* -------------- */ 02381 pseudo_bit_t udp[0x00001]; /* UD Port Check Enable 02382 0 - Port field in Address Vector is ignored 02383 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ 02384 pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations 02385 0 - Host is Little Endian 02386 1 - Host is Big endian 02387 */ 02388 pseudo_bit_t reserved4[0x00001]; 02389 pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ 02390 pseudo_bit_t reserved5[0x0001c]; 02391 /* -------------- */ 02392 pseudo_bit_t reserved6[0x00040]; 02393 /* -------------- */ 02394 struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */ 02395 /* -------------- */ 02396 pseudo_bit_t reserved7[0x00100]; 02397 /* -------------- */ 02398 struct hermonprm_multicastparam_st multicast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */ 02399 /* -------------- */ 02400 pseudo_bit_t reserved8[0x00080]; 02401 /* -------------- */ 02402 struct hermonprm_tptparams_st tpt_parameters; 02403 /* -------------- */ 02404 pseudo_bit_t reserved9[0x00080]; 02405 /* -------------- */ 02406 struct hermonprm_uar_params_st uar_parameters;/* UAR Parameters */ 02407 /* -------------- */ 02408 pseudo_bit_t reserved10[0x00600]; 02409 /* -------------- */ 02410 }; 02411 02412 /* Event Queue Context Table Entry #### michal - gdror fixed */ 02413 02414 struct hermonprm_eqc_st { /* Little Endian */ 02415 pseudo_bit_t reserved0[0x00008]; 02416 pseudo_bit_t st[0x00004]; /* Event delivery state machine 02417 0x9 - Armed 02418 0xA - Fired 02419 0xB - Always_Armed (auto-rearm) 02420 other - reserved */ 02421 pseudo_bit_t reserved1[0x00005]; 02422 pseudo_bit_t oi[0x00001]; /* Oerrun ignore. 02423 If set, HW will not check EQ full condition when writing new EQEs. */ 02424 pseudo_bit_t ec[0x00001]; /* is set, all EQEs are written (coalesced) to first EQ entry */ 02425 pseudo_bit_t reserved2[0x00009]; 02426 pseudo_bit_t status[0x00004]; /* EQ status: 02427 0000 - OK 02428 1010 - EQ write failure 02429 Valid for the QUERY_EQ and HW2SW_EQ commands only */ 02430 /* -------------- */ 02431 pseudo_bit_t reserved3[0x00020]; 02432 /* -------------- */ 02433 pseudo_bit_t reserved4[0x00005]; 02434 pseudo_bit_t page_offset[0x00007]; /* offset bits[11:5] of first EQE in the EQ relative to the first page in memory region mapping this EQ */ 02435 pseudo_bit_t reserved5[0x00014]; 02436 /* -------------- */ 02437 pseudo_bit_t reserved6[0x00018]; 02438 pseudo_bit_t log_eq_size[0x00005]; /* Log (base 2) of the EQ size (in entries). Maximum EQ size is 2^22 EQEs (max log_eq_size is 22) */ 02439 pseudo_bit_t reserved7[0x00003]; 02440 /* -------------- */ 02441 pseudo_bit_t eq_max_count[0x00010]; /* Event Generation Moderation counter */ 02442 pseudo_bit_t eq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 02443 /* -------------- */ 02444 pseudo_bit_t intr[0x0000a]; /* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */ 02445 pseudo_bit_t reserved8[0x00016]; 02446 /* -------------- */ 02447 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */ 02448 pseudo_bit_t reserved9[0x00010]; 02449 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 02450 pseudo_bit_t reserved10[0x00002]; 02451 /* -------------- */ 02452 pseudo_bit_t reserved11[0x00003]; 02453 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */ 02454 /* -------------- */ 02455 pseudo_bit_t reserved12[0x00040]; 02456 /* -------------- */ 02457 pseudo_bit_t consumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ. 02458 Must be 0x0 in EQ initialization. 02459 Maintained by HW (valid for the QUERY_EQ command only). */ 02460 pseudo_bit_t reserved13[0x00008]; 02461 /* -------------- */ 02462 pseudo_bit_t producer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ. 02463 EQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a EQE needs to be added. 02464 Maintained by HW (valid for the QUERY_EQ command only) */ 02465 pseudo_bit_t reserved14[0x00008]; 02466 /* -------------- */ 02467 pseudo_bit_t reserved15[0x00080]; 02468 /* -------------- */ 02469 }; 02470 02471 /* Memory Translation Table (MTT) Entry #### michal - match to PRM */ 02472 02473 struct hermonprm_mtt_st { /* Little Endian */ 02474 pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 02475 /* -------------- */ 02476 pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ 02477 pseudo_bit_t reserved0[0x00002]; 02478 pseudo_bit_t ptag_l[0x0001d]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 02479 /* -------------- */ 02480 }; 02481 02482 /* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */ 02483 02484 struct hermonprm_mpt_st { /* Little Endian */ 02485 pseudo_bit_t reserved0[0x00008]; 02486 pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ 02487 pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation is performed for this region */ 02488 pseudo_bit_t lr[0x00001]; /* If set - local read access is enabled. Must be set for all MPT Entries. */ 02489 pseudo_bit_t lw[0x00001]; /* If set - local write access is enabled */ 02490 pseudo_bit_t rr[0x00001]; /* If set - remote read access is enabled. */ 02491 pseudo_bit_t rw[0x00001]; /* If set - remote write access is enabled */ 02492 pseudo_bit_t atomic[0x00001]; /* If set - remote Atomic access is allowed. */ 02493 pseudo_bit_t eb[0x00001]; /* If set - bind is enabled. Valid only for regions. */ 02494 pseudo_bit_t atc_req[0x00001]; /* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */ 02495 pseudo_bit_t atc_xlated[0x00001]; /* If set, uplink cycle to be issues with “ATC_translated” indicator to force bypass of the chipset IOMMU. */ 02496 pseudo_bit_t reserved1[0x00001]; 02497 pseudo_bit_t no_snoop[0x00001]; /* If set, issue PCIe cycle with ûno Snoopÿ attribute - cycle not to be snooped in CPU caches */ 02498 pseudo_bit_t reserved2[0x00008]; 02499 pseudo_bit_t status[0x00004]; /* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */ 02500 /* -------------- */ 02501 pseudo_bit_t reserved3[0x00007]; 02502 pseudo_bit_t bqp[0x00001]; /* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */ 02503 pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ 02504 /* -------------- */ 02505 pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */ 02506 /* -------------- */ 02507 pseudo_bit_t pd[0x00018]; /* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */ 02508 pseudo_bit_t en_rinv[0x00001]; /* Enable remote invalidation */ 02509 pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ 02510 pseudo_bit_t nce[0x00001]; /* Data can be cached in Network Cache (see ûNetwork Cacheÿ on page 81) */ 02511 pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ 02512 pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */ 02513 pseudo_bit_t w_dif[0x00001]; /* Wire space contains dif */ 02514 pseudo_bit_t m_dif[0x00001]; /* Memory space contains dif */ 02515 pseudo_bit_t reserved4[0x00001]; 02516 /* -------------- */ 02517 pseudo_bit_t start_addr_h[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 02518 /* -------------- */ 02519 pseudo_bit_t start_addr_l[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 02520 /* -------------- */ 02521 pseudo_bit_t len_h[0x00020]; /* Region/Window Length */ 02522 /* -------------- */ 02523 pseudo_bit_t len_l[0x00020]; /* Region/Window Length */ 02524 /* -------------- */ 02525 pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ 02526 /* -------------- */ 02527 pseudo_bit_t win_cnt[0x00018]; /* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ 02528 pseudo_bit_t reserved5[0x00008]; 02529 /* -------------- */ 02530 pseudo_bit_t mtt_rep[0x00004]; /* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */ 02531 pseudo_bit_t reserved6[0x00011]; 02532 pseudo_bit_t block_mode[0x00001]; /* If set, the page size is not power of two, and entity_size is in bytes. */ 02533 pseudo_bit_t len64[0x00001]; /* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */ 02534 pseudo_bit_t fbo_en[0x00001]; /* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */ 02535 pseudo_bit_t reserved7[0x00008]; 02536 /* -------------- */ 02537 pseudo_bit_t mtt_adr_h[0x00008]; /* Offset to MTT list for this region. Must be aligned on 8 bytes. */ 02538 pseudo_bit_t reserved8[0x00018]; 02539 /* -------------- */ 02540 pseudo_bit_t mtt_adr_l[0x00020]; /* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */ 02541 /* -------------- */ 02542 pseudo_bit_t mtt_size[0x00020]; /* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */ 02543 /* -------------- */ 02544 pseudo_bit_t entity_size[0x00015]; /* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */ 02545 pseudo_bit_t reserved9[0x0000b]; 02546 /* -------------- */ 02547 pseudo_bit_t mtt_fbo[0x00015]; /* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */ 02548 pseudo_bit_t reserved10[0x0000b]; 02549 /* -------------- */ 02550 }; 02551 02552 /* Completion Queue Context Table Entry #### michal - match PRM */ 02553 02554 struct hermonprm_completion_queue_context_st { /* Little Endian */ 02555 pseudo_bit_t reserved0[0x00008]; 02556 pseudo_bit_t st[0x00004]; /* Event delivery state machine 02557 0x0 - reserved 02558 0x9 - ARMED (Request for Notification) 02559 0x6 - ARMED SOLICITED (Request Solicited Notification) 02560 0xA - FIRED 02561 other - reserved 02562 02563 Must be 0x0 in CQ initialization. 02564 Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 02565 pseudo_bit_t reserved1[0x00005]; 02566 pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. 02567 When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ 02568 pseudo_bit_t cc[0x00001]; /* is set, all CQEs are written (coalesced) to first CQ entry */ 02569 pseudo_bit_t reserved2[0x00009]; 02570 pseudo_bit_t status[0x00004]; /* CQ status 02571 0000 - OK 02572 1001 - CQ overflow 02573 1010 - CQ write failure 02574 Valid for the QUERY_CQ and HW2SW_CQ commands only */ 02575 /* -------------- */ 02576 pseudo_bit_t reserved3[0x00020]; 02577 /* -------------- */ 02578 pseudo_bit_t reserved4[0x00005]; 02579 pseudo_bit_t page_offset[0x00007]; /* offset of first CQE in the CQ relative to the first page in memory region mapping this CQ */ 02580 pseudo_bit_t reserved5[0x00014]; 02581 /* -------------- */ 02582 pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ 02583 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). 02584 Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ 02585 pseudo_bit_t reserved6[0x00003]; 02586 /* -------------- */ 02587 pseudo_bit_t cq_max_count[0x00010]; /* Event Generation Moderation counter */ 02588 pseudo_bit_t cq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 02589 /* -------------- */ 02590 pseudo_bit_t c_eqn[0x00009]; /* Event Queue this CQ reports completion events to. 02591 Valid values are 0 to 63 02592 If configured to value other than 0-63, completion events will not be reported on the CQ. */ 02593 pseudo_bit_t reserved7[0x00017]; 02594 /* -------------- */ 02595 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 02596 pseudo_bit_t reserved8[0x00010]; 02597 pseudo_bit_t log2_page_size[0x00006]; 02598 pseudo_bit_t reserved9[0x00002]; 02599 /* -------------- */ 02600 pseudo_bit_t reserved10[0x00003]; 02601 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 02602 /* -------------- */ 02603 pseudo_bit_t last_notified_indx[0x00018];/* Maintained by HW. 02604 Valid for QUERY_CQ and HW2SW_CQ commands only. */ 02605 pseudo_bit_t reserved11[0x00008]; 02606 /* -------------- */ 02607 pseudo_bit_t solicit_producer_indx[0x00018];/* Maintained by HW. 02608 Valid for QUERY_CQ and HW2SW_CQ commands only. 02609 */ 02610 pseudo_bit_t reserved12[0x00008]; 02611 /* -------------- */ 02612 pseudo_bit_t consumer_counter[0x00018];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. 02613 */ 02614 pseudo_bit_t reserved13[0x00008]; 02615 /* -------------- */ 02616 pseudo_bit_t producer_counter[0x00018];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. 02617 CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. 02618 Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ 02619 pseudo_bit_t reserved14[0x00008]; 02620 /* -------------- */ 02621 pseudo_bit_t reserved15[0x00020]; 02622 /* -------------- */ 02623 pseudo_bit_t reserved16[0x00020]; 02624 /* -------------- */ 02625 pseudo_bit_t db_record_addr_h[0x00020];/* CQ DB Record physical address [63:32] */ 02626 /* -------------- */ 02627 pseudo_bit_t reserved17[0x00003]; 02628 pseudo_bit_t db_record_addr_l[0x0001d];/* CQ DB Record physical address [31:3] */ 02629 /* -------------- */ 02630 }; 02631 02632 /* GPIO_event_data #### michal - gdror fixed */ 02633 02634 struct hermonprm_gpio_event_data_st { /* Little Endian */ 02635 pseudo_bit_t reserved0[0x00060]; 02636 /* -------------- */ 02637 pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 02638 /* -------------- */ 02639 pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 02640 /* -------------- */ 02641 pseudo_bit_t reserved1[0x00020]; 02642 /* -------------- */ 02643 }; 02644 02645 /* Event_data Field - QP/EE Events #### michal - doesn't match PRM */ 02646 02647 struct hermonprm_qp_ee_event_st { /* Little Endian */ 02648 pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for ###michal - field changed to QP number */ 02649 pseudo_bit_t reserved0[0x00008]; 02650 /* -------------- */ 02651 pseudo_bit_t reserved1[0x00020]; 02652 /* -------------- */ 02653 pseudo_bit_t reserved2[0x0001c]; 02654 pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field 02655 Not valid on SRQ events ###michal - field replaced with RESERVED */ 02656 pseudo_bit_t reserved3[0x00003]; 02657 /* -------------- */ 02658 pseudo_bit_t reserved4[0x00060]; 02659 /* -------------- */ 02660 }; 02661 02662 /* InfiniHost-III-EX Type0 Configuration Header ####michal - doesn't match PRM (new fields added, see below) */ 02663 02664 struct hermonprm_mt25208_type0_st { /* Little Endian */ 02665 pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ 02666 pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode 02667 25408 (decimal) - InfiniHost-III EX mode (the mode described in this manual) 02668 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode 02669 */ 02670 /* -------------- */ 02671 pseudo_bit_t command[0x00010]; /* PCI Command Register */ 02672 pseudo_bit_t status[0x00010]; /* PCI Status Register */ 02673 /* -------------- */ 02674 pseudo_bit_t revision_id[0x00008]; 02675 pseudo_bit_t class_code_hca_class_code[0x00018]; 02676 /* -------------- */ 02677 pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ 02678 pseudo_bit_t latency_timer[0x00008]; 02679 pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ 02680 pseudo_bit_t bist[0x00008]; 02681 /* -------------- */ 02682 pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ 02683 pseudo_bit_t reserved0[0x00010]; 02684 pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ 02685 /* -------------- */ 02686 pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ 02687 /* -------------- */ 02688 pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ 02689 pseudo_bit_t reserved1[0x00010]; 02690 pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ 02691 /* -------------- */ 02692 pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ 02693 /* -------------- */ 02694 pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ 02695 pseudo_bit_t reserved2[0x00010]; 02696 pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 02697 /* -------------- */ 02698 pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 02699 /* -------------- */ 02700 pseudo_bit_t cardbus_cis_pointer[0x00020]; 02701 /* -------------- */ 02702 pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ 02703 pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ 02704 /* -------------- */ 02705 pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 02706 pseudo_bit_t reserved3[0x0000a]; 02707 pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 02708 /* -------------- */ 02709 pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ 02710 pseudo_bit_t reserved4[0x00018]; 02711 /* -------------- */ 02712 pseudo_bit_t reserved5[0x00020]; 02713 /* -------------- */ 02714 pseudo_bit_t interrupt_line[0x00008]; 02715 pseudo_bit_t interrupt_pin[0x00008]; 02716 pseudo_bit_t min_gnt[0x00008]; 02717 pseudo_bit_t max_latency[0x00008]; 02718 /* -------------- */ 02719 pseudo_bit_t reserved6[0x00100]; 02720 /* -------------- */ 02721 pseudo_bit_t msi_cap_id[0x00008]; 02722 pseudo_bit_t msi_next_cap_ptr[0x00008]; 02723 pseudo_bit_t msi_en[0x00001]; 02724 pseudo_bit_t multiple_msg_cap[0x00003]; 02725 pseudo_bit_t multiple_msg_en[0x00003]; 02726 pseudo_bit_t cap_64_bit_addr[0x00001]; 02727 pseudo_bit_t reserved7[0x00008]; 02728 /* -------------- */ 02729 pseudo_bit_t msg_addr_l[0x00020]; 02730 /* -------------- */ 02731 pseudo_bit_t msg_addr_h[0x00020]; 02732 /* -------------- */ 02733 pseudo_bit_t msg_data[0x00010]; 02734 pseudo_bit_t reserved8[0x00010]; 02735 /* -------------- */ 02736 pseudo_bit_t reserved9[0x00080]; 02737 /* -------------- */ 02738 pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ 02739 pseudo_bit_t pm_next_cap_ptr[0x00008]; 02740 pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h 02741 [3] PME clock - 0h 02742 [4] RsvP 02743 [5] Device specific initialization - 0h 02744 [8:6] AUX current - 0h 02745 [9] D1 support - 0h 02746 [10] D2 support - 0h 02747 [15:11] PME support - 0h */ 02748 /* -------------- */ 02749 pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ 02750 pseudo_bit_t pm_control_status_brdg_ext[0x00008]; 02751 pseudo_bit_t data[0x00008]; 02752 /* -------------- */ 02753 pseudo_bit_t reserved10[0x00040]; 02754 /* -------------- */ 02755 pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ 02756 pseudo_bit_t vpd_next_cap_id[0x00008]; 02757 pseudo_bit_t vpd_address[0x0000f]; 02758 pseudo_bit_t f[0x00001]; 02759 /* -------------- */ 02760 pseudo_bit_t vpd_data[0x00020]; 02761 /* -------------- */ 02762 pseudo_bit_t reserved11[0x00040]; 02763 /* -------------- */ 02764 pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ 02765 pseudo_bit_t pciex_next_cap_ptr[0x00008]; 02766 pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h 02767 [7:4] Device/Port Type - 0h 02768 [8] Slot implemented - 0h 02769 [13:9] Interrupt message number 02770 */ 02771 /* -------------- */ 02772 pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h 02773 [4:3] Phantom Function supported - 0h 02774 [5] Extended Tag Filed supported - 0h 02775 [8:6] Endpoint L0s Acceptable Latency - TBD 02776 [11:9] Endpoint L1 Acceptable Latency - TBD 02777 [12] Attention Button Present - configured through InfiniBurn 02778 [13] Attention Indicator Present - configured through InfiniBurn 02779 [14] Power Indicator Present - configured through InfiniBurn 02780 [25:18] Captured Slot Power Limit Value 02781 [27:26] Captured Slot Power Limit Scale */ 02782 /* -------------- */ 02783 pseudo_bit_t device_control[0x00010]; 02784 pseudo_bit_t device_status[0x00010]; 02785 /* -------------- */ 02786 pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h 02787 [9:4] Maximum Link Width - 8h 02788 [11:10] Active State Power Management Support - 3h 02789 [14:12] L0s Exit Latency - TBD 02790 [17:15] L1 Exit Latency - TBD 02791 [31:24] Port Number - 0h */ 02792 /* -------------- */ 02793 pseudo_bit_t link_control[0x00010]; 02794 pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h 02795 [9:4] Negotiated Link Width 02796 [12] Slot clock configuration - 1h */ 02797 /* -------------- */ 02798 pseudo_bit_t reserved12[0x00260]; 02799 /* -------------- */ 02800 pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ 02801 pseudo_bit_t capability_version[0x00004];/* 1h */ 02802 pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ 02803 /* -------------- */ 02804 pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status 02805 4 Data Link Protocol Error Status 02806 12 Poisoned TLP Status 02807 13 Flow Control Protocol Error Status 02808 14 Completion Timeout Status 02809 15 Completer Abort Status 02810 16 Unexpected Completion Status 02811 17 Receiver Overflow Status 02812 18 Malformed TLP Status 02813 19 ECRC Error Status 02814 20 Unsupported Request Error Status */ 02815 /* -------------- */ 02816 pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask 02817 4 Data Link Protocol Error Mask 02818 12 Poisoned TLP Mask 02819 13 Flow Control Protocol Error Mask 02820 14 Completion Timeout Mask 02821 15 Completer Abort Mask 02822 16 Unexpected Completion Mask 02823 17 Receiver Overflow Mask 02824 18 Malformed TLP Mask 02825 19 ECRC Error Mask 02826 20 Unsupported Request Error Mask */ 02827 /* -------------- */ 02828 pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity 02829 4 Data Link Protocol Error Severity 02830 12 Poisoned TLP Severity 02831 13 Flow Control Protocol Error Severity 02832 14 Completion Timeout Severity 02833 15 Completer Abort Severity 02834 16 Unexpected Completion Severity 02835 17 Receiver Overflow Severity 02836 18 Malformed TLP Severity 02837 19 ECRC Error Severity 02838 20 Unsupported Request Error Severity */ 02839 /* -------------- */ 02840 pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status 02841 6 Bad TLP Status 02842 7 Bad DLLP Status 02843 8 REPLAY_NUM Rollover Status 02844 12 Replay Timer Timeout Status */ 02845 /* -------------- */ 02846 pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask 02847 6 Bad TLP Mask 02848 7 Bad DLLP Mask 02849 8 REPLAY_NUM Rollover Mask 02850 12 Replay Timer Timeout Mask */ 02851 /* -------------- */ 02852 pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; 02853 /* -------------- */ 02854 struct hermonprm_header_log_register_st header_log_register; 02855 /* -------------- */ 02856 pseudo_bit_t reserved13[0x006a0]; 02857 /* -------------- */ 02858 }; 02859 02860 /* Event Data Field - Performance Monitor */ 02861 02862 struct hermonprm_performance_monitor_event_st { /* Little Endian */ 02863 struct hermonprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ 02864 /* -------------- */ 02865 pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC 02866 0x02 - RQPC 02867 0x03 - CQC 02868 0x04 - Rkey 02869 0x05 - TLB 02870 0x06 - port0 02871 0x07 - port1 */ 02872 pseudo_bit_t reserved0[0x00018]; 02873 /* -------------- */ 02874 pseudo_bit_t reserved1[0x00040]; 02875 /* -------------- */ 02876 }; 02877 02878 /* Event_data Field - Page Faults */ 02879 02880 struct hermonprm_page_fault_event_data_st { /* Little Endian */ 02881 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 02882 /* -------------- */ 02883 pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 02884 /* -------------- */ 02885 pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ 02886 /* -------------- */ 02887 pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ 02888 pseudo_bit_t reserved0[0x00003]; 02889 pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ 02890 pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ 02891 pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ 02892 pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ 02893 pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ 02894 /* -------------- */ 02895 pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ 02896 pseudo_bit_t reserved1[0x00008]; 02897 /* -------------- */ 02898 pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ 02899 /* -------------- */ 02900 }; 02901 02902 /* WQE segments format */ 02903 02904 struct hermonprm_wqe_segment_st { /* Little Endian */ 02905 struct hermonprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ 02906 /* -------------- */ 02907 pseudo_bit_t reserved0[0x00280]; 02908 /* -------------- */ 02909 struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ 02910 /* -------------- */ 02911 pseudo_bit_t reserved1[0x00100]; 02912 /* -------------- */ 02913 pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */ 02914 /* -------------- */ 02915 pseudo_bit_t reserved2[0x00080]; 02916 /* -------------- */ 02917 }; 02918 02919 /* Event_data Field - Port State Change #### michal - match PRM */ 02920 02921 struct hermonprm_port_state_change_st { /* Little Endian */ 02922 pseudo_bit_t reserved0[0x00040]; 02923 /* -------------- */ 02924 pseudo_bit_t reserved1[0x0001c]; 02925 pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ 02926 pseudo_bit_t reserved2[0x00002]; 02927 /* -------------- */ 02928 pseudo_bit_t reserved3[0x00060]; 02929 /* -------------- */ 02930 }; 02931 02932 /* Event_data Field - Completion Queue Error #### michal - match PRM */ 02933 02934 struct hermonprm_completion_queue_error_st { /* Little Endian */ 02935 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 02936 pseudo_bit_t reserved0[0x00008]; 02937 /* -------------- */ 02938 pseudo_bit_t reserved1[0x00020]; 02939 /* -------------- */ 02940 pseudo_bit_t syndrome[0x00008]; /* Error syndrome 02941 0x01 - CQ overrun 02942 0x02 - CQ access violation error */ 02943 pseudo_bit_t reserved2[0x00018]; 02944 /* -------------- */ 02945 pseudo_bit_t reserved3[0x00060]; 02946 /* -------------- */ 02947 }; 02948 02949 /* Event_data Field - Completion Event #### michal - match PRM */ 02950 02951 struct hermonprm_completion_event_st { /* Little Endian */ 02952 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 02953 pseudo_bit_t reserved0[0x00008]; 02954 /* -------------- */ 02955 pseudo_bit_t reserved1[0x000a0]; 02956 /* -------------- */ 02957 }; 02958 02959 /* Event Queue Entry #### michal - match to PRM */ 02960 02961 struct hermonprm_event_queue_entry_st { /* Little Endian */ 02962 pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. 02963 Defined for events which have sub types, zero elsewhere. */ 02964 pseudo_bit_t reserved0[0x00008]; 02965 pseudo_bit_t event_type[0x00008]; /* Event Type */ 02966 pseudo_bit_t reserved1[0x00008]; 02967 /* -------------- */ 02968 pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ 02969 /* -------------- */ 02970 pseudo_bit_t reserved2[0x00007]; 02971 pseudo_bit_t owner[0x00001]; /* Owner of the entry 02972 0 SW 02973 1 HW */ 02974 pseudo_bit_t reserved3[0x00018]; 02975 /* -------------- */ 02976 }; 02977 02978 /* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */ 02979 02980 struct hermonprm_qp_ee_state_transitions_st { /* Little Endian */ 02981 pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ 02982 /* -------------- */ 02983 pseudo_bit_t reserved0[0x00020]; 02984 /* -------------- */ 02985 struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */ 02986 /* -------------- */ 02987 pseudo_bit_t reserved1[0x00800]; 02988 /* -------------- */ 02989 }; 02990 02991 /* Completion Queue Entry Format #### michal - fixed by gdror */ 02992 02993 struct hermonprm_completion_queue_entry_st { /* Little Endian */ 02994 pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 02995 pseudo_bit_t reserved0[0x00002]; 02996 pseudo_bit_t d2s[0x00001]; /* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers 02997 packet only to send-associated sniffer receive queue. */ 02998 pseudo_bit_t fcrc_sd[0x00001]; /* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only. 02999 SD: CQ associated with Sniffer receive queue. If set, packets were skipped due to lack of receive buffers on the Sniffer receive queue */ 03000 pseudo_bit_t fl[0x00001]; /* Force Loopback Valid for responder RawEth and UD only. */ 03001 pseudo_bit_t vlan[0x00002]; /* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue 03002 00 - No VLAN header was present in the packet 03003 01 - C-VLAN (802.1q) Header was present in the frame. 03004 10 - S-VLAN (802.1ad) Header was present in the frame. */ 03005 pseudo_bit_t dife[0x00001]; /* DIF Error */ 03006 /* -------------- */ 03007 pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message. 03008 For a responder CQE, if completed WQE Opcode is Send With Invalidate, this field contains the R_key that was invalidated. 03009 For a responder CQE of a GSI packet this filed contains the Pkey Index of the packet. 03010 For IPoIB (UD) and RawEth CQEs this field contains the RSS hash function value. 03011 Otherwise, this field is reserved. */ 03012 /* -------------- */ 03013 pseudo_bit_t srq_rqpn[0x00018]; /* For Responder UD QPs, Remote (source) QP number. 03014 For Responder SRC QPs, SRQ number. 03015 Otherwise, this field is reserved. */ 03016 pseudo_bit_t ml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast. 03017 For responder UD over Ethernet and RawEth CQEs: Index of the MAC Table entry that the packet DMAC was matched against. 03018 Otherwise, this field is reserved. */ 03019 pseudo_bit_t g[0x00001]; /* For responder UD over IB CQE this bit indicates the presence of a GRH 03020 For responder UD over Ethernet CQE this bit is set if IPv6 L3 header was present in the packet, this bit is cleared if IPv4 L3 Header was present in the packet. 03021 Otherwise, this field is reserved. */ 03022 /* -------------- */ 03023 pseudo_bit_t slid_smac47_32[0x00010];/* For responder UD over IB CQE it is the source LID of the packet. 03024 For responder UD over Ethernet and RawEth CQEs it is the source-MAC[47:32] of the packet. 03025 Otherwise, this field is reserved. */ 03026 pseudo_bit_t vid[0x0000c]; /* Frame VID, valid for Responder Raw Ethernet and UD over Ethernet QP. Otherwise, this field is reserved. */ 03027 pseudo_bit_t sl[0x00004]; /* For responder UD over IB - the Service Level of the packet. 03028 For responder UD over Ethernet and RawEth - it is VLAN-header[15:12] 03029 Otherwise, this field is reserved. */ 03030 /* -------------- */ 03031 pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020];/* For responder UD over Ethernet - source MAC[31:0] of the packet. 03032 For responder RawEth and UD over IB - RawEth-IPoIB status {3 reserved, ipok,udp,tcp,ipv4opt,ipv6,ipv4vf,ipv4,rht(6),ipv6extmask(6),reserved(2),l2am,reserved(2),bfcs,reserved(2),enc} 03033 Otherwise, this field is reserved. */ 03034 /* -------------- */ 03035 pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data transferred. Applicable for RDMA-read, Atomic and all receive operations. completions. 03036 For Receive Queue that is subject for headers. separation, byte_cnt[31:24] specify number of bytes scattered to the first scatter entry (headers. length). Byte_cnt[23:0] specify total byte count received (including headers). */ 03037 /* -------------- */ 03038 pseudo_bit_t checksum[0x00010]; /* Valid for RawEth and IPoIB only. */ 03039 pseudo_bit_t wqe_counter[0x00010]; 03040 /* -------------- */ 03041 pseudo_bit_t opcode[0x00005]; /* Send completions - same encoding as WQE. 03042 Error coding is 0x1F 03043 Receive: 03044 0x0 - RDMA-Write with Immediate 03045 0x1 - Send 03046 0x2 - Send with Immediate 03047 0x3 - Send & Invalidate 03048 */ 03049 pseudo_bit_t is[0x00001]; /* inline scatter */ 03050 pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 03051 pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 03052 pseudo_bit_t reserved1[0x00010]; 03053 pseudo_bit_t reserved2[0x00008]; 03054 /* -------------- */ 03055 }; 03056 03057 /* */ 03058 03059 struct hermonprm_mcg_qps_st { /* Little Endian */ 03060 struct hermonprm_mcg_qp_dw_st dw[128]; 03061 /* -------------- */ 03062 }; 03063 03064 /* */ 03065 03066 struct hermonprm_mcg_hdr_st { /* Little Endian */ 03067 pseudo_bit_t reserved0[0x00006]; 03068 pseudo_bit_t next_mcg[0x0001a]; 03069 /* -------------- */ 03070 pseudo_bit_t members_count[0x00018]; 03071 pseudo_bit_t member_remove[0x00001]; 03072 pseudo_bit_t reserved1[0x00005]; 03073 pseudo_bit_t protocol[0x00002]; 03074 /* -------------- */ 03075 pseudo_bit_t reserved2[0x00020]; 03076 /* -------------- */ 03077 pseudo_bit_t reserved3[0x00020]; 03078 /* -------------- */ 03079 pseudo_bit_t gid3[0x00020]; 03080 /* -------------- */ 03081 pseudo_bit_t gid2[0x00020]; 03082 /* -------------- */ 03083 pseudo_bit_t gid1[0x00020]; 03084 /* -------------- */ 03085 pseudo_bit_t gid0[0x00020]; 03086 /* -------------- */ 03087 }; 03088 03089 /* */ 03090 03091 struct hermonprm_sched_queue_context_st { /* Little Endian */ 03092 pseudo_bit_t policy[0x00003]; /* Schedule Queue Policy - 0 - LLSQ, 1 - GBSQ, 2 - BESQ */ 03093 pseudo_bit_t vl15[0x00001]; 03094 pseudo_bit_t sl[0x00004]; /* SL this Schedule Queue is associated with (if vl15 bit is 0) */ 03095 pseudo_bit_t port[0x00002]; /* Port this Schedule Queue is associated with */ 03096 pseudo_bit_t reserved0[0x00006]; 03097 pseudo_bit_t weight[0x00010]; /* Weight of this SchQ */ 03098 /* -------------- */ 03099 }; 03100 03101 /* */ 03102 03103 struct hermonprm_ecc_detect_event_data_st { /* Little Endian */ 03104 pseudo_bit_t reserved0[0x00080]; 03105 /* -------------- */ 03106 pseudo_bit_t cause_lsb[0x00001]; 03107 pseudo_bit_t reserved1[0x00002]; 03108 pseudo_bit_t cause_msb[0x00001]; 03109 pseudo_bit_t reserved2[0x00002]; 03110 pseudo_bit_t err_rmw[0x00001]; 03111 pseudo_bit_t err_src_id[0x00003]; 03112 pseudo_bit_t err_da[0x00002]; 03113 pseudo_bit_t err_ba[0x00002]; 03114 pseudo_bit_t reserved3[0x00011]; 03115 pseudo_bit_t overflow[0x00001]; 03116 /* -------------- */ 03117 pseudo_bit_t err_ra[0x00010]; 03118 pseudo_bit_t err_ca[0x00010]; 03119 /* -------------- */ 03120 }; 03121 03122 /* Event_data Field - ECC Detection Event */ 03123 03124 struct hermonprm_scrubbing_event_st { /* Little Endian */ 03125 pseudo_bit_t reserved0[0x00080]; 03126 /* -------------- */ 03127 pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: 03128 single ECC error in the 64bit lsb data, on the rise edge of the clock */ 03129 pseudo_bit_t reserved1[0x00002]; 03130 pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: 03131 single ECC error in the 64bit msb data, on the fall edge of the clock */ 03132 pseudo_bit_t reserved2[0x00002]; 03133 pseudo_bit_t err_rmw[0x00001]; /* transaction type: 03134 0 - read 03135 1 - read/modify/write */ 03136 pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ 03137 pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ 03138 pseudo_bit_t err_ba[0x00002]; /* Error bank address */ 03139 pseudo_bit_t reserved3[0x00011]; 03140 pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ 03141 /* -------------- */ 03142 pseudo_bit_t err_ra[0x00010]; /* Error row address */ 03143 pseudo_bit_t err_ca[0x00010]; /* Error column address */ 03144 /* -------------- */ 03145 }; 03146 03147 /* */ 03148 03149 struct hermonprm_eq_cmd_doorbell_st { /* Little Endian */ 03150 pseudo_bit_t reserved0[0x00020]; 03151 /* -------------- */ 03152 }; 03153 03154 /* 0 */ 03155 03156 struct hermonprm_hermon_prm_st { /* Little Endian */ 03157 struct hermonprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ 03158 /* -------------- */ 03159 pseudo_bit_t reserved0[0x7ff00]; 03160 /* -------------- */ 03161 struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ 03162 /* -------------- */ 03163 pseudo_bit_t reserved1[0x7f000]; 03164 /* -------------- */ 03165 struct hermonprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ 03166 /* -------------- */ 03167 pseudo_bit_t reserved2[0x7ff00]; 03168 /* -------------- */ 03169 struct hermonprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ 03170 /* -------------- */ 03171 pseudo_bit_t reserved3[0x7ff40]; 03172 /* -------------- */ 03173 struct hermonprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ 03174 /* -------------- */ 03175 pseudo_bit_t reserved4[0x7ff40]; 03176 /* -------------- */ 03177 struct hermonprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ 03178 /* -------------- */ 03179 pseudo_bit_t reserved5[0x7ff40]; 03180 /* -------------- */ 03181 struct hermonprm_wqe_segment_st wqe_segment;/* WQE segments format */ 03182 /* -------------- */ 03183 pseudo_bit_t reserved6[0x7f000]; 03184 /* -------------- */ 03185 struct hermonprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ 03186 /* -------------- */ 03187 pseudo_bit_t reserved7[0x7ff40]; 03188 /* -------------- */ 03189 struct hermonprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ 03190 /* -------------- */ 03191 pseudo_bit_t reserved8[0xfff20]; 03192 /* -------------- */ 03193 struct hermonprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ 03194 /* -------------- */ 03195 pseudo_bit_t reserved9[0x7f000]; 03196 /* -------------- */ 03197 struct hermonprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ 03198 /* -------------- */ 03199 pseudo_bit_t reserved10[0x00040]; 03200 /* -------------- */ 03201 struct hermonprm_gpio_event_data_st gpio_event_data; 03202 /* -------------- */ 03203 pseudo_bit_t reserved11[0x7fe40]; 03204 /* -------------- */ 03205 struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 03206 /* -------------- */ 03207 pseudo_bit_t reserved12[0x7ff00]; 03208 /* -------------- */ 03209 struct hermonprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ 03210 /* -------------- */ 03211 pseudo_bit_t reserved13[0x7f840]; 03212 /* -------------- */ 03213 struct hermonprm_address_path_st address_path;/* Address Path */ 03214 /* -------------- */ 03215 pseudo_bit_t reserved14[0x7fea0]; 03216 /* -------------- */ 03217 struct hermonprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ 03218 /* -------------- */ 03219 pseudo_bit_t reserved15[0x7fe00]; 03220 /* -------------- */ 03221 struct hermonprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ 03222 /* -------------- */ 03223 pseudo_bit_t reserved16[0x7fe00]; 03224 /* -------------- */ 03225 struct hermonprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ 03226 /* -------------- */ 03227 pseudo_bit_t reserved17[0x7ffc0]; 03228 /* -------------- */ 03229 struct hermonprm_eqc_st eqc; /* Event Queue Context Table Entry */ 03230 /* -------------- */ 03231 pseudo_bit_t reserved18[0x7fe00]; 03232 /* -------------- */ 03233 struct hermonprm_performance_monitors_st performance_monitors;/* Performance Monitors */ 03234 /* -------------- */ 03235 pseudo_bit_t reserved19[0x7ff80]; 03236 /* -------------- */ 03237 struct hermonprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ 03238 /* -------------- */ 03239 pseudo_bit_t reserved20[0xfff20]; 03240 /* -------------- */ 03241 struct hermonprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ 03242 /* -------------- */ 03243 pseudo_bit_t reserved21[0x7f000]; 03244 /* -------------- */ 03245 struct hermonprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ 03246 /* -------------- */ 03247 pseudo_bit_t reserved22[0x7fc00]; 03248 /* -------------- */ 03249 struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ 03250 /* -------------- */ 03251 pseudo_bit_t reserved23[0x7ffc0]; 03252 /* -------------- */ 03253 struct hermonprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ 03254 /* -------------- */ 03255 pseudo_bit_t reserved24[0x7ff00]; 03256 /* -------------- */ 03257 struct hermonprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ 03258 /* -------------- */ 03259 pseudo_bit_t reserved25[0x7ff00]; 03260 /* -------------- */ 03261 pseudo_bit_t reserved26[0x00800]; 03262 /* -------------- */ 03263 pseudo_bit_t reserved27[0x00100]; 03264 /* -------------- */ 03265 pseudo_bit_t reserved28[0x7f700]; 03266 /* -------------- */ 03267 pseudo_bit_t reserved29[0x00100]; 03268 /* -------------- */ 03269 pseudo_bit_t reserved30[0x7ff00]; 03270 /* -------------- */ 03271 struct hermonprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ 03272 /* -------------- */ 03273 pseudo_bit_t reserved31[0x7f800]; 03274 /* -------------- */ 03275 struct hermonprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ 03276 /* -------------- */ 03277 pseudo_bit_t reserved32[0x7f800]; 03278 /* -------------- */ 03279 struct hermonprm_query_dev_cap_st query_dev_cap;/* Query Device Limitations */ 03280 /* -------------- */ 03281 pseudo_bit_t reserved33[0x7f800]; 03282 /* -------------- */ 03283 struct hermonprm_uar_params_st uar_params;/* UAR Parameters */ 03284 /* -------------- */ 03285 pseudo_bit_t reserved34[0x7ff00]; 03286 /* -------------- */ 03287 struct hermonprm_init_port_st init_port;/* INIT_PORT Parameters */ 03288 /* -------------- */ 03289 pseudo_bit_t reserved35[0x7f800]; 03290 /* -------------- */ 03291 struct hermonprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ 03292 /* -------------- */ 03293 pseudo_bit_t reserved36[0x7fe00]; 03294 /* -------------- */ 03295 struct hermonprm_set_ib_st set_ib; /* SET_IB Parameters */ 03296 /* -------------- */ 03297 pseudo_bit_t reserved37[0x7fe00]; 03298 /* -------------- */ 03299 struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ 03300 /* -------------- */ 03301 pseudo_bit_t reserved38[0x7ff80]; 03302 /* -------------- */ 03303 struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 03304 /* -------------- */ 03305 pseudo_bit_t reserved39[0x7ffc0]; 03306 /* -------------- */ 03307 struct hermonprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ 03308 /* -------------- */ 03309 pseudo_bit_t reserved40[0x7ffc0]; 03310 /* -------------- */ 03311 struct hermonprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ 03312 /* -------------- */ 03313 pseudo_bit_t reserved41[0xfffc0]; 03314 /* -------------- */ 03315 struct hermonprm_uar_st uar; /* User Access Region */ 03316 /* -------------- */ 03317 pseudo_bit_t reserved42[0x7c000]; 03318 /* -------------- */ 03319 struct hermonprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ 03320 /* -------------- */ 03321 pseudo_bit_t reserved43[0x7ffe0]; 03322 /* -------------- */ 03323 struct hermonprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ 03324 /* -------------- */ 03325 pseudo_bit_t reserved44[0x7f800]; 03326 /* -------------- */ 03327 struct hermonprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ 03328 /* -------------- */ 03329 pseudo_bit_t reserved45[0x00900]; 03330 /* -------------- */ 03331 struct hermonprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ 03332 /* -------------- */ 03333 pseudo_bit_t reserved46[0x7e6e0]; 03334 /* -------------- */ 03335 struct hermonprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ 03336 /* -------------- */ 03337 pseudo_bit_t reserved47[0x7fe00]; 03338 /* -------------- */ 03339 struct hermonprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ 03340 /* -------------- */ 03341 pseudo_bit_t reserved48[0x7ff00]; 03342 /* -------------- */ 03343 struct hermonprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ 03344 /* -------------- */ 03345 pseudo_bit_t reserved49[0x7ff40]; 03346 /* -------------- */ 03347 struct hermonprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ 03348 /* -------------- */ 03349 pseudo_bit_t reserved50[0x7f000]; 03350 /* -------------- */ 03351 struct hermonprm_performance_counters_st performance_counters;/* Performance Counters */ 03352 /* -------------- */ 03353 pseudo_bit_t reserved51[0x9ff800]; 03354 /* -------------- */ 03355 struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 03356 /* -------------- */ 03357 pseudo_bit_t reserved52[0x7ff00]; 03358 /* -------------- */ 03359 struct hermonprm_pbl_st pbl; /* Physical Buffer List */ 03360 /* -------------- */ 03361 pseudo_bit_t reserved53[0x7ff00]; 03362 /* -------------- */ 03363 struct hermonprm_srq_context_st srq_context;/* SRQ Context */ 03364 /* -------------- */ 03365 pseudo_bit_t reserved54[0x7fe80]; 03366 /* -------------- */ 03367 struct hermonprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ 03368 /* -------------- */ 03369 pseudo_bit_t reserved55[0x7f800]; 03370 /* -------------- */ 03371 struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ 03372 /* -------------- */ 03373 pseudo_bit_t reserved56[0x7ff80]; 03374 /* -------------- */ 03375 struct hermonprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ 03376 /* -------------- */ 03377 pseudo_bit_t reserved57[0x7ffc0]; 03378 /* -------------- */ 03379 struct hermonprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ 03380 /* -------------- */ 03381 pseudo_bit_t reserved58[0x7ffc0]; 03382 /* -------------- */ 03383 struct hermonprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ 03384 /* -------------- */ 03385 pseudo_bit_t reserved59[0x00020]; 03386 /* -------------- */ 03387 pseudo_bit_t reserved60[0x1fffc0]; 03388 /* -------------- */ 03389 struct hermonprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ 03390 /* -------------- */ 03391 struct hermonprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ 03392 /* -------------- */ 03393 pseudo_bit_t reserved61[0x01000]; 03394 /* -------------- */ 03395 pseudo_bit_t reserved62[0x00040]; 03396 /* -------------- */ 03397 pseudo_bit_t reserved63[0x00fc0]; 03398 /* -------------- */ 03399 struct hermonprm_clr_int_st clr_int; /* Clear Interrupt Register */ 03400 /* -------------- */ 03401 pseudo_bit_t reserved64[0xffcfc0]; 03402 /* -------------- */ 03403 }; 03404 #endif /* H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H */
1.7.6.1