iPXE
MT25408_PRM.h
Go to the documentation of this file.
1 /*
2  This software is available to you under a choice of one of two
3  licenses. You may choose to be licensed under the terms of the GNU
4  General Public License (GPL) Version 2, available at
5  <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
6  license, available in the LICENSE.TXT file accompanying this
7  software. These details are also available at
8  <http://openib.org/license.html>.
9 
10  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13  NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15  ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16  CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17  SOFTWARE.
18 
19  Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
20 */
21 
22 FILE_LICENCE ( GPL2_ONLY );
23 
24 /***
25  *** This file was generated at "Mon Apr 16 23:22:02 2007"
26  *** by:
27  *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix hermonprm_ -bits -fixnames MT25408_PRM.csp
28  ***/
29 
30 #ifndef H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H
31 #define H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H
32 
33 /* UD Address Vector */
34 
35 struct hermonprm_ud_address_vector_st { /* Little Endian */
36  pseudo_bit_t pd[0x00018]; /* Protection Domain */
37  pseudo_bit_t port_number[0x00002]; /* Port number
38  1 - Port 1
39  2 - Port 2
40  other - reserved */
41  pseudo_bit_t reserved0[0x00005];
42  pseudo_bit_t fl[0x00001]; /* force loopback */
43 /* -------------- */
44  pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
45  pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
46  pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
47  pseudo_bit_t reserved1[0x00008];
48 /* -------------- */
49  pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
50  pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control.
51  0 - 4X injection rate
52  1 - 1X injection rate
53  other - reserved
54  */
55  pseudo_bit_t reserved2[0x00004];
56  pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table
57  mgid_index = (port_number-1) * 2^log_max_gid + gid_index
58  Where:
59  1. log_max_gid is taken from QUERY_DEV_CAP command
60  2. gid_index is the index to the GID table */
61  pseudo_bit_t reserved3[0x00009];
62 /* -------------- */
63  pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
64  pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
65  pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
66 /* -------------- */
67  pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
68 /* -------------- */
69  pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
70 /* -------------- */
71  pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
72 /* -------------- */
73  pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
74 /* -------------- */
75 };
76 
77 /* Send doorbell */
78 
79 struct hermonprm_send_doorbell_st { /* Little Endian */
80  pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */
81  pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */
82  pseudo_bit_t reserved0[0x00002];
83  pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
84  pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */
85 /* -------------- */
86  pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */
87  pseudo_bit_t reserved1[0x00002];
88  pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
89 /* -------------- */
90 };
91 
92 /* Send wqe segment data inline */
93 
94 struct hermonprm_wqe_segment_data_inline_st { /* Little Endian */
95  pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */
96  pseudo_bit_t reserved0[0x00015];
97  pseudo_bit_t always1[0x00001];
98 /* -------------- */
99  pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */
100  pseudo_bit_t reserved1[0x00008];
101 /* -------------- */
102  pseudo_bit_t reserved2[0x00040];
103 /* -------------- */
104 };
105 
106 /* Send wqe segment data ptr */
107 
108 struct hermonprm_wqe_segment_data_ptr_st { /* Little Endian */
109  pseudo_bit_t byte_count[0x0001f];
110  pseudo_bit_t always0[0x00001];
111 /* -------------- */
112  pseudo_bit_t l_key[0x00020];
113 /* -------------- */
114  pseudo_bit_t local_address_h[0x00020];
115 /* -------------- */
116  pseudo_bit_t local_address_l[0x00020];
117 /* -------------- */
118 };
119 
120 /* Send wqe segment rd */
121 
122 struct hermonprm_local_invalidate_segment_st { /* Little Endian */
123  pseudo_bit_t reserved0[0x00040];
124 /* -------------- */
125  pseudo_bit_t mem_key[0x00018];
126  pseudo_bit_t reserved1[0x00008];
127 /* -------------- */
128  pseudo_bit_t reserved2[0x000a0];
129 /* -------------- */
130 };
131 
132 /* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */
133 
134 struct hermonprm_fast_registration_segment_st { /* Little Endian */
135  pseudo_bit_t reserved0[0x0001b];
136  pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */
137  pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */
138  pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */
139  pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */
140  pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */
141 /* -------------- */
142  pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */
143 /* -------------- */
144  pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */
145 /* -------------- */
146  pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
147  page_size should be less than 20. ###michal - field doesn't exsist (see replacement above) */
148  pseudo_bit_t reserved1[0x00002];
149  pseudo_bit_t zb[0x00001]; /* Zero Based Region ###michal - field doesn't exsist (see replacement above) */
150  pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */
151 /* -------------- */
152  pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
153 /* -------------- */
154  pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
155 /* -------------- */
156  pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */
157 /* -------------- */
158  pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */
159 /* -------------- */
160 };
161 
162 /* Send wqe segment atomic */
163 
164 struct hermonprm_wqe_segment_atomic_st { /* Little Endian */
165  pseudo_bit_t swap_add_h[0x00020];
166 /* -------------- */
167  pseudo_bit_t swap_add_l[0x00020];
168 /* -------------- */
169  pseudo_bit_t compare_h[0x00020];
170 /* -------------- */
171  pseudo_bit_t compare_l[0x00020];
172 /* -------------- */
173 };
174 
175 /* Send wqe segment remote address */
176 
177 struct hermonprm_wqe_segment_remote_address_st { /* Little Endian */
178  pseudo_bit_t remote_virt_addr_h[0x00020];
179 /* -------------- */
180  pseudo_bit_t remote_virt_addr_l[0x00020];
181 /* -------------- */
182  pseudo_bit_t rkey[0x00020];
183 /* -------------- */
184  pseudo_bit_t reserved0[0x00020];
185 /* -------------- */
186 };
187 
188 /* end wqe segment bind */
189 
190 struct hermonprm_wqe_segment_bind_st { /* Little Endian */
191  pseudo_bit_t reserved0[0x0001d];
192  pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */
193  pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window.
194  */
195  pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */
196 /* -------------- */
197  pseudo_bit_t reserved1[0x0001e];
198  pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */
199  pseudo_bit_t type[0x00001]; /* Window type.
200  0 - Type one window
201  1 - Type two window
202  */
203 /* -------------- */
204  pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */
205 /* -------------- */
206  pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */
207 /* -------------- */
208  pseudo_bit_t start_address_h[0x00020];
209 /* -------------- */
210  pseudo_bit_t start_address_l[0x00020];
211 /* -------------- */
212  pseudo_bit_t length_h[0x00020];
213 /* -------------- */
214  pseudo_bit_t length_l[0x00020];
215 /* -------------- */
216 };
217 
218 /* Send wqe segment ud */
219 
220 struct hermonprm_wqe_segment_ud_st { /* Little Endian */
221  struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
222 /* -------------- */
223  pseudo_bit_t destination_qp[0x00018];
224  pseudo_bit_t reserved0[0x00008];
225 /* -------------- */
226  pseudo_bit_t q_key[0x00020];
227 /* -------------- */
228  pseudo_bit_t reserved1[0x00040];
229 /* -------------- */
230 };
231 
232 /* Send wqe segment rd */
233 
234 struct hermonprm_wqe_segment_rd_st { /* Little Endian */
235  pseudo_bit_t destination_qp[0x00018];
236  pseudo_bit_t reserved0[0x00008];
237 /* -------------- */
238  pseudo_bit_t q_key[0x00020];
239 /* -------------- */
240  pseudo_bit_t reserved1[0x00040];
241 /* -------------- */
242 };
243 
244 /* Send wqe segment ctrl */
245 
246 struct hermonprm_wqe_segment_ctrl_send_st { /* Little Endian */
247  pseudo_bit_t opcode[0x00005];
248  pseudo_bit_t reserved0[0x0001a];
249  pseudo_bit_t owner[0x00001];
250 /* -------------- */
251  pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */
252  pseudo_bit_t f[0x00001]; /* fence */
253  pseudo_bit_t reserved1[0x00019];
254 /* -------------- */
255  pseudo_bit_t fl[0x00001]; /* Force LoopBack */
256  pseudo_bit_t s[0x00001]; /* Remote Solicited Event */
257  pseudo_bit_t c[0x00002]; /* completion required: 0b00 - no 0b11 - yes */
258  pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
259  pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
260  pseudo_bit_t reserved2[0x00001];
261  pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
262  pseudo_bit_t src_remote_buf[0x00018];
263 /* -------------- */
264  pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
265 /* -------------- */
266 };
267 
268 /* Address Path # ###michal - match to PRM */
269 
270 struct hermonprm_address_path_st { /* Little Endian */
271  pseudo_bit_t pkey_index[0x00007]; /* PKey table index */
272  pseudo_bit_t reserved0[0x00016];
273  pseudo_bit_t sv[0x00001]; /* Service VLAN on QP */
274  pseudo_bit_t cv[0x00001]; /* Customer VLAN in QP */
275  pseudo_bit_t fl[0x00001]; /* Force LoopBack */
276 /* -------------- */
277  pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
278  pseudo_bit_t my_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
279  pseudo_bit_t grh_ip[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
280  pseudo_bit_t reserved1[0x00008];
281 /* -------------- */
282  pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
283  pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control.
284  0 - 100% injection rate
285  1 - 25% injection rate
286  2 - 12.5% injection rate
287  3 - 50% injection rate
288  7: 2.5 Gb/s.
289  8: 10 Gb/s.
290  9: 30 Gb/s.
291  10: 5 Gb/s.
292  11: 20 Gb/s.
293  12: 40 Gb/s.
294  13: 60 Gb/s.
295  14: 80 Gb/s.
296  15: 120 Gb/s. */
297  pseudo_bit_t reserved2[0x00004];
298  pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table */
299  pseudo_bit_t reserved3[0x00004];
300  pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
301  The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
302 /* -------------- */
303  pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
304  pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
305  pseudo_bit_t reserved4[0x00004];
306 /* -------------- */
307  pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
308 /* -------------- */
309  pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
310 /* -------------- */
311  pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
312 /* -------------- */
313  pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
314 /* -------------- */
315  pseudo_bit_t reserved5[0x00008];
316  pseudo_bit_t sp[0x00001]; /* if set, spoofing protection is enforced on this QP and Ethertype headers are restricted */
317  pseudo_bit_t reserved6[0x00002];
318  pseudo_bit_t fvl[0x00001]; /* force VLAN */
319  pseudo_bit_t fsip[0x00001]; /* force source IP */
320  pseudo_bit_t fsm[0x00001]; /* force source MAC */
321  pseudo_bit_t reserved7[0x0000a];
322  pseudo_bit_t sched_queue[0x00008];
323 /* -------------- */
324  pseudo_bit_t dmac_47_32[0x00010];
325  pseudo_bit_t vlan_index[0x00007];
326  pseudo_bit_t reserved8[0x00001];
327  pseudo_bit_t counter_index[0x00008];/* Index to a table of counters that counts egress packets and bytes, 0xFF not valid */
328 /* -------------- */
329  pseudo_bit_t dmac_31_0[0x00020];
330 /* -------------- */
331 };
332 
333 /* HCA Command Register (HCR) #### michal - match PRM */
334 
335 struct hermonprm_hca_command_register_st { /* Little Endian */
336  pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
337 /* -------------- */
338  pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
339 /* -------------- */
340  pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */
341 /* -------------- */
342  pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
343 /* -------------- */
344  pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
345 /* -------------- */
346  pseudo_bit_t reserved0[0x00010];
347  pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
348 /* -------------- */
349  pseudo_bit_t opcode[0x0000c]; /* Command opcode */
350  pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
351  pseudo_bit_t reserved1[0x00005];
352  pseudo_bit_t t[0x00001]; /* Toggle */
353  pseudo_bit_t e[0x00001]; /* Event Request
354  0 - Don't report event (software will poll the GO bit)
355  1 - Report event to EQ when the command completes */
356  pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
357  Software can write to the HCR only if Go bit is cleared.
358  Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
359  pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
360  0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
361 /* -------------- */
362 };
363 
364 /* CQ Doorbell */
365 
366 struct hermonprm_cq_cmd_doorbell_st { /* Little Endian */
367  pseudo_bit_t cqn[0x00018]; /* CQ number accessed */
368  pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ
369  0x0 - Reserved
370  0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
371  0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
372  0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
373  Other - Reserved */
374  pseudo_bit_t reserved0[0x00001];
375  pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
376  This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited
377  completion or Request notification for multiple completions doorbells after receiving completion notification.
378  This field is initialized to Zero */
379  pseudo_bit_t reserved1[0x00002];
380 /* -------------- */
381  pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */
382 /* -------------- */
383 };
384 
385 /* RD-send doorbell */
386 
387 struct hermonprm_rd_send_doorbell_st { /* Little Endian */
388  pseudo_bit_t reserved0[0x00008];
389  pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram)
390  Must be zero for Nop and Bind operations */
391 /* -------------- */
392  pseudo_bit_t reserved1[0x00008];
393  pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
394 /* -------------- */
395  struct hermonprm_send_doorbell_st send_doorbell;/* Send Parameters */
396 /* -------------- */
397 };
398 
399 /* Multicast Group Member QP #### michal - match PRM */
400 
401 struct hermonprm_mgmqp_st { /* Little Endian */
402  pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
403  pseudo_bit_t reserved0[0x00006];
404  pseudo_bit_t blck_lb[0x00001]; /* Block self-loopback messages arriving to this qp */
405  pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */
406 /* -------------- */
407 };
408 
409 /* vsd */
410 
411 struct hermonprm_vsd_st { /* Little Endian */
412  pseudo_bit_t vsd_dw0[0x00020];
413 /* -------------- */
414  pseudo_bit_t vsd_dw1[0x00020];
415 /* -------------- */
416  pseudo_bit_t vsd_dw2[0x00020];
417 /* -------------- */
418  pseudo_bit_t vsd_dw3[0x00020];
419 /* -------------- */
420  pseudo_bit_t vsd_dw4[0x00020];
421 /* -------------- */
422  pseudo_bit_t vsd_dw5[0x00020];
423 /* -------------- */
424  pseudo_bit_t vsd_dw6[0x00020];
425 /* -------------- */
426  pseudo_bit_t vsd_dw7[0x00020];
427 /* -------------- */
428  pseudo_bit_t vsd_dw8[0x00020];
429 /* -------------- */
430  pseudo_bit_t vsd_dw9[0x00020];
431 /* -------------- */
432  pseudo_bit_t vsd_dw10[0x00020];
433 /* -------------- */
434  pseudo_bit_t vsd_dw11[0x00020];
435 /* -------------- */
436  pseudo_bit_t vsd_dw12[0x00020];
437 /* -------------- */
438  pseudo_bit_t vsd_dw13[0x00020];
439 /* -------------- */
440  pseudo_bit_t vsd_dw14[0x00020];
441 /* -------------- */
442  pseudo_bit_t vsd_dw15[0x00020];
443 /* -------------- */
444  pseudo_bit_t vsd_dw16[0x00020];
445 /* -------------- */
446  pseudo_bit_t vsd_dw17[0x00020];
447 /* -------------- */
448  pseudo_bit_t vsd_dw18[0x00020];
449 /* -------------- */
450  pseudo_bit_t vsd_dw19[0x00020];
451 /* -------------- */
452  pseudo_bit_t vsd_dw20[0x00020];
453 /* -------------- */
454  pseudo_bit_t vsd_dw21[0x00020];
455 /* -------------- */
456  pseudo_bit_t vsd_dw22[0x00020];
457 /* -------------- */
458  pseudo_bit_t vsd_dw23[0x00020];
459 /* -------------- */
460  pseudo_bit_t vsd_dw24[0x00020];
461 /* -------------- */
462  pseudo_bit_t vsd_dw25[0x00020];
463 /* -------------- */
464  pseudo_bit_t vsd_dw26[0x00020];
465 /* -------------- */
466  pseudo_bit_t vsd_dw27[0x00020];
467 /* -------------- */
468  pseudo_bit_t vsd_dw28[0x00020];
469 /* -------------- */
470  pseudo_bit_t vsd_dw29[0x00020];
471 /* -------------- */
472  pseudo_bit_t vsd_dw30[0x00020];
473 /* -------------- */
474  pseudo_bit_t vsd_dw31[0x00020];
475 /* -------------- */
476  pseudo_bit_t vsd_dw32[0x00020];
477 /* -------------- */
478  pseudo_bit_t vsd_dw33[0x00020];
479 /* -------------- */
480  pseudo_bit_t vsd_dw34[0x00020];
481 /* -------------- */
482  pseudo_bit_t vsd_dw35[0x00020];
483 /* -------------- */
484  pseudo_bit_t vsd_dw36[0x00020];
485 /* -------------- */
486  pseudo_bit_t vsd_dw37[0x00020];
487 /* -------------- */
488  pseudo_bit_t vsd_dw38[0x00020];
489 /* -------------- */
490  pseudo_bit_t vsd_dw39[0x00020];
491 /* -------------- */
492  pseudo_bit_t vsd_dw40[0x00020];
493 /* -------------- */
494  pseudo_bit_t vsd_dw41[0x00020];
495 /* -------------- */
496  pseudo_bit_t vsd_dw42[0x00020];
497 /* -------------- */
498  pseudo_bit_t vsd_dw43[0x00020];
499 /* -------------- */
500  pseudo_bit_t vsd_dw44[0x00020];
501 /* -------------- */
502  pseudo_bit_t vsd_dw45[0x00020];
503 /* -------------- */
504  pseudo_bit_t vsd_dw46[0x00020];
505 /* -------------- */
506  pseudo_bit_t vsd_dw47[0x00020];
507 /* -------------- */
508  pseudo_bit_t vsd_dw48[0x00020];
509 /* -------------- */
510  pseudo_bit_t vsd_dw49[0x00020];
511 /* -------------- */
512  pseudo_bit_t vsd_dw50[0x00020];
513 /* -------------- */
514  pseudo_bit_t vsd_dw51[0x00020];
515 /* -------------- */
516  pseudo_bit_t vsd_dw52[0x00020];
517 /* -------------- */
518  pseudo_bit_t vsd_dw53[0x00020];
519 /* -------------- */
520  pseudo_bit_t vsd_dw54[0x00020];
521 /* -------------- */
522  pseudo_bit_t vsd_dw55[0x00020];
523 /* -------------- */
524 };
525 
526 /* UAR Parameters */
527 
528 struct hermonprm_uar_params_st { /* Little Endian */
529  pseudo_bit_t reserved0[0x00040];
530 /* -------------- */
531  pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page.
532  Size of UAR Page is 4KB*2^UAR_Page_Size */
533  pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */
534  pseudo_bit_t reserved1[0x00014];
535 /* -------------- */
536  pseudo_bit_t reserved2[0x000a0];
537 /* -------------- */
538 };
539 
540 /* Translation and Protection Tables Parameters */
541 
542 struct hermonprm_tptparams_st { /* Little Endian */
543  pseudo_bit_t dmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32].
544  Entry size is 64 bytes.
545  Table must be aligned to its size.
546  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
547 /* -------------- */
548  pseudo_bit_t dmpt_base_adr_l[0x00020];/* dMPT - Memory Protection Table base physical address [31:0].
549  Entry size is 64 bytes.
550  Table must be aligned to its size.
551  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
552 /* -------------- */
553  pseudo_bit_t log_dmpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the dMPT table. */
554  pseudo_bit_t reserved0[0x00002];
555  pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout -
556  The field returned in RNR Naks generated when a page fault is detected.
557  It has no effect when on-demand-paging is not used. */
558  pseudo_bit_t reserved1[0x00013];
559 /* -------------- */
560  pseudo_bit_t reserved2[0x00020];
561 /* -------------- */
562  pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
563  Table must be aligned to its size.
564  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
565 /* -------------- */
566  pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
567  Table must be aligned to its size.
568  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
569 /* -------------- */
570  pseudo_bit_t cmpt_base_adr_h[0x00020];/* cMPT - Memory Protection Table base physical address [63:32].
571  Entry size is 64 bytes.
572  Table must be aligned to its size. */
573 /* -------------- */
574  pseudo_bit_t cmpt_base_adr_l[0x00020];/* cMPT - Memory Protection Table base physical address [31:0].
575  Entry size is 64 bytes.
576  Table must be aligned to its size. */
577 /* -------------- */
578 };
579 
580 /* Multicast Support Parameters #### michal - match PRM */
581 
582 struct hermonprm_multicastparam_st { /* Little Endian */
583  pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
584  The base address must be aligned to the entry size.
585  Address may be set to 0xFFFFFFFF if multicast is not supported. */
586 /* -------------- */
587  pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0].
588  The base address must be aligned to the entry size.
589  Address may be set to 0xFFFFFFFF if multicast is not supported. */
590 /* -------------- */
591  pseudo_bit_t reserved0[0x00040];
592 /* -------------- */
593  pseudo_bit_t log_mc_table_entry_sz[0x00005];/* Log2 of the Size of multicast group member (MGM) entry.
594  Must be greater than 5 (to allow CTRL and GID sections).
595  That implies the number of QPs per MC table entry. */
596  pseudo_bit_t reserved1[0x0000b];
597  pseudo_bit_t reserved2[0x00010];
598 /* -------------- */
599  pseudo_bit_t log_mc_table_hash_sz[0x00005];/* Number of entries in multicast DGID hash table (must be power of 2)
600  INIT_HCA - the required number of entries
601  QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
602  pseudo_bit_t reserved3[0x0001b];
603 /* -------------- */
604  pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
605  pseudo_bit_t reserved4[0x00013];
606  pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function
607  0 - Default hash function
608  other - reserved */
609  pseudo_bit_t uc_group_steering[0x00001];
610  pseudo_bit_t reserved5[0x00004];
611 /* -------------- */
612  pseudo_bit_t reserved6[0x00020];
613 /* -------------- */
614 };
615 
616 /* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */
617 
618 struct hermonprm_qpcbaseaddr_st { /* Little Endian */
619  pseudo_bit_t reserved0[0x00080];
620 /* -------------- */
621  pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
622  Table must be aligned on its size */
623 /* -------------- */
624  pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
625  pseudo_bit_t qpc_base_addr_l[0x0001b];/* QPC Base Address [31:7]
626  Table must be aligned on its size */
627 /* -------------- */
628  pseudo_bit_t reserved1[0x00040];
629 /* -------------- */
630  pseudo_bit_t reserved2[0x00040];
631 /* -------------- */
632  pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
633  Table must be aligned on its size
634  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
635 /* -------------- */
636  pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
637  pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
638  Table must be aligned on its size
639  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
640 /* -------------- */
641  pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
642  Table must be aligned on its size */
643 /* -------------- */
644  pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
645  pseudo_bit_t cqc_base_addr_l[0x0001b];/* CQC Base Address [31:6]
646  Table must be aligned on its size */
647 /* -------------- */
648  pseudo_bit_t reserved3[0x00040];
649 /* -------------- */
650  pseudo_bit_t altc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32]
651  Table has same number of entries as QPC table.
652  Table must be aligned to entry size. */
653 /* -------------- */
654  pseudo_bit_t altc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0]
655  Table has same number of entries as QPC table.
656  Table must be aligned to entry size. */
657 /* -------------- */
658  pseudo_bit_t reserved4[0x00040];
659 /* -------------- */
660  pseudo_bit_t auxc_base_addr_h[0x00020];
661 /* -------------- */
662  pseudo_bit_t auxc_base_addr_l[0x00020];
663 /* -------------- */
664  pseudo_bit_t reserved5[0x00040];
665 /* -------------- */
666  pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
667  Address may be set to 0xFFFFFFFF if EQs are not supported.
668  Table must be aligned to entry size. */
669 /* -------------- */
670  pseudo_bit_t log_num_of_eq[0x00005];/* Log base 2 of number of supported EQs.
671  Must be 6 or less in InfiniHost-III-EX. */
672  pseudo_bit_t eqc_base_addr_l[0x0001b];/* EQC Base Address [31:6]
673  Address may be set to 0xFFFFFFFF if EQs are not supported.
674  Table must be aligned to entry size. */
675 /* -------------- */
676  pseudo_bit_t reserved6[0x00040];
677 /* -------------- */
678  pseudo_bit_t rdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */
679 /* -------------- */
680  pseudo_bit_t log_num_rd[0x00003]; /* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */
681  pseudo_bit_t reserved7[0x00002];
682  pseudo_bit_t rdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0].
683  Table must be aligned to RDB entry size (32 bytes). */
684 /* -------------- */
685  pseudo_bit_t reserved8[0x00040];
686 /* -------------- */
687 };
688 
689 /* Header_Log_Register */
690 
691 struct hermonprm_header_log_register_st { /* Little Endian */
692  pseudo_bit_t place_holder[0x00020];
693 /* -------------- */
694  pseudo_bit_t reserved0[0x00060];
695 /* -------------- */
696 };
697 
698 /* Performance Monitors */
699 
700 struct hermonprm_performance_monitors_st { /* Little Endian */
701  pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */
702  pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */
703  pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */
704  pseudo_bit_t reserved0[0x00001];
705  pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
706  pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
707  pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
708  pseudo_bit_t reserved1[0x00001];
709  pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
710  pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
711  pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
712  pseudo_bit_t reserved2[0x00001];
713  pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
714  pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
715  pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
716  pseudo_bit_t reserved3[0x00001];
717  pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
718  pseudo_bit_t reserved4[0x00003];
719  pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
720  pseudo_bit_t reserved5[0x00003];
721 /* -------------- */
722  pseudo_bit_t clock_counter[0x00020];
723 /* -------------- */
724  pseudo_bit_t event_counter1[0x00020];
725 /* -------------- */
726  pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
727 /* -------------- */
728 };
729 
730 /* MLX WQE segment format */
731 
732 struct hermonprm_wqe_segment_ctrl_mlx_st { /* Little Endian */
733  pseudo_bit_t opcode[0x00005]; /* must be 0xA = SEND */
734  pseudo_bit_t reserved0[0x0001a];
735  pseudo_bit_t owner[0x00001];
736 /* -------------- */
737  pseudo_bit_t ds[0x00006]; /* Descriptor Size */
738  pseudo_bit_t reserved1[0x0001a];
739 /* -------------- */
740  pseudo_bit_t fl[0x00001]; /* Force LoopBack */
741  pseudo_bit_t reserved2[0x00001];
742  pseudo_bit_t c[0x00002]; /* Create CQE (for "requested signalling" QP) */
743  pseudo_bit_t icrc[0x00001]; /* last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. 1 - Leave last dword as is. */
744  pseudo_bit_t reserved3[0x00003];
745  pseudo_bit_t sl[0x00004];
746  pseudo_bit_t max_statrate[0x00004];
747  pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */
748  pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */
749  pseudo_bit_t reserved4[0x0000e];
750 /* -------------- */
751  pseudo_bit_t reserved5[0x00010];
752  pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */
753 /* -------------- */
754 };
755 
756 /* Send WQE segment format */
757 
758 struct hermonprm_send_wqe_segment_st { /* Little Endian */
759  struct hermonprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */
760 /* -------------- */
761  struct hermonprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */
762 /* -------------- */
763  struct hermonprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */
764 /* -------------- */
765  struct hermonprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */
766 /* -------------- */
767  pseudo_bit_t reserved0[0x00180];
768 /* -------------- */
769  struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */
770 /* -------------- */
771  struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */
772 /* -------------- */
773  struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */
774 /* -------------- */
775  struct hermonprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */
776 /* -------------- */
777  struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */
778 /* -------------- */
779  struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */
780 /* -------------- */
781  pseudo_bit_t reserved1[0x00200];
782 /* -------------- */
783 };
784 
785 /* QP and EE Context Entry */
786 
787 struct hermonprm_queue_pair_ee_context_entry_st { /* Little Endian */
788  pseudo_bit_t reserved0[0x00008];
789  pseudo_bit_t reserved1[0x00001];
790  pseudo_bit_t reserved2[0x00002];
791  pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm)
792  11-Migrated
793  00-Armed
794  01-Rearm
795  10-Reserved
796  Should be set to 11 for UD QPs and for QPs which do not support APM */
797  pseudo_bit_t reserved3[0x00003];
798  pseudo_bit_t st[0x00004]; /* Transport Service Type: RC: 0, UC: 1, RD: 2, UD: 3, FCMND:4, FEXCH:5, SRC:6, MLX 7, Raw Eth 11 */
799  pseudo_bit_t reserved4[0x00008];
800  pseudo_bit_t state[0x00004]; /* QP/EE state:
801  0 - RST
802  1 - INIT
803  2 - RTR
804  3 - RTS
805  4 - SQEr
806  5 - SQD (Send Queue Drained)
807  6 - ERR
808  7 - Send Queue Draining
809  8 - Reserved
810  9 - Suspended
811  A- F - Reserved
812  (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
813 /* -------------- */
814  pseudo_bit_t pd[0x00018];
815  pseudo_bit_t reserved5[0x00008];
816 /* -------------- */
817  pseudo_bit_t reserved6[0x00004];
818  pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */
819  pseudo_bit_t reserved7[0x00003];
820  pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
821  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
822  pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */
823  pseudo_bit_t reserved8[0x00001];
824  pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
825  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
826  pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */
827  pseudo_bit_t reserved9[0x00001];
828  pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
829  Must be equal to MTU for UD and MLX QPs. */
830  pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative):
831  0x1 - 256 bytes
832  0x2 - 512
833  0x3 - 1024
834  0x4 - 2048
835  other - reserved
836 
837  Should be configured to 0x4 for UD and MLX QPs. */
838 /* -------------- */
839  pseudo_bit_t usr_page[0x00018]; /* UAR number to ring doorbells for this QP (aliased to doorbell and Blue Flame pages) */
840  pseudo_bit_t reserved10[0x00008];
841 /* -------------- */
842  pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
843  This field is valid for QUERY and ERR2RST commands only. */
844  pseudo_bit_t reserved11[0x00008];
845 /* -------------- */
846  pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */
847  pseudo_bit_t reserved12[0x00008];
848 /* -------------- */
849  struct hermonprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */
850 /* -------------- */
851  struct hermonprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */
852 /* -------------- */
853  pseudo_bit_t reserved13[0x00003];
854  pseudo_bit_t reserved14[0x00001];
855  pseudo_bit_t reserved15[0x00001];
856  pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
857  The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
858  pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
859  The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
860  pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */
861  pseudo_bit_t reserved16[0x00001];
862  pseudo_bit_t rnr_retry[0x00003];
863  pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */
864  pseudo_bit_t reserved17[0x00002];
865  pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
866  pseudo_bit_t reserved18[0x00004];
867  pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
868 /* -------------- */
869  pseudo_bit_t reserved19[0x00020];
870 /* -------------- */
871  pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */
872  pseudo_bit_t reserved20[0x00008];
873 /* -------------- */
874  pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
875  pseudo_bit_t reserved21[0x00008];
876 /* -------------- */
877  pseudo_bit_t reserved22[0x00040];
878 /* -------------- */
879  pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
880  pseudo_bit_t reserved23[0x00008];
881 /* -------------- */
882  pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */
883  pseudo_bit_t reserved24[0x00008];
884 /* -------------- */
885  pseudo_bit_t reserved25[0x00004];
886  pseudo_bit_t ric[0x00001]; /* Invalid Credits.
887  1 - place "Invalid Credits" to ACKs sent from this queue.
888  0 - ACKs report the actual number of end to end credits on the connection.
889  Not valid (reserved) in EE context.
890  Must be set to 1 on QPs which are attached to SRQ. */
891  pseudo_bit_t reserved26[0x00001];
892  pseudo_bit_t page_offset[0x00006]; /* start address of wqes in first page (11:6), bits [5:0] reserved */
893  pseudo_bit_t reserved27[0x00001];
894  pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
895  pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
896  pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
897  pseudo_bit_t reserved28[0x00005];
898  pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
899  Must be 0 for EE context. */
900  pseudo_bit_t physical_function[0x00008];
901 /* -------------- */
902  pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
903  pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
904  Not valid (reserved) in EE context. */
905  pseudo_bit_t reserved30[0x00003];
906 /* -------------- */
907  pseudo_bit_t srcd[0x00010]; /* Scalable Reliable Connection Domain. Valid for SRC transport service */
908  pseudo_bit_t reserved31[0x00010];
909 /* -------------- */
910  pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
911  pseudo_bit_t reserved32[0x00008];
912 /* -------------- */
913  pseudo_bit_t db_record_addr_h[0x00020];/* QP DB Record physical address */
914 /* -------------- */
915  pseudo_bit_t reserved33[0x00002];
916  pseudo_bit_t db_record_addr_l[0x0001e];/* QP DB Record physical address */
917 /* -------------- */
918  pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams.
919  On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
920  Not valid (reserved) in EE context. */
921 /* -------------- */
922  pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
923  SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
924  pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
925  pseudo_bit_t reserved34[0x00007];
926 /* -------------- */
927  pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */
928  pseudo_bit_t reserved35[0x00008];
929 /* -------------- */
930  pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
931  Must be 0x0 in SQ initialization.
932  (QUERY_QPEE only). */
933  pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
934  Must be 0x0 in RQ initialization.
935  (QUERY_QPEE only). */
936 /* -------------- */
937  pseudo_bit_t reserved36[0x00040];
938 /* -------------- */
939  pseudo_bit_t rmc_parent_qpn[0x00018];/* reliable multicast parent queue number */
940  pseudo_bit_t hs[0x00001]; /* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */
941  pseudo_bit_t is[0x00001]; /* when set - inline scatter is enabled for this RQ */
942  pseudo_bit_t reserved37[0x00001];
943  pseudo_bit_t rme[0x00002]; /* Reliable Multicast
944  00 - disabled
945  01 - parent QP (requester)
946  10 - child QP (requester)
947  11 - responder QP
948  Note that Reliable Multicast is a preliminary definition which can be subject to change. */
949  pseudo_bit_t reserved38[0x00002];
950  pseudo_bit_t mkey_rmp[0x00001]; /* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */
951 /* -------------- */
952  pseudo_bit_t base_mkey[0x00018]; /* Base Mkey bits [31:8]. Lower 8 bits must be zero. */
953  pseudo_bit_t num_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */
954 /* -------------- */
955  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
956  pseudo_bit_t reserved39[0x00010];
957  pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
958  pseudo_bit_t reserved40[0x00002];
959 /* -------------- */
960  pseudo_bit_t reserved41[0x00003];
961  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
962 /* -------------- */
963  pseudo_bit_t vft_lan[0x0000c];
964  pseudo_bit_t vft_prio[0x00003]; /* The Priority filed in the VFT header for FCP */
965  pseudo_bit_t reserved42[0x00001];
966  pseudo_bit_t cs_ctl[0x00009]; /* The Priority filed in the VFT header for FCP */
967  pseudo_bit_t reserved43[0x00006];
968  pseudo_bit_t ve[0x00001]; /* Should we add/check the VFT header */
969 /* -------------- */
970  pseudo_bit_t exch_base[0x00010]; /* For init QP only - The base exchanges */
971  pseudo_bit_t reserved44[0x00008];
972  pseudo_bit_t exch_size[0x00004]; /* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */
973  pseudo_bit_t reserved45[0x00003];
974  pseudo_bit_t fc[0x00001]; /* When set it mean that this QP is used for FIBRE CHANNEL. */
975 /* -------------- */
976  pseudo_bit_t remote_id[0x00018]; /* Peer NX port ID */
977  pseudo_bit_t reserved46[0x00008];
978 /* -------------- */
979  pseudo_bit_t fcp_mtu[0x0000a]; /* In 4*Bytes units. The MTU Size */
980  pseudo_bit_t reserved47[0x00006];
981  pseudo_bit_t my_id_indx[0x00008]; /* Index to My NX port ID table */
982  pseudo_bit_t vft_hop_count[0x00008];/* HopCnt value for the VFT header */
983 /* -------------- */
984  pseudo_bit_t reserved48[0x000c0];
985 /* -------------- */
986 };
987 
988 /* */
989 
990 struct hermonprm_mcg_qp_dw_st { /* Little Endian */
991  pseudo_bit_t qpn[0x00018];
992  pseudo_bit_t reserved0[0x00006];
993  pseudo_bit_t blck_lb[0x00001];
994  pseudo_bit_t reserved1[0x00001];
995 /* -------------- */
996 };
997 
998 /* Clear Interrupt [63:0] #### michal - match to PRM */
999 
1000 struct hermonprm_clr_int_st { /* Little Endian */
1001  pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32]
1002  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1003  This register is write-only. Reading from this register will cause undefined result
1004  */
1005 /* -------------- */
1006  pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0]
1007  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1008  This register is write-only. Reading from this register will cause undefined result */
1009 /* -------------- */
1010 };
1011 
1012 /* EQ Set CI DBs Table */
1013 
1014 struct hermonprm_eq_set_ci_table_st { /* Little Endian */
1015  pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */
1016 /* -------------- */
1017  pseudo_bit_t reserved0[0x00020];
1018 /* -------------- */
1019  pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */
1020 /* -------------- */
1021  pseudo_bit_t reserved1[0x00020];
1022 /* -------------- */
1023  pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */
1024 /* -------------- */
1025  pseudo_bit_t reserved2[0x00020];
1026 /* -------------- */
1027  pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */
1028 /* -------------- */
1029  pseudo_bit_t reserved3[0x00020];
1030 /* -------------- */
1031  pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */
1032 /* -------------- */
1033  pseudo_bit_t reserved4[0x00020];
1034 /* -------------- */
1035  pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */
1036 /* -------------- */
1037  pseudo_bit_t reserved5[0x00020];
1038 /* -------------- */
1039  pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */
1040 /* -------------- */
1041  pseudo_bit_t reserved6[0x00020];
1042 /* -------------- */
1043  pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */
1044 /* -------------- */
1045  pseudo_bit_t reserved7[0x00020];
1046 /* -------------- */
1047  pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */
1048 /* -------------- */
1049  pseudo_bit_t reserved8[0x00020];
1050 /* -------------- */
1051  pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */
1052 /* -------------- */
1053  pseudo_bit_t reserved9[0x00020];
1054 /* -------------- */
1055  pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */
1056 /* -------------- */
1057  pseudo_bit_t reserved10[0x00020];
1058 /* -------------- */
1059  pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */
1060 /* -------------- */
1061  pseudo_bit_t reserved11[0x00020];
1062 /* -------------- */
1063  pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */
1064 /* -------------- */
1065  pseudo_bit_t reserved12[0x00020];
1066 /* -------------- */
1067  pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */
1068 /* -------------- */
1069  pseudo_bit_t reserved13[0x00020];
1070 /* -------------- */
1071  pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */
1072 /* -------------- */
1073  pseudo_bit_t reserved14[0x00020];
1074 /* -------------- */
1075  pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */
1076 /* -------------- */
1077  pseudo_bit_t reserved15[0x00020];
1078 /* -------------- */
1079  pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */
1080 /* -------------- */
1081  pseudo_bit_t reserved16[0x00020];
1082 /* -------------- */
1083  pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */
1084 /* -------------- */
1085  pseudo_bit_t reserved17[0x00020];
1086 /* -------------- */
1087  pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */
1088 /* -------------- */
1089  pseudo_bit_t reserved18[0x00020];
1090 /* -------------- */
1091  pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */
1092 /* -------------- */
1093  pseudo_bit_t reserved19[0x00020];
1094 /* -------------- */
1095  pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */
1096 /* -------------- */
1097  pseudo_bit_t reserved20[0x00020];
1098 /* -------------- */
1099  pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */
1100 /* -------------- */
1101  pseudo_bit_t reserved21[0x00020];
1102 /* -------------- */
1103  pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */
1104 /* -------------- */
1105  pseudo_bit_t reserved22[0x00020];
1106 /* -------------- */
1107  pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */
1108 /* -------------- */
1109  pseudo_bit_t reserved23[0x00020];
1110 /* -------------- */
1111  pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */
1112 /* -------------- */
1113  pseudo_bit_t reserved24[0x00020];
1114 /* -------------- */
1115  pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */
1116 /* -------------- */
1117  pseudo_bit_t reserved25[0x00020];
1118 /* -------------- */
1119  pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */
1120 /* -------------- */
1121  pseudo_bit_t reserved26[0x00020];
1122 /* -------------- */
1123  pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */
1124 /* -------------- */
1125  pseudo_bit_t reserved27[0x00020];
1126 /* -------------- */
1127  pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */
1128 /* -------------- */
1129  pseudo_bit_t reserved28[0x00020];
1130 /* -------------- */
1131  pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */
1132 /* -------------- */
1133  pseudo_bit_t reserved29[0x00020];
1134 /* -------------- */
1135  pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */
1136 /* -------------- */
1137  pseudo_bit_t reserved30[0x00020];
1138 /* -------------- */
1139  pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */
1140 /* -------------- */
1141  pseudo_bit_t reserved31[0x00020];
1142 /* -------------- */
1143  pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */
1144 /* -------------- */
1145  pseudo_bit_t reserved32[0x00020];
1146 /* -------------- */
1147  pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */
1148 /* -------------- */
1149  pseudo_bit_t reserved33[0x00020];
1150 /* -------------- */
1151  pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */
1152 /* -------------- */
1153  pseudo_bit_t reserved34[0x00020];
1154 /* -------------- */
1155  pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */
1156 /* -------------- */
1157  pseudo_bit_t reserved35[0x00020];
1158 /* -------------- */
1159  pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */
1160 /* -------------- */
1161  pseudo_bit_t reserved36[0x00020];
1162 /* -------------- */
1163  pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */
1164 /* -------------- */
1165  pseudo_bit_t reserved37[0x00020];
1166 /* -------------- */
1167  pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */
1168 /* -------------- */
1169  pseudo_bit_t reserved38[0x00020];
1170 /* -------------- */
1171  pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */
1172 /* -------------- */
1173  pseudo_bit_t reserved39[0x00020];
1174 /* -------------- */
1175  pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */
1176 /* -------------- */
1177  pseudo_bit_t reserved40[0x00020];
1178 /* -------------- */
1179  pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */
1180 /* -------------- */
1181  pseudo_bit_t reserved41[0x00020];
1182 /* -------------- */
1183  pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */
1184 /* -------------- */
1185  pseudo_bit_t reserved42[0x00020];
1186 /* -------------- */
1187  pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */
1188 /* -------------- */
1189  pseudo_bit_t reserved43[0x00020];
1190 /* -------------- */
1191  pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */
1192 /* -------------- */
1193  pseudo_bit_t reserved44[0x00020];
1194 /* -------------- */
1195  pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */
1196 /* -------------- */
1197  pseudo_bit_t reserved45[0x00020];
1198 /* -------------- */
1199  pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */
1200 /* -------------- */
1201  pseudo_bit_t reserved46[0x00020];
1202 /* -------------- */
1203  pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */
1204 /* -------------- */
1205  pseudo_bit_t reserved47[0x00020];
1206 /* -------------- */
1207  pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */
1208 /* -------------- */
1209  pseudo_bit_t reserved48[0x00020];
1210 /* -------------- */
1211  pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */
1212 /* -------------- */
1213  pseudo_bit_t reserved49[0x00020];
1214 /* -------------- */
1215  pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */
1216 /* -------------- */
1217  pseudo_bit_t reserved50[0x00020];
1218 /* -------------- */
1219  pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */
1220 /* -------------- */
1221  pseudo_bit_t reserved51[0x00020];
1222 /* -------------- */
1223  pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */
1224 /* -------------- */
1225  pseudo_bit_t reserved52[0x00020];
1226 /* -------------- */
1227  pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */
1228 /* -------------- */
1229  pseudo_bit_t reserved53[0x00020];
1230 /* -------------- */
1231  pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */
1232 /* -------------- */
1233  pseudo_bit_t reserved54[0x00020];
1234 /* -------------- */
1235  pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */
1236 /* -------------- */
1237  pseudo_bit_t reserved55[0x00020];
1238 /* -------------- */
1239  pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */
1240 /* -------------- */
1241  pseudo_bit_t reserved56[0x00020];
1242 /* -------------- */
1243  pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */
1244 /* -------------- */
1245  pseudo_bit_t reserved57[0x00020];
1246 /* -------------- */
1247  pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */
1248 /* -------------- */
1249  pseudo_bit_t reserved58[0x00020];
1250 /* -------------- */
1251  pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */
1252 /* -------------- */
1253  pseudo_bit_t reserved59[0x00020];
1254 /* -------------- */
1255  pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */
1256 /* -------------- */
1257  pseudo_bit_t reserved60[0x00020];
1258 /* -------------- */
1259  pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */
1260 /* -------------- */
1261  pseudo_bit_t reserved61[0x00020];
1262 /* -------------- */
1263  pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */
1264 /* -------------- */
1265  pseudo_bit_t reserved62[0x00020];
1266 /* -------------- */
1267  pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */
1268 /* -------------- */
1269  pseudo_bit_t reserved63[0x00020];
1270 /* -------------- */
1271 };
1272 
1273 /* InfiniHost-III-EX Configuration Registers #### michal - match to PRM */
1274 
1275 struct hermonprm_configuration_registers_st { /* Little Endian */
1276  pseudo_bit_t reserved0[0x403400];
1277 /* -------------- */
1278  struct hermonprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */
1279 /* -------------- */
1280  pseudo_bit_t reserved1[0x3fcb20];
1281 /* -------------- */
1282 };
1283 
1284 /* QP_DB_Record ### michal = gdror fixed */
1285 
1286 struct hermonprm_qp_db_record_st { /* Little Endian */
1287  pseudo_bit_t receive_wqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */
1288  pseudo_bit_t reserved0[0x00010];
1289 /* -------------- */
1290 };
1291 
1292 /* CQ_ARM_DB_Record */
1293 
1294 struct hermonprm_cq_arm_db_record_st { /* Little Endian */
1295  pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */
1296 /* -------------- */
1297  pseudo_bit_t cmd[0x00003]; /* 0x0 - No command
1298  0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
1299  0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
1300  0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
1301  Other - Reserved */
1302  pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
1303  pseudo_bit_t res[0x00003]; /* Must be 0x2 */
1304  pseudo_bit_t cq_number[0x00018]; /* CQ number */
1305 /* -------------- */
1306 };
1307 
1308 /* CQ_CI_DB_Record */
1309 
1310 struct hermonprm_cq_ci_db_record_st { /* Little Endian */
1311  pseudo_bit_t counter[0x00020]; /* CQ counter */
1312 /* -------------- */
1313  pseudo_bit_t reserved0[0x00005];
1314  pseudo_bit_t res[0x00003]; /* Must be 0x1 */
1315  pseudo_bit_t cq_number[0x00018]; /* CQ number */
1316 /* -------------- */
1317 };
1318 
1319 /* Virtual_Physical_Mapping */
1320 
1321 struct hermonprm_virtual_physical_mapping_st { /* Little Endian */
1322  pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */
1323 /* -------------- */
1324  pseudo_bit_t reserved0[0x0000c];
1325  pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */
1326 /* -------------- */
1327  pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */
1328 /* -------------- */
1329  pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */
1330  pseudo_bit_t reserved1[0x00006];
1331  pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */
1332 /* -------------- */
1333 };
1334 
1335 /* MOD_STAT_CFG #### michal - gdror fix */
1336 
1337 struct hermonprm_mod_stat_cfg_st { /* Little Endian */
1338  pseudo_bit_t log_pg_sz[0x00008];
1339  pseudo_bit_t log_pg_sz_m[0x00001];
1340  pseudo_bit_t reserved0[0x00005];
1341  pseudo_bit_t dife[0x00001];
1342  pseudo_bit_t dife_m[0x00001];
1343  pseudo_bit_t rx_options[0x00004]; /* number of RX options to sweep when doing SerDes parameters AutoNegotiation. */
1344  pseudo_bit_t reserved1[0x00003];
1345  pseudo_bit_t rx_options_m[0x00001]; /* Modify rx_options */
1346  pseudo_bit_t tx_options[0x00004]; /* number of TX options to sweep when doing SerDes parameters AutoNegotiation. */
1347  pseudo_bit_t reserved2[0x00003];
1348  pseudo_bit_t tx_options_m[0x00001]; /* Modify tx_options */
1349 /* -------------- */
1350  pseudo_bit_t reserved3[0x00010];
1351  pseudo_bit_t qdr_rx_options[0x00004];
1352  pseudo_bit_t reserved4[0x00003];
1353  pseudo_bit_t qdr_rx_options_m[0x00001];
1354  pseudo_bit_t qdr_tx_options[0x00004];
1355  pseudo_bit_t reserved5[0x00003];
1356  pseudo_bit_t qdr_tx_options_m[0x00001];
1357 /* -------------- */
1358  pseudo_bit_t reserved6[0x00020];
1359 /* -------------- */
1360  pseudo_bit_t lid[0x00010]; /* default LID */
1361  pseudo_bit_t lid_m[0x00001]; /* Modify default LID */
1362  pseudo_bit_t reserved7[0x00003];
1363  pseudo_bit_t port_en[0x00001]; /* enable port (E_Key) */
1364  pseudo_bit_t port_en_m[0x00001]; /* Modify port_en */
1365  pseudo_bit_t reserved8[0x00002];
1366  pseudo_bit_t port_pause_mode[0x00002];
1367  pseudo_bit_t reserved9[0x00001];
1368  pseudo_bit_t port_pause_mode_m[0x00001];
1369  pseudo_bit_t reserved10[0x00004];
1370 /* -------------- */
1371  pseudo_bit_t reserved11[0x0001f];
1372  pseudo_bit_t guid_hi_m[0x00001]; /* Modify guid_hi */
1373 /* -------------- */
1374  pseudo_bit_t guid_hi[0x00020];
1375 /* -------------- */
1376  pseudo_bit_t reserved12[0x0001f];
1377  pseudo_bit_t guid_lo_m[0x00001]; /* Modify guid_lo */
1378 /* -------------- */
1379  pseudo_bit_t guid_lo[0x00020];
1380 /* -------------- */
1381  pseudo_bit_t reserved13[0x0001f];
1382  pseudo_bit_t nodeguid_hi_m[0x00001];
1383 /* -------------- */
1384  pseudo_bit_t nodeguid_hi[0x00020];
1385 /* -------------- */
1386  pseudo_bit_t reserved14[0x0001f];
1387  pseudo_bit_t nodeguid_lo_m[0x00001];
1388 /* -------------- */
1389  pseudo_bit_t nodeguid_lo[0x00020];
1390 /* -------------- */
1391  pseudo_bit_t ob_preemp_pre[0x00005];
1392  pseudo_bit_t reserved15[0x00003];
1393  pseudo_bit_t ob_preemp_post[0x00005];
1394  pseudo_bit_t reserved16[0x00003];
1395  pseudo_bit_t ob_preemp_main[0x00005];
1396  pseudo_bit_t reserved17[0x00003];
1397  pseudo_bit_t ob_preemp[0x00005];
1398  pseudo_bit_t reserved18[0x00002];
1399  pseudo_bit_t serdes_m[0x00001];
1400 /* -------------- */
1401  pseudo_bit_t inbuf_ind_en[0x00003];
1402  pseudo_bit_t reserved19[0x00001];
1403  pseudo_bit_t sd_main[0x00004];
1404  pseudo_bit_t reserved20[0x00004];
1405  pseudo_bit_t sd_equal[0x00004];
1406  pseudo_bit_t reserved21[0x00004];
1407  pseudo_bit_t sd_mux_main[0x00002];
1408  pseudo_bit_t reserved22[0x00002];
1409  pseudo_bit_t mux_eq[0x00002];
1410  pseudo_bit_t reserved23[0x00002];
1411  pseudo_bit_t sigdet_th[0x00003];
1412  pseudo_bit_t reserved24[0x00001];
1413 /* -------------- */
1414  pseudo_bit_t reserved25[0x00040];
1415 /* -------------- */
1416  pseudo_bit_t port_protocol[0x00008];
1417  pseudo_bit_t port_dual[0x00001];
1418  pseudo_bit_t reserved26[0x00006];
1419  pseudo_bit_t port_protocol_m[0x00001];
1420  pseudo_bit_t num_port[0x00008];
1421  pseudo_bit_t reserved27[0x00008];
1422 /* -------------- */
1423  pseudo_bit_t port_protocol_vpi[0x00008];
1424  pseudo_bit_t reserved28[0x00018];
1425 /* -------------- */
1426  pseudo_bit_t reserved29[0x00180];
1427 /* -------------- */
1428  pseudo_bit_t fw_rev_major[0x00010];
1429  pseudo_bit_t reserved30[0x0000f];
1430  pseudo_bit_t fw_rev_support[0x00001];
1431 /* -------------- */
1432  pseudo_bit_t fw_rev_minor[0x00010];
1433  pseudo_bit_t fw_rev_subminor[0x00010];
1434 /* -------------- */
1435  pseudo_bit_t cmd_interface_rev[0x00010];
1436  pseudo_bit_t reserved31[0x00010];
1437 /* -------------- */
1438  pseudo_bit_t reserved32[0x00060];
1439 /* -------------- */
1440  pseudo_bit_t mac_high[0x00010];
1441  pseudo_bit_t reserved33[0x0000f];
1442  pseudo_bit_t mac_m[0x00001];
1443 /* -------------- */
1444  pseudo_bit_t mac_low[0x00020];
1445 /* -------------- */
1446  pseudo_bit_t reserved34[0x00010];
1447  pseudo_bit_t num_veps[0x00008];
1448  pseudo_bit_t num_vep_groups[0x00008];
1449 /* -------------- */
1450  pseudo_bit_t reserved35[0x00020];
1451 /* -------------- */
1452  pseudo_bit_t reserved36[0x00018];
1453  pseudo_bit_t outer_vlan_en[0x00001];
1454  pseudo_bit_t reserved37[0x00002];
1455  pseudo_bit_t outer_vlan_en_m[0x00001];
1456  pseudo_bit_t port_net_boot[0x00001];
1457  pseudo_bit_t reserved38[0x00002];
1458  pseudo_bit_t port_net_boot_m[0x00001];
1459 /* -------------- */
1460  pseudo_bit_t reserved39[0x00060];
1461 /* -------------- */
1462  pseudo_bit_t port_eth_mode_capability[0x0001f];
1463  pseudo_bit_t reserved40[0x00001];
1464 /* -------------- */
1465  pseudo_bit_t port_eth_mode_enabled[0x0001f];
1466  pseudo_bit_t port_eth_mod_m[0x00001];
1467 /* -------------- */
1468  pseudo_bit_t port_eth_mode_current[0x0001f];
1469  pseudo_bit_t reserved41[0x00001];
1470 /* -------------- */
1471  pseudo_bit_t reserved42[0x00220];
1472 };
1473 
1474 /* SRQ Context */
1475 
1476 struct hermonprm_srq_context_st { /* Little Endian */
1477  pseudo_bit_t srqn[0x00018]; /* SRQ number */
1478  pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue.
1479  Maximum value is 0x10, i.e. 16M WQEs. */
1480  pseudo_bit_t state[0x00004]; /* SRQ State:
1481  1111 - SW Ownership
1482  0000 - HW Ownership
1483  0001 - Error
1484  Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1485 /* -------------- */
1486  pseudo_bit_t src_domain[0x00010]; /* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */
1487  pseudo_bit_t reserved0[0x00008];
1488  pseudo_bit_t log_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
1489  pseudo_bit_t reserved1[0x00005];
1490 /* -------------- */
1491  pseudo_bit_t cqn[0x00018]; /* Completion Queue to report SRC messages directed to this SRQ. */
1492  pseudo_bit_t page_offset[0x00006]; /* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,“Work Queue Buffer Structure”) */
1493  pseudo_bit_t reserved2[0x00002];
1494 /* -------------- */
1495  pseudo_bit_t reserved3[0x00020];
1496 /* -------------- */
1497  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
1498  pseudo_bit_t reserved4[0x00010];
1499  pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
1500  pseudo_bit_t reserved5[0x00002];
1501 /* -------------- */
1502  pseudo_bit_t reserved6[0x00003];
1503  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
1504 /* -------------- */
1505  pseudo_bit_t pd[0x00018]; /* SRQ protection domain */
1506  pseudo_bit_t reserved7[0x00008];
1507 /* -------------- */
1508  pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */
1509  pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */
1510 /* -------------- */
1511  pseudo_bit_t srq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */
1512  pseudo_bit_t reserved8[0x00010];
1513 /* -------------- */
1514  pseudo_bit_t reserved9[0x00020];
1515 /* -------------- */
1516  pseudo_bit_t db_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */
1517 /* -------------- */
1518  pseudo_bit_t reserved10[0x00002];
1519  pseudo_bit_t db_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */
1520 /* -------------- */
1521 };
1522 
1523 /* PBL */
1524 
1525 struct hermonprm_pbl_st { /* Little Endian */
1526  pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */
1527 /* -------------- */
1528  pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */
1529 /* -------------- */
1530  pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */
1531 /* -------------- */
1532  pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */
1533 /* -------------- */
1534  pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */
1535 /* -------------- */
1536  pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */
1537 /* -------------- */
1538  pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */
1539 /* -------------- */
1540  pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */
1541 /* -------------- */
1542 };
1543 
1544 /* Performance Counters #### michal - gdror fixed */
1545 
1546 struct hermonprm_performance_counters_st { /* Little Endian */
1547  pseudo_bit_t reserved0[0x00080];
1548 /* -------------- */
1549  pseudo_bit_t reserved1[0x00080];
1550 /* -------------- */
1551  pseudo_bit_t reserved2[0x00080];
1552 /* -------------- */
1553  pseudo_bit_t reserved3[0x00060];
1554 /* -------------- */
1555  pseudo_bit_t reserved4[0x00620];
1556 /* -------------- */
1557 };
1558 
1559 /* Transport and CI Error Counters */
1560 
1561 struct hermonprm_transport_and_ci_error_counters_st { /* Little Endian */
1562  pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */
1563 /* -------------- */
1564  pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */
1565 /* -------------- */
1566  pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */
1567 /* -------------- */
1568  pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */
1569 /* -------------- */
1570  pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */
1571 /* -------------- */
1572  pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */
1573 /* -------------- */
1574  pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */
1575 /* -------------- */
1576  pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */
1577 /* -------------- */
1578  pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error.
1579  Incremented each time a CQE with error is generated */
1580 /* -------------- */
1581  pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error.
1582  Incremented each time a CQE with error is generated */
1583 /* -------------- */
1584  pseudo_bit_t reserved0[0x00020];
1585 /* -------------- */
1586  pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */
1587 /* -------------- */
1588  pseudo_bit_t reserved1[0x00020];
1589 /* -------------- */
1590  pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */
1591 /* -------------- */
1592  pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */
1593 /* -------------- */
1594  pseudo_bit_t reserved2[0x00040];
1595 /* -------------- */
1596  pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors
1597  NAK-Invalid Request on:
1598  1. Unsupported OpCode: Responder detected an unsupported OpCode.
1599  2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such
1600  as a missing "Last" packet.
1601  Note: there is no PSN error, thus this does not indicate a dropped packet. */
1602 /* -------------- */
1603  pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors.
1604  NAK may or may not be sent.
1605  1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only):
1606  Inbound request OpCode was either reserved, or was for a function not supported by this
1607  QP. (E.g. RDMA or ATOMIC on QP not set up for this).
1608  2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion.
1609  3. Too many RDMA READ or ATOMIC Requests: There were more requests received
1610  and not ACKed than allowed for the connection.
1611  4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder
1612  detected an error in the sequence of OpCodes; a missing "Last" packet
1613  5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder
1614  detected an error in the sequence of OpCodes; a missing "First" packet
1615  6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able
1616  buffer space.
1617  7. Length error: RDMA WRITE request message contained too much or too little pay-load
1618  data compared to the DMA length advertised in the first or only packet.
1619  8. Length error: Payload length was not consistent with the opcode:
1620  a: 0 byte <= "only" <= PMTU bytes
1621  b: ("first" or "middle") == PMTU bytes
1622  c: 1byte <= "last" <= PMTU bytes
1623  9. Length error: Inbound message exceeded the size supported by the CA port. */
1624 /* -------------- */
1625  pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors.
1626  NAK-Remote Access Error on:
1627  R_Key Violation: Responder detected an invalid R_Key while executing an RDMA
1628  Request. */
1629 /* -------------- */
1630  pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors.
1631  R_Key Violation Responder detected an R_Key violation while executing an RDMA
1632  request.
1633  NAK may or may not be sent. */
1634 /* -------------- */
1635  pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors.
1636  NAK-Remote Operation Error on:
1637  Remote Operation Error: Responder encountered an error, (local to the responder),
1638  which prevented it from completing the request. */
1639 /* -------------- */
1640  pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors.
1641  NAK-Remote Operation Error on:
1642  1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing
1643  the packet.
1644  2. Remote Operation Error: Responder encountered an error, (local to the responder),
1645  which prevented it from completing the request. */
1646 /* -------------- */
1647  pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */
1648 /* -------------- */
1649  pseudo_bit_t reserved3[0x00020];
1650 /* -------------- */
1651  pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */
1652 /* -------------- */
1653  pseudo_bit_t rq_num_rnr[0x00020]; /* Responder - the number of RNR Naks sent */
1654 /* -------------- */
1655  pseudo_bit_t sq_num_rnr[0x00020]; /* Requester - the number of RNR Naks received */
1656 /* -------------- */
1657  pseudo_bit_t reserved4[0x00040];
1658 /* -------------- */
1659  pseudo_bit_t reserved5[0x00020];
1660 /* -------------- */
1661  pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */
1662 /* -------------- */
1663  pseudo_bit_t reserved6[0x00020];
1664 /* -------------- */
1665  pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */
1666 /* -------------- */
1667  pseudo_bit_t reserved7[0x00020];
1668 /* -------------- */
1669  pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */
1670 /* -------------- */
1671  pseudo_bit_t reserved8[0x00380];
1672 /* -------------- */
1673  pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */
1674 /* -------------- */
1675  pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */
1676 /* -------------- */
1677  pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */
1678 /* -------------- */
1679  pseudo_bit_t reserved9[0x00020];
1680 /* -------------- */
1681  pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */
1682 /* -------------- */
1683  pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */
1684 /* -------------- */
1685  pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */
1686 /* -------------- */
1687  pseudo_bit_t reserved10[0x00020];
1688 /* -------------- */
1689  pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */
1690 /* -------------- */
1691  pseudo_bit_t reserved11[0x003e0];
1692 /* -------------- */
1693  pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */
1694 /* -------------- */
1695  pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */
1696 /* -------------- */
1697  pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */
1698 /* -------------- */
1699  pseudo_bit_t reserved12[0x002a0];
1700 /* -------------- */
1701 };
1702 
1703 /* Event_data Field - HCR Completion Event #### michal - match PRM */
1704 
1705 struct hermonprm_hcr_completion_event_st { /* Little Endian */
1706  pseudo_bit_t token[0x00010]; /* HCR Token */
1707  pseudo_bit_t reserved0[0x00010];
1708 /* -------------- */
1709  pseudo_bit_t reserved1[0x00020];
1710 /* -------------- */
1711  pseudo_bit_t status[0x00008]; /* HCR Status */
1712  pseudo_bit_t reserved2[0x00018];
1713 /* -------------- */
1714  pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */
1715 /* -------------- */
1716  pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */
1717 /* -------------- */
1718  pseudo_bit_t reserved3[0x00020];
1719 /* -------------- */
1720 };
1721 
1722 /* Completion with Error CQE #### michal - gdror fixed */
1723 
1724 struct hermonprm_completion_with_error_st { /* Little Endian */
1725  pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */
1726  pseudo_bit_t reserved0[0x00008];
1727 /* -------------- */
1728  pseudo_bit_t reserved1[0x000a0];
1729 /* -------------- */
1730  pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome:
1731  0x01 - Local Length Error
1732  0x02 - Local QP Operation Error
1733  0x03 - Local EE Context Operation Error
1734  0x04 - Local Protection Error
1735  0x05 - Work Request Flushed Error
1736  0x06 - Memory Window Bind Error
1737  0x10 - Bad Response Error
1738  0x11 - Local Access Error
1739  0x12 - Remote Invalid Request Error
1740  0x13 - Remote Access Error
1741  0x14 - Remote Operation Error
1742  0x15 - Transport Retry Counter Exceeded
1743  0x16 - RNR Retry Counter Exceeded
1744  0x20 - Local RDD Violation Error
1745  0x21 - Remote Invalid RD Request
1746  0x22 - Remote Aborted Error
1747  0x23 - Invalid EE Context Number
1748  0x24 - Invalid EE Context State
1749  other - Reserved
1750  Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
1751  pseudo_bit_t vendor_error_syndrome[0x00008];
1752  pseudo_bit_t wqe_counter[0x00010];
1753 /* -------------- */
1754  pseudo_bit_t opcode[0x00005]; /* The opcode of WQE completion is reported for.
1755 
1756  The following values are reported in case of completion with error:
1757  0xFE - For completion with error on Receive Queues
1758  0xFF - For completion with error on Send Queues */
1759  pseudo_bit_t reserved2[0x00001];
1760  pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */
1761  pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */
1762  pseudo_bit_t reserved3[0x00018];
1763 /* -------------- */
1764 };
1765 
1766 /* Resize CQ Input Mailbox */
1767 
1768 struct hermonprm_resize_cq_st { /* Little Endian */
1769  pseudo_bit_t reserved0[0x00040];
1770 /* -------------- */
1771  pseudo_bit_t reserved1[0x00006];
1772  pseudo_bit_t page_offset[0x00006];
1773  pseudo_bit_t reserved2[0x00014];
1774 /* -------------- */
1775  pseudo_bit_t reserved3[0x00018];
1776  pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */
1777  pseudo_bit_t reserved4[0x00003];
1778 /* -------------- */
1779  pseudo_bit_t reserved5[0x00020];
1780 /* -------------- */
1781  pseudo_bit_t mtt_base_addr_h[0x00008];
1782  pseudo_bit_t reserved6[0x00010];
1783  pseudo_bit_t log2_page_size[0x00006];
1784  pseudo_bit_t reserved7[0x00002];
1785 /* -------------- */
1786  pseudo_bit_t reserved8[0x00003];
1787  pseudo_bit_t mtt_base_addr_l[0x0001d];
1788 /* -------------- */
1789  pseudo_bit_t reserved9[0x00020];
1790 /* -------------- */
1791  pseudo_bit_t reserved10[0x00100];
1792 /* -------------- */
1793 };
1794 
1795 /* MAD_IFC Input Modifier */
1796 
1797 struct hermonprm_mad_ifc_input_modifier_st { /* Little Endian */
1798  pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */
1799  pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
1800  Required for trap generation when BKey check is enabled and for global routed packets. */
1801  pseudo_bit_t reserved0[0x00007];
1802  pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
1803  This field is required for trap generation upon MKey/BKey validation. */
1804 /* -------------- */
1805 };
1806 
1807 /* MAD_IFC Input Mailbox ###michal -gdror fixed */
1808 
1809 struct hermonprm_mad_ifc_st { /* Little Endian */
1810  pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
1811 /* -------------- */
1812  pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD.
1813  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1814  pseudo_bit_t reserved0[0x00008];
1815 /* -------------- */
1816  pseudo_bit_t reserved1[0x00020];
1817 /* -------------- */
1818  pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD.
1819  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1820  pseudo_bit_t reserved2[0x00008];
1821 /* -------------- */
1822  pseudo_bit_t reserved3[0x00010];
1823  pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD.
1824  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1825  pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid.
1826  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1827  pseudo_bit_t reserved4[0x00004];
1828  pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD.
1829  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1830 /* -------------- */
1831  pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD.
1832  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1833  pseudo_bit_t reserved5[0x00010];
1834 /* -------------- */
1835  pseudo_bit_t reserved6[0x00160];
1836 /* -------------- */
1837  pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list.
1838  Valid if Mad_extended_info bit (in the input modifier) and g bit are set.
1839  Otherwise this field is reserved. */
1840 /* -------------- */
1841  pseudo_bit_t reserved7[0x004c0];
1842 /* -------------- */
1843 };
1844 
1845 /* Query Debug Message #### michal - gdror fixed */
1846 
1847 struct hermonprm_query_debug_msg_st { /* Little Endian */
1848  pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */
1849 /* -------------- */
1850  pseudo_bit_t v[0x00001]; /* Physical translation is valid */
1851  pseudo_bit_t reserved0[0x0000b];
1852  pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */
1853 /* -------------- */
1854  pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
1855 /* -------------- */
1856  pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */
1857 /* -------------- */
1858  pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */
1859 /* -------------- */
1860  pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */
1861 /* -------------- */
1862  pseudo_bit_t reserved1[0x000c0];
1863 /* -------------- */
1864  pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */
1865 /* -------------- */
1866  pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */
1867 /* -------------- */
1868  pseudo_bit_t reserved2[0x00040];
1869 /* -------------- */
1870  pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */
1871 /* -------------- */
1872  pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */
1873 /* -------------- */
1874  pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */
1875 /* -------------- */
1876  pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */
1877 /* -------------- */
1878  pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */
1879 /* -------------- */
1880  pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */
1881 /* -------------- */
1882  pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */
1883 /* -------------- */
1884  pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */
1885 /* -------------- */
1886  pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */
1887 /* -------------- */
1888  pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */
1889 /* -------------- */
1890  pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */
1891 /* -------------- */
1892  pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */
1893 /* -------------- */
1894  pseudo_bit_t reserved3[0x00080];
1895 /* -------------- */
1896  pseudo_bit_t hw_buff_addr[0x00020]; /* Dror Mux Bohrer tracer */
1897 /* -------------- */
1898  pseudo_bit_t hw_buff_size[0x00020];
1899 /* -------------- */
1900  pseudo_bit_t reserved4[0x003c0];
1901 /* -------------- */
1902 };
1903 
1904 /* User Access Region */
1905 
1906 struct hermonprm_uar_st { /* Little Endian */
1907  struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */
1908 /* -------------- */
1909  struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */
1910 /* -------------- */
1911  pseudo_bit_t reserved0[0x00040];
1912 /* -------------- */
1913  struct hermonprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */
1914 /* -------------- */
1915  pseudo_bit_t reserved1[0x03ec0];
1916 /* -------------- */
1917 };
1918 
1919 /* Receive doorbell */
1920 
1921 struct hermonprm_receive_doorbell_st { /* Little Endian */
1922  pseudo_bit_t reserved0[0x00008];
1923  pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
1924  pseudo_bit_t reserved1[0x00008];
1925 /* -------------- */
1926  pseudo_bit_t reserved2[0x00005];
1927  pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */
1928  pseudo_bit_t reserved3[0x00002];
1929  pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */
1930 /* -------------- */
1931 };
1932 
1933 /* SET_IB Parameters */
1934 
1935 struct hermonprm_set_ib_st { /* Little Endian */
1936  pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */
1937  pseudo_bit_t reserved0[0x00011];
1938  pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
1939  system_image_guid and sig must be the same for all ports. */
1940  pseudo_bit_t reserved1[0x0000d];
1941 /* -------------- */
1942  pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */
1943 /* -------------- */
1944  pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
1945  Must be the same for both ports. */
1946 /* -------------- */
1947  pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
1948  Must be the same for both ports. */
1949 /* -------------- */
1950  pseudo_bit_t reserved2[0x00180];
1951 /* -------------- */
1952 };
1953 
1954 /* Multicast Group Member #### michal - gdror fixed */
1955 
1956 struct hermonprm_mgm_entry_st { /* Little Endian */
1957  pseudo_bit_t reserved0[0x00006];
1958  pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
1959  The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
1960  next_gid_index=0 means end of the chain. */
1961 /* -------------- */
1962  pseudo_bit_t reserved1[0x00060];
1963 /* -------------- */
1964  pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format.
1965  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1966 /* -------------- */
1967  pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format.
1968  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1969 /* -------------- */
1970  pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format.
1971  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1972 /* -------------- */
1973  pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format.
1974  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1975 /* -------------- */
1976  struct hermonprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */
1977 /* -------------- */
1978  struct hermonprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */
1979 /* -------------- */
1980  struct hermonprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */
1981 /* -------------- */
1982  struct hermonprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */
1983 /* -------------- */
1984  struct hermonprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */
1985 /* -------------- */
1986  struct hermonprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */
1987 /* -------------- */
1988  struct hermonprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */
1989 /* -------------- */
1990  struct hermonprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */
1991 /* -------------- */
1992 };
1993 
1994 /* INIT_PORT Parameters #### michal - match PRM */
1995 
1996 struct hermonprm_init_port_st { /* Little Endian */
1997  pseudo_bit_t reserved0[0x00004];
1998  pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15.
1999  Legal values are 1,2,4 and 8. */
2000  pseudo_bit_t port_width_cap[0x00004];/* IB Port Width
2001  1 - 1x
2002  3 - 1x, 4x
2003  11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208)
2004  else - Reserved */
2005  pseudo_bit_t reserved1[0x00004];
2006  pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */
2007  pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified.
2008  node_guid and ng must be the same for all ports. */
2009  pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
2010  system_image_guid and sig must be the same for all ports. */
2011  pseudo_bit_t reserved2[0x0000d];
2012 /* -------------- */
2013  pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */
2014  pseudo_bit_t mtu[0x00010]; /* Maximum MTU Supported in bytes
2015  must be: 256, 512, 1024, 2048 or 4096
2016  For Eth port, can be any
2017  Field must not cross device capabilities as reported
2018  */
2019 /* -------------- */
2020  pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port.
2021  Must be the same for both ports. */
2022  pseudo_bit_t reserved3[0x00010];
2023 /* -------------- */
2024  pseudo_bit_t reserved4[0x00020];
2025 /* -------------- */
2026  pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
2027 /* -------------- */
2028  pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
2029 /* -------------- */
2030  pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set
2031  Must be the same for both ports. */
2032 /* -------------- */
2033  pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set
2034  Must be the same for both ports. */
2035 /* -------------- */
2036  pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
2037  Must be the same for both ports. */
2038 /* -------------- */
2039  pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
2040  Must be the same for both ports. */
2041 /* -------------- */
2042  pseudo_bit_t reserved5[0x006c0];
2043 /* -------------- */
2044 };
2045 
2046 /* Query Device Capablities #### michal - gdror fixed */
2047 
2048 struct hermonprm_query_dev_cap_st { /* Little Endian */
2049  pseudo_bit_t reserved0[0x00080];
2050 /* -------------- */
2051  pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */
2052  pseudo_bit_t reserved1[0x00003];
2053  pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
2054  The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
2055  pseudo_bit_t reserved2[0x00004];
2056  pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
2057  pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
2058 /* -------------- */
2059  pseudo_bit_t log_max_scqs[0x00004]; /* log base 2 of number of supported schedule queues */
2060  pseudo_bit_t reserved3[0x00004];
2061  pseudo_bit_t num_rsvd_scqs[0x00006];
2062  pseudo_bit_t reserved4[0x00002];
2063  pseudo_bit_t log_max_srqs[0x00005];
2064  pseudo_bit_t reserved5[0x00007];
2065  pseudo_bit_t log2_rsvd_srqs[0x00004];
2066 /* -------------- */
2067  pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */
2068  pseudo_bit_t reserved6[0x00003];
2069  pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
2070  The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
2071  pseudo_bit_t reserved7[0x00004];
2072  pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
2073  pseudo_bit_t num_rsvd_eqs[0x00008]; /* The number of EQs reserved for firmware use
2074  The reserved resources are numbered from 0 to num_rsvd_eqs-1
2075  If 0 - no resources are reserved. */
2076 /* -------------- */
2077  pseudo_bit_t log_max_eq[0x00004]; /* Log2 of the Maximum number of EQs */
2078  pseudo_bit_t reserved9[0x00004];
2079  pseudo_bit_t log2_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
2080  The reserved resources are numbered from 0 to num_rsvd_eqs-1
2081  If 0 - no resources are reserved. */
2082  pseudo_bit_t reserved10[0x00004];
2083  pseudo_bit_t log_max_d_mpts[0x00006];/* Log (base 2) of the maximum number of data MPT entries (the number of Regions/Windows) */
2084  pseudo_bit_t reserved11[0x00002];
2085  pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
2086 /* -------------- */
2087  pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */
2088  pseudo_bit_t reserved12[0x00002];
2089  pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
2090  The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
2091  pseudo_bit_t reserved13[0x00004];
2092  pseudo_bit_t log_max_mrw_sz[0x00007];/* Log2 of the Maximum Size of Memory Region/Window. is it in PRM layout? */
2093  pseudo_bit_t reserved14[0x00005];
2094  pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
2095  The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
2096  */
2097 /* -------------- */
2098  pseudo_bit_t reserved15[0x00020];
2099 /* -------------- */
2100  pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
2101  pseudo_bit_t reserved16[0x0000a];
2102  pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
2103  pseudo_bit_t reserved17[0x0000a];
2104 /* -------------- */
2105  pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
2106  pseudo_bit_t reserved18[0x0001a];
2107 /* -------------- */
2108  pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */
2109  pseudo_bit_t reserved19[0x0001f];
2110 /* -------------- */
2111  pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */
2112  pseudo_bit_t reserved47[0x00004];
2113  pseudo_bit_t pci_pf_num[0x00008]; /* Number of supported physical functions */
2114  pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
2115  The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
2116  pseudo_bit_t port_type[0x00004]; /* Hermon New. bit per port. bit0 is first port. value '1' is ehternet. '0' is IB */
2117  pseudo_bit_t reserved20[0x00004];
2118  pseudo_bit_t w[0x00001]; /* Hermon New. 10GB eth support */
2119  pseudo_bit_t j[0x00001]; /* Hermon New. Jumbo frame support */
2120  pseudo_bit_t reserved21[0x00001];
2121 /* -------------- */
2122  pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */
2123  pseudo_bit_t reserved22[0x00004];
2124  pseudo_bit_t log_ethtype[0x00004]; /* Hermon New. log2 eth type table size */
2125  pseudo_bit_t reserved23[0x00004];
2126  pseudo_bit_t log_drain_size[0x00008];/* Log (base 2) of minimum size of the NoDropVLDrain buffer, specified in 4Kpages units */
2127  pseudo_bit_t log_max_msg[0x00005]; /* Log (base 2) of the maximum message size supported by the device */
2128  pseudo_bit_t reserved24[0x00003];
2129 /* -------------- */
2130  pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
2131  pseudo_bit_t reserved25[0x0000c];
2132  pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported
2133  bit 0 - full bw
2134  bit 1 - 1/4 bw
2135  bit 2 - 1/8 bw
2136  bit 3 - 1/2 bw; */
2137 /* -------------- */
2138  pseudo_bit_t reserved26[0x00008];
2139  pseudo_bit_t rss_udp[0x00001];
2140  pseudo_bit_t vep_uc_steering[0x00001];
2141  pseudo_bit_t vep_mc_steering[0x00001];
2142  pseudo_bit_t reserved27[0x00015];
2143 
2144 /* -------------- */
2145  pseudo_bit_t rc[0x00001]; /* RC Transport supported */
2146  pseudo_bit_t uc[0x00001]; /* UC Transport Supported */
2147  pseudo_bit_t ud[0x00001]; /* UD Transport Supported */
2148  pseudo_bit_t src[0x00001]; /* SRC Transport Supported. Hermon New instead of RD. */
2149  pseudo_bit_t rcm[0x00001]; /* Reliable Multicast support. Hermon New instead of IPv6 Transport Supported */
2150  pseudo_bit_t fcoib[0x00001]; /* Hermon New */
2151  pseudo_bit_t srq[0x00001]; /* SRQ is supported
2152  */
2153  pseudo_bit_t checksum[0x00001]; /* IP over IB checksum is supported */
2154  pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */
2155  pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */
2156  pseudo_bit_t vmm[0x00001]; /* Hermon New */
2157  pseudo_bit_t fcoe[0x00001];
2158  pseudo_bit_t dpdp[0x00001]; /* Dual Port Different Protocols */
2159  pseudo_bit_t raw_ethertype[0x00001];
2160  pseudo_bit_t raw_ipv6[0x00001];
2161  pseudo_bit_t blh[0x00001];
2162  pseudo_bit_t mw[0x00001]; /* Memory windows supported */
2163  pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */
2164  pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
2165  pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */
2166  pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */
2167  pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */
2168  pseudo_bit_t reserved28[0x00002];
2169  pseudo_bit_t pg[0x00001]; /* Paging on demand supported */
2170  pseudo_bit_t r[0x00001]; /* Router mode supported */
2171  pseudo_bit_t reserved29[0x00006];
2172 /* -------------- */
2173  pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2).
2174  For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
2175  pseudo_bit_t reserved30[0x00008];
2176  pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */
2177  pseudo_bit_t reserved31[0x00006];
2178  pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
2179  The reserved resources are numbered from 0 to num_reserved_uars-1
2180  Note that UAR number num_reserved_uars is always for the kernel. */
2181 /* -------------- */
2182  pseudo_bit_t log_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */
2183  pseudo_bit_t reserved32[0x00002];
2184  pseudo_bit_t log_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */
2185  pseudo_bit_t reserved33[0x00002];
2186  pseudo_bit_t log_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */
2187  pseudo_bit_t reserved34[0x0000a];
2188  pseudo_bit_t bf[0x00001]; /* If set to "1" then BlueFlame may be used. */
2189 /* -------------- */
2190  pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
2191  pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
2192  pseudo_bit_t reserved35[0x00008];
2193 /* -------------- */
2194  pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
2195  pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
2196  pseudo_bit_t reserved36[0x00008];
2197 /* -------------- */
2198  pseudo_bit_t reserved37[0x00001];
2199  pseudo_bit_t fexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */
2200  pseudo_bit_t fcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */
2201  pseudo_bit_t fexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */
2202 /* -------------- */
2203  pseudo_bit_t reserved38[0x00020];
2204 /* -------------- */
2205  pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */
2206  pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
2207  The reserved resources are numbered from 0 to num_reserved_mcgs-1
2208  If 0 - no resources are reserved. */
2209  pseudo_bit_t reserved39[0x00004];
2210  pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
2211  pseudo_bit_t reserved40[0x00008];
2212 /* -------------- */
2213  pseudo_bit_t log_max_srcds[0x00004];/* Log2 of the maximum number of SRC Domains */
2214  pseudo_bit_t reserved41[0x00008];
2215  pseudo_bit_t num_rsvd_scrds[0x00004];/* The number of SRCDs reserved for firmware use
2216  The reserved resources are numbered from 0 to num_reserved_rdds-1.
2217  If 0 - no resources are reserved. */
2218  pseudo_bit_t log_max_pd[0x00005]; /* Log2 of the maximum number of PDs */
2219  pseudo_bit_t reserved42[0x00007];
2220  pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
2221  The reserved resources are numbered from 0 to num_reserved_pds-1
2222  If 0 - no resources are reserved. */
2223 /* -------------- */
2224  pseudo_bit_t reserved43[0x000c0];
2225 /* -------------- */
2226  pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
2227  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2228  pseudo_bit_t rdmardc_entry_sz[0x00010];/* RdmaRdC Entry Size for the device
2229  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2230 /* -------------- */
2231  pseudo_bit_t altc_entry_sz[0x00010];/* Extended QPC entry size for the device
2232  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2233  pseudo_bit_t aux_entry_sz[0x00010]; /* Auxilary context entry size */
2234 /* -------------- */
2235  pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device
2236  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2237  pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device
2238  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2239 /* -------------- */
2240  pseudo_bit_t c_mpt_entry_sz[0x00010];/* cMPT entry size in Bytes for the device.
2241  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2242  pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device
2243  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2244 /* -------------- */
2245  pseudo_bit_t d_mpt_entry_sz[0x00010];/* dMPT entry size in Bytes for the device.
2246  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2247  pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device.
2248  For the InfiniHost-III-EX MT25208 entry size is 8 bytes */
2249 /* -------------- */
2250  pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */
2251  pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism:
2252  0 - Type 2A - QP Number Association; or
2253  1 - Type 2B - QP Number and PD Association. */
2254  pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */
2255  pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. */
2256  pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */
2257  pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */
2258  pseudo_bit_t reserved44[0x0001a];
2259 /* -------------- */
2260  pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */
2261 /* -------------- */
2262  pseudo_bit_t reserved45[0x00020];
2263 /* -------------- */
2264  pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
2265 /* -------------- */
2266  pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
2267 /* -------------- */
2268  pseudo_bit_t reserved46[0x002c0];
2269 /* -------------- */
2270 };
2271 
2272 /* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */
2273 
2274 struct hermonprm_query_adapter_st { /* Little Endian */
2275  pseudo_bit_t reserved0[0x00080];
2276 /* -------------- */
2277  pseudo_bit_t reserved1[0x00018];
2278  pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
2279 /* -------------- */
2280  pseudo_bit_t reserved2[0x00060];
2281 /* -------------- */
2282  struct hermonprm_vsd_st vsd; /* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */
2283 /* -------------- */
2284 };
2285 
2286 /* QUERY_FW Parameters Block #### michal - doesn't match PRM */
2287 
2288 struct hermonprm_query_fw_st { /* Little Endian */
2289  pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */
2290  pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
2291 /* -------------- */
2292  pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
2293  pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
2294 /* -------------- */
2295  pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
2296  pseudo_bit_t reserved0[0x00010];
2297 /* -------------- */
2298  pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
2299  pseudo_bit_t reserved1[0x00017];
2300  pseudo_bit_t dt[0x00001]; /* Debug Trace Support
2301  0 - Debug trace is not supported
2302  1 - Debug trace is supported */
2303 /* -------------- */
2304  pseudo_bit_t reserved2[0x00001];
2305  pseudo_bit_t ccq[0x00001]; /* CCQ support */
2306  pseudo_bit_t reserved3[0x00006];
2307  pseudo_bit_t fw_seconds[0x00008]; /* FW timestamp - seconds. Dispalyed as Hexadecimal number */
2308  pseudo_bit_t fw_minutes[0x00008]; /* FW timestamp - minutes. Dispalyed as Hexadecimal number */
2309  pseudo_bit_t fw_hour[0x00008]; /* FW timestamp - hour. Dispalyed as Hexadecimal number */
2310 /* -------------- */
2311  pseudo_bit_t fw_day[0x00008]; /* FW timestamp - day. Dispalyed as Hexadecimal number */
2312  pseudo_bit_t fw_month[0x00008]; /* FW timestamp - month. Dispalyed as Hexadecimal number */
2313  pseudo_bit_t fw_year[0x00010]; /* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */
2314 /* -------------- */
2315  pseudo_bit_t reserved4[0x00040];
2316 /* -------------- */
2317  pseudo_bit_t clr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */
2318 /* -------------- */
2319  pseudo_bit_t clr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */
2320 /* -------------- */
2321  pseudo_bit_t reserved5[0x0001e];
2322  pseudo_bit_t clr_int_bar[0x00002]; /* PCI base address register (BAR) where clr_int register is located.
2323  00 - BAR 0-1
2324  01 - BAR 2-3
2325  10 - BAR 4-5
2326  11 - Reserved
2327  The PCI BARs of ConnectX are 64 bit BARs.
2328  In ConnectX, clr_int register is located on BAR 0-1. */
2329 /* -------------- */
2330  pseudo_bit_t reserved6[0x00020];
2331 /* -------------- */
2332  pseudo_bit_t error_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */
2333 /* -------------- */
2334  pseudo_bit_t error_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */
2335 /* -------------- */
2336  pseudo_bit_t error_buf_size[0x00020];/* Size in words */
2337 /* -------------- */
2338  pseudo_bit_t reserved7[0x0001e];
2339  pseudo_bit_t error_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located.
2340  00 - BAR 0-1
2341  01 - BAR 2-3
2342  10 - BAR 4-5
2343  11 - Reserved
2344  The PCI BARs of ConnectX are 64 bit BARs.
2345  In ConnectX, error_buf register is located on BAR 0-1. */
2346 /* -------------- */
2347  pseudo_bit_t reserved8[0x00600];
2348 /* -------------- */
2349 };
2350 
2351 /* Memory Access Parameters for UD Address Vector Table */
2352 
2353 struct hermonprm_udavtable_memory_parameters_st { /* Little Endian */
2354  pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */
2355 /* -------------- */
2356  pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */
2357  pseudo_bit_t reserved0[0x00005];
2358  pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
2359  pseudo_bit_t reserved1[0x00002];
2360 /* -------------- */
2361 };
2362 
2363 /* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */
2364 
2365 struct hermonprm_init_hca_st { /* Little Endian */
2366  pseudo_bit_t reserved0[0x00018];
2367  pseudo_bit_t version[0x00008];
2368 /* -------------- */
2369  pseudo_bit_t reserved1[0x00040];
2370 /* -------------- */
2371  pseudo_bit_t reserved2[0x00010];
2372  pseudo_bit_t hca_core_clock[0x00010];/* Internal Clock freq in MHz */
2373 /* -------------- */
2374  pseudo_bit_t router_qp[0x00018]; /* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet.
2375  Valid only if RE bit is set */
2376  pseudo_bit_t reserved3[0x00005];
2377  pseudo_bit_t ipr2[0x00001]; /* Hermon New. IP router on port 2 */
2378  pseudo_bit_t ipr1[0x00001]; /* Hermon New. IP router on port 1 */
2379  pseudo_bit_t ibr[0x00001]; /* InfiniBand Router Mode */
2380 /* -------------- */
2381  pseudo_bit_t udp[0x00001]; /* UD Port Check Enable
2382  0 - Port field in Address Vector is ignored
2383  1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
2384  pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations
2385  0 - Host is Little Endian
2386  1 - Host is Big endian
2387  */
2388  pseudo_bit_t reserved4[0x00001];
2389  pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
2390  pseudo_bit_t reserved5[0x0001c];
2391 /* -------------- */
2392  pseudo_bit_t reserved6[0x00040];
2393 /* -------------- */
2394  struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */
2395 /* -------------- */
2396  pseudo_bit_t reserved7[0x00100];
2397 /* -------------- */
2398  struct hermonprm_multicastparam_st multicast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */
2399 /* -------------- */
2400  pseudo_bit_t reserved8[0x00080];
2401 /* -------------- */
2402  struct hermonprm_tptparams_st tpt_parameters;
2403 /* -------------- */
2404  pseudo_bit_t reserved9[0x00080];
2405 /* -------------- */
2406  struct hermonprm_uar_params_st uar_parameters;/* UAR Parameters */
2407 /* -------------- */
2408  pseudo_bit_t reserved10[0x00600];
2409 /* -------------- */
2410 };
2411 
2412 /* Event Queue Context Table Entry #### michal - gdror fixed */
2413 
2414 struct hermonprm_eqc_st { /* Little Endian */
2415  pseudo_bit_t reserved0[0x00008];
2416  pseudo_bit_t st[0x00004]; /* Event delivery state machine
2417  0x9 - Armed
2418  0xA - Fired
2419  0xB - Always_Armed (auto-rearm)
2420  other - reserved */
2421  pseudo_bit_t reserved1[0x00005];
2422  pseudo_bit_t oi[0x00001]; /* Oerrun ignore.
2423  If set, HW will not check EQ full condition when writing new EQEs. */
2424  pseudo_bit_t ec[0x00001]; /* is set, all EQEs are written (coalesced) to first EQ entry */
2425  pseudo_bit_t reserved2[0x00009];
2426  pseudo_bit_t status[0x00004]; /* EQ status:
2427  0000 - OK
2428  1010 - EQ write failure
2429  Valid for the QUERY_EQ and HW2SW_EQ commands only */
2430 /* -------------- */
2431  pseudo_bit_t reserved3[0x00020];
2432 /* -------------- */
2433  pseudo_bit_t reserved4[0x00005];
2434  pseudo_bit_t page_offset[0x00007]; /* offset bits[11:5] of first EQE in the EQ relative to the first page in memory region mapping this EQ */
2435  pseudo_bit_t reserved5[0x00014];
2436 /* -------------- */
2437  pseudo_bit_t reserved6[0x00018];
2438  pseudo_bit_t log_eq_size[0x00005]; /* Log (base 2) of the EQ size (in entries). Maximum EQ size is 2^22 EQEs (max log_eq_size is 22) */
2439  pseudo_bit_t reserved7[0x00003];
2440 /* -------------- */
2441  pseudo_bit_t eq_max_count[0x00010]; /* Event Generation Moderation counter */
2442  pseudo_bit_t eq_period[0x00010]; /* Event Generation moderation timed, microseconds */
2443 /* -------------- */
2444  pseudo_bit_t intr[0x0000a]; /* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */
2445  pseudo_bit_t reserved8[0x00016];
2446 /* -------------- */
2447  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */
2448  pseudo_bit_t reserved9[0x00010];
2449  pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
2450  pseudo_bit_t reserved10[0x00002];
2451 /* -------------- */
2452  pseudo_bit_t reserved11[0x00003];
2453  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */
2454 /* -------------- */
2455  pseudo_bit_t reserved12[0x00040];
2456 /* -------------- */
2457  pseudo_bit_t consumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ.
2458  Must be 0x0 in EQ initialization.
2459  Maintained by HW (valid for the QUERY_EQ command only). */
2460  pseudo_bit_t reserved13[0x00008];
2461 /* -------------- */
2462  pseudo_bit_t producer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ.
2463  EQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a EQE needs to be added.
2464  Maintained by HW (valid for the QUERY_EQ command only) */
2465  pseudo_bit_t reserved14[0x00008];
2466 /* -------------- */
2467  pseudo_bit_t reserved15[0x00080];
2468 /* -------------- */
2469 };
2470 
2471 /* Memory Translation Table (MTT) Entry #### michal - match to PRM */
2472 
2473 struct hermonprm_mtt_st { /* Little Endian */
2474  pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2475 /* -------------- */
2476  pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
2477  pseudo_bit_t reserved0[0x00002];
2478  pseudo_bit_t ptag_l[0x0001d]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2479 /* -------------- */
2480 };
2481 
2482 /* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */
2483 
2484 struct hermonprm_mpt_st { /* Little Endian */
2485  pseudo_bit_t reserved0[0x00008];
2486  pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */
2487  pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation is performed for this region */
2488  pseudo_bit_t lr[0x00001]; /* If set - local read access is enabled. Must be set for all MPT Entries. */
2489  pseudo_bit_t lw[0x00001]; /* If set - local write access is enabled */
2490  pseudo_bit_t rr[0x00001]; /* If set - remote read access is enabled. */
2491  pseudo_bit_t rw[0x00001]; /* If set - remote write access is enabled */
2492  pseudo_bit_t atomic[0x00001]; /* If set - remote Atomic access is allowed. */
2493  pseudo_bit_t eb[0x00001]; /* If set - bind is enabled. Valid only for regions. */
2494  pseudo_bit_t atc_req[0x00001]; /* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */
2495  pseudo_bit_t atc_xlated[0x00001]; /* If set, uplink cycle to be issues with “ATC_translated” indicator to force bypass of the chipset IOMMU. */
2496  pseudo_bit_t reserved1[0x00001];
2497  pseudo_bit_t no_snoop[0x00001]; /* If set, issue PCIe cycle with ûno Snoopÿ attribute - cycle not to be snooped in CPU caches */
2498  pseudo_bit_t reserved2[0x00008];
2499  pseudo_bit_t status[0x00004]; /* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */
2500 /* -------------- */
2501  pseudo_bit_t reserved3[0x00007];
2502  pseudo_bit_t bqp[0x00001]; /* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */
2503  pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
2504 /* -------------- */
2505  pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */
2506 /* -------------- */
2507  pseudo_bit_t pd[0x00018]; /* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */
2508  pseudo_bit_t en_rinv[0x00001]; /* Enable remote invalidation */
2509  pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
2510  pseudo_bit_t nce[0x00001]; /* Data can be cached in Network Cache (see ûNetwork Cacheÿ on page 81) */
2511  pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */
2512  pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */
2513  pseudo_bit_t w_dif[0x00001]; /* Wire space contains dif */
2514  pseudo_bit_t m_dif[0x00001]; /* Memory space contains dif */
2515  pseudo_bit_t reserved4[0x00001];
2516 /* -------------- */
2517  pseudo_bit_t start_addr_h[0x00020]; /* Start Address - Virtual Address where this region/window starts */
2518 /* -------------- */
2519  pseudo_bit_t start_addr_l[0x00020]; /* Start Address - Virtual Address where this region/window starts */
2520 /* -------------- */
2521  pseudo_bit_t len_h[0x00020]; /* Region/Window Length */
2522 /* -------------- */
2523  pseudo_bit_t len_l[0x00020]; /* Region/Window Length */
2524 /* -------------- */
2525  pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
2526 /* -------------- */
2527  pseudo_bit_t win_cnt[0x00018]; /* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
2528  pseudo_bit_t reserved5[0x00008];
2529 /* -------------- */
2530  pseudo_bit_t mtt_rep[0x00004]; /* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */
2531  pseudo_bit_t reserved6[0x00011];
2532  pseudo_bit_t block_mode[0x00001]; /* If set, the page size is not power of two, and entity_size is in bytes. */
2533  pseudo_bit_t len64[0x00001]; /* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */
2534  pseudo_bit_t fbo_en[0x00001]; /* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */
2535  pseudo_bit_t reserved7[0x00008];
2536 /* -------------- */
2537  pseudo_bit_t mtt_adr_h[0x00008]; /* Offset to MTT list for this region. Must be aligned on 8 bytes. */
2538  pseudo_bit_t reserved8[0x00018];
2539 /* -------------- */
2540  pseudo_bit_t mtt_adr_l[0x00020]; /* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */
2541 /* -------------- */
2542  pseudo_bit_t mtt_size[0x00020]; /* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */
2543 /* -------------- */
2544  pseudo_bit_t entity_size[0x00015]; /* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */
2545  pseudo_bit_t reserved9[0x0000b];
2546 /* -------------- */
2547  pseudo_bit_t mtt_fbo[0x00015]; /* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */
2548  pseudo_bit_t reserved10[0x0000b];
2549 /* -------------- */
2550 };
2551 
2552 /* Completion Queue Context Table Entry #### michal - match PRM */
2553 
2554 struct hermonprm_completion_queue_context_st { /* Little Endian */
2555  pseudo_bit_t reserved0[0x00008];
2556  pseudo_bit_t st[0x00004]; /* Event delivery state machine
2557  0x0 - reserved
2558  0x9 - ARMED (Request for Notification)
2559  0x6 - ARMED SOLICITED (Request Solicited Notification)
2560  0xA - FIRED
2561  other - reserved
2562 
2563  Must be 0x0 in CQ initialization.
2564  Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2565  pseudo_bit_t reserved1[0x00005];
2566  pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled.
2567  When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
2568  pseudo_bit_t cc[0x00001]; /* is set, all CQEs are written (coalesced) to first CQ entry */
2569  pseudo_bit_t reserved2[0x00009];
2570  pseudo_bit_t status[0x00004]; /* CQ status
2571  0000 - OK
2572  1001 - CQ overflow
2573  1010 - CQ write failure
2574  Valid for the QUERY_CQ and HW2SW_CQ commands only */
2575 /* -------------- */
2576  pseudo_bit_t reserved3[0x00020];
2577 /* -------------- */
2578  pseudo_bit_t reserved4[0x00005];
2579  pseudo_bit_t page_offset[0x00007]; /* offset of first CQE in the CQ relative to the first page in memory region mapping this CQ */
2580  pseudo_bit_t reserved5[0x00014];
2581 /* -------------- */
2582  pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
2583  pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries).
2584  Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
2585  pseudo_bit_t reserved6[0x00003];
2586 /* -------------- */
2587  pseudo_bit_t cq_max_count[0x00010]; /* Event Generation Moderation counter */
2588  pseudo_bit_t cq_period[0x00010]; /* Event Generation moderation timed, microseconds */
2589 /* -------------- */
2590  pseudo_bit_t c_eqn[0x00009]; /* Event Queue this CQ reports completion events to.
2591  Valid values are 0 to 63
2592  If configured to value other than 0-63, completion events will not be reported on the CQ. */
2593  pseudo_bit_t reserved7[0x00017];
2594 /* -------------- */
2595  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
2596  pseudo_bit_t reserved8[0x00010];
2597  pseudo_bit_t log2_page_size[0x00006];
2598  pseudo_bit_t reserved9[0x00002];
2599 /* -------------- */
2600  pseudo_bit_t reserved10[0x00003];
2601  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
2602 /* -------------- */
2603  pseudo_bit_t last_notified_indx[0x00018];/* Maintained by HW.
2604  Valid for QUERY_CQ and HW2SW_CQ commands only. */
2605  pseudo_bit_t reserved11[0x00008];
2606 /* -------------- */
2607  pseudo_bit_t solicit_producer_indx[0x00018];/* Maintained by HW.
2608  Valid for QUERY_CQ and HW2SW_CQ commands only.
2609  */
2610  pseudo_bit_t reserved12[0x00008];
2611 /* -------------- */
2612  pseudo_bit_t consumer_counter[0x00018];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
2613  */
2614  pseudo_bit_t reserved13[0x00008];
2615 /* -------------- */
2616  pseudo_bit_t producer_counter[0x00018];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
2617  CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
2618  Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
2619  pseudo_bit_t reserved14[0x00008];
2620 /* -------------- */
2621  pseudo_bit_t reserved15[0x00020];
2622 /* -------------- */
2623  pseudo_bit_t reserved16[0x00020];
2624 /* -------------- */
2625  pseudo_bit_t db_record_addr_h[0x00020];/* CQ DB Record physical address [63:32] */
2626 /* -------------- */
2627  pseudo_bit_t reserved17[0x00003];
2628  pseudo_bit_t db_record_addr_l[0x0001d];/* CQ DB Record physical address [31:3] */
2629 /* -------------- */
2630 };
2631 
2632 /* GPIO_event_data #### michal - gdror fixed */
2633 
2634 struct hermonprm_gpio_event_data_st { /* Little Endian */
2635  pseudo_bit_t reserved0[0x00060];
2636 /* -------------- */
2637  pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2638 /* -------------- */
2639  pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2640 /* -------------- */
2641  pseudo_bit_t reserved1[0x00020];
2642 /* -------------- */
2643 };
2644 
2645 /* Event_data Field - QP/EE Events #### michal - doesn't match PRM */
2646 
2647 struct hermonprm_qp_ee_event_st { /* Little Endian */
2648  pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for ###michal - field changed to QP number */
2649  pseudo_bit_t reserved0[0x00008];
2650 /* -------------- */
2651  pseudo_bit_t reserved1[0x00020];
2652 /* -------------- */
2653  pseudo_bit_t reserved2[0x0001c];
2654  pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field
2655  Not valid on SRQ events ###michal - field replaced with RESERVED */
2656  pseudo_bit_t reserved3[0x00003];
2657 /* -------------- */
2658  pseudo_bit_t reserved4[0x00060];
2659 /* -------------- */
2660 };
2661 
2662 /* InfiniHost-III-EX Type0 Configuration Header ####michal - doesn't match PRM (new fields added, see below) */
2663 
2664 struct hermonprm_mt25208_type0_st { /* Little Endian */
2665  pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */
2666  pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode
2667  25408 (decimal) - InfiniHost-III EX mode (the mode described in this manual)
2668  25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode
2669  */
2670 /* -------------- */
2671  pseudo_bit_t command[0x00010]; /* PCI Command Register */
2672  pseudo_bit_t status[0x00010]; /* PCI Status Register */
2673 /* -------------- */
2674  pseudo_bit_t revision_id[0x00008];
2675  pseudo_bit_t class_code_hca_class_code[0x00018];
2676 /* -------------- */
2677  pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */
2678  pseudo_bit_t latency_timer[0x00008];
2679  pseudo_bit_t header_type[0x00008]; /* hardwired to zero */
2680  pseudo_bit_t bist[0x00008];
2681 /* -------------- */
2682  pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */
2683  pseudo_bit_t reserved0[0x00010];
2684  pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */
2685 /* -------------- */
2686  pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */
2687 /* -------------- */
2688  pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */
2689  pseudo_bit_t reserved1[0x00010];
2690  pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */
2691 /* -------------- */
2692  pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */
2693 /* -------------- */
2694  pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */
2695  pseudo_bit_t reserved2[0x00010];
2696  pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2697 /* -------------- */
2698  pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2699 /* -------------- */
2700  pseudo_bit_t cardbus_cis_pointer[0x00020];
2701 /* -------------- */
2702  pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
2703  pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
2704 /* -------------- */
2705  pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2706  pseudo_bit_t reserved3[0x0000a];
2707  pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2708 /* -------------- */
2709  pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
2710  pseudo_bit_t reserved4[0x00018];
2711 /* -------------- */
2712  pseudo_bit_t reserved5[0x00020];
2713 /* -------------- */
2714  pseudo_bit_t interrupt_line[0x00008];
2715  pseudo_bit_t interrupt_pin[0x00008];
2716  pseudo_bit_t min_gnt[0x00008];
2717  pseudo_bit_t max_latency[0x00008];
2718 /* -------------- */
2719  pseudo_bit_t reserved6[0x00100];
2720 /* -------------- */
2721  pseudo_bit_t msi_cap_id[0x00008];
2722  pseudo_bit_t msi_next_cap_ptr[0x00008];
2723  pseudo_bit_t msi_en[0x00001];
2724  pseudo_bit_t multiple_msg_cap[0x00003];
2725  pseudo_bit_t multiple_msg_en[0x00003];
2726  pseudo_bit_t cap_64_bit_addr[0x00001];
2727  pseudo_bit_t reserved7[0x00008];
2728 /* -------------- */
2729  pseudo_bit_t msg_addr_l[0x00020];
2730 /* -------------- */
2731  pseudo_bit_t msg_addr_h[0x00020];
2732 /* -------------- */
2733  pseudo_bit_t msg_data[0x00010];
2734  pseudo_bit_t reserved8[0x00010];
2735 /* -------------- */
2736  pseudo_bit_t reserved9[0x00080];
2737 /* -------------- */
2738  pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */
2739  pseudo_bit_t pm_next_cap_ptr[0x00008];
2740  pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h
2741  [3] PME clock - 0h
2742  [4] RsvP
2743  [5] Device specific initialization - 0h
2744  [8:6] AUX current - 0h
2745  [9] D1 support - 0h
2746  [10] D2 support - 0h
2747  [15:11] PME support - 0h */
2748 /* -------------- */
2749  pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */
2750  pseudo_bit_t pm_control_status_brdg_ext[0x00008];
2751  pseudo_bit_t data[0x00008];
2752 /* -------------- */
2753  pseudo_bit_t reserved10[0x00040];
2754 /* -------------- */
2755  pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */
2756  pseudo_bit_t vpd_next_cap_id[0x00008];
2757  pseudo_bit_t vpd_address[0x0000f];
2758  pseudo_bit_t f[0x00001];
2759 /* -------------- */
2760  pseudo_bit_t vpd_data[0x00020];
2761 /* -------------- */
2762  pseudo_bit_t reserved11[0x00040];
2763 /* -------------- */
2764  pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */
2765  pseudo_bit_t pciex_next_cap_ptr[0x00008];
2766  pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h
2767  [7:4] Device/Port Type - 0h
2768  [8] Slot implemented - 0h
2769  [13:9] Interrupt message number
2770  */
2771 /* -------------- */
2772  pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h
2773  [4:3] Phantom Function supported - 0h
2774  [5] Extended Tag Filed supported - 0h
2775  [8:6] Endpoint L0s Acceptable Latency - TBD
2776  [11:9] Endpoint L1 Acceptable Latency - TBD
2777  [12] Attention Button Present - configured through InfiniBurn
2778  [13] Attention Indicator Present - configured through InfiniBurn
2779  [14] Power Indicator Present - configured through InfiniBurn
2780  [25:18] Captured Slot Power Limit Value
2781  [27:26] Captured Slot Power Limit Scale */
2782 /* -------------- */
2783  pseudo_bit_t device_control[0x00010];
2784  pseudo_bit_t device_status[0x00010];
2785 /* -------------- */
2786  pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h
2787  [9:4] Maximum Link Width - 8h
2788  [11:10] Active State Power Management Support - 3h
2789  [14:12] L0s Exit Latency - TBD
2790  [17:15] L1 Exit Latency - TBD
2791  [31:24] Port Number - 0h */
2792 /* -------------- */
2793  pseudo_bit_t link_control[0x00010];
2794  pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h
2795  [9:4] Negotiated Link Width
2796  [12] Slot clock configuration - 1h */
2797 /* -------------- */
2798  pseudo_bit_t reserved12[0x00260];
2799 /* -------------- */
2800  pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */
2801  pseudo_bit_t capability_version[0x00004];/* 1h */
2802  pseudo_bit_t next_capability_offset[0x0000c];/* 0h */
2803 /* -------------- */
2804  pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status
2805  4 Data Link Protocol Error Status
2806  12 Poisoned TLP Status
2807  13 Flow Control Protocol Error Status
2808  14 Completion Timeout Status
2809  15 Completer Abort Status
2810  16 Unexpected Completion Status
2811  17 Receiver Overflow Status
2812  18 Malformed TLP Status
2813  19 ECRC Error Status
2814  20 Unsupported Request Error Status */
2815 /* -------------- */
2816  pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask
2817  4 Data Link Protocol Error Mask
2818  12 Poisoned TLP Mask
2819  13 Flow Control Protocol Error Mask
2820  14 Completion Timeout Mask
2821  15 Completer Abort Mask
2822  16 Unexpected Completion Mask
2823  17 Receiver Overflow Mask
2824  18 Malformed TLP Mask
2825  19 ECRC Error Mask
2826  20 Unsupported Request Error Mask */
2827 /* -------------- */
2828  pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity
2829  4 Data Link Protocol Error Severity
2830  12 Poisoned TLP Severity
2831  13 Flow Control Protocol Error Severity
2832  14 Completion Timeout Severity
2833  15 Completer Abort Severity
2834  16 Unexpected Completion Severity
2835  17 Receiver Overflow Severity
2836  18 Malformed TLP Severity
2837  19 ECRC Error Severity
2838  20 Unsupported Request Error Severity */
2839 /* -------------- */
2840  pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status
2841  6 Bad TLP Status
2842  7 Bad DLLP Status
2843  8 REPLAY_NUM Rollover Status
2844  12 Replay Timer Timeout Status */
2845 /* -------------- */
2846  pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask
2847  6 Bad TLP Mask
2848  7 Bad DLLP Mask
2849  8 REPLAY_NUM Rollover Mask
2850  12 Replay Timer Timeout Mask */
2851 /* -------------- */
2852  pseudo_bit_t advance_error_capabilities_and_control_register[0x00020];
2853 /* -------------- */
2854  struct hermonprm_header_log_register_st header_log_register;
2855 /* -------------- */
2856  pseudo_bit_t reserved13[0x006a0];
2857 /* -------------- */
2858 };
2859 
2860 /* Event Data Field - Performance Monitor */
2861 
2862 struct hermonprm_performance_monitor_event_st { /* Little Endian */
2863  struct hermonprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */
2864 /* -------------- */
2865  pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC
2866  0x02 - RQPC
2867  0x03 - CQC
2868  0x04 - Rkey
2869  0x05 - TLB
2870  0x06 - port0
2871  0x07 - port1 */
2872  pseudo_bit_t reserved0[0x00018];
2873 /* -------------- */
2874  pseudo_bit_t reserved1[0x00040];
2875 /* -------------- */
2876 };
2877 
2878 /* Event_data Field - Page Faults */
2879 
2880 struct hermonprm_page_fault_event_data_st { /* Little Endian */
2881  pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
2882 /* -------------- */
2883  pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
2884 /* -------------- */
2885  pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */
2886 /* -------------- */
2887  pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */
2888  pseudo_bit_t reserved0[0x00003];
2889  pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */
2890  pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */
2891  pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */
2892  pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */
2893  pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */
2894 /* -------------- */
2895  pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */
2896  pseudo_bit_t reserved1[0x00008];
2897 /* -------------- */
2898  pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
2899 /* -------------- */
2900 };
2901 
2902 /* WQE segments format */
2903 
2904 struct hermonprm_wqe_segment_st { /* Little Endian */
2905  struct hermonprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */
2906 /* -------------- */
2907  pseudo_bit_t reserved0[0x00280];
2908 /* -------------- */
2909  struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */
2910 /* -------------- */
2911  pseudo_bit_t reserved1[0x00100];
2912 /* -------------- */
2913  pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */
2914 /* -------------- */
2915  pseudo_bit_t reserved2[0x00080];
2916 /* -------------- */
2917 };
2918 
2919 /* Event_data Field - Port State Change #### michal - match PRM */
2920 
2921 struct hermonprm_port_state_change_st { /* Little Endian */
2922  pseudo_bit_t reserved0[0x00040];
2923 /* -------------- */
2924  pseudo_bit_t reserved1[0x0001c];
2925  pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */
2926  pseudo_bit_t reserved2[0x00002];
2927 /* -------------- */
2928  pseudo_bit_t reserved3[0x00060];
2929 /* -------------- */
2930 };
2931 
2932 /* Event_data Field - Completion Queue Error #### michal - match PRM */
2933 
2934 struct hermonprm_completion_queue_error_st { /* Little Endian */
2935  pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
2936  pseudo_bit_t reserved0[0x00008];
2937 /* -------------- */
2938  pseudo_bit_t reserved1[0x00020];
2939 /* -------------- */
2940  pseudo_bit_t syndrome[0x00008]; /* Error syndrome
2941  0x01 - CQ overrun
2942  0x02 - CQ access violation error */
2943  pseudo_bit_t reserved2[0x00018];
2944 /* -------------- */
2945  pseudo_bit_t reserved3[0x00060];
2946 /* -------------- */
2947 };
2948 
2949 /* Event_data Field - Completion Event #### michal - match PRM */
2950 
2951 struct hermonprm_completion_event_st { /* Little Endian */
2952  pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
2953  pseudo_bit_t reserved0[0x00008];
2954 /* -------------- */
2955  pseudo_bit_t reserved1[0x000a0];
2956 /* -------------- */
2957 };
2958 
2959 /* Event Queue Entry #### michal - match to PRM */
2960 
2961 struct hermonprm_event_queue_entry_st { /* Little Endian */
2962  pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type.
2963  Defined for events which have sub types, zero elsewhere. */
2964  pseudo_bit_t reserved0[0x00008];
2965  pseudo_bit_t event_type[0x00008]; /* Event Type */
2966  pseudo_bit_t reserved1[0x00008];
2967 /* -------------- */
2968  pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */
2969 /* -------------- */
2970  pseudo_bit_t reserved2[0x00007];
2971  pseudo_bit_t owner[0x00001]; /* Owner of the entry
2972  0 SW
2973  1 HW */
2974  pseudo_bit_t reserved3[0x00018];
2975 /* -------------- */
2976 };
2977 
2978 /* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */
2979 
2980 struct hermonprm_qp_ee_state_transitions_st { /* Little Endian */
2981  pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
2982 /* -------------- */
2983  pseudo_bit_t reserved0[0x00020];
2984 /* -------------- */
2985  struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */
2986 /* -------------- */
2987  pseudo_bit_t reserved1[0x00800];
2988 /* -------------- */
2989 };
2990 
2991 /* Completion Queue Entry Format #### michal - fixed by gdror */
2992 
2993 struct hermonprm_completion_queue_entry_st { /* Little Endian */
2994  pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */
2995  pseudo_bit_t reserved0[0x00002];
2996  pseudo_bit_t d2s[0x00001]; /* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers
2997  packet only to send-associated sniffer receive queue. */
2998  pseudo_bit_t fcrc_sd[0x00001]; /* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only.
2999  SD: CQ associated with Sniffer receive queue. If set, packets were skipped due to lack of receive buffers on the Sniffer receive queue */
3000  pseudo_bit_t fl[0x00001]; /* Force Loopback Valid for responder RawEth and UD only. */
3001  pseudo_bit_t vlan[0x00002]; /* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue
3002  00 - No VLAN header was present in the packet
3003  01 - C-VLAN (802.1q) Header was present in the frame.
3004  10 - S-VLAN (802.1ad) Header was present in the frame. */
3005  pseudo_bit_t dife[0x00001]; /* DIF Error */
3006 /* -------------- */
3007  pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message.
3008  For a responder CQE, if completed WQE Opcode is Send With Invalidate, this field contains the R_key that was invalidated.
3009  For a responder CQE of a GSI packet this filed contains the Pkey Index of the packet.
3010  For IPoIB (UD) and RawEth CQEs this field contains the RSS hash function value.
3011  Otherwise, this field is reserved. */
3012 /* -------------- */
3013  pseudo_bit_t srq_rqpn[0x00018]; /* For Responder UD QPs, Remote (source) QP number.
3014  For Responder SRC QPs, SRQ number.
3015  Otherwise, this field is reserved. */
3016  pseudo_bit_t ml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast.
3017  For responder UD over Ethernet and RawEth CQEs: Index of the MAC Table entry that the packet DMAC was matched against.
3018  Otherwise, this field is reserved. */
3019  pseudo_bit_t g[0x00001]; /* For responder UD over IB CQE this bit indicates the presence of a GRH
3020  For responder UD over Ethernet CQE this bit is set if IPv6 L3 header was present in the packet, this bit is cleared if IPv4 L3 Header was present in the packet.
3021  Otherwise, this field is reserved. */
3022 /* -------------- */
3023  pseudo_bit_t slid_smac47_32[0x00010];/* For responder UD over IB CQE it is the source LID of the packet.
3024  For responder UD over Ethernet and RawEth CQEs it is the source-MAC[47:32] of the packet.
3025  Otherwise, this field is reserved. */
3026  pseudo_bit_t vid[0x0000c]; /* Frame VID, valid for Responder Raw Ethernet and UD over Ethernet QP. Otherwise, this field is reserved. */
3027  pseudo_bit_t sl[0x00004]; /* For responder UD over IB - the Service Level of the packet.
3028  For responder UD over Ethernet and RawEth - it is VLAN-header[15:12]
3029  Otherwise, this field is reserved. */
3030 /* -------------- */
3031  pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020];/* For responder UD over Ethernet - source MAC[31:0] of the packet.
3032  For responder RawEth and UD over IB - RawEth-IPoIB status {3 reserved, ipok,udp,tcp,ipv4opt,ipv6,ipv4vf,ipv4,rht(6),ipv6extmask(6),reserved(2),l2am,reserved(2),bfcs,reserved(2),enc}
3033  Otherwise, this field is reserved. */
3034 /* -------------- */
3035  pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data transferred. Applicable for RDMA-read, Atomic and all receive operations. completions.
3036  For Receive Queue that is subject for headers. separation, byte_cnt[31:24] specify number of bytes scattered to the first scatter entry (headers. length). Byte_cnt[23:0] specify total byte count received (including headers). */
3037 /* -------------- */
3038  pseudo_bit_t checksum[0x00010]; /* Valid for RawEth and IPoIB only. */
3039  pseudo_bit_t wqe_counter[0x00010];
3040 /* -------------- */
3041  pseudo_bit_t opcode[0x00005]; /* Send completions - same encoding as WQE.
3042  Error coding is 0x1F
3043  Receive:
3044  0x0 - RDMA-Write with Immediate
3045  0x1 - Send
3046  0x2 - Send with Immediate
3047  0x3 - Send & Invalidate
3048  */
3049  pseudo_bit_t is[0x00001]; /* inline scatter */
3050  pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */
3051  pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */
3052  pseudo_bit_t reserved1[0x00010];
3053  pseudo_bit_t reserved2[0x00008];
3054 /* -------------- */
3055 };
3056 
3057 /* */
3058 
3059 struct hermonprm_mcg_qps_st { /* Little Endian */
3060  struct hermonprm_mcg_qp_dw_st dw[128];
3061 /* -------------- */
3062 };
3063 
3064 /* */
3065 
3066 struct hermonprm_mcg_hdr_st { /* Little Endian */
3067  pseudo_bit_t reserved0[0x00006];
3068  pseudo_bit_t next_mcg[0x0001a];
3069 /* -------------- */
3070  pseudo_bit_t members_count[0x00018];
3071  pseudo_bit_t member_remove[0x00001];
3072  pseudo_bit_t reserved1[0x00005];
3073  pseudo_bit_t protocol[0x00002];
3074 /* -------------- */
3075  pseudo_bit_t reserved2[0x00020];
3076 /* -------------- */
3077  pseudo_bit_t reserved3[0x00020];
3078 /* -------------- */
3079  pseudo_bit_t gid3[0x00020];
3080 /* -------------- */
3081  pseudo_bit_t gid2[0x00020];
3082 /* -------------- */
3083  pseudo_bit_t gid1[0x00020];
3084 /* -------------- */
3085  pseudo_bit_t gid0[0x00020];
3086 /* -------------- */
3087 };
3088 
3089 /* */
3090 
3091 struct hermonprm_sched_queue_context_st { /* Little Endian */
3092  pseudo_bit_t policy[0x00003]; /* Schedule Queue Policy - 0 - LLSQ, 1 - GBSQ, 2 - BESQ */
3093  pseudo_bit_t vl15[0x00001];
3094  pseudo_bit_t sl[0x00004]; /* SL this Schedule Queue is associated with (if vl15 bit is 0) */
3095  pseudo_bit_t port[0x00002]; /* Port this Schedule Queue is associated with */
3096  pseudo_bit_t reserved0[0x00006];
3097  pseudo_bit_t weight[0x00010]; /* Weight of this SchQ */
3098 /* -------------- */
3099 };
3100 
3101 /* */
3102 
3103 struct hermonprm_ecc_detect_event_data_st { /* Little Endian */
3104  pseudo_bit_t reserved0[0x00080];
3105 /* -------------- */
3106  pseudo_bit_t cause_lsb[0x00001];
3107  pseudo_bit_t reserved1[0x00002];
3108  pseudo_bit_t cause_msb[0x00001];
3109  pseudo_bit_t reserved2[0x00002];
3110  pseudo_bit_t err_rmw[0x00001];
3111  pseudo_bit_t err_src_id[0x00003];
3112  pseudo_bit_t err_da[0x00002];
3113  pseudo_bit_t err_ba[0x00002];
3114  pseudo_bit_t reserved3[0x00011];
3115  pseudo_bit_t overflow[0x00001];
3116 /* -------------- */
3117  pseudo_bit_t err_ra[0x00010];
3118  pseudo_bit_t err_ca[0x00010];
3119 /* -------------- */
3120 };
3121 
3122 /* Event_data Field - ECC Detection Event */
3123 
3124 struct hermonprm_scrubbing_event_st { /* Little Endian */
3125  pseudo_bit_t reserved0[0x00080];
3126 /* -------------- */
3127  pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause:
3128  single ECC error in the 64bit lsb data, on the rise edge of the clock */
3129  pseudo_bit_t reserved1[0x00002];
3130  pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause:
3131  single ECC error in the 64bit msb data, on the fall edge of the clock */
3132  pseudo_bit_t reserved2[0x00002];
3133  pseudo_bit_t err_rmw[0x00001]; /* transaction type:
3134  0 - read
3135  1 - read/modify/write */
3136  pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */
3137  pseudo_bit_t err_da[0x00002]; /* Error DIMM address */
3138  pseudo_bit_t err_ba[0x00002]; /* Error bank address */
3139  pseudo_bit_t reserved3[0x00011];
3140  pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
3141 /* -------------- */
3142  pseudo_bit_t err_ra[0x00010]; /* Error row address */
3143  pseudo_bit_t err_ca[0x00010]; /* Error column address */
3144 /* -------------- */
3145 };
3146 
3147 /* */
3148 
3149 struct hermonprm_eq_cmd_doorbell_st { /* Little Endian */
3150  pseudo_bit_t reserved0[0x00020];
3151 /* -------------- */
3152 };
3153 
3154 /* 0 */
3155 
3156 struct hermonprm_hermon_prm_st { /* Little Endian */
3157  struct hermonprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */
3158 /* -------------- */
3159  pseudo_bit_t reserved0[0x7ff00];
3160 /* -------------- */
3161  struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */
3162 /* -------------- */
3163  pseudo_bit_t reserved1[0x7f000];
3164 /* -------------- */
3165  struct hermonprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */
3166 /* -------------- */
3167  pseudo_bit_t reserved2[0x7ff00];
3168 /* -------------- */
3169  struct hermonprm_completion_event_st completion_event;/* Event_data Field - Completion Event */
3170 /* -------------- */
3171  pseudo_bit_t reserved3[0x7ff40];
3172 /* -------------- */
3173  struct hermonprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */
3174 /* -------------- */
3175  pseudo_bit_t reserved4[0x7ff40];
3176 /* -------------- */
3177  struct hermonprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */
3178 /* -------------- */
3179  pseudo_bit_t reserved5[0x7ff40];
3180 /* -------------- */
3181  struct hermonprm_wqe_segment_st wqe_segment;/* WQE segments format */
3182 /* -------------- */
3183  pseudo_bit_t reserved6[0x7f000];
3184 /* -------------- */
3185  struct hermonprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */
3186 /* -------------- */
3187  pseudo_bit_t reserved7[0x7ff40];
3188 /* -------------- */
3189  struct hermonprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */
3190 /* -------------- */
3191  pseudo_bit_t reserved8[0xfff20];
3192 /* -------------- */
3193  struct hermonprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */
3194 /* -------------- */
3195  pseudo_bit_t reserved9[0x7f000];
3196 /* -------------- */
3197  struct hermonprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */
3198 /* -------------- */
3199  pseudo_bit_t reserved10[0x00040];
3200 /* -------------- */
3201  struct hermonprm_gpio_event_data_st gpio_event_data;
3202 /* -------------- */
3203  pseudo_bit_t reserved11[0x7fe40];
3204 /* -------------- */
3205  struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
3206 /* -------------- */
3207  pseudo_bit_t reserved12[0x7ff00];
3208 /* -------------- */
3209  struct hermonprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */
3210 /* -------------- */
3211  pseudo_bit_t reserved13[0x7f840];
3212 /* -------------- */
3213  struct hermonprm_address_path_st address_path;/* Address Path */
3214 /* -------------- */
3215  pseudo_bit_t reserved14[0x7fea0];
3216 /* -------------- */
3217  struct hermonprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */
3218 /* -------------- */
3219  pseudo_bit_t reserved15[0x7fe00];
3220 /* -------------- */
3221  struct hermonprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */
3222 /* -------------- */
3223  pseudo_bit_t reserved16[0x7fe00];
3224 /* -------------- */
3225  struct hermonprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */
3226 /* -------------- */
3227  pseudo_bit_t reserved17[0x7ffc0];
3228 /* -------------- */
3229  struct hermonprm_eqc_st eqc; /* Event Queue Context Table Entry */
3230 /* -------------- */
3231  pseudo_bit_t reserved18[0x7fe00];
3232 /* -------------- */
3233  struct hermonprm_performance_monitors_st performance_monitors;/* Performance Monitors */
3234 /* -------------- */
3235  pseudo_bit_t reserved19[0x7ff80];
3236 /* -------------- */
3237  struct hermonprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */
3238 /* -------------- */
3239  pseudo_bit_t reserved20[0xfff20];
3240 /* -------------- */
3241  struct hermonprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */
3242 /* -------------- */
3243  pseudo_bit_t reserved21[0x7f000];
3244 /* -------------- */
3245  struct hermonprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */
3246 /* -------------- */
3247  pseudo_bit_t reserved22[0x7fc00];
3248 /* -------------- */
3249  struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */
3250 /* -------------- */
3251  pseudo_bit_t reserved23[0x7ffc0];
3252 /* -------------- */
3253  struct hermonprm_multicastparam_st multicastparam;/* Multicast Support Parameters */
3254 /* -------------- */
3255  pseudo_bit_t reserved24[0x7ff00];
3256 /* -------------- */
3257  struct hermonprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */
3258 /* -------------- */
3259  pseudo_bit_t reserved25[0x7ff00];
3260 /* -------------- */
3261  pseudo_bit_t reserved26[0x00800];
3262 /* -------------- */
3263  pseudo_bit_t reserved27[0x00100];
3264 /* -------------- */
3265  pseudo_bit_t reserved28[0x7f700];
3266 /* -------------- */
3267  pseudo_bit_t reserved29[0x00100];
3268 /* -------------- */
3269  pseudo_bit_t reserved30[0x7ff00];
3270 /* -------------- */
3271  struct hermonprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */
3272 /* -------------- */
3273  pseudo_bit_t reserved31[0x7f800];
3274 /* -------------- */
3275  struct hermonprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */
3276 /* -------------- */
3277  pseudo_bit_t reserved32[0x7f800];
3278 /* -------------- */
3279  struct hermonprm_query_dev_cap_st query_dev_cap;/* Query Device Limitations */
3280 /* -------------- */
3281  pseudo_bit_t reserved33[0x7f800];
3282 /* -------------- */
3283  struct hermonprm_uar_params_st uar_params;/* UAR Parameters */
3284 /* -------------- */
3285  pseudo_bit_t reserved34[0x7ff00];
3286 /* -------------- */
3287  struct hermonprm_init_port_st init_port;/* INIT_PORT Parameters */
3288 /* -------------- */
3289  pseudo_bit_t reserved35[0x7f800];
3290 /* -------------- */
3291  struct hermonprm_mgm_entry_st mgm_entry;/* Multicast Group Member */
3292 /* -------------- */
3293  pseudo_bit_t reserved36[0x7fe00];
3294 /* -------------- */
3295  struct hermonprm_set_ib_st set_ib; /* SET_IB Parameters */
3296 /* -------------- */
3297  pseudo_bit_t reserved37[0x7fe00];
3298 /* -------------- */
3299  struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */
3300 /* -------------- */
3301  pseudo_bit_t reserved38[0x7ff80];
3302 /* -------------- */
3303  struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */
3304 /* -------------- */
3305  pseudo_bit_t reserved39[0x7ffc0];
3306 /* -------------- */
3307  struct hermonprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */
3308 /* -------------- */
3309  pseudo_bit_t reserved40[0x7ffc0];
3310 /* -------------- */
3311  struct hermonprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */
3312 /* -------------- */
3313  pseudo_bit_t reserved41[0xfffc0];
3314 /* -------------- */
3315  struct hermonprm_uar_st uar; /* User Access Region */
3316 /* -------------- */
3317  pseudo_bit_t reserved42[0x7c000];
3318 /* -------------- */
3319  struct hermonprm_mgmqp_st mgmqp; /* Multicast Group Member QP */
3320 /* -------------- */
3321  pseudo_bit_t reserved43[0x7ffe0];
3322 /* -------------- */
3323  struct hermonprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */
3324 /* -------------- */
3325  pseudo_bit_t reserved44[0x7f800];
3326 /* -------------- */
3327  struct hermonprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */
3328 /* -------------- */
3329  pseudo_bit_t reserved45[0x00900];
3330 /* -------------- */
3331  struct hermonprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */
3332 /* -------------- */
3333  pseudo_bit_t reserved46[0x7e6e0];
3334 /* -------------- */
3335  struct hermonprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */
3336 /* -------------- */
3337  pseudo_bit_t reserved47[0x7fe00];
3338 /* -------------- */
3339  struct hermonprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */
3340 /* -------------- */
3341  pseudo_bit_t reserved48[0x7ff00];
3342 /* -------------- */
3343  struct hermonprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */
3344 /* -------------- */
3345  pseudo_bit_t reserved49[0x7ff40];
3346 /* -------------- */
3347  struct hermonprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */
3348 /* -------------- */
3349  pseudo_bit_t reserved50[0x7f000];
3350 /* -------------- */
3351  struct hermonprm_performance_counters_st performance_counters;/* Performance Counters */
3352 /* -------------- */
3353  pseudo_bit_t reserved51[0x9ff800];
3354 /* -------------- */
3355  struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */
3356 /* -------------- */
3357  pseudo_bit_t reserved52[0x7ff00];
3358 /* -------------- */
3359  struct hermonprm_pbl_st pbl; /* Physical Buffer List */
3360 /* -------------- */
3361  pseudo_bit_t reserved53[0x7ff00];
3362 /* -------------- */
3363  struct hermonprm_srq_context_st srq_context;/* SRQ Context */
3364 /* -------------- */
3365  pseudo_bit_t reserved54[0x7fe80];
3366 /* -------------- */
3367  struct hermonprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */
3368 /* -------------- */
3369  pseudo_bit_t reserved55[0x7f800];
3370 /* -------------- */
3371  struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */
3372 /* -------------- */
3373  pseudo_bit_t reserved56[0x7ff80];
3374 /* -------------- */
3375  struct hermonprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */
3376 /* -------------- */
3377  pseudo_bit_t reserved57[0x7ffc0];
3378 /* -------------- */
3379  struct hermonprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */
3380 /* -------------- */
3381  pseudo_bit_t reserved58[0x7ffc0];
3382 /* -------------- */
3383  struct hermonprm_qp_db_record_st qp_db_record;/* QP_DB_Record */
3384 /* -------------- */
3385  pseudo_bit_t reserved59[0x00020];
3386 /* -------------- */
3387  pseudo_bit_t reserved60[0x1fffc0];
3388 /* -------------- */
3389  struct hermonprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */
3390 /* -------------- */
3391  struct hermonprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */
3392 /* -------------- */
3393  pseudo_bit_t reserved61[0x01000];
3394 /* -------------- */
3395  pseudo_bit_t reserved62[0x00040];
3396 /* -------------- */
3397  pseudo_bit_t reserved63[0x00fc0];
3398 /* -------------- */
3399  struct hermonprm_clr_int_st clr_int; /* Clear Interrupt Register */
3400 /* -------------- */
3401  pseudo_bit_t reserved64[0xffcfc0];
3402 /* -------------- */
3403 };
3404 #endif /* H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H */
hermonprm_query_fw_st::fw_day
pseudo_bit_t fw_day[0x00008]
Definition: MT25408_PRM.h:2311
hermonprm_vsd_st::vsd_dw21
pseudo_bit_t vsd_dw21[0x00020]
Definition: MT25408_PRM.h:454
hermonprm_performance_monitors_st::event_counter1
pseudo_bit_t event_counter1[0x00020]
Definition: MT25408_PRM.h:724
hermonprm_eq_set_ci_table_st::eq57_set_ci
pseudo_bit_t eq57_set_ci[0x00020]
Definition: MT25408_PRM.h:1243
hermonprm_performance_counters_st::reserved3
pseudo_bit_t reserved3[0x00060]
Definition: MT25408_PRM.h:1553
hermonprm_transport_and_ci_error_counters_st::sq_num_ieecne
pseudo_bit_t sq_num_ieecne[0x00020]
Definition: MT25408_PRM.h:1665
hermonprm_mpt_st::fbo_en
pseudo_bit_t fbo_en[0x00001]
Definition: MT25408_PRM.h:2534
hermonprm_mt25208_type0_st::reserved7
pseudo_bit_t reserved7[0x00008]
Definition: MT25408_PRM.h:2727
hermonprm_wqe_segment_ctrl_mlx_st::reserved2
pseudo_bit_t reserved2[0x00001]
Definition: MT25408_PRM.h:741
hermonprm_mt25208_type0_st::vpd_address
pseudo_bit_t vpd_address[0x0000f]
Definition: MT25408_PRM.h:2757
hermonprm_query_fw_st::reserved4
pseudo_bit_t reserved4[0x00040]
Definition: MT25408_PRM.h:2315
hermonprm_queue_pair_ee_context_entry_st::reserved31
pseudo_bit_t reserved31[0x00010]
Definition: MT25408_PRM.h:908
hermonprm_qpcbaseaddr_st::eqc_base_addr_h
pseudo_bit_t eqc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:666
hermonprm_srq_context_st::log2_page_size
pseudo_bit_t log2_page_size[0x00006]
Definition: MT25408_PRM.h:1499
hermonprm_qpcbaseaddr_st::log_num_of_qp
pseudo_bit_t log_num_of_qp[0x00005]
Definition: MT25408_PRM.h:624
hermonprm_hca_command_register_st::in_param_l
pseudo_bit_t in_param_l[0x00020]
Definition: MT25408_PRM.h:338
hermonprm_queue_pair_ee_context_entry_st::cqn_snd
pseudo_bit_t cqn_snd[0x00018]
Definition: MT25408_PRM.h:874
hermonprm_wqe_segment_data_ptr_st::l_key
pseudo_bit_t l_key[0x00020]
Definition: MT25408_PRM.h:112
hermonprm_vsd_st::vsd_dw12
pseudo_bit_t vsd_dw12[0x00020]
Definition: MT25408_PRM.h:436
hermonprm_hca_command_register_st::token
pseudo_bit_t token[0x00010]
Definition: MT25408_PRM.h:347
hermonprm_mod_stat_cfg_st::qdr_tx_options
pseudo_bit_t qdr_tx_options[0x00004]
Definition: MT25408_PRM.h:1354
hermonprm_scrubbing_event_st::err_ca
pseudo_bit_t err_ca[0x00010]
Definition: MT25408_PRM.h:3143
hermonprm_init_hca_st::ipr1
pseudo_bit_t ipr1[0x00001]
Definition: MT25408_PRM.h:2378
hermonprm_mad_ifc_st::request_mad_packet
pseudo_bit_t request_mad_packet[64][0x00020]
Definition: MT25408_PRM.h:1810
hermonprm_vsd_st::vsd_dw38
pseudo_bit_t vsd_dw38[0x00020]
Definition: MT25408_PRM.h:488
hermonprm_hermon_prm_st::srq_context
struct hermonprm_srq_context_st srq_context
Definition: MT25408_PRM.h:3363
hermonprm_qpcbaseaddr_st::eqc_base_addr_l
pseudo_bit_t eqc_base_addr_l[0x0001b]
Definition: MT25408_PRM.h:672
hermonprm_mod_stat_cfg_st::rx_options_m
pseudo_bit_t rx_options_m[0x00001]
Definition: MT25408_PRM.h:1345
hermonprm_page_fault_event_data_st::va_l
pseudo_bit_t va_l[0x00020]
Definition: MT25408_PRM.h:2883
hermonprm_mt25208_type0_st::reserved2
pseudo_bit_t reserved2[0x00010]
Definition: MT25408_PRM.h:2695
hermonprm_mod_stat_cfg_st::nodeguid_lo_m
pseudo_bit_t nodeguid_lo_m[0x00001]
Definition: MT25408_PRM.h:1387
hermonprm_multicastparam_st::mc_base_addr_h
pseudo_bit_t mc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:583
hermonprm_eq_set_ci_table_st::eq16_set_ci
pseudo_bit_t eq16_set_ci[0x00020]
Definition: MT25408_PRM.h:1079
hermonprm_queue_pair_ee_context_entry_st::reserved25
pseudo_bit_t reserved25[0x00004]
Definition: MT25408_PRM.h:885
hermonprm_init_hca_st::tpt_parameters
struct hermonprm_tptparams_st tpt_parameters
Definition: MT25408_PRM.h:2402
hermonprm_mod_stat_cfg_st::reserved37
pseudo_bit_t reserved37[0x00002]
Definition: MT25408_PRM.h:1454
hermonprm_query_dev_cap_st::log_max_scqs
pseudo_bit_t log_max_scqs[0x00004]
Definition: MT25408_PRM.h:2059
hermonprm_transport_and_ci_error_counters_st::reserved4
pseudo_bit_t reserved4[0x00040]
Definition: MT25408_PRM.h:1657
hermonprm_eq_set_ci_table_st::reserved24
pseudo_bit_t reserved24[0x00020]
Definition: MT25408_PRM.h:1113
hermonprm_completion_queue_context_st::solicit_producer_indx
pseudo_bit_t solicit_producer_indx[0x00018]
Definition: MT25408_PRM.h:2607
hermonprm_hermon_prm_st::init_port
struct hermonprm_init_port_st init_port
Definition: MT25408_PRM.h:3287
hermonprm_mcg_hdr_st::next_mcg
pseudo_bit_t next_mcg[0x0001a]
Definition: MT25408_PRM.h:3068
hermonprm_mt25208_type0_st::link_control
pseudo_bit_t link_control[0x00010]
Definition: MT25408_PRM.h:2793
hermonprm_resize_cq_st::page_offset
pseudo_bit_t page_offset[0x00006]
Definition: MT25408_PRM.h:1772
hermonprm_queue_pair_ee_context_entry_st::msg_max
pseudo_bit_t msg_max[0x00005]
Definition: MT25408_PRM.h:828
hermonprm_eq_set_ci_table_st::reserved53
pseudo_bit_t reserved53[0x00020]
Definition: MT25408_PRM.h:1229
hermonprm_completion_queue_entry_st::fl
pseudo_bit_t fl[0x00001]
Definition: MT25408_PRM.h:3000
hermonprm_mt25208_type0_st::cardbus_cis_pointer
pseudo_bit_t cardbus_cis_pointer[0x00020]
Definition: MT25408_PRM.h:2700
hermonprm_virtual_physical_mapping_st::reserved0
pseudo_bit_t reserved0[0x0000c]
Definition: MT25408_PRM.h:1324
hermonprm_mpt_st::status
pseudo_bit_t status[0x00004]
Definition: MT25408_PRM.h:2499
hermonprm_eq_set_ci_table_st::eq50_set_ci
pseudo_bit_t eq50_set_ci[0x00020]
Definition: MT25408_PRM.h:1215
hermonprm_init_hca_st::qpc_eec_cqc_eqc_rdb_parameters
struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters
Definition: MT25408_PRM.h:2394
hermonprm_eq_set_ci_table_st::reserved31
pseudo_bit_t reserved31[0x00020]
Definition: MT25408_PRM.h:1141
hermonprm_completion_queue_entry_st::reserved0
pseudo_bit_t reserved0[0x00002]
Definition: MT25408_PRM.h:2995
hermonprm_mt25208_type0_st::pm_cap
pseudo_bit_t pm_cap[0x00010]
Definition: MT25408_PRM.h:2740
hermonprm_hermon_prm_st::reserved23
pseudo_bit_t reserved23[0x7ffc0]
Definition: MT25408_PRM.h:3251
hermonprm_mt25208_type0_st::bar2_l
pseudo_bit_t bar2_l[0x0000c]
Definition: MT25408_PRM.h:2696
hermonprm_send_doorbell_st::wqe_cnt
pseudo_bit_t wqe_cnt[0x00008]
Definition: MT25408_PRM.h:84
hermonprm_ud_address_vector_st::port_number
pseudo_bit_t port_number[0x00002]
Definition: MT25408_PRM.h:37
hermonprm_eqc_st::reserved14
pseudo_bit_t reserved14[0x00008]
Definition: MT25408_PRM.h:2465
hermonprm_hermon_prm_st::reserved45
pseudo_bit_t reserved45[0x00900]
Definition: MT25408_PRM.h:3329
hermonprm_queue_pair_ee_context_entry_st::state
pseudo_bit_t state[0x00004]
Definition: MT25408_PRM.h:800
hermonprm_queue_pair_ee_context_entry_st::reserved30
pseudo_bit_t reserved30[0x00003]
Definition: MT25408_PRM.h:905
hermonprm_send_wqe_segment_st::wqe_segment_atomic
struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic
Definition: MT25408_PRM.h:771
hermonprm_page_fault_event_data_st::rw
pseudo_bit_t rw[0x00001]
Definition: MT25408_PRM.h:2892
hermonprm_ud_address_vector_st::mgid_index
pseudo_bit_t mgid_index[0x00007]
Definition: MT25408_PRM.h:56
hermonprm_completion_event_st::cqn
pseudo_bit_t cqn[0x00018]
Definition: MT25408_PRM.h:2952
hermonprm_srq_context_st::reserved9
pseudo_bit_t reserved9[0x00020]
Definition: MT25408_PRM.h:1514
hermonprm_mod_stat_cfg_st::reserved31
pseudo_bit_t reserved31[0x00010]
Definition: MT25408_PRM.h:1436
hermonprm_hermon_prm_st::reserved10
pseudo_bit_t reserved10[0x00040]
Definition: MT25408_PRM.h:3199
hermonprm_mt25208_type0_st::header_type
pseudo_bit_t header_type[0x00008]
Definition: MT25408_PRM.h:2679
hermonprm_hca_command_register_st::e
pseudo_bit_t e[0x00001]
Definition: MT25408_PRM.h:353
hermonprm_srq_context_st::reserved10
pseudo_bit_t reserved10[0x00002]
Definition: MT25408_PRM.h:1518
hermonprm_query_dev_cap_st::reserved37
pseudo_bit_t reserved37[0x00001]
Definition: MT25408_PRM.h:2198
hermonprm_cq_arm_db_record_st::counter
pseudo_bit_t counter[0x00020]
Definition: MT25408_PRM.h:1295
hermonprm_eqc_st::mtt_base_addr_h
pseudo_bit_t mtt_base_addr_h[0x00008]
Definition: MT25408_PRM.h:2447
hermonprm_srq_context_st::log_srq_stride
pseudo_bit_t log_srq_stride[0x00003]
Definition: MT25408_PRM.h:1488
hermonprm_page_fault_event_data_st::lr
pseudo_bit_t lr[0x00001]
Definition: MT25408_PRM.h:2891
hermonprm_mt25208_type0_st::cap_64_bit_addr
pseudo_bit_t cap_64_bit_addr[0x00001]
Definition: MT25408_PRM.h:2726
hermonprm_mod_stat_cfg_st::guid_lo_m
pseudo_bit_t guid_lo_m[0x00001]
Definition: MT25408_PRM.h:1377
hermonprm_eq_set_ci_table_st::reserved45
pseudo_bit_t reserved45[0x00020]
Definition: MT25408_PRM.h:1197
hermonprm_queue_pair_ee_context_entry_st::reserved12
pseudo_bit_t reserved12[0x00008]
Definition: MT25408_PRM.h:847
hermonprm_vsd_st::vsd_dw40
pseudo_bit_t vsd_dw40[0x00020]
Definition: MT25408_PRM.h:492
hermonprm_vsd_st::vsd_dw48
pseudo_bit_t vsd_dw48[0x00020]
Definition: MT25408_PRM.h:508
hermonprm_address_path_st::rgid_31_0
pseudo_bit_t rgid_31_0[0x00020]
Definition: MT25408_PRM.h:313
hermonprm_query_fw_st::fw_rev_minor
pseudo_bit_t fw_rev_minor[0x00010]
Definition: MT25408_PRM.h:2292
hermonprm_address_path_st::fsm
pseudo_bit_t fsm[0x00001]
Definition: MT25408_PRM.h:320
hermonprm_mtt_st::reserved0
pseudo_bit_t reserved0[0x00002]
Definition: MT25408_PRM.h:2477
hermonprm_completion_queue_context_st::reserved12
pseudo_bit_t reserved12[0x00008]
Definition: MT25408_PRM.h:2610
hermonprm_mpt_st::pa
pseudo_bit_t pa[0x00001]
Definition: MT25408_PRM.h:2487
hermonprm_vsd_st::vsd_dw28
pseudo_bit_t vsd_dw28[0x00020]
Definition: MT25408_PRM.h:468
hermonprm_mt25208_type0_st::multiple_msg_cap
pseudo_bit_t multiple_msg_cap[0x00003]
Definition: MT25408_PRM.h:2724
hermonprm_eq_set_ci_table_st::reserved40
pseudo_bit_t reserved40[0x00020]
Definition: MT25408_PRM.h:1177
hermonprm_srq_context_st::page_offset
pseudo_bit_t page_offset[0x00006]
Definition: MT25408_PRM.h:1492
hermonprm_wqe_segment_ud_st
Definition: MT25408_PRM.h:220
hermonprm_mcg_hdr_st::members_count
pseudo_bit_t members_count[0x00018]
Definition: MT25408_PRM.h:3070
hermonprm_mt25208_type0_st::vendor_id
pseudo_bit_t vendor_id[0x00010]
Definition: MT25408_PRM.h:2665
hermonprm_hcr_completion_event_st::out_param_h
pseudo_bit_t out_param_h[0x00020]
Definition: MT25408_PRM.h:1714
hermonprm_query_dev_cap_st::raw_ipv6
pseudo_bit_t raw_ipv6[0x00001]
Definition: MT25408_PRM.h:2160
hermonprm_wqe_segment_ctrl_mlx_st::fl
pseudo_bit_t fl[0x00001]
Definition: MT25408_PRM.h:740
hermonprm_multicastparam_st::reserved3
pseudo_bit_t reserved3[0x0001b]
Definition: MT25408_PRM.h:602
hermonprm_query_debug_msg_st::buff4_addr
pseudo_bit_t buff4_addr[0x00020]
Definition: MT25408_PRM.h:1886
hermonprm_queue_pair_ee_context_entry_st::reserved33
pseudo_bit_t reserved33[0x00002]
Definition: MT25408_PRM.h:915
hermonprm_performance_monitor_event_st::reserved0
pseudo_bit_t reserved0[0x00018]
Definition: MT25408_PRM.h:2872
hermonprm_wqe_segment_ctrl_mlx_st::reserved3
pseudo_bit_t reserved3[0x00003]
Definition: MT25408_PRM.h:744
hermonprm_mt25208_type0_st::interrupt_line
pseudo_bit_t interrupt_line[0x00008]
Definition: MT25408_PRM.h:2714
hermonprm_completion_queue_error_st::reserved1
pseudo_bit_t reserved1[0x00020]
Definition: MT25408_PRM.h:2938
hermonprm_configuration_registers_st::hca_command_interface_register
struct hermonprm_hca_command_register_st hca_command_interface_register
Definition: MT25408_PRM.h:1278
hermonprm_query_dev_cap_st::log_max_bf_regs_per_page
pseudo_bit_t log_max_bf_regs_per_page[0x00006]
Definition: MT25408_PRM.h:2184
hermonprm_vsd_st::vsd_dw37
pseudo_bit_t vsd_dw37[0x00020]
Definition: MT25408_PRM.h:486
hermonprm_eq_set_ci_table_st::eq6_set_ci
pseudo_bit_t eq6_set_ci[0x00020]
Definition: MT25408_PRM.h:1039
hermonprm_mod_stat_cfg_st::ob_preemp_post
pseudo_bit_t ob_preemp_post[0x00005]
Definition: MT25408_PRM.h:1393
hermonprm_tptparams_st::mtt_base_addr_h
pseudo_bit_t mtt_base_addr_h[0x00020]
Definition: MT25408_PRM.h:562
hermonprm_address_path_st::reserved6
pseudo_bit_t reserved6[0x00002]
Definition: MT25408_PRM.h:317
hermonprm_queue_pair_ee_context_entry_st::mtt_base_addr_l
pseudo_bit_t mtt_base_addr_l[0x0001d]
Definition: MT25408_PRM.h:961
hermonprm_hermon_prm_st::reserved17
pseudo_bit_t reserved17[0x7ffc0]
Definition: MT25408_PRM.h:3227
hermonprm_rd_send_doorbell_st::send_doorbell
struct hermonprm_send_doorbell_st send_doorbell
Definition: MT25408_PRM.h:395
hermonprm_mod_stat_cfg_st::reserved42
pseudo_bit_t reserved42[0x00220]
Definition: MT25408_PRM.h:1471
hermonprm_eq_set_ci_table_st::eq47_set_ci
pseudo_bit_t eq47_set_ci[0x00020]
Definition: MT25408_PRM.h:1203
hermonprm_srq_context_st::pd
pseudo_bit_t pd[0x00018]
Definition: MT25408_PRM.h:1505
hermonprm_mpt_st::qpn
pseudo_bit_t qpn[0x00018]
Definition: MT25408_PRM.h:2503
hermonprm_performance_monitors_st::i1
pseudo_bit_t i1[0x00001]
Definition: MT25408_PRM.h:710
hermonprm_set_ib_st::reserved0
pseudo_bit_t reserved0[0x00011]
Definition: MT25408_PRM.h:1937
hermonprm_query_dev_cap_st::log_max_eq_sz
pseudo_bit_t log_max_eq_sz[0x00008]
Definition: MT25408_PRM.h:2085
hermonprm_completion_with_error_st::syndrome
pseudo_bit_t syndrome[0x00008]
Definition: MT25408_PRM.h:1730
hermonprm_hermon_prm_st::reserved6
pseudo_bit_t reserved6[0x7f000]
Definition: MT25408_PRM.h:3183
hermonprm_queue_pair_ee_context_entry_st::log_rq_size
pseudo_bit_t log_rq_size[0x00004]
Definition: MT25408_PRM.h:826
hermonprm_page_fault_event_data_st::va_h
pseudo_bit_t va_h[0x00020]
Definition: MT25408_PRM.h:2881
hermonprm_mod_stat_cfg_st::reserved11
pseudo_bit_t reserved11[0x0001f]
Definition: MT25408_PRM.h:1371
hermonprm_clr_int_st::clr_int_h
pseudo_bit_t clr_int_h[0x00020]
Definition: MT25408_PRM.h:1001
hermonprm_query_dev_cap_st::log_max_eq
pseudo_bit_t log_max_eq[0x00004]
Definition: MT25408_PRM.h:2077
hermonprm_query_dev_cap_st::log_max_ra_res_qp
pseudo_bit_t log_max_ra_res_qp[0x00006]
Definition: MT25408_PRM.h:2100
hermonprm_transport_and_ci_error_counters_st::sq_num_rsync
pseudo_bit_t sq_num_rsync[0x00020]
Definition: MT25408_PRM.h:1683
hermonprm_fast_registration_segment_st
Definition: MT25408_PRM.h:134
hermonprm_query_dev_cap_st::reserved26
pseudo_bit_t reserved26[0x00008]
Definition: MT25408_PRM.h:2138
hermonprm_scrubbing_event_st::err_src_id
pseudo_bit_t err_src_id[0x00003]
Definition: MT25408_PRM.h:3136
hermonprm_wqe_segment_bind_st::type
pseudo_bit_t type[0x00001]
Definition: MT25408_PRM.h:199
hermonprm_mod_stat_cfg_st::serdes_m
pseudo_bit_t serdes_m[0x00001]
Definition: MT25408_PRM.h:1399
hermonprm_vsd_st::vsd_dw1
pseudo_bit_t vsd_dw1[0x00020]
Definition: MT25408_PRM.h:414
hermonprm_query_dev_cap_st::reserved4
pseudo_bit_t reserved4[0x00002]
Definition: MT25408_PRM.h:2062
hermonprm_hermon_prm_st::send_doorbell
struct hermonprm_send_doorbell_st send_doorbell
Definition: MT25408_PRM.h:3303
hermonprm_eq_set_ci_table_st::reserved59
pseudo_bit_t reserved59[0x00020]
Definition: MT25408_PRM.h:1253
hermonprm_ud_address_vector_st
Definition: MT25408_PRM.h:35
hermonprm_performance_monitors_st::reserved4
pseudo_bit_t reserved4[0x00003]
Definition: MT25408_PRM.h:718
hermonprm_queue_pair_ee_context_entry_st::reserved48
pseudo_bit_t reserved48[0x000c0]
Definition: MT25408_PRM.h:984
hermonprm_mad_ifc_st::reserved2
pseudo_bit_t reserved2[0x00008]
Definition: MT25408_PRM.h:1820
hermonprm_hermon_prm_st::reserved49
pseudo_bit_t reserved49[0x7ff40]
Definition: MT25408_PRM.h:3345
hermonprm_hermon_prm_st::reserved4
pseudo_bit_t reserved4[0x7ff40]
Definition: MT25408_PRM.h:3175
hermonprm_hca_command_register_st::input_modifier
pseudo_bit_t input_modifier[0x00020]
Definition: MT25408_PRM.h:340
hermonprm_address_path_st::reserved8
pseudo_bit_t reserved8[0x00001]
Definition: MT25408_PRM.h:326
hermonprm_eq_set_ci_table_st::eq48_set_ci
pseudo_bit_t eq48_set_ci[0x00020]
Definition: MT25408_PRM.h:1207
hermonprm_init_port_st::max_pkey
pseudo_bit_t max_pkey[0x00010]
Definition: MT25408_PRM.h:2020
hermonprm_query_dev_cap_st::reserved44
pseudo_bit_t reserved44[0x0001a]
Definition: MT25408_PRM.h:2258
hermonprm_header_log_register_st
Definition: MT25408_PRM.h:691
hermonprm_eq_set_ci_table_st::reserved11
pseudo_bit_t reserved11[0x00020]
Definition: MT25408_PRM.h:1061
hermonprm_query_dev_cap_st::lif
pseudo_bit_t lif[0x00001]
Definition: MT25408_PRM.h:2257
hermonprm_query_fw_st::error_buf_offset_h
pseudo_bit_t error_buf_offset_h[0x00020]
Definition: MT25408_PRM.h:2332
hermonprm_query_dev_cap_st::w
pseudo_bit_t w[0x00001]
Definition: MT25408_PRM.h:2118
hermonprm_qpcbaseaddr_st::cqc_base_addr_h
pseudo_bit_t cqc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:641
hermonprm_hermon_prm_st::reserved41
pseudo_bit_t reserved41[0xfffc0]
Definition: MT25408_PRM.h:3313
hermonprm_mt25208_type0_st::msg_addr_h
pseudo_bit_t msg_addr_h[0x00020]
Definition: MT25408_PRM.h:2731
hermonprm_hermon_prm_st::reserved28
pseudo_bit_t reserved28[0x7f700]
Definition: MT25408_PRM.h:3265
hermonprm_receive_doorbell_st::reserved3
pseudo_bit_t reserved3[0x00002]
Definition: MT25408_PRM.h:1928
hermonprm_queue_pair_ee_context_entry_st::log_sq_stride
pseudo_bit_t log_sq_stride[0x00003]
Definition: MT25408_PRM.h:820
hermonprm_srq_context_st::reserved1
pseudo_bit_t reserved1[0x00005]
Definition: MT25408_PRM.h:1489
hermonprm_queue_pair_ee_context_entry_st::reserved15
pseudo_bit_t reserved15[0x00001]
Definition: MT25408_PRM.h:855
hermonprm_hermon_prm_st::reserved26
pseudo_bit_t reserved26[0x00800]
Definition: MT25408_PRM.h:3261
hermonprm_mtt_st::p
pseudo_bit_t p[0x00001]
Definition: MT25408_PRM.h:2476
hermonprm_query_debug_msg_st::dbg_msk_l
pseudo_bit_t dbg_msk_l[0x00020]
Definition: MT25408_PRM.h:1866
hermonprm_mpt_st::atc_xlated
pseudo_bit_t atc_xlated[0x00001]
Definition: MT25408_PRM.h:2495
hermonprm_wqe_segment_ud_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:224
hermonprm_query_dev_cap_st::log_max_mtts
pseudo_bit_t log_max_mtts[0x00006]
Definition: MT25408_PRM.h:2087
hermonprm_fast_registration_segment_st::rw
pseudo_bit_t rw[0x00001]
Definition: MT25408_PRM.h:139
hermonprm_completion_queue_context_st::reserved13
pseudo_bit_t reserved13[0x00008]
Definition: MT25408_PRM.h:2614
hermonprm_init_hca_st::multicast_parameters
struct hermonprm_multicastparam_st multicast_parameters
Definition: MT25408_PRM.h:2398
hermonprm_eq_set_ci_table_st::reserved56
pseudo_bit_t reserved56[0x00020]
Definition: MT25408_PRM.h:1241
hermonprm_ecc_detect_event_data_st::reserved2
pseudo_bit_t reserved2[0x00002]
Definition: MT25408_PRM.h:3109
hermonprm_query_dev_cap_st::uar_sz
pseudo_bit_t uar_sz[0x00006]
Definition: MT25408_PRM.h:2176
hermonprm_eq_cmd_doorbell_st::reserved0
pseudo_bit_t reserved0[0x00020]
Definition: MT25408_PRM.h:3150
hermonprm_query_dev_cap_st::ud
pseudo_bit_t ud[0x00001]
Definition: MT25408_PRM.h:2147
hermonprm_ud_address_vector_st::max_stat_rate
pseudo_bit_t max_stat_rate[0x00004]
Definition: MT25408_PRM.h:50
hermonprm_completion_with_error_st::owner
pseudo_bit_t owner[0x00001]
Definition: MT25408_PRM.h:1761
hermonprm_gpio_event_data_st::reserved0
pseudo_bit_t reserved0[0x00060]
Definition: MT25408_PRM.h:2635
hermonprm_mod_stat_cfg_st::port_eth_mode_current
pseudo_bit_t port_eth_mode_current[0x0001f]
Definition: MT25408_PRM.h:1468
hermonprm_eq_set_ci_table_st::eq23_set_ci
pseudo_bit_t eq23_set_ci[0x00020]
Definition: MT25408_PRM.h:1107
hermonprm_address_path_st::my_lid_smac_idx
pseudo_bit_t my_lid_smac_idx[0x00007]
Definition: MT25408_PRM.h:278
hermonprm_mtt_st::ptag_h
pseudo_bit_t ptag_h[0x00020]
Definition: MT25408_PRM.h:2474
hermonprm_transport_and_ci_error_counters_st::sq_num_bre
pseudo_bit_t sq_num_bre[0x00020]
Definition: MT25408_PRM.h:1590
hermonprm_mt25208_type0_st::bist
pseudo_bit_t bist[0x00008]
Definition: MT25408_PRM.h:2680
hermonprm_uar_params_st::reserved2
pseudo_bit_t reserved2[0x000a0]
Definition: MT25408_PRM.h:536
hermonprm_send_doorbell_st::nopcode
pseudo_bit_t nopcode[0x00005]
Definition: MT25408_PRM.h:80
hermonprm_mt25208_type0_st::bar1_ctrl
pseudo_bit_t bar1_ctrl[0x00004]
Definition: MT25408_PRM.h:2688
hermonprm_wqe_segment_bind_st::start_address_l
pseudo_bit_t start_address_l[0x00020]
Definition: MT25408_PRM.h:210
hermonprm_mt25208_type0_st::reserved3
pseudo_bit_t reserved3[0x0000a]
Definition: MT25408_PRM.h:2706
hermonprm_hca_command_register_st::go
pseudo_bit_t go[0x00001]
Definition: MT25408_PRM.h:356
hermonprm_wqe_segment_ctrl_mlx_st::v15
pseudo_bit_t v15[0x00001]
Definition: MT25408_PRM.h:748
hermonprm_query_dev_cap_st::log_max_msg
pseudo_bit_t log_max_msg[0x00005]
Definition: MT25408_PRM.h:2127
hermonprm_transport_and_ci_error_counters_st::reserved0
pseudo_bit_t reserved0[0x00020]
Definition: MT25408_PRM.h:1584
hermonprm_hermon_prm_st::reserved19
pseudo_bit_t reserved19[0x7ff80]
Definition: MT25408_PRM.h:3235
hermonprm_mgm_entry_st
Definition: MT25408_PRM.h:1956
hermonprm_hermon_prm_st::set_ib
struct hermonprm_set_ib_st set_ib
Definition: MT25408_PRM.h:3295
hermonprm_query_dev_cap_st::apm
pseudo_bit_t apm[0x00001]
Definition: MT25408_PRM.h:2163
hermonprm_queue_pair_ee_context_entry_st::cur_rnr_retry
pseudo_bit_t cur_rnr_retry[0x00003]
Definition: MT25408_PRM.h:858
hermonprm_sched_queue_context_st::policy
pseudo_bit_t policy[0x00003]
Definition: MT25408_PRM.h:3092
hermonprm_queue_pair_ee_context_entry_st::next_rcv_psn
pseudo_bit_t next_rcv_psn[0x00018]
Definition: MT25408_PRM.h:902
hermonprm_query_dev_cap_st::log2_rsvd_srqs
pseudo_bit_t log2_rsvd_srqs[0x00004]
Definition: MT25408_PRM.h:2065
hermonprm_gpio_event_data_st::gpio_event_hi
pseudo_bit_t gpio_event_hi[0x00020]
Definition: MT25408_PRM.h:2637
hermonprm_udavtable_memory_parameters_st::l_key
pseudo_bit_t l_key[0x00020]
Definition: MT25408_PRM.h:2354
hermonprm_mgm_entry_st::mgmqp_2
struct hermonprm_mgmqp_st mgmqp_2
Definition: MT25408_PRM.h:1980
hermonprm_eq_set_ci_table_st::eq5_set_ci
pseudo_bit_t eq5_set_ci[0x00020]
Definition: MT25408_PRM.h:1035
hermonprm_cq_ci_db_record_st::reserved0
pseudo_bit_t reserved0[0x00005]
Definition: MT25408_PRM.h:1313
hermonprm_queue_pair_ee_context_entry_st::reserved9
pseudo_bit_t reserved9[0x00001]
Definition: MT25408_PRM.h:827
hermonprm_local_invalidate_segment_st
Definition: MT25408_PRM.h:122
hermonprm_configuration_registers_st::reserved0
pseudo_bit_t reserved0[0x403400]
Definition: MT25408_PRM.h:1276
hermonprm_wqe_segment_ctrl_mlx_st::c
pseudo_bit_t c[0x00002]
Definition: MT25408_PRM.h:742
hermonprm_mod_stat_cfg_st::reserved6
pseudo_bit_t reserved6[0x00020]
Definition: MT25408_PRM.h:1358
hermonprm_mod_stat_cfg_st::reserved29
pseudo_bit_t reserved29[0x00180]
Definition: MT25408_PRM.h:1426
hermonprm_qpcbaseaddr_st::reserved5
pseudo_bit_t reserved5[0x00040]
Definition: MT25408_PRM.h:664
hermonprm_fast_registration_segment_st::start_address_l
pseudo_bit_t start_address_l[0x00020]
Definition: MT25408_PRM.h:154
hermonprm_eq_set_ci_table_st::eq21_set_ci
pseudo_bit_t eq21_set_ci[0x00020]
Definition: MT25408_PRM.h:1099
hermonprm_eq_set_ci_table_st::reserved57
pseudo_bit_t reserved57[0x00020]
Definition: MT25408_PRM.h:1245
hermonprm_query_dev_cap_st::reserved23
pseudo_bit_t reserved23[0x00004]
Definition: MT25408_PRM.h:2125
hermonprm_mcg_hdr_st::gid2
pseudo_bit_t gid2[0x00020]
Definition: MT25408_PRM.h:3081
hermonprm_queue_pair_ee_context_entry_st::sra_max
pseudo_bit_t sra_max[0x00003]
Definition: MT25408_PRM.h:865
hermonprm_transport_and_ci_error_counters_st::rq_num_lqpoe
pseudo_bit_t rq_num_lqpoe[0x00020]
Definition: MT25408_PRM.h:1566
hermonprm_wqe_segment_bind_st::region_lkey
pseudo_bit_t region_lkey[0x00020]
Definition: MT25408_PRM.h:206
hermonprm_hermon_prm_st::performance_monitor_event
struct hermonprm_performance_monitor_event_st performance_monitor_event
Definition: MT25408_PRM.h:3189
hermonprm_qpcbaseaddr_st::reserved3
pseudo_bit_t reserved3[0x00040]
Definition: MT25408_PRM.h:648
hermonprm_wqe_segment_bind_st::start_address_h
pseudo_bit_t start_address_h[0x00020]
Definition: MT25408_PRM.h:208
hermonprm_mt25208_type0_st::f
pseudo_bit_t f[0x00001]
Definition: MT25408_PRM.h:2758
hermonprm_hca_command_register_st::opcode_modifier
pseudo_bit_t opcode_modifier[0x00004]
Definition: MT25408_PRM.h:350
hermonprm_query_dev_cap_st::port_type
pseudo_bit_t port_type[0x00004]
Definition: MT25408_PRM.h:2116
hermonprm_wqe_segment_ctrl_send_st::fl
pseudo_bit_t fl[0x00001]
Definition: MT25408_PRM.h:255
hermonprm_eqc_st::reserved7
pseudo_bit_t reserved7[0x00003]
Definition: MT25408_PRM.h:2439
hermonprm_hermon_prm_st::reserved47
pseudo_bit_t reserved47[0x7fe00]
Definition: MT25408_PRM.h:3337
hermonprm_completion_queue_context_st::mtt_base_addr_h
pseudo_bit_t mtt_base_addr_h[0x00008]
Definition: MT25408_PRM.h:2595
hermonprm_eq_set_ci_table_st::eq55_set_ci
pseudo_bit_t eq55_set_ci[0x00020]
Definition: MT25408_PRM.h:1235
hermonprm_pbl_st::mtt_2_l
pseudo_bit_t mtt_2_l[0x00020]
Definition: MT25408_PRM.h:1536
hermonprm_ecc_detect_event_data_st
Definition: MT25408_PRM.h:3103
hermonprm_send_wqe_segment_st::wqe_segment_bind
struct hermonprm_wqe_segment_bind_st wqe_segment_bind
Definition: MT25408_PRM.h:765
hermonprm_vsd_st::vsd_dw6
pseudo_bit_t vsd_dw6[0x00020]
Definition: MT25408_PRM.h:424
hermonprm_queue_pair_ee_context_entry_st::rmc_parent_qpn
pseudo_bit_t rmc_parent_qpn[0x00018]
Definition: MT25408_PRM.h:939
hermonprm_mod_stat_cfg_st::reserved15
pseudo_bit_t reserved15[0x00003]
Definition: MT25408_PRM.h:1392
hermonprm_queue_pair_ee_context_entry_st::ric
pseudo_bit_t ric[0x00001]
Definition: MT25408_PRM.h:886
hermonprm_qpcbaseaddr_st::reserved2
pseudo_bit_t reserved2[0x00040]
Definition: MT25408_PRM.h:630
hermonprm_eq_set_ci_table_st::reserved43
pseudo_bit_t reserved43[0x00020]
Definition: MT25408_PRM.h:1189
hermonprm_queue_pair_ee_context_entry_st::st
pseudo_bit_t st[0x00004]
Definition: MT25408_PRM.h:798
hermonprm_mod_stat_cfg_st::port_protocol_vpi
pseudo_bit_t port_protocol_vpi[0x00008]
Definition: MT25408_PRM.h:1423
hermonprm_mpt_st::rae
pseudo_bit_t rae[0x00001]
Definition: MT25408_PRM.h:2512
hermonprm_init_hca_st::ipr2
pseudo_bit_t ipr2[0x00001]
Definition: MT25408_PRM.h:2377
hermonprm_hermon_prm_st::reserved9
pseudo_bit_t reserved9[0x7f000]
Definition: MT25408_PRM.h:3195
hermonprm_eq_set_ci_table_st::reserved46
pseudo_bit_t reserved46[0x00020]
Definition: MT25408_PRM.h:1201
hermonprm_eq_set_ci_table_st::eq20_set_ci
pseudo_bit_t eq20_set_ci[0x00020]
Definition: MT25408_PRM.h:1095
hermonprm_mod_stat_cfg_st::cmd_interface_rev
pseudo_bit_t cmd_interface_rev[0x00010]
Definition: MT25408_PRM.h:1435
hermonprm_completion_queue_entry_st::checksum
pseudo_bit_t checksum[0x00010]
Definition: MT25408_PRM.h:3038
command
A command-line command.
Definition: command.h:9
hermonprm_queue_pair_ee_context_entry_st::reserved42
pseudo_bit_t reserved42[0x00001]
Definition: MT25408_PRM.h:965
hermonprm_query_dev_cap_st::log2_rsvd_mtts
pseudo_bit_t log2_rsvd_mtts[0x00004]
Definition: MT25408_PRM.h:2094
hermonprm_hermon_prm_st::query_adapter
struct hermonprm_query_adapter_st query_adapter
Definition: MT25408_PRM.h:3275
hermonprm_queue_pair_ee_context_entry_st::reserved23
pseudo_bit_t reserved23[0x00008]
Definition: MT25408_PRM.h:880
hermonprm_hermon_prm_st::reserved60
pseudo_bit_t reserved60[0x1fffc0]
Definition: MT25408_PRM.h:3387
hermonprm_udavtable_memory_parameters_st
Definition: MT25408_PRM.h:2353
hermonprm_query_dev_cap_st::log_max_ra_req_qp
pseudo_bit_t log_max_ra_req_qp[0x00006]
Definition: MT25408_PRM.h:2102
hermonprm_init_hca_st::he
pseudo_bit_t he[0x00001]
Definition: MT25408_PRM.h:2384
hermonprm_query_debug_msg_st::trc_arg_num
pseudo_bit_t trc_arg_num[0x00020]
Definition: MT25408_PRM.h:1860
hermonprm_mod_stat_cfg_st::reserved35
pseudo_bit_t reserved35[0x00020]
Definition: MT25408_PRM.h:1450
hermonprm_queue_pair_ee_context_entry_st::fc
pseudo_bit_t fc[0x00001]
Definition: MT25408_PRM.h:974
hermonprm_queue_pair_ee_context_entry_st::reserved39
pseudo_bit_t reserved39[0x00010]
Definition: MT25408_PRM.h:956
hermonprm_eq_set_ci_table_st::eq8_set_ci
pseudo_bit_t eq8_set_ci[0x00020]
Definition: MT25408_PRM.h:1047
hermonprm_hermon_prm_st::completion_with_error
struct hermonprm_completion_with_error_st completion_with_error
Definition: MT25408_PRM.h:3339
hermonprm_port_state_change_st::reserved3
pseudo_bit_t reserved3[0x00060]
Definition: MT25408_PRM.h:2928
hermonprm_query_dev_cap_st::bmme
pseudo_bit_t bmme[0x00001]
Definition: MT25408_PRM.h:2250
hermonprm_mgm_entry_st::mgid_31_0
pseudo_bit_t mgid_31_0[0x00020]
Definition: MT25408_PRM.h:1973
hermonprm_init_hca_st::reserved1
pseudo_bit_t reserved1[0x00040]
Definition: MT25408_PRM.h:2369
hermonprm_qpcbaseaddr_st::log_num_rd
pseudo_bit_t log_num_rd[0x00003]
Definition: MT25408_PRM.h:680
hermonprm_page_fault_event_data_st::a
pseudo_bit_t a[0x00001]
Definition: MT25408_PRM.h:2889
hermonprm_wqe_segment_st::mlx_wqe_segment_ctrl
struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl
Definition: MT25408_PRM.h:2909
hermonprm_query_dev_cap_st::pg
pseudo_bit_t pg[0x00001]
Definition: MT25408_PRM.h:2169
hermonprm_eq_set_ci_table_st::reserved18
pseudo_bit_t reserved18[0x00020]
Definition: MT25408_PRM.h:1089
hermonprm_send_wqe_segment_st::local_invalidate_segment
struct hermonprm_local_invalidate_segment_st local_invalidate_segment
Definition: MT25408_PRM.h:775
hermonprm_queue_pair_ee_context_entry_st::min_rnr_nak
pseudo_bit_t min_rnr_nak[0x00005]
Definition: MT25408_PRM.h:903
hermonprm_srq_context_st::db_record_addr_h
pseudo_bit_t db_record_addr_h[0x00020]
Definition: MT25408_PRM.h:1516
hermonprm_hermon_prm_st::event_queue_entry
struct hermonprm_event_queue_entry_st event_queue_entry
Definition: MT25408_PRM.h:3165
hermonprm_wqe_segment_ctrl_send_st::reserved2
pseudo_bit_t reserved2[0x00001]
Definition: MT25408_PRM.h:260
hermonprm_hermon_prm_st::reserved48
pseudo_bit_t reserved48[0x7ff00]
Definition: MT25408_PRM.h:3341
hermonprm_mpt_st::rw
pseudo_bit_t rw[0x00001]
Definition: MT25408_PRM.h:2491
hermonprm_mod_stat_cfg_st::guid_lo
pseudo_bit_t guid_lo[0x00020]
Definition: MT25408_PRM.h:1379
hermonprm_eq_set_ci_table_st::reserved47
pseudo_bit_t reserved47[0x00020]
Definition: MT25408_PRM.h:1205
hermonprm_wqe_segment_atomic_st::compare_l
pseudo_bit_t compare_l[0x00020]
Definition: MT25408_PRM.h:171
hermonprm_mcg_hdr_st::reserved3
pseudo_bit_t reserved3[0x00020]
Definition: MT25408_PRM.h:3077
hermonprm_performance_monitors_st::reserved3
pseudo_bit_t reserved3[0x00001]
Definition: MT25408_PRM.h:716
hermonprm_vsd_st::vsd_dw10
pseudo_bit_t vsd_dw10[0x00020]
Definition: MT25408_PRM.h:432
hermonprm_completion_queue_entry_st::dife
pseudo_bit_t dife[0x00001]
Definition: MT25408_PRM.h:3005
hermonprm_eq_set_ci_table_st::reserved36
pseudo_bit_t reserved36[0x00020]
Definition: MT25408_PRM.h:1161
hermonprm_address_path_st::hop_limit
pseudo_bit_t hop_limit[0x00008]
Definition: MT25408_PRM.h:282
hermonprm_wqe_segment_bind_st::zb
pseudo_bit_t zb[0x00001]
Definition: MT25408_PRM.h:198
hermonprm_query_dev_cap_st::reserved13
pseudo_bit_t reserved13[0x00004]
Definition: MT25408_PRM.h:2091
hermonprm_cq_arm_db_record_st::res
pseudo_bit_t res[0x00003]
Definition: MT25408_PRM.h:1303
hermonprm_mpt_st::atc_req
pseudo_bit_t atc_req[0x00001]
Definition: MT25408_PRM.h:2494
hermonprm_completion_queue_error_st::reserved3
pseudo_bit_t reserved3[0x00060]
Definition: MT25408_PRM.h:2945
hermonprm_wqe_segment_ctrl_mlx_st::ds
pseudo_bit_t ds[0x00006]
Definition: MT25408_PRM.h:737
hermonprm_scrubbing_event_st::overflow
pseudo_bit_t overflow[0x00001]
Definition: MT25408_PRM.h:3140
hermonprm_performance_monitors_st::clock_counter
pseudo_bit_t clock_counter[0x00020]
Definition: MT25408_PRM.h:722
hermonprm_wqe_segment_st::reserved0
pseudo_bit_t reserved0[0x00280]
Definition: MT25408_PRM.h:2907
hermonprm_mtt_st
Definition: MT25408_PRM.h:2473
hermonprm_eqc_st::reserved13
pseudo_bit_t reserved13[0x00008]
Definition: MT25408_PRM.h:2460
hermonprm_local_invalidate_segment_st::mem_key
pseudo_bit_t mem_key[0x00018]
Definition: MT25408_PRM.h:125
hermonprm_mt25208_type0_st::vpd_data
pseudo_bit_t vpd_data[0x00020]
Definition: MT25408_PRM.h:2760
hermonprm_transport_and_ci_error_counters_st::rq_num_oos
pseudo_bit_t rq_num_oos[0x00020]
Definition: MT25408_PRM.h:1673
hermonprm_mod_stat_cfg_st::guid_hi_m
pseudo_bit_t guid_hi_m[0x00001]
Definition: MT25408_PRM.h:1372
hermonprm_queue_pair_ee_context_entry_st::reserved47
pseudo_bit_t reserved47[0x00006]
Definition: MT25408_PRM.h:980
hermonprm_query_dev_cap_st::dpdp
pseudo_bit_t dpdp[0x00001]
Definition: MT25408_PRM.h:2158
hermonprm_resize_cq_st
Definition: MT25408_PRM.h:1768
hermonprm_mpt_st::reserved2
pseudo_bit_t reserved2[0x00008]
Definition: MT25408_PRM.h:2498
hermonprm_queue_pair_ee_context_entry_st::reserved36
pseudo_bit_t reserved36[0x00040]
Definition: MT25408_PRM.h:937
hermonprm_uar_st::rd_send_doorbell
struct hermonprm_rd_send_doorbell_st rd_send_doorbell
Definition: MT25408_PRM.h:1907
hermonprm_hermon_prm_st::reserved24
pseudo_bit_t reserved24[0x7ff00]
Definition: MT25408_PRM.h:3255
hermonprm_eq_set_ci_table_st::eq26_set_ci
pseudo_bit_t eq26_set_ci[0x00020]
Definition: MT25408_PRM.h:1119
hermonprm_address_path_st::dmac_31_0
pseudo_bit_t dmac_31_0[0x00020]
Definition: MT25408_PRM.h:329
hermonprm_completion_queue_context_st::cc
pseudo_bit_t cc[0x00001]
Definition: MT25408_PRM.h:2568
hermonprm_ecc_detect_event_data_st::cause_lsb
pseudo_bit_t cause_lsb[0x00001]
Definition: MT25408_PRM.h:3106
hermonprm_vsd_st::vsd_dw25
pseudo_bit_t vsd_dw25[0x00020]
Definition: MT25408_PRM.h:462
hermonprm_queue_pair_ee_context_entry_st::reserved4
pseudo_bit_t reserved4[0x00008]
Definition: MT25408_PRM.h:799
hermonprm_mt25208_type0_st::msi_cap_id
pseudo_bit_t msi_cap_id[0x00008]
Definition: MT25408_PRM.h:2721
hermonprm_queue_pair_ee_context_entry_st::srq
pseudo_bit_t srq[0x00001]
Definition: MT25408_PRM.h:924
hermonprm_hermon_prm_st::resize_cq
struct hermonprm_resize_cq_st resize_cq
Definition: MT25408_PRM.h:3335
hermonprm_mod_stat_cfg_st::port_protocol
pseudo_bit_t port_protocol[0x00008]
Definition: MT25408_PRM.h:1416
hermonprm_mcg_qp_dw_st::blck_lb
pseudo_bit_t blck_lb[0x00001]
Definition: MT25408_PRM.h:993
hermonprm_address_path_st::reserved7
pseudo_bit_t reserved7[0x0000a]
Definition: MT25408_PRM.h:321
hermonprm_query_dev_cap_st::reserved27
pseudo_bit_t reserved27[0x00015]
Definition: MT25408_PRM.h:2142
hermonprm_port_state_change_st::p
pseudo_bit_t p[0x00002]
Definition: MT25408_PRM.h:2925
hermonprm_srq_context_st::mtt_base_addr_l
pseudo_bit_t mtt_base_addr_l[0x0001d]
Definition: MT25408_PRM.h:1503
hermonprm_receive_doorbell_st
Definition: MT25408_PRM.h:1921
hermonprm_mod_stat_cfg_st::log_pg_sz
pseudo_bit_t log_pg_sz[0x00008]
Definition: MT25408_PRM.h:1338
hermonprm_init_port_st::reserved4
pseudo_bit_t reserved4[0x00020]
Definition: MT25408_PRM.h:2024
hermonprm_query_dev_cap_st::log_max_qp
pseudo_bit_t log_max_qp[0x00005]
Definition: MT25408_PRM.h:2051
hermonprm_hcr_completion_event_st::status
pseudo_bit_t status[0x00008]
Definition: MT25408_PRM.h:1711
hermonprm_query_fw_st::clr_int_bar
pseudo_bit_t clr_int_bar[0x00002]
Definition: MT25408_PRM.h:2322
hermonprm_eq_set_ci_table_st::eq61_set_ci
pseudo_bit_t eq61_set_ci[0x00020]
Definition: MT25408_PRM.h:1259
hermonprm_sched_queue_context_st::reserved0
pseudo_bit_t reserved0[0x00006]
Definition: MT25408_PRM.h:3096
hermonprm_query_dev_cap_st::reserved45
pseudo_bit_t reserved45[0x00020]
Definition: MT25408_PRM.h:2262
hermonprm_ud_address_vector_st::rgid_63_32
pseudo_bit_t rgid_63_32[0x00020]
Definition: MT25408_PRM.h:71
hermonprm_eq_set_ci_table_st::eq35_set_ci
pseudo_bit_t eq35_set_ci[0x00020]
Definition: MT25408_PRM.h:1155
hermonprm_vsd_st::vsd_dw23
pseudo_bit_t vsd_dw23[0x00020]
Definition: MT25408_PRM.h:458
hermonprm_mt25208_type0_st::advance_error_capabilities_and_control_register
pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]
Definition: MT25408_PRM.h:2852
hermonprm_multicastparam_st::mc_hash_fn
pseudo_bit_t mc_hash_fn[0x00003]
Definition: MT25408_PRM.h:606
hermonprm_resize_cq_st::log2_page_size
pseudo_bit_t log2_page_size[0x00006]
Definition: MT25408_PRM.h:1783
hermonprm_page_fault_event_data_st::pd
pseudo_bit_t pd[0x00018]
Definition: MT25408_PRM.h:2895
hermonprm_mt25208_type0_st::reserved5
pseudo_bit_t reserved5[0x00020]
Definition: MT25408_PRM.h:2712
hermonprm_mod_stat_cfg_st::reserved22
pseudo_bit_t reserved22[0x00002]
Definition: MT25408_PRM.h:1408
hermonprm_event_queue_entry_st::owner
pseudo_bit_t owner[0x00001]
Definition: MT25408_PRM.h:2971
hermonprm_eq_set_ci_table_st::reserved10
pseudo_bit_t reserved10[0x00020]
Definition: MT25408_PRM.h:1057
hermonprm_mad_ifc_st::grh
pseudo_bit_t grh[10][0x00020]
Definition: MT25408_PRM.h:1837
hermonprm_mod_stat_cfg_st::port_pause_mode_m
pseudo_bit_t port_pause_mode_m[0x00001]
Definition: MT25408_PRM.h:1368
hermonprm_mod_stat_cfg_st::fw_rev_subminor
pseudo_bit_t fw_rev_subminor[0x00010]
Definition: MT25408_PRM.h:1433
hermonprm_pbl_st::mtt_1_l
pseudo_bit_t mtt_1_l[0x00020]
Definition: MT25408_PRM.h:1532
hermonprm_queue_pair_ee_context_entry_st
Definition: MT25408_PRM.h:787
hermonprm_mod_stat_cfg_st::port_pause_mode
pseudo_bit_t port_pause_mode[0x00002]
Definition: MT25408_PRM.h:1366
hermonprm_mod_stat_cfg_st::port_eth_mode_enabled
pseudo_bit_t port_eth_mode_enabled[0x0001f]
Definition: MT25408_PRM.h:1465
hermonprm_query_fw_st::reserved0
pseudo_bit_t reserved0[0x00010]
Definition: MT25408_PRM.h:2296
hermonprm_mad_ifc_st::reserved1
pseudo_bit_t reserved1[0x00020]
Definition: MT25408_PRM.h:1816
hermonprm_scrubbing_event_st::cause_lsb
pseudo_bit_t cause_lsb[0x00001]
Definition: MT25408_PRM.h:3127
hermonprm_eqc_st::reserved8
pseudo_bit_t reserved8[0x00016]
Definition: MT25408_PRM.h:2445
hermonprm_mt25208_type0_st::bar2_h
pseudo_bit_t bar2_h[0x00020]
Definition: MT25408_PRM.h:2698
hermonprm_address_path_st::reserved0
pseudo_bit_t reserved0[0x00016]
Definition: MT25408_PRM.h:272
hermonprm_query_fw_st::fw_seconds
pseudo_bit_t fw_seconds[0x00008]
Definition: MT25408_PRM.h:2307
hermonprm_mt25208_type0_st::data
pseudo_bit_t data[0x00008]
Definition: MT25408_PRM.h:2751
hermonprm_query_dev_cap_st::reserved24
pseudo_bit_t reserved24[0x00003]
Definition: MT25408_PRM.h:2128
hermonprm_wqe_segment_bind_st
Definition: MT25408_PRM.h:190
hermonprm_completion_queue_context_st::reserved11
pseudo_bit_t reserved11[0x00008]
Definition: MT25408_PRM.h:2605
hermonprm_wqe_segment_ctrl_mlx_st
Definition: MT25408_PRM.h:732
hermonprm_query_dev_cap_st::reserved7
pseudo_bit_t reserved7[0x00004]
Definition: MT25408_PRM.h:2071
hermonprm_address_path_st::sv
pseudo_bit_t sv[0x00001]
Definition: MT25408_PRM.h:273
hermonprm_query_fw_st::reserved2
pseudo_bit_t reserved2[0x00001]
Definition: MT25408_PRM.h:2304
hermonprm_resize_cq_st::mtt_base_addr_h
pseudo_bit_t mtt_base_addr_h[0x00008]
Definition: MT25408_PRM.h:1781
hermonprm_vsd_st::vsd_dw22
pseudo_bit_t vsd_dw22[0x00020]
Definition: MT25408_PRM.h:456
hermonprm_eqc_st::producer_counter
pseudo_bit_t producer_counter[0x00018]
Definition: MT25408_PRM.h:2462
hermonprm_local_invalidate_segment_st::reserved2
pseudo_bit_t reserved2[0x000a0]
Definition: MT25408_PRM.h:128
hermonprm_configuration_registers_st::reserved1
pseudo_bit_t reserved1[0x3fcb20]
Definition: MT25408_PRM.h:1280
hermonprm_mad_ifc_input_modifier_st::port_number
pseudo_bit_t port_number[0x00008]
Definition: MT25408_PRM.h:1798
hermonprm_transport_and_ci_error_counters_st::rq_num_lle
pseudo_bit_t rq_num_lle[0x00020]
Definition: MT25408_PRM.h:1562
hermonprm_qp_ee_state_transitions_st::qpc_eec_data
struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data
Definition: MT25408_PRM.h:2985
hermonprm_wqe_segment_data_ptr_st::local_address_h
pseudo_bit_t local_address_h[0x00020]
Definition: MT25408_PRM.h:114
hermonprm_receive_doorbell_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:1924
hermonprm_query_dev_cap_st::stat_rate_support
pseudo_bit_t stat_rate_support[0x00010]
Definition: MT25408_PRM.h:2132
hermonprm_qpcbaseaddr_st::rdmardc_base_addr_l
pseudo_bit_t rdmardc_base_addr_l[0x0001b]
Definition: MT25408_PRM.h:682
hermonprm_vsd_st::vsd_dw31
pseudo_bit_t vsd_dw31[0x00020]
Definition: MT25408_PRM.h:474
hermonprm_query_dev_cap_st::checksum
pseudo_bit_t checksum[0x00001]
Definition: MT25408_PRM.h:2153
hermonprm_vsd_st::vsd_dw7
pseudo_bit_t vsd_dw7[0x00020]
Definition: MT25408_PRM.h:426
hermonprm_eqc_st::st
pseudo_bit_t st[0x00004]
Definition: MT25408_PRM.h:2416
hermonprm_performance_monitors_st::e1
pseudo_bit_t e1[0x00001]
Definition: MT25408_PRM.h:702
hermonprm_transport_and_ci_error_counters_st::rq_num_rae
pseudo_bit_t rq_num_rae[0x00020]
Definition: MT25408_PRM.h:1630
hermonprm_address_path_st::max_stat_rate
pseudo_bit_t max_stat_rate[0x00004]
Definition: MT25408_PRM.h:283
hermonprm_completion_queue_entry_st::byte_cnt
pseudo_bit_t byte_cnt[0x00020]
Definition: MT25408_PRM.h:3035
hermonprm_mt25208_type0_st::bar0_ctrl
pseudo_bit_t bar0_ctrl[0x00004]
Definition: MT25408_PRM.h:2682
hermonprm_srq_context_st::log_srq_size
pseudo_bit_t log_srq_size[0x00004]
Definition: MT25408_PRM.h:1478
hermonprm_hermon_prm_st::qp_ee_event
struct hermonprm_qp_ee_event_st qp_ee_event
Definition: MT25408_PRM.h:3197
hermonprm_queue_pair_ee_context_entry_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:788
hermonprm_mod_stat_cfg_st::reserved0
pseudo_bit_t reserved0[0x00005]
Definition: MT25408_PRM.h:1340
hermonprm_query_dev_cap_st::num_rsvd_uars
pseudo_bit_t num_rsvd_uars[0x00004]
Definition: MT25408_PRM.h:2178
hermonprm_mcg_hdr_st::reserved2
pseudo_bit_t reserved2[0x00020]
Definition: MT25408_PRM.h:3075
hermonprm_query_dev_cap_st::pkv
pseudo_bit_t pkv[0x00001]
Definition: MT25408_PRM.h:2154
hermonprm_rd_send_doorbell_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:388
hermonprm_wqe_segment_ctrl_send_st::reserved1
pseudo_bit_t reserved1[0x00019]
Definition: MT25408_PRM.h:253
hermonprm_query_dev_cap_st::reserved0
pseudo_bit_t reserved0[0x00080]
Definition: MT25408_PRM.h:2049
hermonprm_hca_command_register_st
Definition: MT25408_PRM.h:335
hermonprm_query_dev_cap_st::aux_entry_sz
pseudo_bit_t aux_entry_sz[0x00010]
Definition: MT25408_PRM.h:2233
hermonprm_eq_set_ci_table_st::eq40_set_ci
pseudo_bit_t eq40_set_ci[0x00020]
Definition: MT25408_PRM.h:1175
hermonprm_transport_and_ci_error_counters_st::rq_num_roe
pseudo_bit_t rq_num_roe[0x00020]
Definition: MT25408_PRM.h:1640
hermonprm_hermon_prm_st::reserved13
pseudo_bit_t reserved13[0x7f840]
Definition: MT25408_PRM.h:3211
hermonprm_tptparams_st::reserved2
pseudo_bit_t reserved2[0x00020]
Definition: MT25408_PRM.h:560
hermonprm_mod_stat_cfg_st::qdr_rx_options_m
pseudo_bit_t qdr_rx_options_m[0x00001]
Definition: MT25408_PRM.h:1353
hermonprm_completion_queue_context_st::reserved5
pseudo_bit_t reserved5[0x00014]
Definition: MT25408_PRM.h:2580
hermonprm_hermon_prm_st::mtt
struct hermonprm_mtt_st mtt
Definition: MT25408_PRM.h:3225
hermonprm_hermon_prm_st::reserved43
pseudo_bit_t reserved43[0x7ffe0]
Definition: MT25408_PRM.h:3321
hermonprm_eq_set_ci_table_st::eq39_set_ci
pseudo_bit_t eq39_set_ci[0x00020]
Definition: MT25408_PRM.h:1171
hermonprm_eq_set_ci_table_st::eq11_set_ci
pseudo_bit_t eq11_set_ci[0x00020]
Definition: MT25408_PRM.h:1059
hermonprm_eq_set_ci_table_st::reserved17
pseudo_bit_t reserved17[0x00020]
Definition: MT25408_PRM.h:1085
hermonprm_query_dev_cap_st::eqc_entry_sz
pseudo_bit_t eqc_entry_sz[0x00010]
Definition: MT25408_PRM.h:2237
hermonprm_mt25208_type0_st::pm_cap_id
pseudo_bit_t pm_cap_id[0x00008]
Definition: MT25408_PRM.h:2738
hermonprm_fast_registration_segment_st::reg_len_l
pseudo_bit_t reg_len_l[0x00020]
Definition: MT25408_PRM.h:158
hermonprm_query_dev_cap_st::reserved28
pseudo_bit_t reserved28[0x00002]
Definition: MT25408_PRM.h:2168
hermonprm_queue_pair_ee_context_entry_st::log_sq_size
pseudo_bit_t log_sq_size[0x00004]
Definition: MT25408_PRM.h:822
hermonprm_query_debug_msg_st::phy_addr_l
pseudo_bit_t phy_addr_l[0x00014]
Definition: MT25408_PRM.h:1852
hermonprm_mpt_st::reserved1
pseudo_bit_t reserved1[0x00001]
Definition: MT25408_PRM.h:2496
hermonprm_fast_registration_segment_st::zb
pseudo_bit_t zb[0x00001]
Definition: MT25408_PRM.h:149
hermonprm_fast_registration_segment_st::a
pseudo_bit_t a[0x00001]
Definition: MT25408_PRM.h:140
hermonprm_completion_queue_context_st::log2_page_size
pseudo_bit_t log2_page_size[0x00006]
Definition: MT25408_PRM.h:2597
hermonprm_init_hca_st::reserved10
pseudo_bit_t reserved10[0x00600]
Definition: MT25408_PRM.h:2408
hermonprm_vsd_st::vsd_dw42
pseudo_bit_t vsd_dw42[0x00020]
Definition: MT25408_PRM.h:496
hermonprm_mcg_qp_dw_st::qpn
pseudo_bit_t qpn[0x00018]
Definition: MT25408_PRM.h:991
hermonprm_queue_pair_ee_context_entry_st::remote_id
pseudo_bit_t remote_id[0x00018]
Definition: MT25408_PRM.h:976
hermonprm_vsd_st::vsd_dw18
pseudo_bit_t vsd_dw18[0x00020]
Definition: MT25408_PRM.h:448
hermonprm_mpt_st::len_l
pseudo_bit_t len_l[0x00020]
Definition: MT25408_PRM.h:2523
hermonprm_eq_set_ci_table_st::eq63_set_ci
pseudo_bit_t eq63_set_ci[0x00020]
Definition: MT25408_PRM.h:1267
hermonprm_query_fw_st::fw_year
pseudo_bit_t fw_year[0x00010]
Definition: MT25408_PRM.h:2313
hermonprm_query_dev_cap_st::d_mpt_entry_sz
pseudo_bit_t d_mpt_entry_sz[0x00010]
Definition: MT25408_PRM.h:2245
hermonprm_hermon_prm_st::transport_and_ci_error_counters
struct hermonprm_transport_and_ci_error_counters_st transport_and_ci_error_counters
Definition: MT25408_PRM.h:3347
hermonprm_mod_stat_cfg_st::port_en_m
pseudo_bit_t port_en_m[0x00001]
Definition: MT25408_PRM.h:1364
hermonprm_hermon_prm_st::configuration_registers
struct hermonprm_configuration_registers_st configuration_registers
Definition: MT25408_PRM.h:3389
hermonprm_eq_set_ci_table_st::reserved58
pseudo_bit_t reserved58[0x00020]
Definition: MT25408_PRM.h:1249
hermonprm_page_fault_event_data_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:2896
hermonprm_ecc_detect_event_data_st::err_ca
pseudo_bit_t err_ca[0x00010]
Definition: MT25408_PRM.h:3118
hermonprm_resize_cq_st::reserved10
pseudo_bit_t reserved10[0x00100]
Definition: MT25408_PRM.h:1791
hermonprm_eq_set_ci_table_st::eq41_set_ci
pseudo_bit_t eq41_set_ci[0x00020]
Definition: MT25408_PRM.h:1179
hermonprm_mpt_st::mem_key
pseudo_bit_t mem_key[0x00020]
Definition: MT25408_PRM.h:2505
hermonprm_query_dev_cap_st::log_max_mrw_sz
pseudo_bit_t log_max_mrw_sz[0x00007]
Definition: MT25408_PRM.h:2092
hermonprm_hermon_prm_st::qpcbaseaddr
struct hermonprm_qpcbaseaddr_st qpcbaseaddr
Definition: MT25408_PRM.h:3245
hermonprm_queue_pair_ee_context_entry_st::ack_req_freq
pseudo_bit_t ack_req_freq[0x00004]
Definition: MT25408_PRM.h:867
hermonprm_udavtable_memory_parameters_st::reserved0
pseudo_bit_t reserved0[0x00005]
Definition: MT25408_PRM.h:2357
hermonprm_wqe_segment_data_inline_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:100
hermonprm_uar_st::reserved1
pseudo_bit_t reserved1[0x03ec0]
Definition: MT25408_PRM.h:1915
hermonprm_query_dev_cap_st::log2_rsvd_cqs
pseudo_bit_t log2_rsvd_cqs[0x00004]
Definition: MT25408_PRM.h:2069
hermonprm_wqe_segment_bind_st::a
pseudo_bit_t a[0x00001]
Definition: MT25408_PRM.h:195
hermonprm_completion_queue_entry_st::g
pseudo_bit_t g[0x00001]
Definition: MT25408_PRM.h:3019
pseudo_bit_t
unsigned char pseudo_bit_t
Datatype used to represent a bit in the pseudo-structures.
Definition: nx_bitops.h:37
hermonprm_query_debug_msg_st::buff5_size
pseudo_bit_t buff5_size[0x00020]
Definition: MT25408_PRM.h:1892
hermonprm_performance_monitor_event_st::monitor_number
pseudo_bit_t monitor_number[0x00008]
Definition: MT25408_PRM.h:2865
hermonprm_hermon_prm_st::pbl
struct hermonprm_pbl_st pbl
Definition: MT25408_PRM.h:3359
hermonprm_fast_registration_segment_st::reserved1
pseudo_bit_t reserved1[0x00002]
Definition: MT25408_PRM.h:148
hermonprm_queue_pair_ee_context_entry_st::srcd
pseudo_bit_t srcd[0x00010]
Definition: MT25408_PRM.h:907
hermonprm_transport_and_ci_error_counters_st::sq_num_lle
pseudo_bit_t sq_num_lle[0x00020]
Definition: MT25408_PRM.h:1564
hermonprm_query_fw_st::cmd_interface_rev
pseudo_bit_t cmd_interface_rev[0x00010]
Definition: MT25408_PRM.h:2295
hermonprm_queue_pair_ee_context_entry_st::reserved8
pseudo_bit_t reserved8[0x00001]
Definition: MT25408_PRM.h:823
hermonprm_queue_pair_ee_context_entry_st::reserved17
pseudo_bit_t reserved17[0x00002]
Definition: MT25408_PRM.h:864
hermonprm_performance_monitors_st::e2
pseudo_bit_t e2[0x00001]
Definition: MT25408_PRM.h:703
hermonprm_query_dev_cap_st::fexch_base_qp_23_16
pseudo_bit_t fexch_base_qp_23_16[0x00008]
Definition: MT25408_PRM.h:2201
hermonprm_hermon_prm_st::reserved25
pseudo_bit_t reserved25[0x7ff00]
Definition: MT25408_PRM.h:3259
hermonprm_mod_stat_cfg_st::inbuf_ind_en
pseudo_bit_t inbuf_ind_en[0x00003]
Definition: MT25408_PRM.h:1401
hermonprm_vsd_st::vsd_dw29
pseudo_bit_t vsd_dw29[0x00020]
Definition: MT25408_PRM.h:470
hermonprm_send_doorbell_st::reserved1
pseudo_bit_t reserved1[0x00002]
Definition: MT25408_PRM.h:87
hermonprm_mad_ifc_st
Definition: MT25408_PRM.h:1809
hermonprm_wqe_segment_atomic_st::compare_h
pseudo_bit_t compare_h[0x00020]
Definition: MT25408_PRM.h:169
hermonprm_query_dev_cap_st::reserved21
pseudo_bit_t reserved21[0x00001]
Definition: MT25408_PRM.h:2120
hermonprm_performance_monitors_st::i0
pseudo_bit_t i0[0x00001]
Definition: MT25408_PRM.h:709
hermonprm_eq_set_ci_table_st::eq14_set_ci
pseudo_bit_t eq14_set_ci[0x00020]
Definition: MT25408_PRM.h:1071
hermonprm_wqe_segment_data_inline_st::data
pseudo_bit_t data[0x00018]
Definition: MT25408_PRM.h:99
hermonprm_multicastparam_st::reserved1
pseudo_bit_t reserved1[0x0000b]
Definition: MT25408_PRM.h:596
hermonprm_completion_queue_context_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:2555
hermonprm_performance_monitors_st::r1
pseudo_bit_t r1[0x00001]
Definition: MT25408_PRM.h:706
hermonprm_eq_set_ci_table_st::eq36_set_ci
pseudo_bit_t eq36_set_ci[0x00020]
Definition: MT25408_PRM.h:1159
hermonprm_query_dev_cap_st::reserved2
pseudo_bit_t reserved2[0x00004]
Definition: MT25408_PRM.h:2055
hermonprm_eq_set_ci_table_st::eq58_set_ci
pseudo_bit_t eq58_set_ci[0x00020]
Definition: MT25408_PRM.h:1247
hermonprm_queue_pair_ee_context_entry_st::pd
pseudo_bit_t pd[0x00018]
Definition: MT25408_PRM.h:814
hermonprm_qpcbaseaddr_st::altc_base_addr_l
pseudo_bit_t altc_base_addr_l[0x00020]
Definition: MT25408_PRM.h:654
hermonprm_scrubbing_event_st
Definition: MT25408_PRM.h:3124
hermonprm_completion_queue_entry_st::is
pseudo_bit_t is[0x00001]
Definition: MT25408_PRM.h:3049
hermonprm_vsd_st::vsd_dw2
pseudo_bit_t vsd_dw2[0x00020]
Definition: MT25408_PRM.h:416
hermonprm_mod_stat_cfg_st::reserved41
pseudo_bit_t reserved41[0x00001]
Definition: MT25408_PRM.h:1469
hermonprm_wqe_segment_bind_st::length_h
pseudo_bit_t length_h[0x00020]
Definition: MT25408_PRM.h:212
hermonprm_mod_stat_cfg_st::reserved5
pseudo_bit_t reserved5[0x00003]
Definition: MT25408_PRM.h:1355
hermonprm_query_dev_cap_st::fcoe
pseudo_bit_t fcoe[0x00001]
Definition: MT25408_PRM.h:2157
hermonprm_mcg_hdr_st::gid0
pseudo_bit_t gid0[0x00020]
Definition: MT25408_PRM.h:3085
hermonprm_eqc_st::reserved6
pseudo_bit_t reserved6[0x00018]
Definition: MT25408_PRM.h:2437
hermonprm_query_dev_cap_st::reserved9
pseudo_bit_t reserved9[0x00004]
Definition: MT25408_PRM.h:2078
hermonprm_hermon_prm_st::performance_monitors
struct hermonprm_performance_monitors_st performance_monitors
Definition: MT25408_PRM.h:3233
hermonprm_init_port_st::reserved3
pseudo_bit_t reserved3[0x00010]
Definition: MT25408_PRM.h:2022
hermonprm_qpcbaseaddr_st::reserved7
pseudo_bit_t reserved7[0x00002]
Definition: MT25408_PRM.h:681
hermonprm_mpt_st::lr
pseudo_bit_t lr[0x00001]
Definition: MT25408_PRM.h:2488
hermonprm_queue_pair_ee_context_entry_st::pm_state
pseudo_bit_t pm_state[0x00002]
Definition: MT25408_PRM.h:791
hermonprm_vsd_st::vsd_dw16
pseudo_bit_t vsd_dw16[0x00020]
Definition: MT25408_PRM.h:444
hermonprm_init_hca_st::version
pseudo_bit_t version[0x00008]
Definition: MT25408_PRM.h:2367
hermonprm_mod_stat_cfg_st::outer_vlan_en
pseudo_bit_t outer_vlan_en[0x00001]
Definition: MT25408_PRM.h:1453
hermonprm_init_hca_st::reserved0
pseudo_bit_t reserved0[0x00018]
Definition: MT25408_PRM.h:2366
hermonprm_eq_set_ci_table_st::reserved2
pseudo_bit_t reserved2[0x00020]
Definition: MT25408_PRM.h:1025
hermonprm_mt25208_type0_st::pm_status_control
pseudo_bit_t pm_status_control[0x00010]
Definition: MT25408_PRM.h:2749
hermonprm_wqe_segment_ctrl_send_st::so
pseudo_bit_t so[0x00001]
Definition: MT25408_PRM.h:261
hermonprm_wqe_segment_ctrl_mlx_st::slr
pseudo_bit_t slr[0x00001]
Definition: MT25408_PRM.h:747
hermonprm_mpt_st::block_mode
pseudo_bit_t block_mode[0x00001]
Definition: MT25408_PRM.h:2532
hermonprm_eq_set_ci_table_st::eq38_set_ci
pseudo_bit_t eq38_set_ci[0x00020]
Definition: MT25408_PRM.h:1167
hermonprm_address_path_st::pkey_index
pseudo_bit_t pkey_index[0x00007]
Definition: MT25408_PRM.h:271
hermonprm_mod_stat_cfg_st::reserved16
pseudo_bit_t reserved16[0x00003]
Definition: MT25408_PRM.h:1394
hermonprm_mgmqp_st::qi
pseudo_bit_t qi[0x00001]
Definition: MT25408_PRM.h:405
hermonprm_receive_doorbell_st::srq
pseudo_bit_t srq[0x00001]
Definition: MT25408_PRM.h:1927
hermonprm_eqc_st
Definition: MT25408_PRM.h:2414
hermonprm_multicastparam_st::log_mc_table_sz
pseudo_bit_t log_mc_table_sz[0x00005]
Definition: MT25408_PRM.h:604
hermonprm_wqe_segment_atomic_st
Definition: MT25408_PRM.h:164
hermonprm_hermon_prm_st::reserved44
pseudo_bit_t reserved44[0x7f800]
Definition: MT25408_PRM.h:3325
hermonprm_mod_stat_cfg_st::reserved40
pseudo_bit_t reserved40[0x00001]
Definition: MT25408_PRM.h:1463
hermonprm_port_state_change_st::reserved1
pseudo_bit_t reserved1[0x0001c]
Definition: MT25408_PRM.h:2924
hermonprm_hermon_prm_st::reserved31
pseudo_bit_t reserved31[0x7f800]
Definition: MT25408_PRM.h:3273
hermonprm_hca_command_register_st::opcode
pseudo_bit_t opcode[0x0000c]
Definition: MT25408_PRM.h:349
hermonprm_wqe_segment_remote_address_st::rkey
pseudo_bit_t rkey[0x00020]
Definition: MT25408_PRM.h:182
hermonprm_qp_ee_state_transitions_st
Definition: MT25408_PRM.h:2980
hermonprm_mt25208_type0_st::uncorrectable_severity_mask_register
pseudo_bit_t uncorrectable_severity_mask_register[0x00020]
Definition: MT25408_PRM.h:2828
hermonprm_wqe_segment_ctrl_mlx_st::reserved0
pseudo_bit_t reserved0[0x0001a]
Definition: MT25408_PRM.h:734
hermonprm_configuration_registers_st
Definition: MT25408_PRM.h:1275
hermonprm_query_dev_cap_st::log_max_mcg
pseudo_bit_t log_max_mcg[0x00008]
Definition: MT25408_PRM.h:2205
hermonprm_hermon_prm_st::query_fw
struct hermonprm_query_fw_st query_fw
Definition: MT25408_PRM.h:3271
hermonprm_transport_and_ci_error_counters_st::sq_num_rabrte
pseudo_bit_t sq_num_rabrte[0x00020]
Definition: MT25408_PRM.h:1661
hermonprm_tptparams_st::mtt_base_addr_l
pseudo_bit_t mtt_base_addr_l[0x00020]
Definition: MT25408_PRM.h:566
hermonprm_queue_pair_ee_context_entry_st::sq_wqe_counter
pseudo_bit_t sq_wqe_counter[0x00010]
Definition: MT25408_PRM.h:930
hermonprm_hermon_prm_st::init_hca
struct hermonprm_init_hca_st init_hca
Definition: MT25408_PRM.h:3241
hermonprm_wqe_segment_ctrl_mlx_st::rlid
pseudo_bit_t rlid[0x00010]
Definition: MT25408_PRM.h:752
hermonprm_transport_and_ci_error_counters_st::reserved10
pseudo_bit_t reserved10[0x00020]
Definition: MT25408_PRM.h:1687
hermonprm_query_dev_cap_st::vep_uc_steering
pseudo_bit_t vep_uc_steering[0x00001]
Definition: MT25408_PRM.h:2140
hermonprm_completion_queue_context_st::reserved10
pseudo_bit_t reserved10[0x00003]
Definition: MT25408_PRM.h:2600
hermonprm_uar_st::reserved0
pseudo_bit_t reserved0[0x00040]
Definition: MT25408_PRM.h:1911
hermonprm_virtual_physical_mapping_st
Definition: MT25408_PRM.h:1321
hermonprm_hermon_prm_st::cq_arm_db_record
struct hermonprm_cq_arm_db_record_st cq_arm_db_record
Definition: MT25408_PRM.h:3379
hermonprm_transport_and_ci_error_counters_st::sq_num_oos
pseudo_bit_t sq_num_oos[0x00020]
Definition: MT25408_PRM.h:1675
hermonprm_queue_pair_ee_context_entry_st::rmsn
pseudo_bit_t rmsn[0x00018]
Definition: MT25408_PRM.h:927
hermonprm_queue_pair_ee_context_entry_st::num_rmc_peers
pseudo_bit_t num_rmc_peers[0x00008]
Definition: MT25408_PRM.h:953
hermonprm_queue_pair_ee_context_entry_st::rnr_retry
pseudo_bit_t rnr_retry[0x00003]
Definition: MT25408_PRM.h:862
hermonprm_eqc_st::intr
pseudo_bit_t intr[0x0000a]
Definition: MT25408_PRM.h:2444
hermonprm_hermon_prm_st::reserved20
pseudo_bit_t reserved20[0xfff20]
Definition: MT25408_PRM.h:3239
hermonprm_hermon_prm_st::mgmqp
struct hermonprm_mgmqp_st mgmqp
Definition: MT25408_PRM.h:3319
hermonprm_query_fw_st::fw_rev_major
pseudo_bit_t fw_rev_major[0x00010]
Definition: MT25408_PRM.h:2289
hermonprm_query_dev_cap_st::max_sg_rq
pseudo_bit_t max_sg_rq[0x00008]
Definition: MT25408_PRM.h:2195
hermonprm_eqc_st::reserved3
pseudo_bit_t reserved3[0x00020]
Definition: MT25408_PRM.h:2431
hermonprm_scrubbing_event_st::err_rmw
pseudo_bit_t err_rmw[0x00001]
Definition: MT25408_PRM.h:3133
hermonprm_completion_queue_error_st::syndrome
pseudo_bit_t syndrome[0x00008]
Definition: MT25408_PRM.h:2940
hermonprm_vsd_st::vsd_dw17
pseudo_bit_t vsd_dw17[0x00020]
Definition: MT25408_PRM.h:446
hermonprm_performance_monitors_st::ev_cnt2
pseudo_bit_t ev_cnt2[0x00005]
Definition: MT25408_PRM.h:719
hermonprm_eq_set_ci_table_st::eq10_set_ci
pseudo_bit_t eq10_set_ci[0x00020]
Definition: MT25408_PRM.h:1055
hermonprm_hermon_prm_st::queue_pair_ee_context_entry
struct hermonprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry
Definition: MT25408_PRM.h:3209
hermonprm_fast_registration_segment_st::mem_key
pseudo_bit_t mem_key[0x00020]
Definition: MT25408_PRM.h:144
hermonprm_queue_pair_ee_context_entry_st::reserved14
pseudo_bit_t reserved14[0x00001]
Definition: MT25408_PRM.h:854
hermonprm_mod_stat_cfg_st::reserved33
pseudo_bit_t reserved33[0x0000f]
Definition: MT25408_PRM.h:1441
hermonprm_event_queue_entry_st::reserved3
pseudo_bit_t reserved3[0x00018]
Definition: MT25408_PRM.h:2974
hermonprm_scrubbing_event_st::reserved2
pseudo_bit_t reserved2[0x00002]
Definition: MT25408_PRM.h:3132
hermonprm_completion_with_error_st::reserved2
pseudo_bit_t reserved2[0x00001]
Definition: MT25408_PRM.h:1759
hermonprm_completion_queue_context_st::reserved3
pseudo_bit_t reserved3[0x00020]
Definition: MT25408_PRM.h:2576
hermonprm_query_dev_cap_st::reserved34
pseudo_bit_t reserved34[0x0000a]
Definition: MT25408_PRM.h:2187
hermonprm_query_dev_cap_st::log_max_bf_pages
pseudo_bit_t log_max_bf_pages[0x00006]
Definition: MT25408_PRM.h:2182
hermonprm_cq_cmd_doorbell_st::cq_param
pseudo_bit_t cq_param[0x00020]
Definition: MT25408_PRM.h:381
hermonprm_queue_pair_ee_context_entry_st::log_rq_stride
pseudo_bit_t log_rq_stride[0x00003]
Definition: MT25408_PRM.h:824
hermonprm_mcg_hdr_st::protocol
pseudo_bit_t protocol[0x00002]
Definition: MT25408_PRM.h:3073
hermonprm_wqe_segment_bind_st::rw
pseudo_bit_t rw[0x00001]
Definition: MT25408_PRM.h:193
hermonprm_query_fw_st::fw_pages
pseudo_bit_t fw_pages[0x00010]
Definition: MT25408_PRM.h:2290
hermonprm_eq_set_ci_table_st::eq54_set_ci
pseudo_bit_t eq54_set_ci[0x00020]
Definition: MT25408_PRM.h:1231
hermonprm_fast_registration_segment_st::lr
pseudo_bit_t lr[0x00001]
Definition: MT25408_PRM.h:136
hermonprm_wqe_segment_ctrl_send_st::ip
pseudo_bit_t ip[0x00001]
Definition: MT25408_PRM.h:258
hermonprm_queue_pair_ee_context_entry_st::mtu
pseudo_bit_t mtu[0x00003]
Definition: MT25408_PRM.h:830
hermonprm_mt25208_type0_st::device_status
pseudo_bit_t device_status[0x00010]
Definition: MT25408_PRM.h:2784
hermonprm_vsd_st::vsd_dw51
pseudo_bit_t vsd_dw51[0x00020]
Definition: MT25408_PRM.h:514
hermonprm_mad_ifc_input_modifier_st::reserved0
pseudo_bit_t reserved0[0x00007]
Definition: MT25408_PRM.h:1801
hermonprm_send_wqe_segment_st::wqe_segment_ctrl_send
struct hermonprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send
Definition: MT25408_PRM.h:759
hermonprm_send_doorbell_st::reserved0
pseudo_bit_t reserved0[0x00002]
Definition: MT25408_PRM.h:82
hermonprm_queue_pair_ee_context_entry_st::reserved22
pseudo_bit_t reserved22[0x00040]
Definition: MT25408_PRM.h:877
hermonprm_mt25208_type0_st::correctable_error_status_register
pseudo_bit_t correctable_error_status_register[0x00020]
Definition: MT25408_PRM.h:2840
hermonprm_ecc_detect_event_data_st::cause_msb
pseudo_bit_t cause_msb[0x00001]
Definition: MT25408_PRM.h:3108
hermonprm_query_dev_cap_st::reserved17
pseudo_bit_t reserved17[0x0000a]
Definition: MT25408_PRM.h:2103
hermonprm_mt25208_type0_st::bar1_h
pseudo_bit_t bar1_h[0x00020]
Definition: MT25408_PRM.h:2692
hermonprm_query_dev_cap_st::num_rsvd_pds
pseudo_bit_t num_rsvd_pds[0x00004]
Definition: MT25408_PRM.h:2220
hermonprm_gpio_event_data_st::gpio_event_lo
pseudo_bit_t gpio_event_lo[0x00020]
Definition: MT25408_PRM.h:2639
hermonprm_hermon_prm_st::reserved55
pseudo_bit_t reserved55[0x7f800]
Definition: MT25408_PRM.h:3369
hermonprm_resize_cq_st::reserved2
pseudo_bit_t reserved2[0x00014]
Definition: MT25408_PRM.h:1773
hermonprm_mod_stat_cfg_st::reserved27
pseudo_bit_t reserved27[0x00008]
Definition: MT25408_PRM.h:1421
hermonprm_queue_pair_ee_context_entry_st::mkey_rmp
pseudo_bit_t mkey_rmp[0x00001]
Definition: MT25408_PRM.h:950
hermonprm_mcg_hdr_st::reserved1
pseudo_bit_t reserved1[0x00005]
Definition: MT25408_PRM.h:3072
hermonprm_hcr_completion_event_st::reserved3
pseudo_bit_t reserved3[0x00020]
Definition: MT25408_PRM.h:1718
hermonprm_vsd_st::vsd_dw13
pseudo_bit_t vsd_dw13[0x00020]
Definition: MT25408_PRM.h:438
hermonprm_mgm_entry_st::mgmqp_7
struct hermonprm_mgmqp_st mgmqp_7
Definition: MT25408_PRM.h:1990
hermonprm_qpcbaseaddr_st::reserved0
pseudo_bit_t reserved0[0x00080]
Definition: MT25408_PRM.h:619
hermonprm_completion_queue_context_st::page_offset
pseudo_bit_t page_offset[0x00007]
Definition: MT25408_PRM.h:2579
hermonprm_performance_monitors_st::f1
pseudo_bit_t f1[0x00001]
Definition: MT25408_PRM.h:714
hermonprm_query_dev_cap_st::log_max_cq
pseudo_bit_t log_max_cq[0x00005]
Definition: MT25408_PRM.h:2067
hermonprm_clr_int_st::clr_int_l
pseudo_bit_t clr_int_l[0x00020]
Definition: MT25408_PRM.h:1006
hermonprm_mod_stat_cfg_st::port_eth_mod_m
pseudo_bit_t port_eth_mod_m[0x00001]
Definition: MT25408_PRM.h:1466
hermonprm_address_path_st::vlan_index
pseudo_bit_t vlan_index[0x00007]
Definition: MT25408_PRM.h:325
hermonprm_mod_stat_cfg_st::log_pg_sz_m
pseudo_bit_t log_pg_sz_m[0x00001]
Definition: MT25408_PRM.h:1339
hermonprm_receive_doorbell_st::qpn
pseudo_bit_t qpn[0x00018]
Definition: MT25408_PRM.h:1929
hermonprm_eq_set_ci_table_st::reserved37
pseudo_bit_t reserved37[0x00020]
Definition: MT25408_PRM.h:1165
hermonprm_address_path_st::sp
pseudo_bit_t sp[0x00001]
Definition: MT25408_PRM.h:316
hermonprm_vsd_st::vsd_dw55
pseudo_bit_t vsd_dw55[0x00020]
Definition: MT25408_PRM.h:522
hermonprm_query_dev_cap_st::rcm
pseudo_bit_t rcm[0x00001]
Definition: MT25408_PRM.h:2149
hermonprm_mt25208_type0_st::reserved13
pseudo_bit_t reserved13[0x006a0]
Definition: MT25408_PRM.h:2856
hermonprm_transport_and_ci_error_counters_st::reserved9
pseudo_bit_t reserved9[0x00020]
Definition: MT25408_PRM.h:1679
hermonprm_hermon_prm_st::reserved38
pseudo_bit_t reserved38[0x7ff80]
Definition: MT25408_PRM.h:3301
hermonprm_completion_with_error_st::reserved3
pseudo_bit_t reserved3[0x00018]
Definition: MT25408_PRM.h:1762
hermonprm_eq_set_ci_table_st::eq24_set_ci
pseudo_bit_t eq24_set_ci[0x00020]
Definition: MT25408_PRM.h:1111
hermonprm_address_path_st::sched_queue
pseudo_bit_t sched_queue[0x00008]
Definition: MT25408_PRM.h:322
hermonprm_query_dev_cap_st::reserved18
pseudo_bit_t reserved18[0x0001a]
Definition: MT25408_PRM.h:2106
hermonprm_hcr_completion_event_st::reserved0
pseudo_bit_t reserved0[0x00010]
Definition: MT25408_PRM.h:1707
hermonprm_query_dev_cap_st::reserved3
pseudo_bit_t reserved3[0x00004]
Definition: MT25408_PRM.h:2060
hermonprm_mt25208_type0_st
Definition: MT25408_PRM.h:2664
hermonprm_uar_st
Definition: MT25408_PRM.h:1906
hermonprm_set_ib_st::system_image_guid_l
pseudo_bit_t system_image_guid_l[0x00020]
Definition: MT25408_PRM.h:1947
hermonprm_resize_cq_st::log_cq_size
pseudo_bit_t log_cq_size[0x00005]
Definition: MT25408_PRM.h:1776
hermonprm_hermon_prm_st::qp_db_record
struct hermonprm_qp_db_record_st qp_db_record
Definition: MT25408_PRM.h:3383
hermonprm_queue_pair_ee_context_entry_st::reserved5
pseudo_bit_t reserved5[0x00008]
Definition: MT25408_PRM.h:815
hermonprm_tptparams_st::cmpt_base_adr_h
pseudo_bit_t cmpt_base_adr_h[0x00020]
Definition: MT25408_PRM.h:570
hermonprm_query_dev_cap_st::mtt_entry_sz
pseudo_bit_t mtt_entry_sz[0x00010]
Definition: MT25408_PRM.h:2247
hermonprm_eq_set_ci_table_st::reserved39
pseudo_bit_t reserved39[0x00020]
Definition: MT25408_PRM.h:1173
hermonprm_transport_and_ci_error_counters_st::sq_num_ieecse
pseudo_bit_t sq_num_ieecse[0x00020]
Definition: MT25408_PRM.h:1669
hermonprm_mod_stat_cfg_st::guid_hi
pseudo_bit_t guid_hi[0x00020]
Definition: MT25408_PRM.h:1374
hermonprm_mtt_st::ptag_l
pseudo_bit_t ptag_l[0x0001d]
Definition: MT25408_PRM.h:2478
hermonprm_mgm_entry_st::next_gid_index
pseudo_bit_t next_gid_index[0x0001a]
Definition: MT25408_PRM.h:1958
hermonprm_qpcbaseaddr_st::log_num_of_eq
pseudo_bit_t log_num_of_eq[0x00005]
Definition: MT25408_PRM.h:670
hermonprm_query_dev_cap_st::win_type
pseudo_bit_t win_type[0x00001]
Definition: MT25408_PRM.h:2251
hermonprm_performance_monitors_st::reserved5
pseudo_bit_t reserved5[0x00003]
Definition: MT25408_PRM.h:720
hermonprm_completion_with_error_st
Definition: MT25408_PRM.h:1724
hermonprm_vsd_st::vsd_dw43
pseudo_bit_t vsd_dw43[0x00020]
Definition: MT25408_PRM.h:498
hermonprm_completion_queue_error_st::cqn
pseudo_bit_t cqn[0x00018]
Definition: MT25408_PRM.h:2935
hermonprm_mt25208_type0_st::min_gnt
pseudo_bit_t min_gnt[0x00008]
Definition: MT25408_PRM.h:2716
hermonprm_query_dev_cap_st::reserved38
pseudo_bit_t reserved38[0x00020]
Definition: MT25408_PRM.h:2203
hermonprm_query_dev_cap_st::reserved32
pseudo_bit_t reserved32[0x00002]
Definition: MT25408_PRM.h:2183
hermonprm_vsd_st::vsd_dw30
pseudo_bit_t vsd_dw30[0x00020]
Definition: MT25408_PRM.h:472
hermonprm_mt25208_type0_st::reserved6
pseudo_bit_t reserved6[0x00100]
Definition: MT25408_PRM.h:2719
hermonprm_hermon_prm_st::reserved16
pseudo_bit_t reserved16[0x7fe00]
Definition: MT25408_PRM.h:3223
hermonprm_queue_pair_ee_context_entry_st::usr_page
pseudo_bit_t usr_page[0x00018]
Definition: MT25408_PRM.h:839
hermonprm_hermon_prm_st::reserved34
pseudo_bit_t reserved34[0x7ff00]
Definition: MT25408_PRM.h:3285
hermonprm_eqc_st::reserved9
pseudo_bit_t reserved9[0x00010]
Definition: MT25408_PRM.h:2448
hermonprm_eq_set_ci_table_st::eq43_set_ci
pseudo_bit_t eq43_set_ci[0x00020]
Definition: MT25408_PRM.h:1187
hermonprm_eq_set_ci_table_st::reserved15
pseudo_bit_t reserved15[0x00020]
Definition: MT25408_PRM.h:1077
hermonprm_hermon_prm_st::reserved53
pseudo_bit_t reserved53[0x7ff00]
Definition: MT25408_PRM.h:3361
hermonprm_wqe_segment_bind_st::new_rkey
pseudo_bit_t new_rkey[0x00020]
Definition: MT25408_PRM.h:204
hermonprm_qpcbaseaddr_st::qpc_base_addr_l
pseudo_bit_t qpc_base_addr_l[0x0001b]
Definition: MT25408_PRM.h:625
hermonprm_query_dev_cap_st::resd_lkey
pseudo_bit_t resd_lkey[0x00020]
Definition: MT25408_PRM.h:2260
hermonprm_tptparams_st
Definition: MT25408_PRM.h:542
hermonprm_hermon_prm_st::reserved15
pseudo_bit_t reserved15[0x7fe00]
Definition: MT25408_PRM.h:3219
hermonprm_mod_stat_cfg_st::reserved13
pseudo_bit_t reserved13[0x0001f]
Definition: MT25408_PRM.h:1381
hermonprm_udavtable_memory_parameters_st::reserved1
pseudo_bit_t reserved1[0x00002]
Definition: MT25408_PRM.h:2359
hermonprm_queue_pair_ee_context_entry_st::rae
pseudo_bit_t rae[0x00001]
Definition: MT25408_PRM.h:894
hermonprm_completion_queue_entry_st::immediate_rssvalue_invalidatekey
pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020]
Definition: MT25408_PRM.h:3007
hermonprm_mt25208_type0_st::cache_line_size
pseudo_bit_t cache_line_size[0x00008]
Definition: MT25408_PRM.h:2677
hermonprm_eq_set_ci_table_st::eq59_set_ci
pseudo_bit_t eq59_set_ci[0x00020]
Definition: MT25408_PRM.h:1251
hermonprm_wqe_segment_data_inline_st
Definition: MT25408_PRM.h:94
hermonprm_header_log_register_st::place_holder
pseudo_bit_t place_holder[0x00020]
Definition: MT25408_PRM.h:692
hermonprm_hca_command_register_st::out_param_h
pseudo_bit_t out_param_h[0x00020]
Definition: MT25408_PRM.h:342
hermonprm_query_dev_cap_st::log_max_d_mpts
pseudo_bit_t log_max_d_mpts[0x00006]
Definition: MT25408_PRM.h:2083
hermonprm_eq_set_ci_table_st::reserved33
pseudo_bit_t reserved33[0x00020]
Definition: MT25408_PRM.h:1149
hermonprm_wqe_segment_atomic_st::swap_add_h
pseudo_bit_t swap_add_h[0x00020]
Definition: MT25408_PRM.h:165
hermonprm_eq_set_ci_table_st::reserved61
pseudo_bit_t reserved61[0x00020]
Definition: MT25408_PRM.h:1261
hermonprm_mad_ifc_input_modifier_st::mad_extended_info
pseudo_bit_t mad_extended_info[0x00001]
Definition: MT25408_PRM.h:1799
hermonprm_query_dev_cap_st::max_sg_sq
pseudo_bit_t max_sg_sq[0x00008]
Definition: MT25408_PRM.h:2191
hermonprm_query_dev_cap_st::udm
pseudo_bit_t udm[0x00001]
Definition: MT25408_PRM.h:2167
hermonprm_qpcbaseaddr_st::srqc_base_addr_h
pseudo_bit_t srqc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:632
hermonprm_eq_set_ci_table_st::reserved44
pseudo_bit_t reserved44[0x00020]
Definition: MT25408_PRM.h:1193
hermonprm_hermon_prm_st::reserved7
pseudo_bit_t reserved7[0x7ff40]
Definition: MT25408_PRM.h:3187
hermonprm_mod_stat_cfg_st::reserved2
pseudo_bit_t reserved2[0x00003]
Definition: MT25408_PRM.h:1347
hermonprm_query_dev_cap_st::log_max_gid
pseudo_bit_t log_max_gid[0x00004]
Definition: MT25408_PRM.h:2122
hermonprm_cq_arm_db_record_st::cmd_sn
pseudo_bit_t cmd_sn[0x00002]
Definition: MT25408_PRM.h:1302
hermonprm_queue_pair_ee_context_entry_st::reserved16
pseudo_bit_t reserved16[0x00001]
Definition: MT25408_PRM.h:861
hermonprm_mt25208_type0_st::bar0_l
pseudo_bit_t bar0_l[0x0000c]
Definition: MT25408_PRM.h:2684
hermonprm_mod_stat_cfg_st::dife
pseudo_bit_t dife[0x00001]
Definition: MT25408_PRM.h:1341
hermonprm_completion_queue_context_st::reserved9
pseudo_bit_t reserved9[0x00002]
Definition: MT25408_PRM.h:2598
hermonprm_vsd_st::vsd_dw49
pseudo_bit_t vsd_dw49[0x00020]
Definition: MT25408_PRM.h:510
hermonprm_mpt_st::m_dif
pseudo_bit_t m_dif[0x00001]
Definition: MT25408_PRM.h:2514
hermonprm_mad_ifc_st::g
pseudo_bit_t g[0x00001]
Definition: MT25408_PRM.h:1825
hermonprm_hca_command_register_st::status
pseudo_bit_t status[0x00008]
Definition: MT25408_PRM.h:359
hermonprm_completion_queue_context_st::reserved2
pseudo_bit_t reserved2[0x00009]
Definition: MT25408_PRM.h:2569
hermonprm_completion_queue_context_st::reserved7
pseudo_bit_t reserved7[0x00017]
Definition: MT25408_PRM.h:2593
hermonprm_transport_and_ci_error_counters_st::sq_num_wrfe
pseudo_bit_t sq_num_wrfe[0x00020]
Definition: MT25408_PRM.h:1581
hermonprm_completion_queue_entry_st::wqe_counter
pseudo_bit_t wqe_counter[0x00010]
Definition: MT25408_PRM.h:3039
hermonprm_hcr_completion_event_st::reserved1
pseudo_bit_t reserved1[0x00020]
Definition: MT25408_PRM.h:1709
hermonprm_mod_stat_cfg_st::mux_eq
pseudo_bit_t mux_eq[0x00002]
Definition: MT25408_PRM.h:1409
hermonprm_ud_address_vector_st::rgid_95_64
pseudo_bit_t rgid_95_64[0x00020]
Definition: MT25408_PRM.h:69
hermonprm_transport_and_ci_error_counters_st::num_baddb
pseudo_bit_t num_baddb[0x00020]
Definition: MT25408_PRM.h:1697
hermonprm_query_dev_cap_st::mps
pseudo_bit_t mps[0x00001]
Definition: MT25408_PRM.h:2254
hermonprm_page_fault_event_data_st::rr
pseudo_bit_t rr[0x00001]
Definition: MT25408_PRM.h:2893
hermonprm_vsd_st::vsd_dw36
pseudo_bit_t vsd_dw36[0x00020]
Definition: MT25408_PRM.h:484
hermonprm_mod_stat_cfg_st::reserved38
pseudo_bit_t reserved38[0x00002]
Definition: MT25408_PRM.h:1457
hermonprm_wqe_segment_data_inline_st::always1
pseudo_bit_t always1[0x00001]
Definition: MT25408_PRM.h:97
hermonprm_hermon_prm_st::completion_queue_context
struct hermonprm_completion_queue_context_st completion_queue_context
Definition: MT25408_PRM.h:3217
hermonprm_vsd_st::vsd_dw46
pseudo_bit_t vsd_dw46[0x00020]
Definition: MT25408_PRM.h:504
hermonprm_page_fault_event_data_st::lw
pseudo_bit_t lw[0x00001]
Definition: MT25408_PRM.h:2890
hermonprm_address_path_st::tclass
pseudo_bit_t tclass[0x00008]
Definition: MT25408_PRM.h:304
hermonprm_mod_stat_cfg_st::fw_rev_major
pseudo_bit_t fw_rev_major[0x00010]
Definition: MT25408_PRM.h:1428
hermonprm_mod_stat_cfg_st::reserved36
pseudo_bit_t reserved36[0x00018]
Definition: MT25408_PRM.h:1452
hermonprm_hermon_prm_st::virtual_physical_mapping
struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping
Definition: MT25408_PRM.h:3371
hermonprm_wqe_segment_ctrl_mlx_st::max_statrate
pseudo_bit_t max_statrate[0x00004]
Definition: MT25408_PRM.h:746
hermonprm_wqe_segment_ctrl_send_st::ds
pseudo_bit_t ds[0x00006]
Definition: MT25408_PRM.h:251
hermonprm_query_dev_cap_st::avp
pseudo_bit_t avp[0x00001]
Definition: MT25408_PRM.h:2166
hermonprm_query_dev_cap_st::atm
pseudo_bit_t atm[0x00001]
Definition: MT25408_PRM.h:2164
hermonprm_query_dev_cap_st::vep_mc_steering
pseudo_bit_t vep_mc_steering[0x00001]
Definition: MT25408_PRM.h:2141
hermonprm_performance_monitors_st::reserved0
pseudo_bit_t reserved0[0x00001]
Definition: MT25408_PRM.h:704
hermonprm_hermon_prm_st::reserved62
pseudo_bit_t reserved62[0x00040]
Definition: MT25408_PRM.h:3395
hermonprm_tptparams_st::log_dmpt_sz
pseudo_bit_t log_dmpt_sz[0x00006]
Definition: MT25408_PRM.h:553
hermonprm_query_dev_cap_st::reserved16
pseudo_bit_t reserved16[0x0000a]
Definition: MT25408_PRM.h:2101
hermonprm_transport_and_ci_error_counters_st::reserved8
pseudo_bit_t reserved8[0x00380]
Definition: MT25408_PRM.h:1671
hermonprm_mt25208_type0_st::status
pseudo_bit_t status[0x00010]
Definition: MT25408_PRM.h:2672
hermonprm_eq_set_ci_table_st::reserved21
pseudo_bit_t reserved21[0x00020]
Definition: MT25408_PRM.h:1101
hermonprm_address_path_st::reserved5
pseudo_bit_t reserved5[0x00008]
Definition: MT25408_PRM.h:315
hermonprm_ud_address_vector_st::flow_label
pseudo_bit_t flow_label[0x00014]
Definition: MT25408_PRM.h:63
hermonprm_query_fw_st::reserved1
pseudo_bit_t reserved1[0x00017]
Definition: MT25408_PRM.h:2299
hermonprm_queue_pair_ee_context_entry_st::reserved10
pseudo_bit_t reserved10[0x00008]
Definition: MT25408_PRM.h:840
hermonprm_hermon_prm_st::reserved0
pseudo_bit_t reserved0[0x7ff00]
Definition: MT25408_PRM.h:3159
hermonprm_vsd_st::vsd_dw35
pseudo_bit_t vsd_dw35[0x00020]
Definition: MT25408_PRM.h:482
hermonprm_ud_address_vector_st::fl
pseudo_bit_t fl[0x00001]
Definition: MT25408_PRM.h:42
hermonprm_completion_queue_context_st::producer_counter
pseudo_bit_t producer_counter[0x00018]
Definition: MT25408_PRM.h:2616
hermonprm_query_dev_cap_st::max_desc_sz_sq
pseudo_bit_t max_desc_sz_sq[0x00010]
Definition: MT25408_PRM.h:2190
hermonprm_eq_set_ci_table_st::eq45_set_ci
pseudo_bit_t eq45_set_ci[0x00020]
Definition: MT25408_PRM.h:1195
hermonprm_eq_set_ci_table_st::reserved41
pseudo_bit_t reserved41[0x00020]
Definition: MT25408_PRM.h:1181
hermonprm_mt25208_type0_st::max_latency
pseudo_bit_t max_latency[0x00008]
Definition: MT25408_PRM.h:2717
hermonprm_mgm_entry_st::mgmqp_4
struct hermonprm_mgmqp_st mgmqp_4
Definition: MT25408_PRM.h:1984
hermonprm_qpcbaseaddr_st::log_num_of_srq
pseudo_bit_t log_num_of_srq[0x00005]
Definition: MT25408_PRM.h:636
hermonprm_init_port_st::guid0_l
pseudo_bit_t guid0_l[0x00020]
Definition: MT25408_PRM.h:2028
hermonprm_hermon_prm_st::receive_doorbell
struct hermonprm_receive_doorbell_st receive_doorbell
Definition: MT25408_PRM.h:3307
hermonprm_query_dev_cap_st::raw_ethertype
pseudo_bit_t raw_ethertype[0x00001]
Definition: MT25408_PRM.h:2159
hermonprm_mod_stat_cfg_st::outer_vlan_en_m
pseudo_bit_t outer_vlan_en_m[0x00001]
Definition: MT25408_PRM.h:1455
hermonprm_query_dev_cap_st::log_max_srqs
pseudo_bit_t log_max_srqs[0x00005]
Definition: MT25408_PRM.h:2063
hermonprm_performance_monitor_event_st::reserved1
pseudo_bit_t reserved1[0x00040]
Definition: MT25408_PRM.h:2874
hermonprm_completion_queue_error_st::reserved2
pseudo_bit_t reserved2[0x00018]
Definition: MT25408_PRM.h:2943
hermonprm_mt25208_type0_st::class_code_hca_class_code
pseudo_bit_t class_code_hca_class_code[0x00018]
Definition: MT25408_PRM.h:2675
hermonprm_qp_ee_event_st::reserved1
pseudo_bit_t reserved1[0x00020]
Definition: MT25408_PRM.h:2651
hermonprm_hermon_prm_st::reserved42
pseudo_bit_t reserved42[0x7c000]
Definition: MT25408_PRM.h:3317
hermonprm_query_dev_cap_st::max_desc_sz_rq
pseudo_bit_t max_desc_sz_rq[0x00010]
Definition: MT25408_PRM.h:2194
hermonprm_vsd_st::vsd_dw53
pseudo_bit_t vsd_dw53[0x00020]
Definition: MT25408_PRM.h:518
hermonprm_completion_queue_context_st::reserved15
pseudo_bit_t reserved15[0x00020]
Definition: MT25408_PRM.h:2621
hermonprm_hcr_completion_event_st
Definition: MT25408_PRM.h:1705
hermonprm_transport_and_ci_error_counters_st::rq_num_leeoe
pseudo_bit_t rq_num_leeoe[0x00020]
Definition: MT25408_PRM.h:1570
hermonprm_eq_set_ci_table_st::reserved27
pseudo_bit_t reserved27[0x00020]
Definition: MT25408_PRM.h:1125
hermonprm_wqe_segment_ctrl_send_st
Definition: MT25408_PRM.h:246
hermonprm_queue_pair_ee_context_entry_st::ssn
pseudo_bit_t ssn[0x00018]
Definition: MT25408_PRM.h:882
hermonprm_scrubbing_event_st::err_ba
pseudo_bit_t err_ba[0x00002]
Definition: MT25408_PRM.h:3138
hermonprm_wqe_segment_remote_address_st::remote_virt_addr_l
pseudo_bit_t remote_virt_addr_l[0x00020]
Definition: MT25408_PRM.h:180
hermonprm_performance_counters_st::reserved1
pseudo_bit_t reserved1[0x00080]
Definition: MT25408_PRM.h:1549
hermonprm_completion_queue_context_st::cq_period
pseudo_bit_t cq_period[0x00010]
Definition: MT25408_PRM.h:2588
hermonprm_eqc_st::ec
pseudo_bit_t ec[0x00001]
Definition: MT25408_PRM.h:2424
hermonprm_completion_with_error_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:1726
hermonprm_init_port_st::reserved1
pseudo_bit_t reserved1[0x00004]
Definition: MT25408_PRM.h:2005
hermonprm_resize_cq_st::mtt_base_addr_l
pseudo_bit_t mtt_base_addr_l[0x0001d]
Definition: MT25408_PRM.h:1787
hermonprm_send_doorbell_st::f
pseudo_bit_t f[0x00001]
Definition: MT25408_PRM.h:81
hermonprm_eqc_st::reserved4
pseudo_bit_t reserved4[0x00005]
Definition: MT25408_PRM.h:2433
hermonprm_performance_monitors_st::ev_cnt1
pseudo_bit_t ev_cnt1[0x00005]
Definition: MT25408_PRM.h:717
hermonprm_eq_set_ci_table_st::reserved16
pseudo_bit_t reserved16[0x00020]
Definition: MT25408_PRM.h:1081
hermonprm_mt25208_type0_st::multiple_msg_en
pseudo_bit_t multiple_msg_en[0x00003]
Definition: MT25408_PRM.h:2725
hermonprm_mad_ifc_st::reserved3
pseudo_bit_t reserved3[0x00010]
Definition: MT25408_PRM.h:1822
hermonprm_eq_set_ci_table_st::reserved55
pseudo_bit_t reserved55[0x00020]
Definition: MT25408_PRM.h:1237
hermonprm_wqe_segment_ctrl_mlx_st::reserved4
pseudo_bit_t reserved4[0x0000e]
Definition: MT25408_PRM.h:749
hermonprm_mod_stat_cfg_st::reserved10
pseudo_bit_t reserved10[0x00004]
Definition: MT25408_PRM.h:1369
hermonprm_mod_stat_cfg_st::ob_preemp_main
pseudo_bit_t ob_preemp_main[0x00005]
Definition: MT25408_PRM.h:1395
hermonprm_init_port_st::node_guid_h
pseudo_bit_t node_guid_h[0x00020]
Definition: MT25408_PRM.h:2030
hermonprm_mgm_entry_st::reserved1
pseudo_bit_t reserved1[0x00060]
Definition: MT25408_PRM.h:1962
hermonprm_multicastparam_st::log_mc_table_hash_sz
pseudo_bit_t log_mc_table_hash_sz[0x00005]
Definition: MT25408_PRM.h:599
hermonprm_hermon_prm_st::reserved58
pseudo_bit_t reserved58[0x7ffc0]
Definition: MT25408_PRM.h:3381
hermonprm_scrubbing_event_st::err_ra
pseudo_bit_t err_ra[0x00010]
Definition: MT25408_PRM.h:3142
hermonprm_wqe_segment_ctrl_mlx_st::icrc
pseudo_bit_t icrc[0x00001]
Definition: MT25408_PRM.h:743
hermonprm_mod_stat_cfg_st::reserved26
pseudo_bit_t reserved26[0x00006]
Definition: MT25408_PRM.h:1418
hermonprm_wqe_segment_st::send_wqe_segment
struct hermonprm_send_wqe_segment_st send_wqe_segment
Definition: MT25408_PRM.h:2905
hermonprm_mpt_st::len64
pseudo_bit_t len64[0x00001]
Definition: MT25408_PRM.h:2533
hermonprm_query_fw_st::reserved8
pseudo_bit_t reserved8[0x00600]
Definition: MT25408_PRM.h:2347
hermonprm_hermon_prm_st::mod_stat_cfg
struct hermonprm_mod_stat_cfg_st mod_stat_cfg
Definition: MT25408_PRM.h:3367
hermonprm_srq_context_st::state
pseudo_bit_t state[0x00004]
Definition: MT25408_PRM.h:1480
hermonprm_wqe_segment_ctrl_mlx_st::sl
pseudo_bit_t sl[0x00004]
Definition: MT25408_PRM.h:745
hermonprm_send_wqe_segment_st::fast_registration_segment
struct hermonprm_fast_registration_segment_st fast_registration_segment
Definition: MT25408_PRM.h:773
hermonprm_address_path_st::fvl
pseudo_bit_t fvl[0x00001]
Definition: MT25408_PRM.h:318
hermonprm_completion_queue_context_st::consumer_counter
pseudo_bit_t consumer_counter[0x00018]
Definition: MT25408_PRM.h:2612
hermonprm_eq_set_ci_table_st::eq27_set_ci
pseudo_bit_t eq27_set_ci[0x00020]
Definition: MT25408_PRM.h:1123
hermonprm_completion_queue_entry_st::smac31_0_rawether_ipoib_status
pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020]
Definition: MT25408_PRM.h:3031
hermonprm_mt25208_type0_st::capabilities_pointer
pseudo_bit_t capabilities_pointer[0x00008]
Definition: MT25408_PRM.h:2709
hermonprm_query_dev_cap_st::reserved22
pseudo_bit_t reserved22[0x00004]
Definition: MT25408_PRM.h:2123
hermonprm_rd_send_doorbell_st::qpn
pseudo_bit_t qpn[0x00018]
Definition: MT25408_PRM.h:393
hermonprm_eq_set_ci_table_st::eq49_set_ci
pseudo_bit_t eq49_set_ci[0x00020]
Definition: MT25408_PRM.h:1211
hermonprm_mpt_st::mtt_fbo
pseudo_bit_t mtt_fbo[0x00015]
Definition: MT25408_PRM.h:2547
hermonprm_eq_set_ci_table_st::reserved20
pseudo_bit_t reserved20[0x00020]
Definition: MT25408_PRM.h:1097
hermonprm_queue_pair_ee_context_entry_st::reserved34
pseudo_bit_t reserved34[0x00007]
Definition: MT25408_PRM.h:925
hermonprm_eq_set_ci_table_st::eq1_set_ci
pseudo_bit_t eq1_set_ci[0x00020]
Definition: MT25408_PRM.h:1019
hermonprm_hermon_prm_st::reserved11
pseudo_bit_t reserved11[0x7fe40]
Definition: MT25408_PRM.h:3203
hermonprm_mpt_st::eb
pseudo_bit_t eb[0x00001]
Definition: MT25408_PRM.h:2493
hermonprm_completion_event_st::reserved1
pseudo_bit_t reserved1[0x000a0]
Definition: MT25408_PRM.h:2955
hermonprm_pbl_st::mtt_2_h
pseudo_bit_t mtt_2_h[0x00020]
Definition: MT25408_PRM.h:1534
hermonprm_srq_context_st::reserved4
pseudo_bit_t reserved4[0x00010]
Definition: MT25408_PRM.h:1498
hermonprm_mgm_entry_st::mgmqp_3
struct hermonprm_mgmqp_st mgmqp_3
Definition: MT25408_PRM.h:1982
hermonprm_wqe_segment_data_ptr_st::always0
pseudo_bit_t always0[0x00001]
Definition: MT25408_PRM.h:110
hermonprm_address_path_st::fsip
pseudo_bit_t fsip[0x00001]
Definition: MT25408_PRM.h:319
hermonprm_ecc_detect_event_data_st::overflow
pseudo_bit_t overflow[0x00001]
Definition: MT25408_PRM.h:3115
hermonprm_send_wqe_segment_st
Definition: MT25408_PRM.h:758
hermonprm_hermon_prm_st::mt25208_type0
struct hermonprm_mt25208_type0_st mt25208_type0
Definition: MT25408_PRM.h:3193
hermonprm_wqe_segment_ctrl_send_st::s
pseudo_bit_t s[0x00001]
Definition: MT25408_PRM.h:256
hermonprm_cq_arm_db_record_st::cq_number
pseudo_bit_t cq_number[0x00018]
Definition: MT25408_PRM.h:1304
hermonprm_queue_pair_ee_context_entry_st::reserved44
pseudo_bit_t reserved44[0x00008]
Definition: MT25408_PRM.h:971
hermonprm_mt25208_type0_st::latency_timer
pseudo_bit_t latency_timer[0x00008]
Definition: MT25408_PRM.h:2678
hermonprm_transport_and_ci_error_counters_st::rq_num_wrfe
pseudo_bit_t rq_num_wrfe[0x00020]
Definition: MT25408_PRM.h:1578
hermonprm_eqc_st::reserved12
pseudo_bit_t reserved12[0x00040]
Definition: MT25408_PRM.h:2455
hermonprm_qpcbaseaddr_st::qpc_base_addr_h
pseudo_bit_t qpc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:621
hermonprm_query_dev_cap_st::reserved6
pseudo_bit_t reserved6[0x00003]
Definition: MT25408_PRM.h:2068
hermonprm_completion_queue_entry_st::d2s
pseudo_bit_t d2s[0x00001]
Definition: MT25408_PRM.h:2996
hermonprm_query_dev_cap_st::reserved14
pseudo_bit_t reserved14[0x00005]
Definition: MT25408_PRM.h:2093
hermonprm_fast_registration_segment_st::pbl_ptr_31_8
pseudo_bit_t pbl_ptr_31_8[0x00018]
Definition: MT25408_PRM.h:150
hermonprm_query_dev_cap_st::reserved19
pseudo_bit_t reserved19[0x0001f]
Definition: MT25408_PRM.h:2109
hermonprm_eqc_st::reserved11
pseudo_bit_t reserved11[0x00003]
Definition: MT25408_PRM.h:2452
hermonprm_ud_address_vector_st::rgid_31_0
pseudo_bit_t rgid_31_0[0x00020]
Definition: MT25408_PRM.h:73
hermonprm_mod_stat_cfg_st::num_veps
pseudo_bit_t num_veps[0x00008]
Definition: MT25408_PRM.h:1447
hermonprm_sched_queue_context_st::port
pseudo_bit_t port[0x00002]
Definition: MT25408_PRM.h:3095
hermonprm_queue_pair_ee_context_entry_st::reserved19
pseudo_bit_t reserved19[0x00020]
Definition: MT25408_PRM.h:869
hermonprm_eq_set_ci_table_st::reserved54
pseudo_bit_t reserved54[0x00020]
Definition: MT25408_PRM.h:1233
hermonprm_hermon_prm_st::reserved32
pseudo_bit_t reserved32[0x7f800]
Definition: MT25408_PRM.h:3277
hermonprm_vsd_st::vsd_dw3
pseudo_bit_t vsd_dw3[0x00020]
Definition: MT25408_PRM.h:418
hermonprm_eq_set_ci_table_st::reserved42
pseudo_bit_t reserved42[0x00020]
Definition: MT25408_PRM.h:1185
hermonprm_ud_address_vector_st::g
pseudo_bit_t g[0x00001]
Definition: MT25408_PRM.h:46
hermonprm_queue_pair_ee_context_entry_st::next_send_psn
pseudo_bit_t next_send_psn[0x00018]
Definition: MT25408_PRM.h:871
hermonprm_queue_pair_ee_context_entry_st::vft_hop_count
pseudo_bit_t vft_hop_count[0x00008]
Definition: MT25408_PRM.h:982
hermonprm_address_path_st::counter_index
pseudo_bit_t counter_index[0x00008]
Definition: MT25408_PRM.h:327
hermonprm_mad_ifc_st::sl
pseudo_bit_t sl[0x00004]
Definition: MT25408_PRM.h:1828
hermonprm_receive_doorbell_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:1922
hermonprm_query_debug_msg_st::buff4_size
pseudo_bit_t buff4_size[0x00020]
Definition: MT25408_PRM.h:1888
hermonprm_mpt_st::mtt_adr_h
pseudo_bit_t mtt_adr_h[0x00008]
Definition: MT25408_PRM.h:2537
hermonprm_ud_address_vector_st::pd
pseudo_bit_t pd[0x00018]
Definition: MT25408_PRM.h:36
hermonprm_query_dev_cap_st::j
pseudo_bit_t j[0x00001]
Definition: MT25408_PRM.h:2119
hermonprm_queue_pair_ee_context_entry_st::rra_max
pseudo_bit_t rra_max[0x00003]
Definition: MT25408_PRM.h:898
hermonprm_completion_queue_context_st::last_notified_indx
pseudo_bit_t last_notified_indx[0x00018]
Definition: MT25408_PRM.h:2603
hermonprm_eq_set_ci_table_st::eq9_set_ci
pseudo_bit_t eq9_set_ci[0x00020]
Definition: MT25408_PRM.h:1051
hermonprm_queue_pair_ee_context_entry_st::rme
pseudo_bit_t rme[0x00002]
Definition: MT25408_PRM.h:943
hermonprm_hcr_completion_event_st::token
pseudo_bit_t token[0x00010]
Definition: MT25408_PRM.h:1706
hermonprm_transport_and_ci_error_counters_st::rq_num_rnr
pseudo_bit_t rq_num_rnr[0x00020]
Definition: MT25408_PRM.h:1653
hermonprm_mgmqp_st
Definition: MT25408_PRM.h:401
hermonprm_completion_queue_context_st::oi
pseudo_bit_t oi[0x00001]
Definition: MT25408_PRM.h:2566
hermonprm_performance_monitors_st::reserved1
pseudo_bit_t reserved1[0x00001]
Definition: MT25408_PRM.h:708
hermonprm_mt25208_type0_st::pciex_cap
pseudo_bit_t pciex_cap[0x00010]
Definition: MT25408_PRM.h:2766
hermonprm_queue_pair_ee_context_entry_st::reserved11
pseudo_bit_t reserved11[0x00008]
Definition: MT25408_PRM.h:844
hermonprm_mod_stat_cfg_st::reserved4
pseudo_bit_t reserved4[0x00003]
Definition: MT25408_PRM.h:1352
hermonprm_query_debug_msg_st
Definition: MT25408_PRM.h:1847
hermonprm_mod_stat_cfg_st::reserved17
pseudo_bit_t reserved17[0x00003]
Definition: MT25408_PRM.h:1396
hermonprm_eq_set_ci_table_st::reserved12
pseudo_bit_t reserved12[0x00020]
Definition: MT25408_PRM.h:1065
hermonprm_query_fw_st::reserved5
pseudo_bit_t reserved5[0x0001e]
Definition: MT25408_PRM.h:2321
hermonprm_mt25208_type0_st::correctable_error_mask_register
pseudo_bit_t correctable_error_mask_register[0x00020]
Definition: MT25408_PRM.h:2846
hermonprm_mad_ifc_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:1814
hermonprm_queue_pair_ee_context_entry_st::reserved2
pseudo_bit_t reserved2[0x00002]
Definition: MT25408_PRM.h:790
hermonprm_mod_stat_cfg_st::reserved34
pseudo_bit_t reserved34[0x00010]
Definition: MT25408_PRM.h:1446
hermonprm_query_dev_cap_st::reserved41
pseudo_bit_t reserved41[0x00008]
Definition: MT25408_PRM.h:2214
hermonprm_wqe_segment_atomic_st::swap_add_l
pseudo_bit_t swap_add_l[0x00020]
Definition: MT25408_PRM.h:167
hermonprm_mad_ifc_st::pkey_indx
pseudo_bit_t pkey_indx[0x00010]
Definition: MT25408_PRM.h:1831
hermonprm_virtual_physical_mapping_st::va_l
pseudo_bit_t va_l[0x00014]
Definition: MT25408_PRM.h:1325
hermonprm_eq_set_ci_table_st::eq37_set_ci
pseudo_bit_t eq37_set_ci[0x00020]
Definition: MT25408_PRM.h:1163
hermonprm_query_adapter_st::reserved1
pseudo_bit_t reserved1[0x00018]
Definition: MT25408_PRM.h:2277
hermonprm_query_dev_cap_st::num_rsvd_mcgs
pseudo_bit_t num_rsvd_mcgs[0x00004]
Definition: MT25408_PRM.h:2206
hermonprm_hermon_prm_st::port_state_change
struct hermonprm_port_state_change_st port_state_change
Definition: MT25408_PRM.h:3177
hermonprm_mt25208_type0_st::uncorrectable_error_status_register
pseudo_bit_t uncorrectable_error_status_register[0x00020]
Definition: MT25408_PRM.h:2804
hermonprm_query_dev_cap_st::log2_rsvd_qps
pseudo_bit_t log2_rsvd_qps[0x00004]
Definition: MT25408_PRM.h:2053
hermonprm_mt25208_type0_st::bar0_h
pseudo_bit_t bar0_h[0x00020]
Definition: MT25408_PRM.h:2686
hermonprm_ecc_detect_event_data_st::err_src_id
pseudo_bit_t err_src_id[0x00003]
Definition: MT25408_PRM.h:3111
hermonprm_transport_and_ci_error_counters_st::num_eqovf
pseudo_bit_t num_eqovf[0x00020]
Definition: MT25408_PRM.h:1695
hermonprm_wqe_segment_rd_st
Definition: MT25408_PRM.h:234
hermonprm_qp_ee_event_st::reserved3
pseudo_bit_t reserved3[0x00003]
Definition: MT25408_PRM.h:2656
hermonprm_qpcbaseaddr_st::auxc_base_addr_h
pseudo_bit_t auxc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:660
hermonprm_mt25208_type0_st::reserved8
pseudo_bit_t reserved8[0x00010]
Definition: MT25408_PRM.h:2734
hermonprm_transport_and_ci_error_counters_st::reserved5
pseudo_bit_t reserved5[0x00020]
Definition: MT25408_PRM.h:1659
hermonprm_wqe_segment_ctrl_mlx_st::opcode
pseudo_bit_t opcode[0x00005]
Definition: MT25408_PRM.h:733
hermonprm_query_fw_st::dt
pseudo_bit_t dt[0x00001]
Definition: MT25408_PRM.h:2300
hermonprm_transport_and_ci_error_counters_st
Definition: MT25408_PRM.h:1561
hermonprm_eq_set_ci_table_st::reserved6
pseudo_bit_t reserved6[0x00020]
Definition: MT25408_PRM.h:1041
hermonprm_vsd_st::vsd_dw0
pseudo_bit_t vsd_dw0[0x00020]
Definition: MT25408_PRM.h:412
hermonprm_queue_pair_ee_context_entry_st::q_key
pseudo_bit_t q_key[0x00020]
Definition: MT25408_PRM.h:918
hermonprm_queue_pair_ee_context_entry_st::cqn_rcv
pseudo_bit_t cqn_rcv[0x00018]
Definition: MT25408_PRM.h:910
hermonprm_eq_set_ci_table_st::reserved0
pseudo_bit_t reserved0[0x00020]
Definition: MT25408_PRM.h:1017
hermonprm_eq_set_ci_table_st::reserved50
pseudo_bit_t reserved50[0x00020]
Definition: MT25408_PRM.h:1217
hermonprm_vsd_st::vsd_dw32
pseudo_bit_t vsd_dw32[0x00020]
Definition: MT25408_PRM.h:476
hermonprm_query_adapter_st::reserved2
pseudo_bit_t reserved2[0x00060]
Definition: MT25408_PRM.h:2280
hermonprm_mt25208_type0_st::reserved0
pseudo_bit_t reserved0[0x00010]
Definition: MT25408_PRM.h:2683
hermonprm_query_dev_cap_st::reserved1
pseudo_bit_t reserved1[0x00003]
Definition: MT25408_PRM.h:2052
hermonprm_hermon_prm_st::uar_params
struct hermonprm_uar_params_st uar_params
Definition: MT25408_PRM.h:3283
hermonprm_event_queue_entry_st::event_sub_type
pseudo_bit_t event_sub_type[0x00008]
Definition: MT25408_PRM.h:2962
hermonprm_hermon_prm_st::reserved57
pseudo_bit_t reserved57[0x7ffc0]
Definition: MT25408_PRM.h:3377
hermonprm_mcg_qp_dw_st::reserved1
pseudo_bit_t reserved1[0x00001]
Definition: MT25408_PRM.h:994
hermonprm_wqe_segment_data_inline_st::reserved0
pseudo_bit_t reserved0[0x00015]
Definition: MT25408_PRM.h:96
hermonprm_hca_command_register_st::reserved1
pseudo_bit_t reserved1[0x00005]
Definition: MT25408_PRM.h:351
hermonprm_vsd_st::vsd_dw19
pseudo_bit_t vsd_dw19[0x00020]
Definition: MT25408_PRM.h:450
hermonprm_mod_stat_cfg_st::mac_high
pseudo_bit_t mac_high[0x00010]
Definition: MT25408_PRM.h:1440
hermonprm_completion_queue_error_st
Definition: MT25408_PRM.h:2934
hermonprm_hermon_prm_st::reserved27
pseudo_bit_t reserved27[0x00100]
Definition: MT25408_PRM.h:3263
hermonprm_eqc_st::eq_period
pseudo_bit_t eq_period[0x00010]
Definition: MT25408_PRM.h:2442
hermonprm_vsd_st::vsd_dw47
pseudo_bit_t vsd_dw47[0x00020]
Definition: MT25408_PRM.h:506
hermonprm_udavtable_memory_parameters_st::pd
pseudo_bit_t pd[0x00018]
Definition: MT25408_PRM.h:2356
hermonprm_transport_and_ci_error_counters_st::reserved11
pseudo_bit_t reserved11[0x003e0]
Definition: MT25408_PRM.h:1691
hermonprm_hermon_prm_st::reserved52
pseudo_bit_t reserved52[0x7ff00]
Definition: MT25408_PRM.h:3357
hermonprm_mod_stat_cfg_st::sd_main
pseudo_bit_t sd_main[0x00004]
Definition: MT25408_PRM.h:1403
hermonprm_eq_set_ci_table_st::reserved32
pseudo_bit_t reserved32[0x00020]
Definition: MT25408_PRM.h:1145
hermonprm_pbl_st::mtt_3_l
pseudo_bit_t mtt_3_l[0x00020]
Definition: MT25408_PRM.h:1540
hermonprm_queue_pair_ee_context_entry_st::srqn
pseudo_bit_t srqn[0x00018]
Definition: MT25408_PRM.h:922
hermonprm_vsd_st::vsd_dw50
pseudo_bit_t vsd_dw50[0x00020]
Definition: MT25408_PRM.h:512
hermonprm_query_dev_cap_st::zb
pseudo_bit_t zb[0x00001]
Definition: MT25408_PRM.h:2256
hermonprm_hcr_completion_event_st::out_param_l
pseudo_bit_t out_param_l[0x00020]
Definition: MT25408_PRM.h:1716
hermonprm_query_dev_cap_st::reserved25
pseudo_bit_t reserved25[0x0000c]
Definition: MT25408_PRM.h:2131
hermonprm_sched_queue_context_st::weight
pseudo_bit_t weight[0x00010]
Definition: MT25408_PRM.h:3097
hermonprm_srq_context_st::reserved3
pseudo_bit_t reserved3[0x00020]
Definition: MT25408_PRM.h:1495
hermonprm_mod_stat_cfg_st::fw_rev_minor
pseudo_bit_t fw_rev_minor[0x00010]
Definition: MT25408_PRM.h:1432
hermonprm_eqc_st::reserved2
pseudo_bit_t reserved2[0x00009]
Definition: MT25408_PRM.h:2425
hermonprm_queue_pair_ee_context_entry_st::reserved3
pseudo_bit_t reserved3[0x00003]
Definition: MT25408_PRM.h:797
hermonprm_wqe_segment_remote_address_st::remote_virt_addr_h
pseudo_bit_t remote_virt_addr_h[0x00020]
Definition: MT25408_PRM.h:178
hermonprm_transport_and_ci_error_counters_st::reserved3
pseudo_bit_t reserved3[0x00020]
Definition: MT25408_PRM.h:1649
hermonprm_uar_st::send_doorbell
struct hermonprm_send_doorbell_st send_doorbell
Definition: MT25408_PRM.h:1909
hermonprm_mpt_st::reserved4
pseudo_bit_t reserved4[0x00001]
Definition: MT25408_PRM.h:2515
hermonprm_hermon_prm_st::reserved37
pseudo_bit_t reserved37[0x7fe00]
Definition: MT25408_PRM.h:3297
hermonprm_address_path_st::flow_label
pseudo_bit_t flow_label[0x00014]
Definition: MT25408_PRM.h:303
hermonprm_query_dev_cap_st::reserved10
pseudo_bit_t reserved10[0x00004]
Definition: MT25408_PRM.h:2082
hermonprm_query_dev_cap_st::reserved36
pseudo_bit_t reserved36[0x00008]
Definition: MT25408_PRM.h:2196
hermonprm_query_dev_cap_st::reserved33
pseudo_bit_t reserved33[0x00002]
Definition: MT25408_PRM.h:2185
hermonprm_hermon_prm_st::wqe_segment
struct hermonprm_wqe_segment_st wqe_segment
Definition: MT25408_PRM.h:3181
hermonprm_query_dev_cap_st::log_max_pd
pseudo_bit_t log_max_pd[0x00005]
Definition: MT25408_PRM.h:2218
hermonprm_query_debug_msg_st::trc_hdr_sz
pseudo_bit_t trc_hdr_sz[0x00020]
Definition: MT25408_PRM.h:1858
hermonprm_cq_ci_db_record_st::cq_number
pseudo_bit_t cq_number[0x00018]
Definition: MT25408_PRM.h:1315
hermonprm_hermon_prm_st::cq_cmd_doorbell
struct hermonprm_cq_cmd_doorbell_st cq_cmd_doorbell
Definition: MT25408_PRM.h:3311
hermonprm_vsd_st::vsd_dw11
pseudo_bit_t vsd_dw11[0x00020]
Definition: MT25408_PRM.h:434
hermonprm_hermon_prm_st::gpio_event_data
struct hermonprm_gpio_event_data_st gpio_event_data
Definition: MT25408_PRM.h:3201
hermonprm_mod_stat_cfg_st::reserved12
pseudo_bit_t reserved12[0x0001f]
Definition: MT25408_PRM.h:1376
hermonprm_completion_queue_context_st::mtt_base_addr_l
pseudo_bit_t mtt_base_addr_l[0x0001d]
Definition: MT25408_PRM.h:2601
hermonprm_eq_set_ci_table_st::eq30_set_ci
pseudo_bit_t eq30_set_ci[0x00020]
Definition: MT25408_PRM.h:1135
hermonprm_wqe_segment_rd_st::reserved1
pseudo_bit_t reserved1[0x00040]
Definition: MT25408_PRM.h:240
hermonprm_receive_doorbell_st::wqe_counter
pseudo_bit_t wqe_counter[0x00010]
Definition: MT25408_PRM.h:1923
hermonprm_set_ib_st::sig
pseudo_bit_t sig[0x00001]
Definition: MT25408_PRM.h:1938
hermonprm_queue_pair_ee_context_entry_st::db_record_addr_l
pseudo_bit_t db_record_addr_l[0x0001e]
Definition: MT25408_PRM.h:916
hermonprm_qpcbaseaddr_st::altc_base_addr_h
pseudo_bit_t altc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:650
hermonprm_query_adapter_st::intapin
pseudo_bit_t intapin[0x00008]
Definition: MT25408_PRM.h:2278
hermonprm_eq_set_ci_table_st::reserved9
pseudo_bit_t reserved9[0x00020]
Definition: MT25408_PRM.h:1053
hermonprm_eq_set_ci_table_st::reserved28
pseudo_bit_t reserved28[0x00020]
Definition: MT25408_PRM.h:1129
hermonprm_query_dev_cap_st::altc_entry_sz
pseudo_bit_t altc_entry_sz[0x00010]
Definition: MT25408_PRM.h:2231
hermonprm_transport_and_ci_error_counters_st::rq_num_rire
pseudo_bit_t rq_num_rire[0x00020]
Definition: MT25408_PRM.h:1603
hermonprm_resize_cq_st::reserved1
pseudo_bit_t reserved1[0x00006]
Definition: MT25408_PRM.h:1771
hermonprm_cq_cmd_doorbell_st
Definition: MT25408_PRM.h:366
hermonprm_completion_queue_entry_st
Definition: MT25408_PRM.h:2993
hermonprm_qpcbaseaddr_st::srqc_base_addr_l
pseudo_bit_t srqc_base_addr_l[0x0001b]
Definition: MT25408_PRM.h:637
hermonprm_eq_cmd_doorbell_st
Definition: MT25408_PRM.h:3149
hermonprm_transport_and_ci_error_counters_st::reserved2
pseudo_bit_t reserved2[0x00040]
Definition: MT25408_PRM.h:1594
hermonprm_mcg_hdr_st::reserved0
pseudo_bit_t reserved0[0x00006]
Definition: MT25408_PRM.h:3067
hermonprm_scrubbing_event_st::err_da
pseudo_bit_t err_da[0x00002]
Definition: MT25408_PRM.h:3137
hermonprm_mod_stat_cfg_st::num_port
pseudo_bit_t num_port[0x00008]
Definition: MT25408_PRM.h:1420
hermonprm_eq_set_ci_table_st::reserved62
pseudo_bit_t reserved62[0x00020]
Definition: MT25408_PRM.h:1265
hermonprm_ud_address_vector_st::my_lid_path_bits
pseudo_bit_t my_lid_path_bits[0x00007]
Definition: MT25408_PRM.h:45
hermonprm_mpt_st::reserved7
pseudo_bit_t reserved7[0x00008]
Definition: MT25408_PRM.h:2535
hermonprm_completion_queue_context_st::db_record_addr_l
pseudo_bit_t db_record_addr_l[0x0001d]
Definition: MT25408_PRM.h:2628
hermonprm_mcg_qp_dw_st::reserved0
pseudo_bit_t reserved0[0x00006]
Definition: MT25408_PRM.h:992
hermonprm_query_dev_cap_st::rc
pseudo_bit_t rc[0x00001]
Definition: MT25408_PRM.h:2145
hermonprm_queue_pair_ee_context_entry_st::my_id_indx
pseudo_bit_t my_id_indx[0x00008]
Definition: MT25408_PRM.h:981
hermonprm_mt25208_type0_st::device_cap
pseudo_bit_t device_cap[0x00020]
Definition: MT25408_PRM.h:2772
hermonprm_query_debug_msg_st::reserved2
pseudo_bit_t reserved2[0x00040]
Definition: MT25408_PRM.h:1868
hermonprm_mod_stat_cfg_st::reserved24
pseudo_bit_t reserved24[0x00001]
Definition: MT25408_PRM.h:1412
hermonprm_tptparams_st::dmpt_base_adr_l
pseudo_bit_t dmpt_base_adr_l[0x00020]
Definition: MT25408_PRM.h:548
hermonprm_mgmqp_st::qpn_i
pseudo_bit_t qpn_i[0x00018]
Definition: MT25408_PRM.h:402
hermonprm_eq_set_ci_table_st::eq13_set_ci
pseudo_bit_t eq13_set_ci[0x00020]
Definition: MT25408_PRM.h:1067
hermonprm_query_fw_st::fw_hour
pseudo_bit_t fw_hour[0x00008]
Definition: MT25408_PRM.h:2309
hermonprm_mgm_entry_st::mgid_128_96
pseudo_bit_t mgid_128_96[0x00020]
Definition: MT25408_PRM.h:1964
hermonprm_hermon_prm_st::qp_ee_state_transitions
struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions
Definition: MT25408_PRM.h:3161
hermonprm_vsd_st
Definition: MT25408_PRM.h:411
hermonprm_hermon_prm_st::udavtable_memory_parameters
struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters
Definition: MT25408_PRM.h:3249
hermonprm_transport_and_ci_error_counters_st::rq_num_mce
pseudo_bit_t rq_num_mce[0x00020]
Definition: MT25408_PRM.h:1677
hermonprm_wqe_segment_data_ptr_st::local_address_l
pseudo_bit_t local_address_l[0x00020]
Definition: MT25408_PRM.h:116
hermonprm_transport_and_ci_error_counters_st::reserved7
pseudo_bit_t reserved7[0x00020]
Definition: MT25408_PRM.h:1667
hermonprm_queue_pair_ee_context_entry_st::reserved37
pseudo_bit_t reserved37[0x00001]
Definition: MT25408_PRM.h:942
hermonprm_query_dev_cap_st::local_ca_ack_delay
pseudo_bit_t local_ca_ack_delay[0x00005]
Definition: MT25408_PRM.h:2114
hermonprm_hermon_prm_st::reserved63
pseudo_bit_t reserved63[0x00fc0]
Definition: MT25408_PRM.h:3397
hermonprm_send_wqe_segment_st::reserved0
pseudo_bit_t reserved0[0x00180]
Definition: MT25408_PRM.h:767
hermonprm_vsd_st::vsd_dw54
pseudo_bit_t vsd_dw54[0x00020]
Definition: MT25408_PRM.h:520
hermonprm_eq_set_ci_table_st::reserved1
pseudo_bit_t reserved1[0x00020]
Definition: MT25408_PRM.h:1021
hermonprm_wqe_segment_ctrl_mlx_st::reserved1
pseudo_bit_t reserved1[0x0001a]
Definition: MT25408_PRM.h:738
hermonprm_vsd_st::vsd_dw14
pseudo_bit_t vsd_dw14[0x00020]
Definition: MT25408_PRM.h:440
hermonprm_transport_and_ci_error_counters_st::sq_num_rae
pseudo_bit_t sq_num_rae[0x00020]
Definition: MT25408_PRM.h:1625
hermonprm_cq_arm_db_record_st::cmd
pseudo_bit_t cmd[0x00003]
Definition: MT25408_PRM.h:1297
hermonprm_eq_set_ci_table_st::reserved49
pseudo_bit_t reserved49[0x00020]
Definition: MT25408_PRM.h:1213
hermonprm_tptparams_st::reserved1
pseudo_bit_t reserved1[0x00013]
Definition: MT25408_PRM.h:558
hermonprm_wqe_segment_data_ptr_st
Definition: MT25408_PRM.h:108
hermonprm_srq_context_st::srqn
pseudo_bit_t srqn[0x00018]
Definition: MT25408_PRM.h:1477
hermonprm_eq_set_ci_table_st::reserved30
pseudo_bit_t reserved30[0x00020]
Definition: MT25408_PRM.h:1137
hermonprm_wqe_segment_ctrl_send_st::f
pseudo_bit_t f[0x00001]
Definition: MT25408_PRM.h:252
hermonprm_mcg_qps_st
Definition: MT25408_PRM.h:3059
hermonprm_mpt_st::atomic
pseudo_bit_t atomic[0x00001]
Definition: MT25408_PRM.h:2492
hermonprm_query_dev_cap_st::reserved35
pseudo_bit_t reserved35[0x00008]
Definition: MT25408_PRM.h:2192
hermonprm_multicastparam_st::reserved4
pseudo_bit_t reserved4[0x00013]
Definition: MT25408_PRM.h:605
hermonprm_query_fw_st::ccq
pseudo_bit_t ccq[0x00001]
Definition: MT25408_PRM.h:2305
hermonprm_qp_ee_state_transitions_st::reserved1
pseudo_bit_t reserved1[0x00800]
Definition: MT25408_PRM.h:2987
hermonprm_query_dev_cap_st::log_max_qp_sz
pseudo_bit_t log_max_qp_sz[0x00008]
Definition: MT25408_PRM.h:2056
hermonprm_performance_counters_st
Definition: MT25408_PRM.h:1546
hermonprm_ud_address_vector_st::reserved2
pseudo_bit_t reserved2[0x00004]
Definition: MT25408_PRM.h:55
hermonprm_sched_queue_context_st::sl
pseudo_bit_t sl[0x00004]
Definition: MT25408_PRM.h:3094
hermonprm_mpt_st::mtt_rep
pseudo_bit_t mtt_rep[0x00004]
Definition: MT25408_PRM.h:2530
hermonprm_ecc_detect_event_data_st::reserved1
pseudo_bit_t reserved1[0x00002]
Definition: MT25408_PRM.h:3107
hermonprm_send_wqe_segment_st::wqe_segment_remote_address
struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address
Definition: MT25408_PRM.h:769
hermonprm_hermon_prm_st::hcr_completion_event
struct hermonprm_hcr_completion_event_st hcr_completion_event
Definition: MT25408_PRM.h:3343
hermonprm_init_hca_st
Definition: MT25408_PRM.h:2365
hermonprm_query_fw_st::fw_month
pseudo_bit_t fw_month[0x00008]
Definition: MT25408_PRM.h:2312
hermonprm_wqe_segment_rd_st::destination_qp
pseudo_bit_t destination_qp[0x00018]
Definition: MT25408_PRM.h:235
hermonprm_mgm_entry_st::mgmqp_5
struct hermonprm_mgmqp_st mgmqp_5
Definition: MT25408_PRM.h:1986
hermonprm_vsd_st::vsd_dw41
pseudo_bit_t vsd_dw41[0x00020]
Definition: MT25408_PRM.h:494
hermonprm_mt25208_type0_st::capability_version
pseudo_bit_t capability_version[0x00004]
Definition: MT25408_PRM.h:2801
hermonprm_hca_command_register_st::reserved0
pseudo_bit_t reserved0[0x00010]
Definition: MT25408_PRM.h:346
hermonprm_mod_stat_cfg_st::reserved23
pseudo_bit_t reserved23[0x00002]
Definition: MT25408_PRM.h:1410
hermonprm_cq_arm_db_record_st
Definition: MT25408_PRM.h:1294
hermonprm_qp_ee_state_transitions_st::opt_param_mask
pseudo_bit_t opt_param_mask[0x00020]
Definition: MT25408_PRM.h:2981
hermonprm_init_port_st::guid0_h
pseudo_bit_t guid0_h[0x00020]
Definition: MT25408_PRM.h:2026
hermonprm_init_port_st::reserved0
pseudo_bit_t reserved0[0x00004]
Definition: MT25408_PRM.h:1997
hermonprm_mt25208_type0_st::msg_data
pseudo_bit_t msg_data[0x00010]
Definition: MT25408_PRM.h:2733
hermonprm_cq_cmd_doorbell_st::cqn
pseudo_bit_t cqn[0x00018]
Definition: MT25408_PRM.h:367
hermonprm_query_fw_st::error_buf_bar
pseudo_bit_t error_buf_bar[0x00002]
Definition: MT25408_PRM.h:2339
hermonprm_mod_stat_cfg_st::reserved39
pseudo_bit_t reserved39[0x00060]
Definition: MT25408_PRM.h:1460
hermonprm_mad_ifc_st::reserved7
pseudo_bit_t reserved7[0x004c0]
Definition: MT25408_PRM.h:1841
hermonprm_mt25208_type0_st::revision_id
pseudo_bit_t revision_id[0x00008]
Definition: MT25408_PRM.h:2674
hermonprm_qpcbaseaddr_st::reserved4
pseudo_bit_t reserved4[0x00040]
Definition: MT25408_PRM.h:658
hermonprm_send_wqe_segment_st::wqe_segment_data_inline
struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline
Definition: MT25408_PRM.h:779
hermonprm_query_fw_st::clr_int_base_offset_h
pseudo_bit_t clr_int_base_offset_h[0x00020]
Definition: MT25408_PRM.h:2317
hermonprm_mod_stat_cfg_st::sd_mux_main
pseudo_bit_t sd_mux_main[0x00002]
Definition: MT25408_PRM.h:1407
hermonprm_queue_pair_ee_context_entry_st::reserved38
pseudo_bit_t reserved38[0x00002]
Definition: MT25408_PRM.h:949
hermonprm_hermon_prm_st::reserved36
pseudo_bit_t reserved36[0x7fe00]
Definition: MT25408_PRM.h:3293
hermonprm_completion_queue_context_st::reserved16
pseudo_bit_t reserved16[0x00020]
Definition: MT25408_PRM.h:2623
hermonprm_init_hca_st::udp
pseudo_bit_t udp[0x00001]
Definition: MT25408_PRM.h:2381
hermonprm_hermon_prm_st::reserved46
pseudo_bit_t reserved46[0x7e6e0]
Definition: MT25408_PRM.h:3333
hermonprm_query_dev_cap_st::log2_rsvd_eqs
pseudo_bit_t log2_rsvd_eqs[0x00004]
Definition: MT25408_PRM.h:2079
hermonprm_hermon_prm_st::reserved5
pseudo_bit_t reserved5[0x7ff40]
Definition: MT25408_PRM.h:3179
hermonprm_mod_stat_cfg_st::lid_m
pseudo_bit_t lid_m[0x00001]
Definition: MT25408_PRM.h:1361
hermonprm_init_port_st::ng
pseudo_bit_t ng[0x00001]
Definition: MT25408_PRM.h:2007
hermonprm_mpt_st::reserved3
pseudo_bit_t reserved3[0x00007]
Definition: MT25408_PRM.h:2501
hermonprm_eqc_st::status
pseudo_bit_t status[0x00004]
Definition: MT25408_PRM.h:2426
hermonprm_transport_and_ci_error_counters_st::reserved12
pseudo_bit_t reserved12[0x002a0]
Definition: MT25408_PRM.h:1699
hermonprm_mpt_st::r_w
pseudo_bit_t r_w[0x00001]
Definition: MT25408_PRM.h:2486
hermonprm_eq_set_ci_table_st::reserved7
pseudo_bit_t reserved7[0x00020]
Definition: MT25408_PRM.h:1045
hermonprm_set_ib_st::reserved2
pseudo_bit_t reserved2[0x00180]
Definition: MT25408_PRM.h:1950
hermonprm_init_port_st::reserved2
pseudo_bit_t reserved2[0x0000d]
Definition: MT25408_PRM.h:2011
hermonprm_queue_pair_ee_context_entry_st::physical_function
pseudo_bit_t physical_function[0x00008]
Definition: MT25408_PRM.h:900
hermonprm_transport_and_ci_error_counters_st::sq_num_rree
pseudo_bit_t sq_num_rree[0x00020]
Definition: MT25408_PRM.h:1651
hermonprm_query_dev_cap_st::log2_rsvd_mrws
pseudo_bit_t log2_rsvd_mrws[0x00004]
Definition: MT25408_PRM.h:2089
hermonprm_eq_set_ci_table_st::eq51_set_ci
pseudo_bit_t eq51_set_ci[0x00020]
Definition: MT25408_PRM.h:1219
hermonprm_query_dev_cap_st::fcp_ud_base_23_8
pseudo_bit_t fcp_ud_base_23_8[0x00010]
Definition: MT25408_PRM.h:2200
hermonprm_eqc_st::consumer_counter
pseudo_bit_t consumer_counter[0x00018]
Definition: MT25408_PRM.h:2457
hermonprm_mad_ifc_st::my_qpn
pseudo_bit_t my_qpn[0x00018]
Definition: MT25408_PRM.h:1812
hermonprm_query_debug_msg_st::reserved4
pseudo_bit_t reserved4[0x003c0]
Definition: MT25408_PRM.h:1900
hermonprm_wqe_segment_ctrl_mlx_st::reserved5
pseudo_bit_t reserved5[0x00010]
Definition: MT25408_PRM.h:751
hermonprm_mpt_st::reserved10
pseudo_bit_t reserved10[0x0000b]
Definition: MT25408_PRM.h:2548
hermonprm_qpcbaseaddr_st::reserved8
pseudo_bit_t reserved8[0x00040]
Definition: MT25408_PRM.h:685
hermonprm_address_path_st::dmac_47_32
pseudo_bit_t dmac_47_32[0x00010]
Definition: MT25408_PRM.h:324
hermonprm_eqc_st::reserved10
pseudo_bit_t reserved10[0x00002]
Definition: MT25408_PRM.h:2450
hermonprm_mt25208_type0_st::expansion_rom_enable
pseudo_bit_t expansion_rom_enable[0x00001]
Definition: MT25408_PRM.h:2705
hermonprm_wqe_segment_remote_address_st::reserved0
pseudo_bit_t reserved0[0x00020]
Definition: MT25408_PRM.h:184
hermonprm_tptparams_st::reserved0
pseudo_bit_t reserved0[0x00002]
Definition: MT25408_PRM.h:554
hermonprm_wqe_segment_rd_st::q_key
pseudo_bit_t q_key[0x00020]
Definition: MT25408_PRM.h:238
hermonprm_mgm_entry_st::mgid_63_32
pseudo_bit_t mgid_63_32[0x00020]
Definition: MT25408_PRM.h:1970
hermonprm_init_port_st::node_guid_l
pseudo_bit_t node_guid_l[0x00020]
Definition: MT25408_PRM.h:2033
hermonprm_query_fw_st::reserved6
pseudo_bit_t reserved6[0x00020]
Definition: MT25408_PRM.h:2330
hermonprm_mod_stat_cfg_st::nodeguid_hi
pseudo_bit_t nodeguid_hi[0x00020]
Definition: MT25408_PRM.h:1384
hermonprm_qp_ee_event_st::reserved4
pseudo_bit_t reserved4[0x00060]
Definition: MT25408_PRM.h:2658
hermonprm_performance_monitors_st::reserved2
pseudo_bit_t reserved2[0x00001]
Definition: MT25408_PRM.h:712
hermonprm_eq_set_ci_table_st::eq18_set_ci
pseudo_bit_t eq18_set_ci[0x00020]
Definition: MT25408_PRM.h:1087
hermonprm_qpcbaseaddr_st
Definition: MT25408_PRM.h:618
hermonprm_eq_set_ci_table_st::eq33_set_ci
pseudo_bit_t eq33_set_ci[0x00020]
Definition: MT25408_PRM.h:1147
hermonprm_hermon_prm_st::query_dev_cap
struct hermonprm_query_dev_cap_st query_dev_cap
Definition: MT25408_PRM.h:3279
hermonprm_virtual_physical_mapping_st::log2size
pseudo_bit_t log2size[0x00006]
Definition: MT25408_PRM.h:1329
hermonprm_send_wqe_segment_st::wqe_segment_rd
struct hermonprm_wqe_segment_rd_st wqe_segment_rd
Definition: MT25408_PRM.h:761
hermonprm_eqc_st::page_offset
pseudo_bit_t page_offset[0x00007]
Definition: MT25408_PRM.h:2434
hermonprm_mt25208_type0_st::interrupt_pin
pseudo_bit_t interrupt_pin[0x00008]
Definition: MT25408_PRM.h:2715
hermonprm_init_hca_st::reserved6
pseudo_bit_t reserved6[0x00040]
Definition: MT25408_PRM.h:2392
hermonprm_wqe_segment_ctrl_send_st::immediate
pseudo_bit_t immediate[0x00020]
Definition: MT25408_PRM.h:264
hermonprm_wqe_segment_st
Definition: MT25408_PRM.h:2904
hermonprm_send_doorbell_st
Definition: MT25408_PRM.h:79
hermonprm_query_fw_st::fw_rev_subminor
pseudo_bit_t fw_rev_subminor[0x00010]
Definition: MT25408_PRM.h:2293
hermonprm_wqe_segment_data_inline_st::byte_count
pseudo_bit_t byte_count[0x0000a]
Definition: MT25408_PRM.h:95
hermonprm_init_port_st::mtu
pseudo_bit_t mtu[0x00010]
Definition: MT25408_PRM.h:2014
hermonprm_hermon_prm_st::address_path
struct hermonprm_address_path_st address_path
Definition: MT25408_PRM.h:3213
hermonprm_completion_queue_entry_st::ml_path_mac_index
pseudo_bit_t ml_path_mac_index[0x00007]
Definition: MT25408_PRM.h:3016
hermonprm_mod_stat_cfg_st::ob_preemp_pre
pseudo_bit_t ob_preemp_pre[0x00005]
Definition: MT25408_PRM.h:1391
hermonprm_fast_registration_segment_st::reg_len_h
pseudo_bit_t reg_len_h[0x00020]
Definition: MT25408_PRM.h:156
hermonprm_mpt_st::w_dif
pseudo_bit_t w_dif[0x00001]
Definition: MT25408_PRM.h:2513
hermonprm_srq_context_st::mtt_base_addr_h
pseudo_bit_t mtt_base_addr_h[0x00008]
Definition: MT25408_PRM.h:1497
hermonprm_transport_and_ci_error_counters_st::rq_num_lpe
pseudo_bit_t rq_num_lpe[0x00020]
Definition: MT25408_PRM.h:1574
hermonprm_queue_pair_ee_context_entry_st::reserved40
pseudo_bit_t reserved40[0x00002]
Definition: MT25408_PRM.h:958
hermonprm_event_queue_entry_st
Definition: MT25408_PRM.h:2961
hermonprm_queue_pair_ee_context_entry_st::primary_address_path
struct hermonprm_address_path_st primary_address_path
Definition: MT25408_PRM.h:849
hermonprm_query_dev_cap_st::log_max_qp_mcg
pseudo_bit_t log_max_qp_mcg[0x00008]
Definition: MT25408_PRM.h:2210
hermonprm_completion_queue_context_st::reserved14
pseudo_bit_t reserved14[0x00008]
Definition: MT25408_PRM.h:2619
hermonprm_qpcbaseaddr_st::cqc_base_addr_l
pseudo_bit_t cqc_base_addr_l[0x0001b]
Definition: MT25408_PRM.h:645
hermonprm_pbl_st::mtt_0_l
pseudo_bit_t mtt_0_l[0x00020]
Definition: MT25408_PRM.h:1528
hermonprm_mod_stat_cfg_st::tx_options_m
pseudo_bit_t tx_options_m[0x00001]
Definition: MT25408_PRM.h:1348
hermonprm_eq_set_ci_table_st::reserved29
pseudo_bit_t reserved29[0x00020]
Definition: MT25408_PRM.h:1133
hermonprm_mpt_st::nce
pseudo_bit_t nce[0x00001]
Definition: MT25408_PRM.h:2510
hermonprm_query_dev_cap_st::fcoib
pseudo_bit_t fcoib[0x00001]
Definition: MT25408_PRM.h:2150
hermonprm_mod_stat_cfg_st::nodeguid_hi_m
pseudo_bit_t nodeguid_hi_m[0x00001]
Definition: MT25408_PRM.h:1382
hermonprm_address_path_st::rgid_127_96
pseudo_bit_t rgid_127_96[0x00020]
Definition: MT25408_PRM.h:307
hermonprm_query_adapter_st
Definition: MT25408_PRM.h:2274
hermonprm_resize_cq_st::reserved6
pseudo_bit_t reserved6[0x00010]
Definition: MT25408_PRM.h:1782
hermonprm_uar_params_st::uar_page_sz
pseudo_bit_t uar_page_sz[0x00008]
Definition: MT25408_PRM.h:531
hermonprm_query_dev_cap_st::reserved5
pseudo_bit_t reserved5[0x00007]
Definition: MT25408_PRM.h:2064
hermonprm_vsd_st::vsd_dw5
pseudo_bit_t vsd_dw5[0x00020]
Definition: MT25408_PRM.h:422
hermonprm_completion_queue_entry_st::owner
pseudo_bit_t owner[0x00001]
Definition: MT25408_PRM.h:3051
hermonprm_mod_stat_cfg_st::reserved32
pseudo_bit_t reserved32[0x00060]
Definition: MT25408_PRM.h:1438
hermonprm_mod_stat_cfg_st::lid
pseudo_bit_t lid[0x00010]
Definition: MT25408_PRM.h:1360
hermonprm_mad_ifc_st::reserved5
pseudo_bit_t reserved5[0x00010]
Definition: MT25408_PRM.h:1833
hermonprm_ecc_detect_event_data_st::err_da
pseudo_bit_t err_da[0x00002]
Definition: MT25408_PRM.h:3112
hermonprm_set_ib_st::system_image_guid_h
pseudo_bit_t system_image_guid_h[0x00020]
Definition: MT25408_PRM.h:1944
hermonprm_queue_pair_ee_context_entry_st::last_acked_psn
pseudo_bit_t last_acked_psn[0x00018]
Definition: MT25408_PRM.h:879
hermonprm_query_dev_cap_st::reserved47
pseudo_bit_t reserved47[0x00004]
Definition: MT25408_PRM.h:2112
hermonprm_queue_pair_ee_context_entry_st::vft_prio
pseudo_bit_t vft_prio[0x00003]
Definition: MT25408_PRM.h:964
hermonprm_completion_queue_context_st::c_eqn
pseudo_bit_t c_eqn[0x00009]
Definition: MT25408_PRM.h:2590
hermonprm_qpcbaseaddr_st::rdmardc_base_addr_h
pseudo_bit_t rdmardc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:678
hermonprm_queue_pair_ee_context_entry_st::reserved28
pseudo_bit_t reserved28[0x00005]
Definition: MT25408_PRM.h:897
hermonprm_mt25208_type0_st::bar1_l
pseudo_bit_t bar1_l[0x0000c]
Definition: MT25408_PRM.h:2690
hermonprm_address_path_st::grh_ip
pseudo_bit_t grh_ip[0x00001]
Definition: MT25408_PRM.h:279
hermonprm_mod_stat_cfg_st::reserved19
pseudo_bit_t reserved19[0x00001]
Definition: MT25408_PRM.h:1402
hermonprm_init_port_st::g0
pseudo_bit_t g0[0x00001]
Definition: MT25408_PRM.h:2006
hermonprm_completion_queue_entry_st::sl
pseudo_bit_t sl[0x00004]
Definition: MT25408_PRM.h:3027
hermonprm_query_dev_cap_st::vmm
pseudo_bit_t vmm[0x00001]
Definition: MT25408_PRM.h:2156
hermonprm_vsd_st::vsd_dw8
pseudo_bit_t vsd_dw8[0x00020]
Definition: MT25408_PRM.h:428
hermonprm_fast_registration_segment_st::start_address_h
pseudo_bit_t start_address_h[0x00020]
Definition: MT25408_PRM.h:152
hermonprm_eq_set_ci_table_st::eq17_set_ci
pseudo_bit_t eq17_set_ci[0x00020]
Definition: MT25408_PRM.h:1083
hermonprm_mod_stat_cfg_st::reserved8
pseudo_bit_t reserved8[0x00002]
Definition: MT25408_PRM.h:1365
hermonprm_query_dev_cap_st::rsz_srq
pseudo_bit_t rsz_srq[0x00001]
Definition: MT25408_PRM.h:2108
hermonprm_eq_set_ci_table_st::eq53_set_ci
pseudo_bit_t eq53_set_ci[0x00020]
Definition: MT25408_PRM.h:1227
hermonprm_eq_set_ci_table_st::reserved63
pseudo_bit_t reserved63[0x00020]
Definition: MT25408_PRM.h:1269
hermonprm_performance_monitors_st::r0
pseudo_bit_t r0[0x00001]
Definition: MT25408_PRM.h:705
hermonprm_queue_pair_ee_context_entry_st::retry_count
pseudo_bit_t retry_count[0x00003]
Definition: MT25408_PRM.h:863
hermonprm_transport_and_ci_error_counters_st::sq_num_leeoe
pseudo_bit_t sq_num_leeoe[0x00020]
Definition: MT25408_PRM.h:1572
hermonprm_fast_registration_segment_st::page_size
pseudo_bit_t page_size[0x00005]
Definition: MT25408_PRM.h:146
hermonprm_query_debug_msg_st::v
pseudo_bit_t v[0x00001]
Definition: MT25408_PRM.h:1850
hermonprm_page_fault_event_data_st::qp
pseudo_bit_t qp[0x00018]
Definition: MT25408_PRM.h:2887
hermonprm_qp_db_record_st
Definition: MT25408_PRM.h:1286
hermonprm_uar_params_st
Definition: MT25408_PRM.h:528
hermonprm_query_dev_cap_st::log_max_srcds
pseudo_bit_t log_max_srcds[0x00004]
Definition: MT25408_PRM.h:2213
hermonprm_hermon_prm_st::reserved59
pseudo_bit_t reserved59[0x00020]
Definition: MT25408_PRM.h:3385
hermonprm_query_debug_msg_st::hw_buff_size
pseudo_bit_t hw_buff_size[0x00020]
Definition: MT25408_PRM.h:1898
hermonprm_query_fw_st::error_buf_offset_l
pseudo_bit_t error_buf_offset_l[0x00020]
Definition: MT25408_PRM.h:2334
hermonprm_ud_address_vector_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:47
hermonprm_clr_int_st
Definition: MT25408_PRM.h:1000
hermonprm_mod_stat_cfg_st::reserved18
pseudo_bit_t reserved18[0x00002]
Definition: MT25408_PRM.h:1398
hermonprm_address_path_st
Definition: MT25408_PRM.h:270
hermonprm_queue_pair_ee_context_entry_st::hs
pseudo_bit_t hs[0x00001]
Definition: MT25408_PRM.h:940
hermonprm_query_dev_cap_st::log_drain_size
pseudo_bit_t log_drain_size[0x00008]
Definition: MT25408_PRM.h:2126
hermonprm_completion_queue_context_st::reserved4
pseudo_bit_t reserved4[0x00005]
Definition: MT25408_PRM.h:2578
hermonprm_query_dev_cap_st::reserved11
pseudo_bit_t reserved11[0x00002]
Definition: MT25408_PRM.h:2084
hermonprm_query_debug_msg_st::buff2_size
pseudo_bit_t buff2_size[0x00020]
Definition: MT25408_PRM.h:1880
hermonprm_mpt_st::start_addr_l
pseudo_bit_t start_addr_l[0x00020]
Definition: MT25408_PRM.h:2519
hermonprm_queue_pair_ee_context_entry_st::reserved41
pseudo_bit_t reserved41[0x00003]
Definition: MT25408_PRM.h:960
hermonprm_mpt_st::win_cnt
pseudo_bit_t win_cnt[0x00018]
Definition: MT25408_PRM.h:2527
hermonprm_queue_pair_ee_context_entry_st::is
pseudo_bit_t is[0x00001]
Definition: MT25408_PRM.h:941
hermonprm_ecc_detect_event_data_st::reserved0
pseudo_bit_t reserved0[0x00080]
Definition: MT25408_PRM.h:3104
hermonprm_mpt_st::en_rinv
pseudo_bit_t en_rinv[0x00001]
Definition: MT25408_PRM.h:2508
hermonprm_tptparams_st::dmpt_base_adr_h
pseudo_bit_t dmpt_base_adr_h[0x00020]
Definition: MT25408_PRM.h:543
hermonprm_wqe_segment_ud_st::destination_qp
pseudo_bit_t destination_qp[0x00018]
Definition: MT25408_PRM.h:223
hermonprm_query_dev_cap_st::reserved42
pseudo_bit_t reserved42[0x00007]
Definition: MT25408_PRM.h:2219
hermonprm_queue_pair_ee_context_entry_st::page_offset
pseudo_bit_t page_offset[0x00006]
Definition: MT25408_PRM.h:892
hermonprm_query_dev_cap_st
Definition: MT25408_PRM.h:2048
hermonprm_query_dev_cap_st::log_max_ra_res_global
pseudo_bit_t log_max_ra_res_global[0x00006]
Definition: MT25408_PRM.h:2105
hermonprm_init_port_st::port_width_cap
pseudo_bit_t port_width_cap[0x00004]
Definition: MT25408_PRM.h:2000
hermonprm_wqe_segment_ud_st::q_key
pseudo_bit_t q_key[0x00020]
Definition: MT25408_PRM.h:226
hermonprm_mpt_st::fre
pseudo_bit_t fre[0x00001]
Definition: MT25408_PRM.h:2511
hermonprm_hermon_prm_st::reserved22
pseudo_bit_t reserved22[0x7fc00]
Definition: MT25408_PRM.h:3247
hermonprm_cq_cmd_doorbell_st::reserved0
pseudo_bit_t reserved0[0x00001]
Definition: MT25408_PRM.h:374
hermonprm_send_wqe_segment_st::reserved1
pseudo_bit_t reserved1[0x00200]
Definition: MT25408_PRM.h:781
hermonprm_queue_pair_ee_context_entry_st::alternative_address_path
struct hermonprm_address_path_st alternative_address_path
Definition: MT25408_PRM.h:851
hermonprm_query_dev_cap_st::reserved43
pseudo_bit_t reserved43[0x000c0]
Definition: MT25408_PRM.h:2224
hermonprm_performance_monitors_st::r2
pseudo_bit_t r2[0x00001]
Definition: MT25408_PRM.h:707
hermonprm_eq_set_ci_table_st::eq44_set_ci
pseudo_bit_t eq44_set_ci[0x00020]
Definition: MT25408_PRM.h:1191
hermonprm_uar_st::cq_command_doorbell
struct hermonprm_cq_cmd_doorbell_st cq_command_doorbell
Definition: MT25408_PRM.h:1913
hermonprm_mod_stat_cfg_st::port_dual
pseudo_bit_t port_dual[0x00001]
Definition: MT25408_PRM.h:1417
hermonprm_eq_set_ci_table_st::eq3_set_ci
pseudo_bit_t eq3_set_ci[0x00020]
Definition: MT25408_PRM.h:1027
hermonprm_mt25208_type0_st::bar2_ctrl
pseudo_bit_t bar2_ctrl[0x00004]
Definition: MT25408_PRM.h:2694
hermonprm_mpt_st::len_h
pseudo_bit_t len_h[0x00020]
Definition: MT25408_PRM.h:2521
hermonprm_completion_queue_entry_st::slid_smac47_32
pseudo_bit_t slid_smac47_32[0x00010]
Definition: MT25408_PRM.h:3023
hermonprm_hermon_prm_st::reserved30
pseudo_bit_t reserved30[0x7ff00]
Definition: MT25408_PRM.h:3269
hermonprm_srq_context_st::src_domain
pseudo_bit_t src_domain[0x00010]
Definition: MT25408_PRM.h:1486
hermonprm_queue_pair_ee_context_entry_st::mtt_base_addr_h
pseudo_bit_t mtt_base_addr_h[0x00008]
Definition: MT25408_PRM.h:955
hermonprm_query_fw_st::clr_int_base_offset_l
pseudo_bit_t clr_int_base_offset_l[0x00020]
Definition: MT25408_PRM.h:2319
hermonprm_completion_queue_context_st::log_cq_size
pseudo_bit_t log_cq_size[0x00005]
Definition: MT25408_PRM.h:2583
hermonprm_init_hca_st::reserved2
pseudo_bit_t reserved2[0x00010]
Definition: MT25408_PRM.h:2371
hermonprm_eq_set_ci_table_st::eq28_set_ci
pseudo_bit_t eq28_set_ci[0x00020]
Definition: MT25408_PRM.h:1127
hermonprm_eq_set_ci_table_st::eq42_set_ci
pseudo_bit_t eq42_set_ci[0x00020]
Definition: MT25408_PRM.h:1183
hermonprm_vsd_st::vsd_dw33
pseudo_bit_t vsd_dw33[0x00020]
Definition: MT25408_PRM.h:478
hermonprm_qp_ee_event_st::reserved2
pseudo_bit_t reserved2[0x0001c]
Definition: MT25408_PRM.h:2653
hermonprm_mod_stat_cfg_st::port_protocol_m
pseudo_bit_t port_protocol_m[0x00001]
Definition: MT25408_PRM.h:1419
hermonprm_completion_queue_context_st::reserved8
pseudo_bit_t reserved8[0x00010]
Definition: MT25408_PRM.h:2596
hermonprm_hermon_prm_st::mad_ifc
struct hermonprm_mad_ifc_st mad_ifc
Definition: MT25408_PRM.h:3327
hermonprm_query_dev_cap_st::num_rsvd_scqs
pseudo_bit_t num_rsvd_scqs[0x00006]
Definition: MT25408_PRM.h:2061
hermonprm_queue_pair_ee_context_entry_st::log2_page_size
pseudo_bit_t log2_page_size[0x00006]
Definition: MT25408_PRM.h:957
hermonprm_srq_context_st::lwm
pseudo_bit_t lwm[0x00010]
Definition: MT25408_PRM.h:1509
hermonprm_query_debug_msg_st::buff0_addr
pseudo_bit_t buff0_addr[0x00020]
Definition: MT25408_PRM.h:1870
hermonprm_mpt_st::entity_size
pseudo_bit_t entity_size[0x00015]
Definition: MT25408_PRM.h:2544
hermonprm_queue_pair_ee_context_entry_st::reserved46
pseudo_bit_t reserved46[0x00008]
Definition: MT25408_PRM.h:977
hermonprm_hermon_prm_st::reserved12
pseudo_bit_t reserved12[0x7ff00]
Definition: MT25408_PRM.h:3207
hermonprm_queue_pair_ee_context_entry_st::reserved24
pseudo_bit_t reserved24[0x00008]
Definition: MT25408_PRM.h:883
hermonprm_pbl_st::mtt_1_h
pseudo_bit_t mtt_1_h[0x00020]
Definition: MT25408_PRM.h:1530
hermonprm_hermon_prm_st::reserved14
pseudo_bit_t reserved14[0x7fea0]
Definition: MT25408_PRM.h:3215
hermonprm_mpt_st::pd
pseudo_bit_t pd[0x00018]
Definition: MT25408_PRM.h:2507
hermonprm_ud_address_vector_st::hop_limit
pseudo_bit_t hop_limit[0x00008]
Definition: MT25408_PRM.h:49
hermonprm_wqe_segment_remote_address_st
Definition: MT25408_PRM.h:177
hermonprm_mt25208_type0_st::device_control
pseudo_bit_t device_control[0x00010]
Definition: MT25408_PRM.h:2783
hermonprm_rd_send_doorbell_st::een
pseudo_bit_t een[0x00018]
Definition: MT25408_PRM.h:389
hermonprm_mt25208_type0_st::next_capability_offset
pseudo_bit_t next_capability_offset[0x0000c]
Definition: MT25408_PRM.h:2802
hermonprm_query_dev_cap_st::src
pseudo_bit_t src[0x00001]
Definition: MT25408_PRM.h:2148
hermonprm_local_invalidate_segment_st::reserved0
pseudo_bit_t reserved0[0x00040]
Definition: MT25408_PRM.h:123
hermonprm_wqe_segment_st::recv_wqe_segment_ctrl
pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020]
Definition: MT25408_PRM.h:2913
hermonprm_vsd_st::vsd_dw4
pseudo_bit_t vsd_dw4[0x00020]
Definition: MT25408_PRM.h:420
hermonprm_srq_context_st::reserved6
pseudo_bit_t reserved6[0x00003]
Definition: MT25408_PRM.h:1502
hermonprm_eq_set_ci_table_st::eq25_set_ci
pseudo_bit_t eq25_set_ci[0x00020]
Definition: MT25408_PRM.h:1115
hermonprm_wqe_segment_bind_st::reserved1
pseudo_bit_t reserved1[0x0001e]
Definition: MT25408_PRM.h:197
hermonprm_query_debug_msg_st::buff3_addr
pseudo_bit_t buff3_addr[0x00020]
Definition: MT25408_PRM.h:1882
hermonprm_mt25208_type0_st::uncorrectable_error_mask_register
pseudo_bit_t uncorrectable_error_mask_register[0x00020]
Definition: MT25408_PRM.h:2816
hermonprm_srq_context_st::reserved7
pseudo_bit_t reserved7[0x00008]
Definition: MT25408_PRM.h:1506
hermonprm_local_invalidate_segment_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:126
hermonprm_mt25208_type0_st::reserved11
pseudo_bit_t reserved11[0x00040]
Definition: MT25408_PRM.h:2762
hermonprm_queue_pair_ee_context_entry_st::reserved13
pseudo_bit_t reserved13[0x00003]
Definition: MT25408_PRM.h:853
hermonprm_hcr_completion_event_st::reserved2
pseudo_bit_t reserved2[0x00018]
Definition: MT25408_PRM.h:1712
hermonprm_mt25208_type0_st::device_id
pseudo_bit_t device_id[0x00010]
Definition: MT25408_PRM.h:2666
hermonprm_mod_stat_cfg_st::rx_options
pseudo_bit_t rx_options[0x00004]
Definition: MT25408_PRM.h:1343
hermonprm_completion_queue_context_st::status
pseudo_bit_t status[0x00004]
Definition: MT25408_PRM.h:2570
hermonprm_eq_set_ci_table_st::reserved26
pseudo_bit_t reserved26[0x00020]
Definition: MT25408_PRM.h:1121
hermonprm_completion_event_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:2953
hermonprm_sched_queue_context_st::vl15
pseudo_bit_t vl15[0x00001]
Definition: MT25408_PRM.h:3093
hermonprm_query_dev_cap_st::srq
pseudo_bit_t srq[0x00001]
Definition: MT25408_PRM.h:2151
hermonprm_mcg_qp_dw_st
Definition: MT25408_PRM.h:990
hermonprm_eq_set_ci_table_st::eq7_set_ci
pseudo_bit_t eq7_set_ci[0x00020]
Definition: MT25408_PRM.h:1043
hermonprm_address_path_st::fl
pseudo_bit_t fl[0x00001]
Definition: MT25408_PRM.h:275
hermonprm_hermon_prm_st::hca_command_register
struct hermonprm_hca_command_register_st hca_command_register
Definition: MT25408_PRM.h:3237
hermonprm_completion_event_st
Definition: MT25408_PRM.h:2951
hermonprm_transport_and_ci_error_counters_st::reserved1
pseudo_bit_t reserved1[0x00020]
Definition: MT25408_PRM.h:1588
hermonprm_hermon_prm_st::page_fault_event_data
struct hermonprm_page_fault_event_data_st page_fault_event_data
Definition: MT25408_PRM.h:3185
hermonprm_mt25208_type0_st::msi_en
pseudo_bit_t msi_en[0x00001]
Definition: MT25408_PRM.h:2723
hermonprm_query_dev_cap_st::bf
pseudo_bit_t bf[0x00001]
Definition: MT25408_PRM.h:2188
hermonprm_mpt_st::lkey
pseudo_bit_t lkey[0x00020]
Definition: MT25408_PRM.h:2525
hermonprm_eqc_st::log_eq_size
pseudo_bit_t log_eq_size[0x00005]
Definition: MT25408_PRM.h:2438
hermonprm_vsd_st::vsd_dw27
pseudo_bit_t vsd_dw27[0x00020]
Definition: MT25408_PRM.h:466
hermonprm_tptparams_st::pfto
pseudo_bit_t pfto[0x00005]
Definition: MT25408_PRM.h:555
hermonprm_transport_and_ci_error_counters_st::sq_num_lqpoe
pseudo_bit_t sq_num_lqpoe[0x00020]
Definition: MT25408_PRM.h:1568
hermonprm_mod_stat_cfg_st
Definition: MT25408_PRM.h:1337
hermonprm_multicastparam_st::log_mc_table_entry_sz
pseudo_bit_t log_mc_table_entry_sz[0x00005]
Definition: MT25408_PRM.h:593
hermonprm_wqe_segment_ud_st::ud_address_vector
struct hermonprm_ud_address_vector_st ud_address_vector
Definition: MT25408_PRM.h:221
hermonprm_query_dev_cap_st::srq_entry_sz
pseudo_bit_t srq_entry_sz[0x00010]
Definition: MT25408_PRM.h:2242
hermonprm_query_debug_msg_st::buff3_size
pseudo_bit_t buff3_size[0x00020]
Definition: MT25408_PRM.h:1884
hermonprm_mt25208_type0_st::subsystem_vendor_id
pseudo_bit_t subsystem_vendor_id[0x00010]
Definition: MT25408_PRM.h:2702
hermonprm_cq_cmd_doorbell_st::reserved1
pseudo_bit_t reserved1[0x00002]
Definition: MT25408_PRM.h:379
hermonprm_query_debug_msg_st::hw_buff_addr
pseudo_bit_t hw_buff_addr[0x00020]
Definition: MT25408_PRM.h:1896
hermonprm_wqe_segment_ctrl_send_st::opcode
pseudo_bit_t opcode[0x00005]
Definition: MT25408_PRM.h:247
hermonprm_hermon_prm_st::eq_set_ci_table
struct hermonprm_eq_set_ci_table_st eq_set_ci_table
Definition: MT25408_PRM.h:3391
hermonprm_queue_pair_ee_context_entry_st::ve
pseudo_bit_t ve[0x00001]
Definition: MT25408_PRM.h:968
hermonprm_queue_pair_ee_context_entry_st::cs_ctl
pseudo_bit_t cs_ctl[0x00009]
Definition: MT25408_PRM.h:966
hermonprm_query_dev_cap_st::reserved46
pseudo_bit_t reserved46[0x002c0]
Definition: MT25408_PRM.h:2268
hermonprm_transport_and_ci_error_counters_st::reserved6
pseudo_bit_t reserved6[0x00020]
Definition: MT25408_PRM.h:1663
hermonprm_mt25208_type0_st::header_log_register
struct hermonprm_header_log_register_st header_log_register
Definition: MT25408_PRM.h:2854
hermonprm_hca_command_register_st::out_param_l
pseudo_bit_t out_param_l[0x00020]
Definition: MT25408_PRM.h:344
hermonprm_eqc_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:2415
hermonprm_hca_command_register_st::t
pseudo_bit_t t[0x00001]
Definition: MT25408_PRM.h:352
hermonprm_init_port_st::vl_cap
pseudo_bit_t vl_cap[0x00004]
Definition: MT25408_PRM.h:1998
hermonprm_fast_registration_segment_st::reserved0
pseudo_bit_t reserved0[0x0001b]
Definition: MT25408_PRM.h:135
hermonprm_address_path_st::cv
pseudo_bit_t cv[0x00001]
Definition: MT25408_PRM.h:274
hermonprm_performance_monitors_st::f2
pseudo_bit_t f2[0x00001]
Definition: MT25408_PRM.h:715
hermonprm_mt25208_type0_st::msg_addr_l
pseudo_bit_t msg_addr_l[0x00020]
Definition: MT25408_PRM.h:2729
hermonprm_queue_pair_ee_context_entry_st::reserved20
pseudo_bit_t reserved20[0x00008]
Definition: MT25408_PRM.h:872
hermonprm_receive_doorbell_st::reserved2
pseudo_bit_t reserved2[0x00005]
Definition: MT25408_PRM.h:1926
hermonprm_queue_pair_ee_context_entry_st::reserved7
pseudo_bit_t reserved7[0x00003]
Definition: MT25408_PRM.h:819
hermonprm_query_debug_msg_st::phy_addr_h
pseudo_bit_t phy_addr_h[0x00020]
Definition: MT25408_PRM.h:1848
hermonprm_ud_address_vector_st::reserved3
pseudo_bit_t reserved3[0x00009]
Definition: MT25408_PRM.h:61
hermonprm_query_adapter_st::vsd
struct hermonprm_vsd_st vsd
Definition: MT25408_PRM.h:2282
hermonprm_mod_stat_cfg_st::port_eth_mode_capability
pseudo_bit_t port_eth_mode_capability[0x0001f]
Definition: MT25408_PRM.h:1462
hermonprm_eq_set_ci_table_st::eq19_set_ci
pseudo_bit_t eq19_set_ci[0x00020]
Definition: MT25408_PRM.h:1091
hermonprm_vsd_st::vsd_dw15
pseudo_bit_t vsd_dw15[0x00020]
Definition: MT25408_PRM.h:442
hermonprm_init_hca_st::router_qp
pseudo_bit_t router_qp[0x00018]
Definition: MT25408_PRM.h:2374
hermonprm_resize_cq_st::reserved9
pseudo_bit_t reserved9[0x00020]
Definition: MT25408_PRM.h:1789
hermonprm_eq_set_ci_table_st::reserved38
pseudo_bit_t reserved38[0x00020]
Definition: MT25408_PRM.h:1169
hermonprm_mod_stat_cfg_st::dife_m
pseudo_bit_t dife_m[0x00001]
Definition: MT25408_PRM.h:1342
hermonprm_performance_counters_st::reserved4
pseudo_bit_t reserved4[0x00620]
Definition: MT25408_PRM.h:1555
hermonprm_wqe_segment_ctrl_send_st::tcp_udp
pseudo_bit_t tcp_udp[0x00001]
Definition: MT25408_PRM.h:259
hermonprm_vsd_st::vsd_dw20
pseudo_bit_t vsd_dw20[0x00020]
Definition: MT25408_PRM.h:452
hermonprm_multicastparam_st::uc_group_steering
pseudo_bit_t uc_group_steering[0x00001]
Definition: MT25408_PRM.h:609
hermonprm_query_dev_cap_st::blh
pseudo_bit_t blh[0x00001]
Definition: MT25408_PRM.h:2161
hermonprm_hermon_prm_st::completion_event
struct hermonprm_completion_event_st completion_event
Definition: MT25408_PRM.h:3169
hermonprm_eq_set_ci_table_st::reserved13
pseudo_bit_t reserved13[0x00020]
Definition: MT25408_PRM.h:1069
hermonprm_mod_stat_cfg_st::port_net_boot
pseudo_bit_t port_net_boot[0x00001]
Definition: MT25408_PRM.h:1456
hermonprm_mod_stat_cfg_st::sigdet_th
pseudo_bit_t sigdet_th[0x00003]
Definition: MT25408_PRM.h:1411
hermonprm_completion_queue_context_st::reserved17
pseudo_bit_t reserved17[0x00003]
Definition: MT25408_PRM.h:2627
hermonprm_query_debug_msg_st::reserved3
pseudo_bit_t reserved3[0x00080]
Definition: MT25408_PRM.h:1894
hermonprm_ud_address_vector_st::reserved0
pseudo_bit_t reserved0[0x00005]
Definition: MT25408_PRM.h:41
hermonprm_hermon_prm_st::reserved29
pseudo_bit_t reserved29[0x00100]
Definition: MT25408_PRM.h:3267
hermonprm_gpio_event_data_st
Definition: MT25408_PRM.h:2634
hermonprm_queue_pair_ee_context_entry_st::fre
pseudo_bit_t fre[0x00001]
Definition: MT25408_PRM.h:860
hermonprm_wqe_segment_ctrl_send_st::reserved0
pseudo_bit_t reserved0[0x0001a]
Definition: MT25408_PRM.h:248
hermonprm_hermon_prm_st::eqc
struct hermonprm_eqc_st eqc
Definition: MT25408_PRM.h:3229
hermonprm_mgm_entry_st::mgmqp_1
struct hermonprm_mgmqp_st mgmqp_1
Definition: MT25408_PRM.h:1978
hermonprm_queue_pair_ee_context_entry_st::remote_qpn_een
pseudo_bit_t remote_qpn_een[0x00018]
Definition: MT25408_PRM.h:846
hermonprm_scrubbing_event_st::reserved3
pseudo_bit_t reserved3[0x00011]
Definition: MT25408_PRM.h:3139
hermonprm_mpt_st::reserved9
pseudo_bit_t reserved9[0x0000b]
Definition: MT25408_PRM.h:2545
hermonprm_query_dev_cap_st::cqc_entry_sz
pseudo_bit_t cqc_entry_sz[0x00010]
Definition: MT25408_PRM.h:2235
hermonprm_query_dev_cap_st::rm
pseudo_bit_t rm[0x00001]
Definition: MT25408_PRM.h:2165
hermonprm_mod_stat_cfg_st::fw_rev_support
pseudo_bit_t fw_rev_support[0x00001]
Definition: MT25408_PRM.h:1430
hermonprm_queue_pair_ee_context_entry_st::reserved21
pseudo_bit_t reserved21[0x00008]
Definition: MT25408_PRM.h:875
hermonprm_mpt_st::reserved5
pseudo_bit_t reserved5[0x00008]
Definition: MT25408_PRM.h:2528
hermonprm_mt25208_type0_st::link_cap
pseudo_bit_t link_cap[0x00020]
Definition: MT25408_PRM.h:2786
hermonprm_vsd_st::vsd_dw44
pseudo_bit_t vsd_dw44[0x00020]
Definition: MT25408_PRM.h:500
hermonprm_mt25208_type0_st::reserved12
pseudo_bit_t reserved12[0x00260]
Definition: MT25408_PRM.h:2798
hermonprm_wqe_segment_bind_st::reserved0
pseudo_bit_t reserved0[0x0001d]
Definition: MT25408_PRM.h:191
hermonprm_eq_set_ci_table_st::eq32_set_ci
pseudo_bit_t eq32_set_ci[0x00020]
Definition: MT25408_PRM.h:1143
hermonprm_eq_set_ci_table_st::eq22_set_ci
pseudo_bit_t eq22_set_ci[0x00020]
Definition: MT25408_PRM.h:1103
hermonprm_query_dev_cap_st::reserved39
pseudo_bit_t reserved39[0x00004]
Definition: MT25408_PRM.h:2209
hermonprm_completion_queue_context_st::reserved6
pseudo_bit_t reserved6[0x00003]
Definition: MT25408_PRM.h:2585
hermonprm_hermon_prm_st::completion_queue_error
struct hermonprm_completion_queue_error_st completion_queue_error
Definition: MT25408_PRM.h:3173
hermonprm_hermon_prm_st::reserved61
pseudo_bit_t reserved61[0x01000]
Definition: MT25408_PRM.h:3393
hermonprm_queue_pair_ee_context_entry_st::rwe
pseudo_bit_t rwe[0x00001]
Definition: MT25408_PRM.h:895
hermonprm_vsd_st::vsd_dw26
pseudo_bit_t vsd_dw26[0x00020]
Definition: MT25408_PRM.h:464
hermonprm_eq_set_ci_table_st::eq52_set_ci
pseudo_bit_t eq52_set_ci[0x00020]
Definition: MT25408_PRM.h:1223
hermonprm_mod_stat_cfg_st::reserved14
pseudo_bit_t reserved14[0x0001f]
Definition: MT25408_PRM.h:1386
hermonprm_query_debug_msg_st::reserved0
pseudo_bit_t reserved0[0x0000b]
Definition: MT25408_PRM.h:1851
hermonprm_srq_context_st::wqe_cnt
pseudo_bit_t wqe_cnt[0x00010]
Definition: MT25408_PRM.h:1508
hermonprm_qpcbaseaddr_st::reserved6
pseudo_bit_t reserved6[0x00040]
Definition: MT25408_PRM.h:676
hermonprm_query_debug_msg_st::fw_area_base
pseudo_bit_t fw_area_base[0x00020]
Definition: MT25408_PRM.h:1854
hermonprm_performance_monitor_event_st
Definition: MT25408_PRM.h:2862
hermonprm_performance_monitors_st::i2
pseudo_bit_t i2[0x00001]
Definition: MT25408_PRM.h:711
hermonprm_mod_stat_cfg_st::qdr_rx_options
pseudo_bit_t qdr_rx_options[0x00004]
Definition: MT25408_PRM.h:1351
hermonprm_qp_ee_event_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:2649
hermonprm_multicastparam_st::reserved0
pseudo_bit_t reserved0[0x00040]
Definition: MT25408_PRM.h:591
hermonprm_hermon_prm_st::reserved51
pseudo_bit_t reserved51[0x9ff800]
Definition: MT25408_PRM.h:3353
hermonprm_wqe_segment_ctrl_mlx_st::owner
pseudo_bit_t owner[0x00001]
Definition: MT25408_PRM.h:735
hermonprm_tptparams_st::cmpt_base_adr_l
pseudo_bit_t cmpt_base_adr_l[0x00020]
Definition: MT25408_PRM.h:574
hermonprm_send_doorbell_st::nds
pseudo_bit_t nds[0x00006]
Definition: MT25408_PRM.h:86
hermonprm_queue_pair_ee_context_entry_st::reserved26
pseudo_bit_t reserved26[0x00001]
Definition: MT25408_PRM.h:891
hermonprm_transport_and_ci_error_counters_st::rq_num_ucsdprd
pseudo_bit_t rq_num_ucsdprd[0x00020]
Definition: MT25408_PRM.h:1689
hermonprm_query_fw_st::fw_minutes
pseudo_bit_t fw_minutes[0x00008]
Definition: MT25408_PRM.h:2308
hermonprm_mt25208_type0_st::vpd_next_cap_id
pseudo_bit_t vpd_next_cap_id[0x00008]
Definition: MT25408_PRM.h:2756
hermonprm_eq_set_ci_table_st::reserved5
pseudo_bit_t reserved5[0x00020]
Definition: MT25408_PRM.h:1037
hermonprm_multicastparam_st::reserved2
pseudo_bit_t reserved2[0x00010]
Definition: MT25408_PRM.h:597
hermonprm_init_hca_st::ibr
pseudo_bit_t ibr[0x00001]
Definition: MT25408_PRM.h:2379
hermonprm_srq_context_st
Definition: MT25408_PRM.h:1476
hermonprm_qp_ee_event_st::e_q
pseudo_bit_t e_q[0x00001]
Definition: MT25408_PRM.h:2654
hermonprm_queue_pair_ee_context_entry_st::reserved6
pseudo_bit_t reserved6[0x00004]
Definition: MT25408_PRM.h:817
hermonprm_ecc_detect_event_data_st::err_ba
pseudo_bit_t err_ba[0x00002]
Definition: MT25408_PRM.h:3113
hermonprm_mod_stat_cfg_st::mac_low
pseudo_bit_t mac_low[0x00020]
Definition: MT25408_PRM.h:1444
hermonprm_completion_queue_context_st::reserved1
pseudo_bit_t reserved1[0x00005]
Definition: MT25408_PRM.h:2565
hermonprm_srq_context_st::srq_wqe_counter
pseudo_bit_t srq_wqe_counter[0x00010]
Definition: MT25408_PRM.h:1511
hermonprm_multicastparam_st::reserved5
pseudo_bit_t reserved5[0x00004]
Definition: MT25408_PRM.h:610
hermonprm_mt25208_type0_st::reserved9
pseudo_bit_t reserved9[0x00080]
Definition: MT25408_PRM.h:2736
hermonprm_query_dev_cap_st::reserved15
pseudo_bit_t reserved15[0x00020]
Definition: MT25408_PRM.h:2098
hermonprm_hermon_prm_st::reserved1
pseudo_bit_t reserved1[0x7f000]
Definition: MT25408_PRM.h:3163
hermonprm_uar_params_st::log_max_uars
pseudo_bit_t log_max_uars[0x00004]
Definition: MT25408_PRM.h:533
hermonprm_eq_set_ci_table_st::reserved52
pseudo_bit_t reserved52[0x00020]
Definition: MT25408_PRM.h:1225
hermonprm_set_ib_st
Definition: MT25408_PRM.h:1935
hermonprm_mod_stat_cfg_st::reserved9
pseudo_bit_t reserved9[0x00001]
Definition: MT25408_PRM.h:1367
hermonprm_eq_set_ci_table_st::reserved3
pseudo_bit_t reserved3[0x00020]
Definition: MT25408_PRM.h:1029
hermonprm_query_dev_cap_st::reserved40
pseudo_bit_t reserved40[0x00008]
Definition: MT25408_PRM.h:2211
hermonprm_ud_address_vector_st::tclass
pseudo_bit_t tclass[0x00008]
Definition: MT25408_PRM.h:64
hermonprm_query_dev_cap_st::log_bf_reg_size
pseudo_bit_t log_bf_reg_size[0x00005]
Definition: MT25408_PRM.h:2186
hermonprm_mod_stat_cfg_st::reserved21
pseudo_bit_t reserved21[0x00004]
Definition: MT25408_PRM.h:1406
hermonprm_performance_monitor_event_st::performance_monitor_snapshot
struct hermonprm_performance_monitors_st performance_monitor_snapshot
Definition: MT25408_PRM.h:2863
hermonprm_eq_set_ci_table_st::eq31_set_ci
pseudo_bit_t eq31_set_ci[0x00020]
Definition: MT25408_PRM.h:1139
hermonprm_wqe_segment_ud_st::reserved1
pseudo_bit_t reserved1[0x00040]
Definition: MT25408_PRM.h:228
hermonprm_query_dev_cap_st::log_max_pkey
pseudo_bit_t log_max_pkey[0x00004]
Definition: MT25408_PRM.h:2130
hermonprm_eq_set_ci_table_st::reserved51
pseudo_bit_t reserved51[0x00020]
Definition: MT25408_PRM.h:1221
hermonprm_eq_set_ci_table_st::reserved60
pseudo_bit_t reserved60[0x00020]
Definition: MT25408_PRM.h:1257
hermonprm_ud_address_vector_st::sl
pseudo_bit_t sl[0x00004]
Definition: MT25408_PRM.h:65
hermonprm_cq_cmd_doorbell_st::cmd_sn
pseudo_bit_t cmd_sn[0x00002]
Definition: MT25408_PRM.h:375
hermonprm_wqe_segment_st::reserved1
pseudo_bit_t reserved1[0x00100]
Definition: MT25408_PRM.h:2911
hermonprm_query_dev_cap_st::max_icm_size_l
pseudo_bit_t max_icm_size_l[0x00020]
Definition: MT25408_PRM.h:2266
hermonprm_mad_ifc_st::rqpn
pseudo_bit_t rqpn[0x00018]
Definition: MT25408_PRM.h:1818
hermonprm_completion_with_error_st::qpn
pseudo_bit_t qpn[0x00018]
Definition: MT25408_PRM.h:1725
hermonprm_queue_pair_ee_context_entry_st::exch_size
pseudo_bit_t exch_size[0x00004]
Definition: MT25408_PRM.h:972
hermonprm_qp_ee_state_transitions_st::reserved0
pseudo_bit_t reserved0[0x00020]
Definition: MT25408_PRM.h:2983
hermonprm_scrubbing_event_st::reserved1
pseudo_bit_t reserved1[0x00002]
Definition: MT25408_PRM.h:3129
hermonprm_query_fw_st::reserved7
pseudo_bit_t reserved7[0x0001e]
Definition: MT25408_PRM.h:2338
hermonprm_completion_queue_entry_st::vid
pseudo_bit_t vid[0x0000c]
Definition: MT25408_PRM.h:3026
hermonprm_send_wqe_segment_st::wqe_segment_data_ptr
struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr
Definition: MT25408_PRM.h:777
hermonprm_qpcbaseaddr_st::auxc_base_addr_l
pseudo_bit_t auxc_base_addr_l[0x00020]
Definition: MT25408_PRM.h:662
hermonprm_query_debug_msg_st::fw_area_size
pseudo_bit_t fw_area_size[0x00020]
Definition: MT25408_PRM.h:1856
hermonprm_init_port_st::reserved5
pseudo_bit_t reserved5[0x006c0]
Definition: MT25408_PRM.h:2042
hermonprm_init_hca_st::reserved3
pseudo_bit_t reserved3[0x00005]
Definition: MT25408_PRM.h:2376
hermonprm_fast_registration_segment_st::pbl_ptr_63_32
pseudo_bit_t pbl_ptr_63_32[0x00020]
Definition: MT25408_PRM.h:142
hermonprm_multicastparam_st::reserved6
pseudo_bit_t reserved6[0x00020]
Definition: MT25408_PRM.h:612
hermonprm_mgm_entry_st::reserved0
pseudo_bit_t reserved0[0x00006]
Definition: MT25408_PRM.h:1957
hermonprm_queue_pair_ee_context_entry_st::rlky
pseudo_bit_t rlky[0x00001]
Definition: MT25408_PRM.h:818
hermonprm_header_log_register_st::reserved0
pseudo_bit_t reserved0[0x00060]
Definition: MT25408_PRM.h:694
hermonprm_eq_set_ci_table_st::eq4_set_ci
pseudo_bit_t eq4_set_ci[0x00020]
Definition: MT25408_PRM.h:1031
hermonprm_qp_ee_event_st::qpn_een
pseudo_bit_t qpn_een[0x00018]
Definition: MT25408_PRM.h:2648
FILE_LICENCE
FILE_LICENCE(GPL2_ONLY)
hermonprm_completion_queue_entry_st::reserved1
pseudo_bit_t reserved1[0x00010]
Definition: MT25408_PRM.h:3052
hermonprm_eq_set_ci_table_st::eq46_set_ci
pseudo_bit_t eq46_set_ci[0x00020]
Definition: MT25408_PRM.h:1199
hermonprm_mod_stat_cfg_st::reserved7
pseudo_bit_t reserved7[0x00003]
Definition: MT25408_PRM.h:1362
hermonprm_mad_ifc_input_modifier_st::rlid
pseudo_bit_t rlid[0x00010]
Definition: MT25408_PRM.h:1802
hermonprm_hermon_prm_st::uar
struct hermonprm_uar_st uar
Definition: MT25408_PRM.h:3315
hermonprm_transport_and_ci_error_counters_st::sq_num_tree
pseudo_bit_t sq_num_tree[0x00020]
Definition: MT25408_PRM.h:1647
hermonprm_mt25208_type0_st::link_status
pseudo_bit_t link_status[0x00010]
Definition: MT25408_PRM.h:2794
hermonprm_cq_ci_db_record_st::counter
pseudo_bit_t counter[0x00020]
Definition: MT25408_PRM.h:1311
hermonprm_transport_and_ci_error_counters_st::num_cqovf
pseudo_bit_t num_cqovf[0x00020]
Definition: MT25408_PRM.h:1693
hermonprm_uar_params_st::reserved0
pseudo_bit_t reserved0[0x00040]
Definition: MT25408_PRM.h:529
hermonprm_multicastparam_st
Definition: MT25408_PRM.h:582
hermonprm_query_dev_cap_st::reserved30
pseudo_bit_t reserved30[0x00008]
Definition: MT25408_PRM.h:2175
hermonprm_hermon_prm_st::reserved18
pseudo_bit_t reserved18[0x7fe00]
Definition: MT25408_PRM.h:3231
hermonprm_hermon_prm_st::reserved40
pseudo_bit_t reserved40[0x7ffc0]
Definition: MT25408_PRM.h:3309
hermonprm_performance_monitors_st::e0
pseudo_bit_t e0[0x00001]
Definition: MT25408_PRM.h:701
hermonprm_completion_queue_context_st
Definition: MT25408_PRM.h:2554
hermonprm_virtual_physical_mapping_st::pa_h
pseudo_bit_t pa_h[0x00020]
Definition: MT25408_PRM.h:1327
hermonprm_udavtable_memory_parameters_st::xlation_en
pseudo_bit_t xlation_en[0x00001]
Definition: MT25408_PRM.h:2358
hermonprm_query_dev_cap_st::qpc_entry_sz
pseudo_bit_t qpc_entry_sz[0x00010]
Definition: MT25408_PRM.h:2226
hermonprm_event_queue_entry_st::event_type
pseudo_bit_t event_type[0x00008]
Definition: MT25408_PRM.h:2965
hermonprm_mad_ifc_input_modifier_st
Definition: MT25408_PRM.h:1797
hermonprm_hermon_prm_st::multicastparam
struct hermonprm_multicastparam_st multicastparam
Definition: MT25408_PRM.h:3253
hermonprm_resize_cq_st::reserved3
pseudo_bit_t reserved3[0x00018]
Definition: MT25408_PRM.h:1775
hermonprm_mcg_hdr_st::gid3
pseudo_bit_t gid3[0x00020]
Definition: MT25408_PRM.h:3079
hermonprm_mt25208_type0_st::pciex_next_cap_ptr
pseudo_bit_t pciex_next_cap_ptr[0x00008]
Definition: MT25408_PRM.h:2765
hermonprm_init_port_st::sig
pseudo_bit_t sig[0x00001]
Definition: MT25408_PRM.h:2009
hermonprm_hermon_prm_st::cq_ci_db_record
struct hermonprm_cq_ci_db_record_st cq_ci_db_record
Definition: MT25408_PRM.h:3375
hermonprm_queue_pair_ee_context_entry_st::cur_retry_cnt
pseudo_bit_t cur_retry_cnt[0x00003]
Definition: MT25408_PRM.h:856
hermonprm_mt25208_type0_st::pm_control_status_brdg_ext
pseudo_bit_t pm_control_status_brdg_ext[0x00008]
Definition: MT25408_PRM.h:2750
hermonprm_resize_cq_st::reserved5
pseudo_bit_t reserved5[0x00020]
Definition: MT25408_PRM.h:1779
hermonprm_qp_ee_event_st
Definition: MT25408_PRM.h:2647
hermonprm_eq_set_ci_table_st::reserved48
pseudo_bit_t reserved48[0x00020]
Definition: MT25408_PRM.h:1209
hermonprm_hermon_prm_st
Definition: MT25408_PRM.h:3156
hermonprm_eq_set_ci_table_st::eq0_set_ci
pseudo_bit_t eq0_set_ci[0x00020]
Definition: MT25408_PRM.h:1015
hermonprm_eqc_st::mtt_base_addr_l
pseudo_bit_t mtt_base_addr_l[0x0001d]
Definition: MT25408_PRM.h:2453
hermonprm_mgm_entry_st::mgid_95_64
pseudo_bit_t mgid_95_64[0x00020]
Definition: MT25408_PRM.h:1967
hermonprm_hermon_prm_st::rd_send_doorbell
struct hermonprm_rd_send_doorbell_st rd_send_doorbell
Definition: MT25408_PRM.h:3299
hermonprm_init_port_st::max_gid
pseudo_bit_t max_gid[0x00010]
Definition: MT25408_PRM.h:2013
hermonprm_query_dev_cap_st::rdmardc_entry_sz
pseudo_bit_t rdmardc_entry_sz[0x00010]
Definition: MT25408_PRM.h:2228
hermonprm_hermon_prm_st::reserved2
pseudo_bit_t reserved2[0x7ff00]
Definition: MT25408_PRM.h:3167
hermonprm_queue_pair_ee_context_entry_st::reserved43
pseudo_bit_t reserved43[0x00006]
Definition: MT25408_PRM.h:967
hermonprm_mod_stat_cfg_st::reserved25
pseudo_bit_t reserved25[0x00040]
Definition: MT25408_PRM.h:1414
hermonprm_transport_and_ci_error_counters_st::sq_num_mwbe
pseudo_bit_t sq_num_mwbe[0x00020]
Definition: MT25408_PRM.h:1586
hermonprm_query_debug_msg_st::dbg_msk_h
pseudo_bit_t dbg_msk_h[0x00020]
Definition: MT25408_PRM.h:1864
hermonprm_completion_queue_entry_st::qpn
pseudo_bit_t qpn[0x00018]
Definition: MT25408_PRM.h:2994
hermonprm_fast_registration_segment_st::lw
pseudo_bit_t lw[0x00001]
Definition: MT25408_PRM.h:137
hermonprm_eq_set_ci_table_st::reserved23
pseudo_bit_t reserved23[0x00020]
Definition: MT25408_PRM.h:1109
hermonprm_vsd_st::vsd_dw39
pseudo_bit_t vsd_dw39[0x00020]
Definition: MT25408_PRM.h:490
hermonprm_queue_pair_ee_context_entry_st::reserved27
pseudo_bit_t reserved27[0x00001]
Definition: MT25408_PRM.h:893
hermonprm_query_dev_cap_st::log_pg_sz
pseudo_bit_t log_pg_sz[0x00008]
Definition: MT25408_PRM.h:2173
hermonprm_virtual_physical_mapping_st::va_h
pseudo_bit_t va_h[0x00020]
Definition: MT25408_PRM.h:1322
hermonprm_mcg_qps_st::dw
struct hermonprm_mcg_qp_dw_st dw[128]
Definition: MT25408_PRM.h:3060
hermonprm_send_doorbell_st::qpn
pseudo_bit_t qpn[0x00018]
Definition: MT25408_PRM.h:88
hermonprm_hermon_prm_st::reserved3
pseudo_bit_t reserved3[0x7ff40]
Definition: MT25408_PRM.h:3171
hermonprm_event_queue_entry_st::reserved2
pseudo_bit_t reserved2[0x00007]
Definition: MT25408_PRM.h:2970
hermonprm_hermon_prm_st::reserved39
pseudo_bit_t reserved39[0x7ffc0]
Definition: MT25408_PRM.h:3305
hermonprm_srq_context_st::reserved8
pseudo_bit_t reserved8[0x00010]
Definition: MT25408_PRM.h:1512
hermonprm_eq_set_ci_table_st::eq15_set_ci
pseudo_bit_t eq15_set_ci[0x00020]
Definition: MT25408_PRM.h:1075
hermonprm_page_fault_event_data_st::mem_key
pseudo_bit_t mem_key[0x00020]
Definition: MT25408_PRM.h:2885
hermonprm_mpt_st::lw
pseudo_bit_t lw[0x00001]
Definition: MT25408_PRM.h:2489
hermonprm_completion_queue_entry_st::s_r
pseudo_bit_t s_r[0x00001]
Definition: MT25408_PRM.h:3050
hermonprm_srq_context_st::reserved2
pseudo_bit_t reserved2[0x00002]
Definition: MT25408_PRM.h:1493
hermonprm_ud_address_vector_st::rgid_127_96
pseudo_bit_t rgid_127_96[0x00020]
Definition: MT25408_PRM.h:67
hermonprm_query_dev_cap_st::qkv
pseudo_bit_t qkv[0x00001]
Definition: MT25408_PRM.h:2155
hermonprm_performance_counters_st::reserved0
pseudo_bit_t reserved0[0x00080]
Definition: MT25408_PRM.h:1547
hermonprm_address_path_st::ack_timeout
pseudo_bit_t ack_timeout[0x00005]
Definition: MT25408_PRM.h:300
hermonprm_init_hca_st::hca_core_clock
pseudo_bit_t hca_core_clock[0x00010]
Definition: MT25408_PRM.h:2372
hermonprm_send_wqe_segment_st::wqe_segment_ud
struct hermonprm_wqe_segment_ud_st wqe_segment_ud
Definition: MT25408_PRM.h:763
hermonprm_address_path_st::reserved2
pseudo_bit_t reserved2[0x00004]
Definition: MT25408_PRM.h:297
hermonprm_hermon_prm_st::reserved21
pseudo_bit_t reserved21[0x7f000]
Definition: MT25408_PRM.h:3243
hermonprm_hermon_prm_st::ud_address_vector
struct hermonprm_ud_address_vector_st ud_address_vector
Definition: MT25408_PRM.h:3205
hermonprm_query_fw_st::reserved3
pseudo_bit_t reserved3[0x00006]
Definition: MT25408_PRM.h:2306
hermonprm_vsd_st::vsd_dw9
pseudo_bit_t vsd_dw9[0x00020]
Definition: MT25408_PRM.h:430
hermonprm_qpcbaseaddr_st::reserved1
pseudo_bit_t reserved1[0x00040]
Definition: MT25408_PRM.h:628
hermonprm_query_dev_cap_st::c_mpt_entry_sz
pseudo_bit_t c_mpt_entry_sz[0x00010]
Definition: MT25408_PRM.h:2240
hermonprm_eq_set_ci_table_st::eq12_set_ci
pseudo_bit_t eq12_set_ci[0x00020]
Definition: MT25408_PRM.h:1063
hermonprm_rd_send_doorbell_st
Definition: MT25408_PRM.h:387
hermonprm_address_path_st::rlid
pseudo_bit_t rlid[0x00010]
Definition: MT25408_PRM.h:277
hermonprm_performance_monitors_st
Definition: MT25408_PRM.h:700
hermonprm_hermon_prm_st::reserved54
pseudo_bit_t reserved54[0x7fe80]
Definition: MT25408_PRM.h:3365
hermonprm_queue_pair_ee_context_entry_st::reserved45
pseudo_bit_t reserved45[0x00003]
Definition: MT25408_PRM.h:973
hermonprm_eq_set_ci_table_st::eq34_set_ci
pseudo_bit_t eq34_set_ci[0x00020]
Definition: MT25408_PRM.h:1151
hermonprm_hermon_prm_st::reserved64
pseudo_bit_t reserved64[0xffcfc0]
Definition: MT25408_PRM.h:3401
hermonprm_event_queue_entry_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:2966
hermonprm_queue_pair_ee_context_entry_st::db_record_addr_h
pseudo_bit_t db_record_addr_h[0x00020]
Definition: MT25408_PRM.h:913
hermonprm_hermon_prm_st::clr_int
struct hermonprm_clr_int_st clr_int
Definition: MT25408_PRM.h:3399
hermonprm_srq_context_st::cqn
pseudo_bit_t cqn[0x00018]
Definition: MT25408_PRM.h:1491
hermonprm_qp_db_record_st::receive_wqe_counter
pseudo_bit_t receive_wqe_counter[0x00010]
Definition: MT25408_PRM.h:1287
hermonprm_queue_pair_ee_context_entry_st::reserved18
pseudo_bit_t reserved18[0x00004]
Definition: MT25408_PRM.h:866
hermonprm_mod_stat_cfg_st::qdr_tx_options_m
pseudo_bit_t qdr_tx_options_m[0x00001]
Definition: MT25408_PRM.h:1356
hermonprm_query_dev_cap_st::log_max_cq_sz
pseudo_bit_t log_max_cq_sz[0x00008]
Definition: MT25408_PRM.h:2072
hermonprm_init_hca_st::reserved5
pseudo_bit_t reserved5[0x0001c]
Definition: MT25408_PRM.h:2390
hermonprm_query_dev_cap_st::log_max_srq_sz
pseudo_bit_t log_max_srq_sz[0x00008]
Definition: MT25408_PRM.h:2057
hermonprm_completion_queue_entry_st::srq_rqpn
pseudo_bit_t srq_rqpn[0x00018]
Definition: MT25408_PRM.h:3013
hermonprm_eq_set_ci_table_st
Definition: MT25408_PRM.h:1014
hermonprm_event_queue_entry_st::event_data
pseudo_bit_t event_data[6][0x00020]
Definition: MT25408_PRM.h:2968
hermonprm_mt25208_type0_st::reserved10
pseudo_bit_t reserved10[0x00040]
Definition: MT25408_PRM.h:2753
hermonprm_completion_with_error_st::opcode
pseudo_bit_t opcode[0x00005]
Definition: MT25408_PRM.h:1754
hermonprm_address_path_st::reserved3
pseudo_bit_t reserved3[0x00004]
Definition: MT25408_PRM.h:299
hermonprm_eqc_st::eq_max_count
pseudo_bit_t eq_max_count[0x00010]
Definition: MT25408_PRM.h:2441
hermonprm_transport_and_ci_error_counters_st::sq_num_lpe
pseudo_bit_t sq_num_lpe[0x00020]
Definition: MT25408_PRM.h:1576
hermonprm_mcg_hdr_st::member_remove
pseudo_bit_t member_remove[0x00001]
Definition: MT25408_PRM.h:3071
hermonprm_hermon_prm_st::reserved50
pseudo_bit_t reserved50[0x7f000]
Definition: MT25408_PRM.h:3349
hermonprm_query_debug_msg_st::buff1_addr
pseudo_bit_t buff1_addr[0x00020]
Definition: MT25408_PRM.h:1874
hermonprm_mod_stat_cfg_st::port_en
pseudo_bit_t port_en[0x00001]
Definition: MT25408_PRM.h:1363
hermonprm_query_dev_cap_st::pci_pf_num
pseudo_bit_t pci_pf_num[0x00008]
Definition: MT25408_PRM.h:2113
hermonprm_init_port_st::system_image_guid_l
pseudo_bit_t system_image_guid_l[0x00020]
Definition: MT25408_PRM.h:2039
hermonprm_hermon_prm_st::mpt
struct hermonprm_mpt_st mpt
Definition: MT25408_PRM.h:3221
hermonprm_query_dev_cap_st::num_ports
pseudo_bit_t num_ports[0x00004]
Definition: MT25408_PRM.h:2111
hermonprm_port_state_change_st::reserved0
pseudo_bit_t reserved0[0x00040]
Definition: MT25408_PRM.h:2922
hermonprm_hermon_prm_st::reserved33
pseudo_bit_t reserved33[0x7f800]
Definition: MT25408_PRM.h:3281
hermonprm_uar_params_st::reserved1
pseudo_bit_t reserved1[0x00014]
Definition: MT25408_PRM.h:534
hermonprm_query_adapter_st::reserved0
pseudo_bit_t reserved0[0x00080]
Definition: MT25408_PRM.h:2275
hermonprm_eq_set_ci_table_st::eq2_set_ci
pseudo_bit_t eq2_set_ci[0x00020]
Definition: MT25408_PRM.h:1023
hermonprm_scrubbing_event_st::cause_msb
pseudo_bit_t cause_msb[0x00001]
Definition: MT25408_PRM.h:3130
hermonprm_query_debug_msg_st::reserved1
pseudo_bit_t reserved1[0x000c0]
Definition: MT25408_PRM.h:1862
hermonprm_query_dev_cap_st::max_icm_size_h
pseudo_bit_t max_icm_size_h[0x00020]
Definition: MT25408_PRM.h:2264
hermonprm_set_ib_st::rqk
pseudo_bit_t rqk[0x00001]
Definition: MT25408_PRM.h:1936
hermonprm_address_path_st::rgid_95_64
pseudo_bit_t rgid_95_64[0x00020]
Definition: MT25408_PRM.h:309
hermonprm_mad_ifc_st::ml_path
pseudo_bit_t ml_path[0x00007]
Definition: MT25408_PRM.h:1823
hermonprm_init_hca_st::reserved9
pseudo_bit_t reserved9[0x00080]
Definition: MT25408_PRM.h:2404
hermonprm_mt25208_type0_st::expansion_rom_base_address
pseudo_bit_t expansion_rom_base_address[0x00015]
Definition: MT25408_PRM.h:2707
hermonprm_hermon_prm_st::fast_registration_segment
struct hermonprm_fast_registration_segment_st fast_registration_segment
Definition: MT25408_PRM.h:3355
hermonprm_cq_ci_db_record_st::res
pseudo_bit_t res[0x00003]
Definition: MT25408_PRM.h:1314
hermonprm_eqc_st::reserved1
pseudo_bit_t reserved1[0x00005]
Definition: MT25408_PRM.h:2421
hermonprm_hermon_prm_st::mad_ifc_input_modifier
struct hermonprm_mad_ifc_input_modifier_st mad_ifc_input_modifier
Definition: MT25408_PRM.h:3331
hermonprm_hermon_prm_st::query_debug_msg
struct hermonprm_query_debug_msg_st query_debug_msg
Definition: MT25408_PRM.h:3323
hermonprm_mgmqp_st::blck_lb
pseudo_bit_t blck_lb[0x00001]
Definition: MT25408_PRM.h:404
hermonprm_hermon_prm_st::reserved56
pseudo_bit_t reserved56[0x7ff80]
Definition: MT25408_PRM.h:3373
hermonprm_init_hca_st::reserved4
pseudo_bit_t reserved4[0x00001]
Definition: MT25408_PRM.h:2388
hermonprm_query_dev_cap_st::reserved20
pseudo_bit_t reserved20[0x00004]
Definition: MT25408_PRM.h:2117
hermonprm_completion_with_error_st::reserved1
pseudo_bit_t reserved1[0x000a0]
Definition: MT25408_PRM.h:1728
hermonprm_completion_with_error_st::vendor_error_syndrome
pseudo_bit_t vendor_error_syndrome[0x00008]
Definition: MT25408_PRM.h:1751
hermonprm_srq_context_st::db_record_addr_l
pseudo_bit_t db_record_addr_l[0x0001e]
Definition: MT25408_PRM.h:1519
hermonprm_mpt_st::rr
pseudo_bit_t rr[0x00001]
Definition: MT25408_PRM.h:2490
hermonprm_hermon_prm_st::mgm_entry
struct hermonprm_mgm_entry_st mgm_entry
Definition: MT25408_PRM.h:3291
hermonprm_pbl_st::mtt_3_h
pseudo_bit_t mtt_3_h[0x00020]
Definition: MT25408_PRM.h:1538
hermonprm_query_debug_msg_st::buff0_size
pseudo_bit_t buff0_size[0x00020]
Definition: MT25408_PRM.h:1872
hermonprm_completion_queue_entry_st::fcrc_sd
pseudo_bit_t fcrc_sd[0x00001]
Definition: MT25408_PRM.h:2998
hermonprm_query_dev_cap_st::log_ethtype
pseudo_bit_t log_ethtype[0x00004]
Definition: MT25408_PRM.h:2124
hermonprm_query_dev_cap_st::mw
pseudo_bit_t mw[0x00001]
Definition: MT25408_PRM.h:2162
hermonprm_mod_stat_cfg_st::port_net_boot_m
pseudo_bit_t port_net_boot_m[0x00001]
Definition: MT25408_PRM.h:1458
hermonprm_address_path_st::rgid_63_32
pseudo_bit_t rgid_63_32[0x00020]
Definition: MT25408_PRM.h:311
hermonprm_fast_registration_segment_st::rr
pseudo_bit_t rr[0x00001]
Definition: MT25408_PRM.h:138
hermonprm_set_ib_st::reserved1
pseudo_bit_t reserved1[0x0000d]
Definition: MT25408_PRM.h:1940
hermonprm_mod_stat_cfg_st::reserved30
pseudo_bit_t reserved30[0x0000f]
Definition: MT25408_PRM.h:1429
hermonprm_virtual_physical_mapping_st::reserved1
pseudo_bit_t reserved1[0x00006]
Definition: MT25408_PRM.h:1330
hermonprm_pbl_st
Definition: MT25408_PRM.h:1525
hermonprm_ecc_detect_event_data_st::err_rmw
pseudo_bit_t err_rmw[0x00001]
Definition: MT25408_PRM.h:3110
hermonprm_hca_command_register_st::in_param_h
pseudo_bit_t in_param_h[0x00020]
Definition: MT25408_PRM.h:336
hermonprm_query_dev_cap_st::r
pseudo_bit_t r[0x00001]
Definition: MT25408_PRM.h:2170
hermonprm_queue_pair_ee_context_entry_st::reserved1
pseudo_bit_t reserved1[0x00001]
Definition: MT25408_PRM.h:789
hermonprm_query_dev_cap_st::reserved12
pseudo_bit_t reserved12[0x00002]
Definition: MT25408_PRM.h:2088
hermonprm_query_dev_cap_st::num_rsvd_eqs
pseudo_bit_t num_rsvd_eqs[0x00008]
Definition: MT25408_PRM.h:2073
hermonprm_cq_ci_db_record_st
Definition: MT25408_PRM.h:1310
hermonprm_query_fw_st
Definition: MT25408_PRM.h:2288
hermonprm_queue_pair_ee_context_entry_st::local_qpn_een
pseudo_bit_t local_qpn_een[0x00018]
Definition: MT25408_PRM.h:842
hermonprm_init_port_st::system_image_guid_h
pseudo_bit_t system_image_guid_h[0x00020]
Definition: MT25408_PRM.h:2036
hermonprm_performance_monitors_st::f0
pseudo_bit_t f0[0x00001]
Definition: MT25408_PRM.h:713
hermonprm_multicastparam_st::mc_base_addr_l
pseudo_bit_t mc_base_addr_l[0x00020]
Definition: MT25408_PRM.h:587
hermonprm_query_fw_st::error_buf_size
pseudo_bit_t error_buf_size[0x00020]
Definition: MT25408_PRM.h:2336
hermonprm_vsd_st::vsd_dw45
pseudo_bit_t vsd_dw45[0x00020]
Definition: MT25408_PRM.h:502
hermonprm_wqe_segment_ctrl_send_st::src_remote_buf
pseudo_bit_t src_remote_buf[0x00018]
Definition: MT25408_PRM.h:262
hermonprm_transport_and_ci_error_counters_st::rq_num_rsync
pseudo_bit_t rq_num_rsync[0x00020]
Definition: MT25408_PRM.h:1681
hermonprm_ecc_detect_event_data_st::err_ra
pseudo_bit_t err_ra[0x00010]
Definition: MT25408_PRM.h:3117
hermonprm_eq_set_ci_table_st::eq60_set_ci
pseudo_bit_t eq60_set_ci[0x00020]
Definition: MT25408_PRM.h:1255
hermonprm_query_dev_cap_st::reserved31
pseudo_bit_t reserved31[0x00006]
Definition: MT25408_PRM.h:2177
hermonprm_vsd_st::vsd_dw34
pseudo_bit_t vsd_dw34[0x00020]
Definition: MT25408_PRM.h:480
hermonprm_queue_pair_ee_context_entry_st::base_mkey
pseudo_bit_t base_mkey[0x00018]
Definition: MT25408_PRM.h:952
hermonprm_mod_stat_cfg_st::mac_m
pseudo_bit_t mac_m[0x00001]
Definition: MT25408_PRM.h:1442
hermonprm_mod_stat_cfg_st::reserved3
pseudo_bit_t reserved3[0x00010]
Definition: MT25408_PRM.h:1350
hermonprm_query_dev_cap_st::uc
pseudo_bit_t uc[0x00001]
Definition: MT25408_PRM.h:2146
hermonprm_query_debug_msg_st::buff1_size
pseudo_bit_t buff1_size[0x00020]
Definition: MT25408_PRM.h:1876
hermonprm_eq_set_ci_table_st::reserved4
pseudo_bit_t reserved4[0x00020]
Definition: MT25408_PRM.h:1033
hermonprm_mpt_st::start_addr_h
pseudo_bit_t start_addr_h[0x00020]
Definition: MT25408_PRM.h:2517
hermonprm_mgm_entry_st::mgmqp_6
struct hermonprm_mgmqp_st mgmqp_6
Definition: MT25408_PRM.h:1988
hermonprm_mpt_st::reserved8
pseudo_bit_t reserved8[0x00018]
Definition: MT25408_PRM.h:2538
hermonprm_query_dev_cap_st::rss_udp
pseudo_bit_t rss_udp[0x00001]
Definition: MT25408_PRM.h:2139
hermonprm_mod_stat_cfg_st::reserved20
pseudo_bit_t reserved20[0x00004]
Definition: MT25408_PRM.h:1404
hermonprm_completion_queue_entry_st::reserved2
pseudo_bit_t reserved2[0x00008]
Definition: MT25408_PRM.h:3053
hermonprm_wqe_segment_rd_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:236
hermonprm_hermon_prm_st::completion_queue_entry
struct hermonprm_completion_queue_entry_st completion_queue_entry
Definition: MT25408_PRM.h:3157
hermonprm_queue_pair_ee_context_entry_st::fcp_mtu
pseudo_bit_t fcp_mtu[0x0000a]
Definition: MT25408_PRM.h:979
hermonprm_completion_queue_context_st::st
pseudo_bit_t st[0x00004]
Definition: MT25408_PRM.h:2556
hermonprm_mt25208_type0_st::vpd_cap_id
pseudo_bit_t vpd_cap_id[0x00008]
Definition: MT25408_PRM.h:2755
hermonprm_srq_context_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:1487
hermonprm_mad_ifc_st::reserved6
pseudo_bit_t reserved6[0x00160]
Definition: MT25408_PRM.h:1835
hermonprm_queue_pair_ee_context_entry_st::exch_base
pseudo_bit_t exch_base[0x00010]
Definition: MT25408_PRM.h:970
hermonprm_performance_monitors_st::event_counter2
pseudo_bit_t event_counter2[0x00020]
Definition: MT25408_PRM.h:726
hermonprm_port_state_change_st::reserved2
pseudo_bit_t reserved2[0x00002]
Definition: MT25408_PRM.h:2926
hermonprm_wqe_segment_data_inline_st::reserved2
pseudo_bit_t reserved2[0x00040]
Definition: MT25408_PRM.h:102
hermonprm_ud_address_vector_st::rlid
pseudo_bit_t rlid[0x00010]
Definition: MT25408_PRM.h:44
hermonprm_query_fw_st::log_max_outstanding_cmd
pseudo_bit_t log_max_outstanding_cmd[0x00008]
Definition: MT25408_PRM.h:2298
hermonprm_mt25208_type0_st::advanced_error_reporting_cap_id
pseudo_bit_t advanced_error_reporting_cap_id[0x00010]
Definition: MT25408_PRM.h:2800
hermonprm_hermon_prm_st::reserved35
pseudo_bit_t reserved35[0x7f800]
Definition: MT25408_PRM.h:3289
hermonprm_mod_stat_cfg_st::num_vep_groups
pseudo_bit_t num_vep_groups[0x00008]
Definition: MT25408_PRM.h:1448
hermonprm_init_port_st
Definition: MT25408_PRM.h:1996
hermonprm_eq_set_ci_table_st::eq56_set_ci
pseudo_bit_t eq56_set_ci[0x00020]
Definition: MT25408_PRM.h:1239
hermonprm_queue_pair_ee_context_entry_st::reserved35
pseudo_bit_t reserved35[0x00008]
Definition: MT25408_PRM.h:928
hermonprm_eq_set_ci_table_st::reserved8
pseudo_bit_t reserved8[0x00020]
Definition: MT25408_PRM.h:1049
hermonprm_completion_with_error_st::wqe_counter
pseudo_bit_t wqe_counter[0x00010]
Definition: MT25408_PRM.h:1752
hermonprm_eq_set_ci_table_st::reserved35
pseudo_bit_t reserved35[0x00020]
Definition: MT25408_PRM.h:1157
hermonprm_mt25208_type0_st::reserved4
pseudo_bit_t reserved4[0x00018]
Definition: MT25408_PRM.h:2710
hermonprm_mt25208_type0_st::pm_next_cap_ptr
pseudo_bit_t pm_next_cap_ptr[0x00008]
Definition: MT25408_PRM.h:2739
hermonprm_eq_set_ci_table_st::eq29_set_ci
pseudo_bit_t eq29_set_ci[0x00020]
Definition: MT25408_PRM.h:1131
hermonprm_eq_set_ci_table_st::eq62_set_ci
pseudo_bit_t eq62_set_ci[0x00020]
Definition: MT25408_PRM.h:1263
hermonprm_resize_cq_st::reserved8
pseudo_bit_t reserved8[0x00003]
Definition: MT25408_PRM.h:1786
hermonprm_query_dev_cap_st::reserved29
pseudo_bit_t reserved29[0x00006]
Definition: MT25408_PRM.h:2171
hermonprm_srq_context_st::reserved5
pseudo_bit_t reserved5[0x00002]
Definition: MT25408_PRM.h:1500
hermonprm_query_debug_msg_st::buff5_addr
pseudo_bit_t buff5_addr[0x00020]
Definition: MT25408_PRM.h:1890
hermonprm_mt25208_type0_st::reserved1
pseudo_bit_t reserved1[0x00010]
Definition: MT25408_PRM.h:2689
hermonprm_mpt_st::mtt_adr_l
pseudo_bit_t mtt_adr_l[0x00020]
Definition: MT25408_PRM.h:2540
hermonprm_performance_counters_st::reserved2
pseudo_bit_t reserved2[0x00080]
Definition: MT25408_PRM.h:1551
hermonprm_qpcbaseaddr_st::log_num_of_cq
pseudo_bit_t log_num_of_cq[0x00005]
Definition: MT25408_PRM.h:644
hermonprm_init_hca_st::ce
pseudo_bit_t ce[0x00001]
Definition: MT25408_PRM.h:2389
hermonprm_init_hca_st::reserved8
pseudo_bit_t reserved8[0x00080]
Definition: MT25408_PRM.h:2400
hermonprm_eqc_st::reserved5
pseudo_bit_t reserved5[0x00014]
Definition: MT25408_PRM.h:2435
hermonprm_mod_stat_cfg_st::ob_preemp
pseudo_bit_t ob_preemp[0x00005]
Definition: MT25408_PRM.h:1397
hermonprm_page_fault_event_data_st
Definition: MT25408_PRM.h:2880
hermonprm_eq_set_ci_table_st::reserved22
pseudo_bit_t reserved22[0x00020]
Definition: MT25408_PRM.h:1105
hermonprm_eq_set_ci_table_st::reserved14
pseudo_bit_t reserved14[0x00020]
Definition: MT25408_PRM.h:1073
hermonprm_init_hca_st::uar_parameters
struct hermonprm_uar_params_st uar_parameters
Definition: MT25408_PRM.h:2406
hermonprm_mpt_st::reserved6
pseudo_bit_t reserved6[0x00011]
Definition: MT25408_PRM.h:2531
hermonprm_virtual_physical_mapping_st::pa_l
pseudo_bit_t pa_l[0x00014]
Definition: MT25408_PRM.h:1331
hermonprm_query_debug_msg_st::buff2_addr
pseudo_bit_t buff2_addr[0x00020]
Definition: MT25408_PRM.h:1878
hermonprm_queue_pair_ee_context_entry_st::vft_lan
pseudo_bit_t vft_lan[0x0000c]
Definition: MT25408_PRM.h:963
hermonprm_hermon_prm_st::tptparams
struct hermonprm_tptparams_st tptparams
Definition: MT25408_PRM.h:3257
hermonprm_mpt_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:2485
hermonprm_query_dev_cap_st::bl
pseudo_bit_t bl[0x00001]
Definition: MT25408_PRM.h:2255
hermonprm_mod_stat_cfg_st::reserved1
pseudo_bit_t reserved1[0x00003]
Definition: MT25408_PRM.h:1344
hermonprm_rd_send_doorbell_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:392
hermonprm_address_path_st::mgid_index
pseudo_bit_t mgid_index[0x00007]
Definition: MT25408_PRM.h:298
hermonprm_mcg_hdr_st::gid1
pseudo_bit_t gid1[0x00020]
Definition: MT25408_PRM.h:3083
hermonprm_mod_stat_cfg_st::sd_equal
pseudo_bit_t sd_equal[0x00004]
Definition: MT25408_PRM.h:1405
hermonprm_event_queue_entry_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:2964
hermonprm_transport_and_ci_error_counters_st::rq_num_lae
pseudo_bit_t rq_num_lae[0x00020]
Definition: MT25408_PRM.h:1592
hermonprm_completion_queue_context_st::db_record_addr_h
pseudo_bit_t db_record_addr_h[0x00020]
Definition: MT25408_PRM.h:2625
hermonprm_transport_and_ci_error_counters_st::sq_num_roe
pseudo_bit_t sq_num_roe[0x00020]
Definition: MT25408_PRM.h:1635
hermonprm_mpt_st::no_snoop
pseudo_bit_t no_snoop[0x00001]
Definition: MT25408_PRM.h:2497
hermonprm_sched_queue_context_st
Definition: MT25408_PRM.h:3091
hermonprm_mod_stat_cfg_st::reserved28
pseudo_bit_t reserved28[0x00018]
Definition: MT25408_PRM.h:1424
hermonprm_ecc_detect_event_data_st::reserved3
pseudo_bit_t reserved3[0x00011]
Definition: MT25408_PRM.h:3114
hermonprm_query_dev_cap_st::fexch_base_mpt_31_25
pseudo_bit_t fexch_base_mpt_31_25[0x00007]
Definition: MT25408_PRM.h:2199
hermonprm_mgm_entry_st::mgmqp_0
struct hermonprm_mgmqp_st mgmqp_0
Definition: MT25408_PRM.h:1976
hermonprm_set_ib_st::capability_mask
pseudo_bit_t capability_mask[0x00020]
Definition: MT25408_PRM.h:1942
hermonprm_completion_queue_context_st::usr_page
pseudo_bit_t usr_page[0x00018]
Definition: MT25408_PRM.h:2582
hermonprm_wqe_segment_ctrl_send_st::owner
pseudo_bit_t owner[0x00001]
Definition: MT25408_PRM.h:249
hermonprm_hermon_prm_st::reserved8
pseudo_bit_t reserved8[0xfff20]
Definition: MT25408_PRM.h:3191
hermonprm_completion_queue_context_st::cq_max_count
pseudo_bit_t cq_max_count[0x00010]
Definition: MT25408_PRM.h:2587
hermonprm_eqc_st::oi
pseudo_bit_t oi[0x00001]
Definition: MT25408_PRM.h:2422
hermonprm_completion_queue_error_st::reserved0
pseudo_bit_t reserved0[0x00008]
Definition: MT25408_PRM.h:2936
hermonprm_mpt_st::bqp
pseudo_bit_t bqp[0x00001]
Definition: MT25408_PRM.h:2502
hermonprm_queue_pair_ee_context_entry_st::reserved32
pseudo_bit_t reserved32[0x00008]
Definition: MT25408_PRM.h:911
hermonprm_eq_set_ci_table_st::reserved34
pseudo_bit_t reserved34[0x00020]
Definition: MT25408_PRM.h:1153
hermonprm_eqc_st::reserved15
pseudo_bit_t reserved15[0x00080]
Definition: MT25408_PRM.h:2467
hermonprm_send_doorbell_st::wqe_counter
pseudo_bit_t wqe_counter[0x00010]
Definition: MT25408_PRM.h:83
hermonprm_port_state_change_st
Definition: MT25408_PRM.h:2921
hermonprm_mpt_st
Definition: MT25408_PRM.h:2484
hermonprm_wqe_segment_data_ptr_st::byte_count
pseudo_bit_t byte_count[0x0001f]
Definition: MT25408_PRM.h:109
hermonprm_wqe_segment_bind_st::length_l
pseudo_bit_t length_l[0x00020]
Definition: MT25408_PRM.h:214
hermonprm_qp_db_record_st::reserved0
pseudo_bit_t reserved0[0x00010]
Definition: MT25408_PRM.h:1288
hermonprm_page_fault_event_data_st::reserved0
pseudo_bit_t reserved0[0x00003]
Definition: MT25408_PRM.h:2888
hermonprm_completion_queue_entry_st::opcode
pseudo_bit_t opcode[0x00005]
Definition: MT25408_PRM.h:3041
hermonprm_mad_ifc_st::reserved4
pseudo_bit_t reserved4[0x00004]
Definition: MT25408_PRM.h:1827
hermonprm_queue_pair_ee_context_entry_st::rre
pseudo_bit_t rre[0x00001]
Definition: MT25408_PRM.h:896
hermonprm_eq_set_ci_table_st::reserved19
pseudo_bit_t reserved19[0x00020]
Definition: MT25408_PRM.h:1093
hermonprm_mod_stat_cfg_st::tx_options
pseudo_bit_t tx_options[0x00004]
Definition: MT25408_PRM.h:1346
hermonprm_transport_and_ci_error_counters_st::sq_num_rire
pseudo_bit_t sq_num_rire[0x00020]
Definition: MT25408_PRM.h:1596
hermonprm_eqc_st::log2_page_size
pseudo_bit_t log2_page_size[0x00006]
Definition: MT25408_PRM.h:2449
hermonprm_vsd_st::vsd_dw52
pseudo_bit_t vsd_dw52[0x00020]
Definition: MT25408_PRM.h:516
hermonprm_resize_cq_st::reserved4
pseudo_bit_t reserved4[0x00003]
Definition: MT25408_PRM.h:1777
hermonprm_wqe_segment_bind_st::rr
pseudo_bit_t rr[0x00001]
Definition: MT25408_PRM.h:192
hermonprm_wqe_segment_ctrl_send_st::c
pseudo_bit_t c[0x00002]
Definition: MT25408_PRM.h:257
hermonprm_mod_stat_cfg_st::nodeguid_lo
pseudo_bit_t nodeguid_lo[0x00020]
Definition: MT25408_PRM.h:1389
hermonprm_completion_with_error_st::s_r
pseudo_bit_t s_r[0x00001]
Definition: MT25408_PRM.h:1760
hermonprm_mt25208_type0_st::pciex_cap_id
pseudo_bit_t pciex_cap_id[0x00008]
Definition: MT25408_PRM.h:2764
hermonprm_mcg_hdr_st
Definition: MT25408_PRM.h:3066
hermonprm_resize_cq_st::reserved0
pseudo_bit_t reserved0[0x00040]
Definition: MT25408_PRM.h:1769
hermonprm_transport_and_ci_error_counters_st::rq_num_udsdprd
pseudo_bit_t rq_num_udsdprd[0x00020]
Definition: MT25408_PRM.h:1685
hermonprm_address_path_st::reserved1
pseudo_bit_t reserved1[0x00008]
Definition: MT25408_PRM.h:280
hermonprm_pbl_st::mtt_0_h
pseudo_bit_t mtt_0_h[0x00020]
Definition: MT25408_PRM.h:1526
hermonprm_queue_pair_ee_context_entry_st::rq_wqe_counter
pseudo_bit_t rq_wqe_counter[0x00010]
Definition: MT25408_PRM.h:933
hermonprm_mt25208_type0_st::subsystem_id
pseudo_bit_t subsystem_id[0x00010]
Definition: MT25408_PRM.h:2703
hermonprm_mpt_st::mtt_size
pseudo_bit_t mtt_size[0x00020]
Definition: MT25408_PRM.h:2542
hermonprm_mpt_st::ei
pseudo_bit_t ei[0x00001]
Definition: MT25408_PRM.h:2509
hermonprm_resize_cq_st::reserved7
pseudo_bit_t reserved7[0x00002]
Definition: MT25408_PRM.h:1784
hermonprm_init_hca_st::reserved7
pseudo_bit_t reserved7[0x00100]
Definition: MT25408_PRM.h:2396
hermonprm_gpio_event_data_st::reserved1
pseudo_bit_t reserved1[0x00020]
Definition: MT25408_PRM.h:2641
hermonprm_completion_queue_entry_st::vlan
pseudo_bit_t vlan[0x00002]
Definition: MT25408_PRM.h:3001
hermonprm_transport_and_ci_error_counters_st::sq_num_rnr
pseudo_bit_t sq_num_rnr[0x00020]
Definition: MT25408_PRM.h:1655
hermonprm_vsd_st::vsd_dw24
pseudo_bit_t vsd_dw24[0x00020]
Definition: MT25408_PRM.h:460
hermonprm_query_dev_cap_st::num_rsvd_scrds
pseudo_bit_t num_rsvd_scrds[0x00004]
Definition: MT25408_PRM.h:2215
hermonprm_scrubbing_event_st::reserved0
pseudo_bit_t reserved0[0x00080]
Definition: MT25408_PRM.h:3125
hermonprm_eq_set_ci_table_st::reserved25
pseudo_bit_t reserved25[0x00020]
Definition: MT25408_PRM.h:1117
hermonprm_hermon_prm_st::performance_counters
struct hermonprm_performance_counters_st performance_counters
Definition: MT25408_PRM.h:3351
hermonprm_page_fault_event_data_st::prefetch_len
pseudo_bit_t prefetch_len[0x00020]
Definition: MT25408_PRM.h:2898
hermonprm_mgmqp_st::reserved0
pseudo_bit_t reserved0[0x00006]
Definition: MT25408_PRM.h:403
hermonprm_address_path_st::reserved4
pseudo_bit_t reserved4[0x00004]
Definition: MT25408_PRM.h:305
hermonprm_wqe_segment_st::reserved2
pseudo_bit_t reserved2[0x00080]
Definition: MT25408_PRM.h:2915
hermonprm_cq_cmd_doorbell_st::cmd
pseudo_bit_t cmd[0x00003]
Definition: MT25408_PRM.h:368
hermonprm_mt25208_type0_st::msi_next_cap_ptr
pseudo_bit_t msi_next_cap_ptr[0x00008]
Definition: MT25408_PRM.h:2722
Generated by   doxygen 1.8.15