iPXE
Data Structures | Defines | Functions
Pci22.h File Reference

Support for PCI 2.2 standard. More...

Go to the source code of this file.

Data Structures

struct  PCI_DEVICE_INDEPENDENT_REGION
 Common header region in PCI Configuration Space Section 6.1, PCI Local Bus Specification, 2.2. More...
struct  PCI_DEVICE_HEADER_TYPE_REGION
 PCI Device header region in PCI Configuration Space Section 6.1, PCI Local Bus Specification, 2.2. More...
struct  PCI_TYPE00
 PCI Device Configuration Space Section 6.1, PCI Local Bus Specification, 2.2. More...
struct  PCI_BRIDGE_CONTROL_REGISTER
 PCI-PCI Bridge header region in PCI Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1.2. More...
struct  PCI_TYPE01
 PCI-to-PCI Bridge Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1.2. More...
union  PCI_TYPE_GENERIC
struct  PCI_CARDBUS_CONTROL_REGISTER
 CardBus Conroller Configuration Space, Section 4.5.1, PC Card Standard. More...
union  PCI_CONFIG_ACCESS_CF8
 PCI Access Data Format. More...
struct  EFI_PCI_CAPABILITY_HDR
 Capabilities List Header Section 6.7, PCI Local Bus Specification, 2.2. More...
union  EFI_PCI_PMC
 PMC - Power Management Capabilities Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2. More...
union  EFI_PCI_PMCSR
 PMCSR - Power Management Control/Status Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2. More...
union  EFI_PCI_PMCSR_BSE
 PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2. More...
struct  EFI_PCI_CAPABILITY_PMI
 Power Management Register Block Definition Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2. More...
struct  EFI_PCI_CAPABILITY_AGP
 A.G.P Capability Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0. More...
struct  EFI_PCI_CAPABILITY_VPD
 VPD Capability Structure Appendix I, PCI Local Bus Specification, 2.2. More...
struct  EFI_PCI_CAPABILITY_SLOTID
 Slot Numbering Capabilities Register Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2. More...
struct  EFI_PCI_CAPABILITY_MSI32
 Message Capability Structure for 32-bit Message Address Section 6.8.1, PCI Local Bus Specification, 2.2. More...
struct  EFI_PCI_CAPABILITY_MSI64
 Message Capability Structure for 64-bit Message Address Section 6.8.1, PCI Local Bus Specification, 2.2. More...
struct  EFI_PCI_CAPABILITY_HOTPLUG
 Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, CompactPCI Hot Swap Specification PICMG 2.1, R1.0. More...
struct  PCI_EXPANSION_ROM_HEADER
 Standard PCI Expansion ROM Header Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1. More...
struct  EFI_LEGACY_EXPANSION_ROM_HEADER
 Legacy ROM Header Extensions Section 6.3.3.1, PCI Local Bus Specification, 2.2. More...
struct  PCI_DATA_STRUCTURE
 PCI Data Structure Format Section 6.3.1.2, PCI Local Bus Specification, 2.2. More...
struct  EFI_PCI_EXPANSION_ROM_HEADER
 EFI PCI Expansion ROM Header Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1. More...
union  EFI_PCI_ROM_HEADER

Defines

#define PCI_MAX_BUS   255
#define PCI_MAX_DEVICE   31
#define PCI_MAX_FUNC   7
#define PCI_CLASS_OLD   0x00
#define PCI_CLASS_OLD_OTHER   0x00
#define PCI_CLASS_OLD_VGA   0x01
#define PCI_CLASS_MASS_STORAGE   0x01
#define PCI_CLASS_MASS_STORAGE_SCSI   0x00
#define PCI_CLASS_MASS_STORAGE_IDE   0x01
#define PCI_CLASS_MASS_STORAGE_FLOPPY   0x02
#define PCI_CLASS_MASS_STORAGE_IPI   0x03
#define PCI_CLASS_MASS_STORAGE_RAID   0x04
#define PCI_CLASS_MASS_STORAGE_OTHER   0x80
#define PCI_CLASS_NETWORK   0x02
#define PCI_CLASS_NETWORK_ETHERNET   0x00
#define PCI_CLASS_NETWORK_TOKENRING   0x01
#define PCI_CLASS_NETWORK_FDDI   0x02
#define PCI_CLASS_NETWORK_ATM   0x03
#define PCI_CLASS_NETWORK_ISDN   0x04
#define PCI_CLASS_NETWORK_OTHER   0x80
#define PCI_CLASS_DISPLAY   0x03
#define PCI_CLASS_DISPLAY_VGA   0x00
#define PCI_IF_VGA_VGA   0x00
#define PCI_IF_VGA_8514   0x01
#define PCI_CLASS_DISPLAY_XGA   0x01
#define PCI_CLASS_DISPLAY_3D   0x02
#define PCI_CLASS_DISPLAY_OTHER   0x80
#define PCI_CLASS_MEDIA   0x04
#define PCI_CLASS_MEDIA_VIDEO   0x00
#define PCI_CLASS_MEDIA_AUDIO   0x01
#define PCI_CLASS_MEDIA_TELEPHONE   0x02
#define PCI_CLASS_MEDIA_OTHER   0x80
#define PCI_CLASS_MEMORY_CONTROLLER   0x05
#define PCI_CLASS_MEMORY_RAM   0x00
#define PCI_CLASS_MEMORY_FLASH   0x01
#define PCI_CLASS_MEMORY_OTHER   0x80
#define PCI_CLASS_BRIDGE   0x06
#define PCI_CLASS_BRIDGE_HOST   0x00
#define PCI_CLASS_BRIDGE_ISA   0x01
#define PCI_CLASS_BRIDGE_EISA   0x02
#define PCI_CLASS_BRIDGE_MCA   0x03
#define PCI_CLASS_BRIDGE_P2P   0x04
#define PCI_IF_BRIDGE_P2P   0x00
#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE   0x01
#define PCI_CLASS_BRIDGE_PCMCIA   0x05
#define PCI_CLASS_BRIDGE_NUBUS   0x06
#define PCI_CLASS_BRIDGE_CARDBUS   0x07
#define PCI_CLASS_BRIDGE_RACEWAY   0x08
#define PCI_CLASS_BRIDGE_OTHER   0x80
#define PCI_CLASS_BRIDGE_ISA_PDECODE   0x80
#define PCI_CLASS_SCC   0x07
 Simple communications controllers.
#define PCI_SUBCLASS_SERIAL   0x00
#define PCI_IF_GENERIC_XT   0x00
#define PCI_IF_16450   0x01
#define PCI_IF_16550   0x02
#define PCI_IF_16650   0x03
#define PCI_IF_16750   0x04
#define PCI_IF_16850   0x05
#define PCI_IF_16950   0x06
#define PCI_SUBCLASS_PARALLEL   0x01
#define PCI_IF_PARALLEL_PORT   0x00
#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01
#define PCI_IF_ECP_PARALLEL_PORT   0x02
#define PCI_IF_1284_CONTROLLER   0x03
#define PCI_IF_1284_DEVICE   0xFE
#define PCI_SUBCLASS_MULTIPORT_SERIAL   0x02
#define PCI_SUBCLASS_MODEM   0x03
#define PCI_IF_GENERIC_MODEM   0x00
#define PCI_IF_16450_MODEM   0x01
#define PCI_IF_16550_MODEM   0x02
#define PCI_IF_16650_MODEM   0x03
#define PCI_IF_16750_MODEM   0x04
#define PCI_SUBCLASS_SCC_OTHER   0x80
#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
#define PCI_SUBCLASS_PIC   0x00
#define PCI_IF_8259_PIC   0x00
#define PCI_IF_ISA_PIC   0x01
#define PCI_IF_EISA_PIC   0x02
#define PCI_IF_APIC_CONTROLLER   0x10
 I/O APIC interrupt controller , 32 bye none-prefectable memory.
#define PCI_IF_APIC_CONTROLLER2   0x20
#define PCI_SUBCLASS_DMA   0x01
#define PCI_IF_8237_DMA   0x00
#define PCI_IF_ISA_DMA   0x01
#define PCI_IF_EISA_DMA   0x02
#define PCI_SUBCLASS_TIMER   0x02
#define PCI_IF_8254_TIMER   0x00
#define PCI_IF_ISA_TIMER   0x01
#define PCI_IF_EISA_TIMER   0x02
#define PCI_SUBCLASS_RTC   0x03
#define PCI_IF_GENERIC_RTC   0x00
#define PCI_IF_ISA_RTC   0x01
#define PCI_SUBCLASS_PNP_CONTROLLER   0x04
 HotPlug Controller.
#define PCI_SUBCLASS_PERIPHERAL_OTHER   0x80
#define PCI_CLASS_INPUT_DEVICE   0x09
#define PCI_SUBCLASS_KEYBOARD   0x00
#define PCI_SUBCLASS_PEN   0x01
#define PCI_SUBCLASS_MOUSE_CONTROLLER   0x02
#define PCI_SUBCLASS_SCAN_CONTROLLER   0x03
#define PCI_SUBCLASS_GAMEPORT   0x04
#define PCI_IF_GAMEPORT   0x00
#define PCI_IF_GAMEPORT1   0x10
#define PCI_SUBCLASS_INPUT_OTHER   0x80
#define PCI_CLASS_DOCKING_STATION   0x0A
#define PCI_SUBCLASS_DOCKING_GENERIC   0x00
#define PCI_SUBCLASS_DOCKING_OTHER   0x80
#define PCI_CLASS_PROCESSOR   0x0B
#define PCI_SUBCLASS_PROC_386   0x00
#define PCI_SUBCLASS_PROC_486   0x01
#define PCI_SUBCLASS_PROC_PENTIUM   0x02
#define PCI_SUBCLASS_PROC_ALPHA   0x10
#define PCI_SUBCLASS_PROC_POWERPC   0x20
#define PCI_SUBCLASS_PROC_MIPS   0x30
#define PCI_SUBCLASS_PROC_CO_PORC   0x40
 Co-Processor.
#define PCI_CLASS_SERIAL   0x0C
#define PCI_CLASS_SERIAL_FIREWIRE   0x00
#define PCI_IF_1394   0x00
#define PCI_IF_1394_OPEN_HCI   0x10
#define PCI_CLASS_SERIAL_ACCESS_BUS   0x01
#define PCI_CLASS_SERIAL_SSA   0x02
#define PCI_CLASS_SERIAL_USB   0x03
#define PCI_IF_UHCI   0x00
#define PCI_IF_OHCI   0x10
#define PCI_IF_USB_OTHER   0x80
#define PCI_IF_USB_DEVICE   0xFE
#define PCI_CLASS_SERIAL_FIBRECHANNEL   0x04
#define PCI_CLASS_SERIAL_SMB   0x05
#define PCI_CLASS_WIRELESS   0x0D
#define PCI_SUBCLASS_IRDA   0x00
#define PCI_SUBCLASS_IR   0x01
#define PCI_SUBCLASS_RF   0x10
#define PCI_SUBCLASS_WIRELESS_OTHER   0x80
#define PCI_CLASS_INTELLIGENT_IO   0x0E
#define PCI_CLASS_SATELLITE   0x0F
#define PCI_SUBCLASS_TV   0x01
#define PCI_SUBCLASS_AUDIO   0x02
#define PCI_SUBCLASS_VOICE   0x03
#define PCI_SUBCLASS_DATA   0x04
#define PCI_SECURITY_CONTROLLER   0x10
 Encryption and decryption controller.
#define PCI_SUBCLASS_NET_COMPUT   0x00
#define PCI_SUBCLASS_ENTERTAINMENT   0x10
#define PCI_SUBCLASS_SECURITY_OTHER   0x80
#define PCI_CLASS_DPIO   0x11
#define PCI_SUBCLASS_DPIO   0x00
#define PCI_SUBCLASS_DPIO_OTHER   0x80
#define IS_CLASS1(_p, c)   ((_p)->Hdr.ClassCode[2] == (c))
 Macro that checks whether the Base Class code of device matched.
#define IS_CLASS2(_p, c, s)   (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 Macro that checks whether the Base Class code and Sub-Class code of device matched.
#define IS_CLASS3(_p, c, s, p)   (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
#define IS_PCI_DISPLAY(_p)   IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 Macro that checks whether device is a display controller.
#define IS_PCI_VGA(_p)   IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
 Macro that checks whether device is a VGA-compatible controller.
#define IS_PCI_8514(_p)   IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
 Macro that checks whether device is an 8514-compatible controller.
#define IS_PCI_OLD(_p)   IS_CLASS1 (_p, PCI_CLASS_OLD)
 Macro that checks whether device is built before the Class Code field was defined.
#define IS_PCI_OLD_VGA(_p)   IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
#define IS_PCI_IDE(_p)   IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 Macro that checks whether device is an IDE controller.
#define IS_PCI_SCSI(_p)   IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
 Macro that checks whether device is a SCSI bus controller.
#define IS_PCI_RAID(_p)   IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
 Macro that checks whether device is a RAID controller.
#define IS_PCI_LPC(_p)   IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
 Macro that checks whether device is an ISA bridge.
#define IS_PCI_P2P(_p)   IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
 Macro that checks whether device is a PCI-to-PCI bridge.
#define IS_PCI_P2P_SUB(_p)   IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
#define IS_PCI_16550_SERIAL(_p)   IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
 Macro that checks whether device is a 16550-compatible serial controller.
#define IS_PCI_USB(_p)   IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 Macro that checks whether device is a Universal Serial Bus controller.
#define HEADER_TYPE_DEVICE   0x00
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE   0x01
#define HEADER_TYPE_CARDBUS_BRIDGE   0x02
#define HEADER_TYPE_MULTI_FUNCTION   0x80
#define HEADER_LAYOUT_CODE   0x7f
#define IS_PCI_BRIDGE(_p)   (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 Macro that checks whether device is a PCI-PCI bridge.
#define IS_CARDBUS_BRIDGE(_p)   (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 Macro that checks whether device is a CardBus bridge.
#define IS_PCI_MULTI_FUNC(_p)   ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 Macro that checks whether device is a multiple functions device.
#define PCI_BRIDGE_ROMBAR   0x38
 Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,.
#define PCI_MAX_BAR   0x0006
#define PCI_MAX_CONFIG_OFFSET   0x0100
#define PCI_VENDOR_ID_OFFSET   0x00
#define PCI_DEVICE_ID_OFFSET   0x02
#define PCI_COMMAND_OFFSET   0x04
#define PCI_PRIMARY_STATUS_OFFSET   0x06
#define PCI_REVISION_ID_OFFSET   0x08
#define PCI_CLASSCODE_OFFSET   0x09
#define PCI_CACHELINE_SIZE_OFFSET   0x0C
#define PCI_LATENCY_TIMER_OFFSET   0x0D
#define PCI_HEADER_TYPE_OFFSET   0x0E
#define PCI_BIST_OFFSET   0x0F
#define PCI_BASE_ADDRESSREG_OFFSET   0x10
#define PCI_CARDBUS_CIS_OFFSET   0x28
#define PCI_SVID_OFFSET   0x2C
 SubSystem Vendor id.
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET   0x2C
#define PCI_SID_OFFSET   0x2E
 SubSystem ID.
#define PCI_SUBSYSTEM_ID_OFFSET   0x2E
#define PCI_EXPANSION_ROM_BASE   0x30
#define PCI_CAPBILITY_POINTER_OFFSET   0x34
#define PCI_INT_LINE_OFFSET   0x3C
 Interrupt Line Register.
#define PCI_INT_PIN_OFFSET   0x3D
 Interrupt Pin Register.
#define PCI_MAXGNT_OFFSET   0x3E
 Max Grant Register.
#define PCI_MAXLAT_OFFSET   0x3F
 Max Latency Register.
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET   0x18
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET   0x19
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET   0x1a
#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET   0x1E
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET   0x3E
#define PCI_INT_LINE_UNKNOWN   0xFF
 Interrupt Line "Unknown" or "No connection" value defined for x86 based system.
#define EFI_PCI_COMMAND_IO_SPACE   BIT0
 0x0001
#define EFI_PCI_COMMAND_MEMORY_SPACE   BIT1
 0x0002
#define EFI_PCI_COMMAND_BUS_MASTER   BIT2
 0x0004
#define EFI_PCI_COMMAND_SPECIAL_CYCLE   BIT3
 0x0008
#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE   BIT4
 0x0010
#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP   BIT5
 0x0020
#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND   BIT6
 0x0040
#define EFI_PCI_COMMAND_STEPPING_CONTROL   BIT7
 0x0080
#define EFI_PCI_COMMAND_SERR   BIT8
 0x0100
#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK   BIT9
 0x0200
#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE   BIT0
 0x0001
#define EFI_PCI_BRIDGE_CONTROL_SERR   BIT1
 0x0002
#define EFI_PCI_BRIDGE_CONTROL_ISA   BIT2
 0x0004
#define EFI_PCI_BRIDGE_CONTROL_VGA   BIT3
 0x0008
#define EFI_PCI_BRIDGE_CONTROL_VGA_16   BIT4
 0x0010
#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT   BIT5
 0x0020
#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS   BIT6
 0x0040
#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK   BIT7
 0x0080
#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER   BIT8
 0x0100
#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER   BIT9
 0x0200
#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS   BIT10
 0x0400
#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR   BIT11
 0x0800
#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE   BIT7
 0x0080
#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE   BIT8
 0x0100
#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE   BIT9
 0x0200
#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE   BIT10
 0x0400
#define EFI_PCI_STATUS_CAPABILITY   BIT4
 0x0010
#define EFI_PCI_STATUS_66MZ_CAPABLE   BIT5
 0x0020
#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE   BIT7
 0x0080
#define EFI_PCI_MASTER_DATA_PARITY_ERROR   BIT8
 0x0100
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR   0x14
 defined in PC Card Standard
#define EFI_PCI_CAPABILITY_ID_PMI   0x01
#define EFI_PCI_CAPABILITY_ID_AGP   0x02
#define EFI_PCI_CAPABILITY_ID_VPD   0x03
#define EFI_PCI_CAPABILITY_ID_SLOTID   0x04
#define EFI_PCI_CAPABILITY_ID_MSI   0x05
#define EFI_PCI_CAPABILITY_ID_HOTPLUG   0x06
#define EFI_PCI_CAPABILITY_ID_SHPC   0x0C
#define EFI_PCI_PMC_D3_COLD_MASK   (BIT15)
#define PCI_POWER_STATE_D0   0
#define PCI_POWER_STATE_D1   1
#define PCI_POWER_STATE_D2   2
#define PCI_POWER_STATE_D3_HOT   3
#define PCI_BAR_IDX0   0x00
#define PCI_BAR_IDX1   0x01
#define PCI_BAR_IDX2   0x02
#define PCI_BAR_IDX3   0x03
#define PCI_BAR_IDX4   0x04
#define PCI_BAR_IDX5   0x05
#define EFI_ROOT_BRIDGE_LIST   'eprb'
 EFI PCI Option ROM definitions.
#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE   0x0EF1
 defined in UEFI Spec.
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE   0xaa55
#define PCI_DATA_STRUCTURE_SIGNATURE   SIGNATURE_32 ('P', 'C', 'I', 'R')
#define PCI_CODE_TYPE_PCAT_IMAGE   0x00
#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED   0x0001
 defined in UEFI spec.

Functions

 FILE_LICENCE (BSD3)

Detailed Description

Support for PCI 2.2 standard.

This file includes the definitions in the following specifications, PCI Local Bus Specification, 2.2 PCI-to-PCI Bridge Architecture Specification, Revision 1.2 PC Card Standard, 8.0 PCI Power Management Interface Specifiction, Revision 1.2

Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file Pci22.h.


Define Documentation

#define PCI_MAX_BUS   255

Definition at line 27 of file Pci22.h.

#define PCI_MAX_DEVICE   31

Definition at line 28 of file Pci22.h.

#define PCI_MAX_FUNC   7

Definition at line 29 of file Pci22.h.

#define PCI_CLASS_OLD   0x00

Definition at line 150 of file Pci22.h.

#define PCI_CLASS_OLD_OTHER   0x00

Definition at line 151 of file Pci22.h.

#define PCI_CLASS_OLD_VGA   0x01

Definition at line 152 of file Pci22.h.

#define PCI_CLASS_MASS_STORAGE   0x01

Definition at line 154 of file Pci22.h.

#define PCI_CLASS_MASS_STORAGE_SCSI   0x00

Definition at line 155 of file Pci22.h.

#define PCI_CLASS_MASS_STORAGE_IDE   0x01

Definition at line 156 of file Pci22.h.

#define PCI_CLASS_MASS_STORAGE_FLOPPY   0x02

Definition at line 157 of file Pci22.h.

#define PCI_CLASS_MASS_STORAGE_IPI   0x03

Definition at line 158 of file Pci22.h.

#define PCI_CLASS_MASS_STORAGE_RAID   0x04

Definition at line 159 of file Pci22.h.

#define PCI_CLASS_MASS_STORAGE_OTHER   0x80

Definition at line 160 of file Pci22.h.

#define PCI_CLASS_NETWORK   0x02

Definition at line 162 of file Pci22.h.

#define PCI_CLASS_NETWORK_ETHERNET   0x00

Definition at line 163 of file Pci22.h.

#define PCI_CLASS_NETWORK_TOKENRING   0x01

Definition at line 164 of file Pci22.h.

#define PCI_CLASS_NETWORK_FDDI   0x02

Definition at line 165 of file Pci22.h.

#define PCI_CLASS_NETWORK_ATM   0x03

Definition at line 166 of file Pci22.h.

#define PCI_CLASS_NETWORK_ISDN   0x04

Definition at line 167 of file Pci22.h.

#define PCI_CLASS_NETWORK_OTHER   0x80

Definition at line 168 of file Pci22.h.

#define PCI_CLASS_DISPLAY   0x03

Definition at line 170 of file Pci22.h.

#define PCI_CLASS_DISPLAY_VGA   0x00

Definition at line 171 of file Pci22.h.

#define PCI_IF_VGA_VGA   0x00

Definition at line 172 of file Pci22.h.

#define PCI_IF_VGA_8514   0x01

Definition at line 173 of file Pci22.h.

#define PCI_CLASS_DISPLAY_XGA   0x01

Definition at line 174 of file Pci22.h.

#define PCI_CLASS_DISPLAY_3D   0x02

Definition at line 175 of file Pci22.h.

#define PCI_CLASS_DISPLAY_OTHER   0x80

Definition at line 176 of file Pci22.h.

#define PCI_CLASS_MEDIA   0x04

Definition at line 178 of file Pci22.h.

#define PCI_CLASS_MEDIA_VIDEO   0x00

Definition at line 179 of file Pci22.h.

#define PCI_CLASS_MEDIA_AUDIO   0x01

Definition at line 180 of file Pci22.h.

#define PCI_CLASS_MEDIA_TELEPHONE   0x02

Definition at line 181 of file Pci22.h.

#define PCI_CLASS_MEDIA_OTHER   0x80

Definition at line 182 of file Pci22.h.

#define PCI_CLASS_MEMORY_CONTROLLER   0x05

Definition at line 184 of file Pci22.h.

#define PCI_CLASS_MEMORY_RAM   0x00

Definition at line 185 of file Pci22.h.

#define PCI_CLASS_MEMORY_FLASH   0x01

Definition at line 186 of file Pci22.h.

#define PCI_CLASS_MEMORY_OTHER   0x80

Definition at line 187 of file Pci22.h.

#define PCI_CLASS_BRIDGE   0x06

Definition at line 189 of file Pci22.h.

#define PCI_CLASS_BRIDGE_HOST   0x00

Definition at line 190 of file Pci22.h.

#define PCI_CLASS_BRIDGE_ISA   0x01

Definition at line 191 of file Pci22.h.

#define PCI_CLASS_BRIDGE_EISA   0x02

Definition at line 192 of file Pci22.h.

#define PCI_CLASS_BRIDGE_MCA   0x03

Definition at line 193 of file Pci22.h.

#define PCI_CLASS_BRIDGE_P2P   0x04

Definition at line 194 of file Pci22.h.

#define PCI_IF_BRIDGE_P2P   0x00

Definition at line 195 of file Pci22.h.

#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE   0x01

Definition at line 196 of file Pci22.h.

#define PCI_CLASS_BRIDGE_PCMCIA   0x05

Definition at line 197 of file Pci22.h.

#define PCI_CLASS_BRIDGE_NUBUS   0x06

Definition at line 198 of file Pci22.h.

#define PCI_CLASS_BRIDGE_CARDBUS   0x07

Definition at line 199 of file Pci22.h.

#define PCI_CLASS_BRIDGE_RACEWAY   0x08

Definition at line 200 of file Pci22.h.

#define PCI_CLASS_BRIDGE_OTHER   0x80

Definition at line 201 of file Pci22.h.

#define PCI_CLASS_BRIDGE_ISA_PDECODE   0x80

Definition at line 202 of file Pci22.h.

#define PCI_CLASS_SCC   0x07

Simple communications controllers.

Definition at line 204 of file Pci22.h.

#define PCI_SUBCLASS_SERIAL   0x00

Definition at line 205 of file Pci22.h.

#define PCI_IF_GENERIC_XT   0x00

Definition at line 206 of file Pci22.h.

#define PCI_IF_16450   0x01

Definition at line 207 of file Pci22.h.

#define PCI_IF_16550   0x02

Definition at line 208 of file Pci22.h.

#define PCI_IF_16650   0x03

Definition at line 209 of file Pci22.h.

#define PCI_IF_16750   0x04

Definition at line 210 of file Pci22.h.

#define PCI_IF_16850   0x05

Definition at line 211 of file Pci22.h.

#define PCI_IF_16950   0x06

Definition at line 212 of file Pci22.h.

#define PCI_SUBCLASS_PARALLEL   0x01

Definition at line 213 of file Pci22.h.

#define PCI_IF_PARALLEL_PORT   0x00

Definition at line 214 of file Pci22.h.

#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01

Definition at line 215 of file Pci22.h.

#define PCI_IF_ECP_PARALLEL_PORT   0x02

Definition at line 216 of file Pci22.h.

#define PCI_IF_1284_CONTROLLER   0x03

Definition at line 217 of file Pci22.h.

#define PCI_IF_1284_DEVICE   0xFE

Definition at line 218 of file Pci22.h.

#define PCI_SUBCLASS_MULTIPORT_SERIAL   0x02

Definition at line 219 of file Pci22.h.

#define PCI_SUBCLASS_MODEM   0x03

Definition at line 220 of file Pci22.h.

#define PCI_IF_GENERIC_MODEM   0x00

Definition at line 221 of file Pci22.h.

#define PCI_IF_16450_MODEM   0x01

Definition at line 222 of file Pci22.h.

#define PCI_IF_16550_MODEM   0x02

Definition at line 223 of file Pci22.h.

#define PCI_IF_16650_MODEM   0x03

Definition at line 224 of file Pci22.h.

#define PCI_IF_16750_MODEM   0x04

Definition at line 225 of file Pci22.h.

#define PCI_SUBCLASS_SCC_OTHER   0x80

Definition at line 226 of file Pci22.h.

#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08

Definition at line 228 of file Pci22.h.

#define PCI_SUBCLASS_PIC   0x00

Definition at line 229 of file Pci22.h.

#define PCI_IF_8259_PIC   0x00

Definition at line 230 of file Pci22.h.

#define PCI_IF_ISA_PIC   0x01

Definition at line 231 of file Pci22.h.

#define PCI_IF_EISA_PIC   0x02

Definition at line 232 of file Pci22.h.

#define PCI_IF_APIC_CONTROLLER   0x10

I/O APIC interrupt controller , 32 bye none-prefectable memory.

Definition at line 233 of file Pci22.h.

#define PCI_IF_APIC_CONTROLLER2   0x20

Definition at line 234 of file Pci22.h.

#define PCI_SUBCLASS_DMA   0x01

Definition at line 235 of file Pci22.h.

#define PCI_IF_8237_DMA   0x00

Definition at line 236 of file Pci22.h.

#define PCI_IF_ISA_DMA   0x01

Definition at line 237 of file Pci22.h.

#define PCI_IF_EISA_DMA   0x02

Definition at line 238 of file Pci22.h.

#define PCI_SUBCLASS_TIMER   0x02

Definition at line 239 of file Pci22.h.

#define PCI_IF_8254_TIMER   0x00

Definition at line 240 of file Pci22.h.

#define PCI_IF_ISA_TIMER   0x01

Definition at line 241 of file Pci22.h.

#define PCI_IF_EISA_TIMER   0x02

Definition at line 242 of file Pci22.h.

#define PCI_SUBCLASS_RTC   0x03

Definition at line 243 of file Pci22.h.

#define PCI_IF_GENERIC_RTC   0x00

Definition at line 244 of file Pci22.h.

#define PCI_IF_ISA_RTC   0x01

Definition at line 245 of file Pci22.h.

#define PCI_SUBCLASS_PNP_CONTROLLER   0x04

HotPlug Controller.

Definition at line 246 of file Pci22.h.

#define PCI_SUBCLASS_PERIPHERAL_OTHER   0x80

Definition at line 247 of file Pci22.h.

#define PCI_CLASS_INPUT_DEVICE   0x09

Definition at line 249 of file Pci22.h.

#define PCI_SUBCLASS_KEYBOARD   0x00

Definition at line 250 of file Pci22.h.

#define PCI_SUBCLASS_PEN   0x01

Definition at line 251 of file Pci22.h.

#define PCI_SUBCLASS_MOUSE_CONTROLLER   0x02

Definition at line 252 of file Pci22.h.

#define PCI_SUBCLASS_SCAN_CONTROLLER   0x03

Definition at line 253 of file Pci22.h.

#define PCI_SUBCLASS_GAMEPORT   0x04

Definition at line 254 of file Pci22.h.

#define PCI_IF_GAMEPORT   0x00

Definition at line 255 of file Pci22.h.

#define PCI_IF_GAMEPORT1   0x10

Definition at line 256 of file Pci22.h.

#define PCI_SUBCLASS_INPUT_OTHER   0x80

Definition at line 257 of file Pci22.h.

#define PCI_CLASS_DOCKING_STATION   0x0A

Definition at line 259 of file Pci22.h.

#define PCI_SUBCLASS_DOCKING_GENERIC   0x00

Definition at line 260 of file Pci22.h.

#define PCI_SUBCLASS_DOCKING_OTHER   0x80

Definition at line 261 of file Pci22.h.

#define PCI_CLASS_PROCESSOR   0x0B

Definition at line 263 of file Pci22.h.

#define PCI_SUBCLASS_PROC_386   0x00

Definition at line 264 of file Pci22.h.

#define PCI_SUBCLASS_PROC_486   0x01

Definition at line 265 of file Pci22.h.

#define PCI_SUBCLASS_PROC_PENTIUM   0x02

Definition at line 266 of file Pci22.h.

#define PCI_SUBCLASS_PROC_ALPHA   0x10

Definition at line 267 of file Pci22.h.

#define PCI_SUBCLASS_PROC_POWERPC   0x20

Definition at line 268 of file Pci22.h.

#define PCI_SUBCLASS_PROC_MIPS   0x30

Definition at line 269 of file Pci22.h.

#define PCI_SUBCLASS_PROC_CO_PORC   0x40

Co-Processor.

Definition at line 270 of file Pci22.h.

#define PCI_CLASS_SERIAL   0x0C

Definition at line 272 of file Pci22.h.

Referenced by ehci_companion(), and ehci_poll_companions().

#define PCI_CLASS_SERIAL_FIREWIRE   0x00

Definition at line 273 of file Pci22.h.

#define PCI_IF_1394   0x00

Definition at line 274 of file Pci22.h.

#define PCI_IF_1394_OPEN_HCI   0x10

Definition at line 275 of file Pci22.h.

#define PCI_CLASS_SERIAL_ACCESS_BUS   0x01

Definition at line 276 of file Pci22.h.

#define PCI_CLASS_SERIAL_SSA   0x02

Definition at line 277 of file Pci22.h.

#define PCI_CLASS_SERIAL_USB   0x03

Definition at line 278 of file Pci22.h.

Referenced by ehci_companion(), and ehci_poll_companions().

#define PCI_IF_UHCI   0x00

Definition at line 279 of file Pci22.h.

#define PCI_IF_OHCI   0x10

Definition at line 280 of file Pci22.h.

#define PCI_IF_USB_OTHER   0x80

Definition at line 281 of file Pci22.h.

#define PCI_IF_USB_DEVICE   0xFE

Definition at line 282 of file Pci22.h.

#define PCI_CLASS_SERIAL_FIBRECHANNEL   0x04

Definition at line 283 of file Pci22.h.

#define PCI_CLASS_SERIAL_SMB   0x05

Definition at line 284 of file Pci22.h.

#define PCI_CLASS_WIRELESS   0x0D

Definition at line 286 of file Pci22.h.

#define PCI_SUBCLASS_IRDA   0x00

Definition at line 287 of file Pci22.h.

#define PCI_SUBCLASS_IR   0x01

Definition at line 288 of file Pci22.h.

#define PCI_SUBCLASS_RF   0x10

Definition at line 289 of file Pci22.h.

#define PCI_SUBCLASS_WIRELESS_OTHER   0x80

Definition at line 290 of file Pci22.h.

#define PCI_CLASS_INTELLIGENT_IO   0x0E

Definition at line 292 of file Pci22.h.

#define PCI_CLASS_SATELLITE   0x0F

Definition at line 294 of file Pci22.h.

#define PCI_SUBCLASS_TV   0x01

Definition at line 295 of file Pci22.h.

#define PCI_SUBCLASS_AUDIO   0x02

Definition at line 296 of file Pci22.h.

#define PCI_SUBCLASS_VOICE   0x03

Definition at line 297 of file Pci22.h.

#define PCI_SUBCLASS_DATA   0x04

Definition at line 298 of file Pci22.h.

#define PCI_SECURITY_CONTROLLER   0x10

Encryption and decryption controller.

Definition at line 300 of file Pci22.h.

#define PCI_SUBCLASS_NET_COMPUT   0x00

Definition at line 301 of file Pci22.h.

#define PCI_SUBCLASS_ENTERTAINMENT   0x10

Definition at line 302 of file Pci22.h.

#define PCI_SUBCLASS_SECURITY_OTHER   0x80

Definition at line 303 of file Pci22.h.

#define PCI_CLASS_DPIO   0x11

Definition at line 305 of file Pci22.h.

#define PCI_SUBCLASS_DPIO   0x00

Definition at line 306 of file Pci22.h.

#define PCI_SUBCLASS_DPIO_OTHER   0x80

Definition at line 307 of file Pci22.h.

#define IS_CLASS1 (   _p,
 
)    ((_p)->Hdr.ClassCode[2] == (c))

Macro that checks whether the Base Class code of device matched.

Parameters:
_pSpecified device.
cBase Class code needs matching.
Return values:
TRUEBase Class code matches the specified device.
FALSEBase Class code doesn't match the specified device.

Definition at line 319 of file Pci22.h.

#define IS_CLASS2 (   _p,
  c,
 
)    (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))

Macro that checks whether the Base Class code and Sub-Class code of device matched.

Parameters:
_pSpecified device.
cBase Class code needs matching.
sSub-Class code needs matching.
Return values:
TRUEBase Class code and Sub-Class code match the specified device.
FALSEBase Class code and Sub-Class code don't match the specified device.

Definition at line 331 of file Pci22.h.

#define IS_CLASS3 (   _p,
  c,
  s,
 
)    (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))

Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.

Parameters:
_pSpecified device.
cBase Class code needs matching.
sSub-Class code needs matching.
pInterface code needs matching.
Return values:
TRUEBase Class code, Sub-Class code and Interface code match the specified device.
FALSEBase Class code, Sub-Class code and Interface code don't match the specified device.

Definition at line 344 of file Pci22.h.

#define IS_PCI_DISPLAY (   _p)    IS_CLASS1 (_p, PCI_CLASS_DISPLAY)

Macro that checks whether device is a display controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a display controller.
FALSEDevice is not a display controller.

Definition at line 355 of file Pci22.h.

Macro that checks whether device is a VGA-compatible controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a VGA-compatible controller.
FALSEDevice is not a VGA-compatible controller.

Definition at line 365 of file Pci22.h.

Macro that checks whether device is an 8514-compatible controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is an 8514-compatible controller.
FALSEDevice is not an 8514-compatible controller.

Definition at line 375 of file Pci22.h.

#define IS_PCI_OLD (   _p)    IS_CLASS1 (_p, PCI_CLASS_OLD)

Macro that checks whether device is built before the Class Code field was defined.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is an old device.
FALSEDevice is not an old device.

Definition at line 385 of file Pci22.h.

Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is an old VGA-compatible device.
FALSEDevice is not an old VGA-compatible device.

Definition at line 395 of file Pci22.h.

Macro that checks whether device is an IDE controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is an IDE controller.
FALSEDevice is not an IDE controller.

Definition at line 405 of file Pci22.h.

Macro that checks whether device is a SCSI bus controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a SCSI bus controller.
FALSEDevice is not a SCSI bus controller.

Definition at line 415 of file Pci22.h.

Macro that checks whether device is a RAID controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a RAID controller.
FALSEDevice is not a RAID controller.

Definition at line 425 of file Pci22.h.

Macro that checks whether device is an ISA bridge.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is an ISA bridge.
FALSEDevice is not an ISA bridge.

Definition at line 435 of file Pci22.h.

Macro that checks whether device is a PCI-to-PCI bridge.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a PCI-to-PCI bridge.
FALSEDevice is not a PCI-to-PCI bridge.

Definition at line 445 of file Pci22.h.

Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a Subtractive Decode PCI-to-PCI bridge.
FALSEDevice is not a Subtractive Decode PCI-to-PCI bridge.

Definition at line 455 of file Pci22.h.

Macro that checks whether device is a 16550-compatible serial controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a 16550-compatible serial controller.
FALSEDevice is not a 16550-compatible serial controller.

Definition at line 465 of file Pci22.h.

Macro that checks whether device is a Universal Serial Bus controller.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a Universal Serial Bus controller.
FALSEDevice is not a Universal Serial Bus controller.

Definition at line 475 of file Pci22.h.

#define HEADER_TYPE_DEVICE   0x00

Definition at line 480 of file Pci22.h.

#define HEADER_TYPE_PCI_TO_PCI_BRIDGE   0x01

Definition at line 481 of file Pci22.h.

#define HEADER_TYPE_CARDBUS_BRIDGE   0x02

Definition at line 482 of file Pci22.h.

#define HEADER_TYPE_MULTI_FUNCTION   0x80

Definition at line 483 of file Pci22.h.

#define HEADER_LAYOUT_CODE   0x7f

Definition at line 487 of file Pci22.h.

#define IS_PCI_BRIDGE (   _p)    (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))

Macro that checks whether device is a PCI-PCI bridge.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a PCI-PCI bridge.
FALSEDevice is not a PCI-PCI bridge.

Definition at line 497 of file Pci22.h.

#define IS_CARDBUS_BRIDGE (   _p)    (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))

Macro that checks whether device is a CardBus bridge.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a CardBus bridge.
FALSEDevice is not a CardBus bridge.

Definition at line 507 of file Pci22.h.

#define IS_PCI_MULTI_FUNC (   _p)    ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)

Macro that checks whether device is a multiple functions device.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a multiple functions device.
FALSEDevice is not a multiple functions device.

Definition at line 517 of file Pci22.h.

#define PCI_BRIDGE_ROMBAR   0x38

Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,.

Definition at line 522 of file Pci22.h.

#define PCI_MAX_BAR   0x0006

Definition at line 524 of file Pci22.h.

#define PCI_MAX_CONFIG_OFFSET   0x0100

Definition at line 525 of file Pci22.h.

#define PCI_VENDOR_ID_OFFSET   0x00

Definition at line 527 of file Pci22.h.

#define PCI_DEVICE_ID_OFFSET   0x02

Definition at line 528 of file Pci22.h.

#define PCI_COMMAND_OFFSET   0x04

Definition at line 529 of file Pci22.h.

#define PCI_PRIMARY_STATUS_OFFSET   0x06

Definition at line 530 of file Pci22.h.

#define PCI_REVISION_ID_OFFSET   0x08

Definition at line 531 of file Pci22.h.

#define PCI_CLASSCODE_OFFSET   0x09

Definition at line 532 of file Pci22.h.

#define PCI_CACHELINE_SIZE_OFFSET   0x0C

Definition at line 533 of file Pci22.h.

#define PCI_LATENCY_TIMER_OFFSET   0x0D

Definition at line 534 of file Pci22.h.

#define PCI_HEADER_TYPE_OFFSET   0x0E

Definition at line 535 of file Pci22.h.

#define PCI_BIST_OFFSET   0x0F

Definition at line 536 of file Pci22.h.

#define PCI_BASE_ADDRESSREG_OFFSET   0x10

Definition at line 537 of file Pci22.h.

#define PCI_CARDBUS_CIS_OFFSET   0x28

Definition at line 538 of file Pci22.h.

#define PCI_SVID_OFFSET   0x2C

SubSystem Vendor id.

Definition at line 539 of file Pci22.h.

#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET   0x2C

Definition at line 540 of file Pci22.h.

#define PCI_SID_OFFSET   0x2E

SubSystem ID.

Definition at line 541 of file Pci22.h.

#define PCI_SUBSYSTEM_ID_OFFSET   0x2E

Definition at line 542 of file Pci22.h.

#define PCI_EXPANSION_ROM_BASE   0x30

Definition at line 543 of file Pci22.h.

#define PCI_CAPBILITY_POINTER_OFFSET   0x34

Definition at line 544 of file Pci22.h.

#define PCI_INT_LINE_OFFSET   0x3C

Interrupt Line Register.

Definition at line 545 of file Pci22.h.

#define PCI_INT_PIN_OFFSET   0x3D

Interrupt Pin Register.

Definition at line 546 of file Pci22.h.

#define PCI_MAXGNT_OFFSET   0x3E

Max Grant Register.

Definition at line 547 of file Pci22.h.

#define PCI_MAXLAT_OFFSET   0x3F

Max Latency Register.

Definition at line 548 of file Pci22.h.

Definition at line 553 of file Pci22.h.

Definition at line 554 of file Pci22.h.

Definition at line 555 of file Pci22.h.

Definition at line 556 of file Pci22.h.

Definition at line 557 of file Pci22.h.

Definition at line 558 of file Pci22.h.

#define PCI_INT_LINE_UNKNOWN   0xFF

Interrupt Line "Unknown" or "No connection" value defined for x86 based system.

Definition at line 563 of file Pci22.h.

0x0001

Definition at line 582 of file Pci22.h.

0x0002

Definition at line 583 of file Pci22.h.

0x0004

Definition at line 584 of file Pci22.h.

0x0008

Definition at line 585 of file Pci22.h.

0x0010

Definition at line 586 of file Pci22.h.

0x0020

Definition at line 587 of file Pci22.h.

0x0040

Definition at line 588 of file Pci22.h.

0x0080

Definition at line 589 of file Pci22.h.

#define EFI_PCI_COMMAND_SERR   BIT8

0x0100

Definition at line 590 of file Pci22.h.

0x0200

Definition at line 591 of file Pci22.h.

0x0001

Definition at line 596 of file Pci22.h.

0x0002

Definition at line 597 of file Pci22.h.

0x0004

Definition at line 598 of file Pci22.h.

0x0008

Definition at line 599 of file Pci22.h.

0x0010

Definition at line 600 of file Pci22.h.

0x0020

Definition at line 601 of file Pci22.h.

0x0040

Definition at line 602 of file Pci22.h.

0x0080

Definition at line 603 of file Pci22.h.

0x0100

Definition at line 604 of file Pci22.h.

0x0200

Definition at line 605 of file Pci22.h.

0x0400

Definition at line 606 of file Pci22.h.

0x0800

Definition at line 607 of file Pci22.h.

0x0080

Definition at line 612 of file Pci22.h.

0x0100

Definition at line 613 of file Pci22.h.

0x0200

Definition at line 614 of file Pci22.h.

0x0400

Definition at line 615 of file Pci22.h.

0x0010

Definition at line 620 of file Pci22.h.

0x0020

Definition at line 621 of file Pci22.h.

0x0080

Definition at line 622 of file Pci22.h.

0x0100

Definition at line 623 of file Pci22.h.

defined in PC Card Standard

Definition at line 628 of file Pci22.h.

#define EFI_PCI_CAPABILITY_ID_PMI   0x01

Definition at line 634 of file Pci22.h.

#define EFI_PCI_CAPABILITY_ID_AGP   0x02

Definition at line 635 of file Pci22.h.

#define EFI_PCI_CAPABILITY_ID_VPD   0x03

Definition at line 636 of file Pci22.h.

#define EFI_PCI_CAPABILITY_ID_SLOTID   0x04

Definition at line 637 of file Pci22.h.

#define EFI_PCI_CAPABILITY_ID_MSI   0x05

Definition at line 638 of file Pci22.h.

#define EFI_PCI_CAPABILITY_ID_HOTPLUG   0x06

Definition at line 639 of file Pci22.h.

#define EFI_PCI_CAPABILITY_ID_SHPC   0x0C

Definition at line 640 of file Pci22.h.

Definition at line 669 of file Pci22.h.

#define PCI_POWER_STATE_D0   0

Definition at line 689 of file Pci22.h.

#define PCI_POWER_STATE_D1   1

Definition at line 690 of file Pci22.h.

#define PCI_POWER_STATE_D2   2

Definition at line 691 of file Pci22.h.

#define PCI_POWER_STATE_D3_HOT   3

Definition at line 692 of file Pci22.h.

#define PCI_BAR_IDX0   0x00

Definition at line 785 of file Pci22.h.

#define PCI_BAR_IDX1   0x01

Definition at line 786 of file Pci22.h.

#define PCI_BAR_IDX2   0x02

Definition at line 787 of file Pci22.h.

#define PCI_BAR_IDX3   0x03

Definition at line 788 of file Pci22.h.

#define PCI_BAR_IDX4   0x04

Definition at line 789 of file Pci22.h.

#define PCI_BAR_IDX5   0x05

Definition at line 790 of file Pci22.h.

#define EFI_ROOT_BRIDGE_LIST   'eprb'

EFI PCI Option ROM definitions.

Definition at line 795 of file Pci22.h.

defined in UEFI Spec.

Definition at line 796 of file Pci22.h.

Definition at line 798 of file Pci22.h.

#define PCI_DATA_STRUCTURE_SIGNATURE   SIGNATURE_32 ('P', 'C', 'I', 'R')

Definition at line 799 of file Pci22.h.

#define PCI_CODE_TYPE_PCAT_IMAGE   0x00

Definition at line 800 of file Pci22.h.

defined in UEFI spec.

Definition at line 801 of file Pci22.h.


Function Documentation

FILE_LICENCE ( BSD3  )