iPXE
Pci22.h
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00001 /** @file
00002   Support for PCI 2.2 standard.
00003 
00004   This file includes the definitions in the following specifications,
00005     PCI Local Bus Specification, 2.2
00006     PCI-to-PCI Bridge Architecture Specification, Revision 1.2
00007     PC Card Standard, 8.0
00008     PCI Power Management Interface Specifiction, Revision 1.2
00009 
00010   Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
00011   Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
00012   This program and the accompanying materials
00013   are licensed and made available under the terms and conditions of the BSD License
00014   which accompanies this distribution.  The full text of the license may be found at
00015   http://opensource.org/licenses/bsd-license.php
00016 
00017   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
00018   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
00019 
00020 **/
00021 
00022 #ifndef _PCI22_H_
00023 #define _PCI22_H_
00024 
00025 FILE_LICENCE ( BSD3 );
00026 
00027 #define PCI_MAX_BUS     255
00028 #define PCI_MAX_DEVICE  31
00029 #define PCI_MAX_FUNC    7
00030 
00031 #pragma pack(1)
00032 
00033 ///
00034 /// Common header region in PCI Configuration Space
00035 /// Section 6.1, PCI Local Bus Specification, 2.2
00036 ///
00037 typedef struct {
00038   UINT16  VendorId;
00039   UINT16  DeviceId;
00040   UINT16  Command;
00041   UINT16  Status;
00042   UINT8   RevisionID;
00043   UINT8   ClassCode[3];
00044   UINT8   CacheLineSize;
00045   UINT8   LatencyTimer;
00046   UINT8   HeaderType;
00047   UINT8   BIST;
00048 } PCI_DEVICE_INDEPENDENT_REGION;
00049 
00050 ///
00051 /// PCI Device header region in PCI Configuration Space
00052 /// Section 6.1, PCI Local Bus Specification, 2.2
00053 ///
00054 typedef struct {
00055   UINT32  Bar[6];
00056   UINT32  CISPtr;
00057   UINT16  SubsystemVendorID;
00058   UINT16  SubsystemID;
00059   UINT32  ExpansionRomBar;
00060   UINT8   CapabilityPtr;
00061   UINT8   Reserved1[3];
00062   UINT32  Reserved2;
00063   UINT8   InterruptLine;
00064   UINT8   InterruptPin;
00065   UINT8   MinGnt;
00066   UINT8   MaxLat;
00067 } PCI_DEVICE_HEADER_TYPE_REGION;
00068 
00069 ///
00070 /// PCI Device Configuration Space
00071 /// Section 6.1, PCI Local Bus Specification, 2.2
00072 ///
00073 typedef struct {
00074   PCI_DEVICE_INDEPENDENT_REGION Hdr;
00075   PCI_DEVICE_HEADER_TYPE_REGION Device;
00076 } PCI_TYPE00;
00077 
00078 ///
00079 /// PCI-PCI Bridge header region in PCI Configuration Space
00080 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
00081 ///
00082 typedef struct {
00083   UINT32  Bar[2];
00084   UINT8   PrimaryBus;
00085   UINT8   SecondaryBus;
00086   UINT8   SubordinateBus;
00087   UINT8   SecondaryLatencyTimer;
00088   UINT8   IoBase;
00089   UINT8   IoLimit;
00090   UINT16  SecondaryStatus;
00091   UINT16  MemoryBase;
00092   UINT16  MemoryLimit;
00093   UINT16  PrefetchableMemoryBase;
00094   UINT16  PrefetchableMemoryLimit;
00095   UINT32  PrefetchableBaseUpper32;
00096   UINT32  PrefetchableLimitUpper32;
00097   UINT16  IoBaseUpper16;
00098   UINT16  IoLimitUpper16;
00099   UINT8   CapabilityPtr;
00100   UINT8   Reserved[3];
00101   UINT32  ExpansionRomBAR;
00102   UINT8   InterruptLine;
00103   UINT8   InterruptPin;
00104   UINT16  BridgeControl;
00105 } PCI_BRIDGE_CONTROL_REGISTER;
00106 
00107 ///
00108 /// PCI-to-PCI Bridge Configuration Space
00109 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
00110 ///
00111 typedef struct {
00112   PCI_DEVICE_INDEPENDENT_REGION Hdr;
00113   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
00114 } PCI_TYPE01;
00115 
00116 typedef union {
00117   PCI_TYPE00  Device;
00118   PCI_TYPE01  Bridge;
00119 } PCI_TYPE_GENERIC;
00120 
00121 ///
00122 /// CardBus Conroller Configuration Space,
00123 /// Section 4.5.1, PC Card Standard. 8.0
00124 ///
00125 typedef struct {
00126   UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base
00127   UINT8   Cap_Ptr;
00128   UINT8   Reserved;
00129   UINT16  SecondaryStatus;      ///< Secondary Status
00130   UINT8   PciBusNumber;         ///< PCI Bus Number
00131   UINT8   CardBusBusNumber;     ///< CardBus Bus Number
00132   UINT8   SubordinateBusNumber; ///< Subordinate Bus Number
00133   UINT8   CardBusLatencyTimer;  ///< CardBus Latency Timer
00134   UINT32  MemoryBase0;          ///< Memory Base Register 0
00135   UINT32  MemoryLimit0;         ///< Memory Limit Register 0
00136   UINT32  MemoryBase1;
00137   UINT32  MemoryLimit1;
00138   UINT32  IoBase0;
00139   UINT32  IoLimit0;             ///< I/O Base Register 0
00140   UINT32  IoBase1;              ///< I/O Limit Register 0
00141   UINT32  IoLimit1;
00142   UINT8   InterruptLine;        ///< Interrupt Line
00143   UINT8   InterruptPin;         ///< Interrupt Pin
00144   UINT16  BridgeControl;        ///< Bridge Control
00145 } PCI_CARDBUS_CONTROL_REGISTER;
00146 
00147 //
00148 // Definitions of PCI class bytes and manipulation macros.
00149 //
00150 #define PCI_CLASS_OLD                 0x00
00151 #define   PCI_CLASS_OLD_OTHER           0x00
00152 #define   PCI_CLASS_OLD_VGA             0x01
00153 
00154 #define PCI_CLASS_MASS_STORAGE        0x01
00155 #define   PCI_CLASS_MASS_STORAGE_SCSI   0x00
00156 #define   PCI_CLASS_MASS_STORAGE_IDE    0x01
00157 #define   PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
00158 #define   PCI_CLASS_MASS_STORAGE_IPI    0x03
00159 #define   PCI_CLASS_MASS_STORAGE_RAID   0x04
00160 #define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
00161 
00162 #define PCI_CLASS_NETWORK             0x02
00163 #define   PCI_CLASS_NETWORK_ETHERNET    0x00
00164 #define   PCI_CLASS_NETWORK_TOKENRING   0x01
00165 #define   PCI_CLASS_NETWORK_FDDI        0x02
00166 #define   PCI_CLASS_NETWORK_ATM         0x03
00167 #define   PCI_CLASS_NETWORK_ISDN        0x04
00168 #define   PCI_CLASS_NETWORK_OTHER       0x80
00169 
00170 #define PCI_CLASS_DISPLAY             0x03
00171 #define   PCI_CLASS_DISPLAY_VGA         0x00
00172 #define     PCI_IF_VGA_VGA                0x00
00173 #define     PCI_IF_VGA_8514               0x01
00174 #define   PCI_CLASS_DISPLAY_XGA         0x01
00175 #define   PCI_CLASS_DISPLAY_3D          0x02
00176 #define   PCI_CLASS_DISPLAY_OTHER       0x80
00177 
00178 #define PCI_CLASS_MEDIA               0x04
00179 #define   PCI_CLASS_MEDIA_VIDEO         0x00
00180 #define   PCI_CLASS_MEDIA_AUDIO         0x01
00181 #define   PCI_CLASS_MEDIA_TELEPHONE     0x02
00182 #define   PCI_CLASS_MEDIA_OTHER         0x80
00183 
00184 #define PCI_CLASS_MEMORY_CONTROLLER   0x05
00185 #define   PCI_CLASS_MEMORY_RAM          0x00
00186 #define   PCI_CLASS_MEMORY_FLASH        0x01
00187 #define   PCI_CLASS_MEMORY_OTHER        0x80
00188 
00189 #define PCI_CLASS_BRIDGE              0x06
00190 #define   PCI_CLASS_BRIDGE_HOST         0x00
00191 #define   PCI_CLASS_BRIDGE_ISA          0x01
00192 #define   PCI_CLASS_BRIDGE_EISA         0x02
00193 #define   PCI_CLASS_BRIDGE_MCA          0x03
00194 #define   PCI_CLASS_BRIDGE_P2P          0x04
00195 #define     PCI_IF_BRIDGE_P2P             0x00
00196 #define     PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
00197 #define   PCI_CLASS_BRIDGE_PCMCIA       0x05
00198 #define   PCI_CLASS_BRIDGE_NUBUS        0x06
00199 #define   PCI_CLASS_BRIDGE_CARDBUS      0x07
00200 #define   PCI_CLASS_BRIDGE_RACEWAY      0x08
00201 #define   PCI_CLASS_BRIDGE_OTHER        0x80
00202 #define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
00203 
00204 #define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers
00205 #define   PCI_SUBCLASS_SERIAL           0x00
00206 #define     PCI_IF_GENERIC_XT             0x00
00207 #define     PCI_IF_16450                  0x01
00208 #define     PCI_IF_16550                  0x02
00209 #define     PCI_IF_16650                  0x03
00210 #define     PCI_IF_16750                  0x04
00211 #define     PCI_IF_16850                  0x05
00212 #define     PCI_IF_16950                  0x06
00213 #define   PCI_SUBCLASS_PARALLEL         0x01
00214 #define     PCI_IF_PARALLEL_PORT          0x00
00215 #define     PCI_IF_BI_DIR_PARALLEL_PORT   0x01
00216 #define     PCI_IF_ECP_PARALLEL_PORT      0x02
00217 #define     PCI_IF_1284_CONTROLLER        0x03
00218 #define     PCI_IF_1284_DEVICE            0xFE
00219 #define   PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
00220 #define   PCI_SUBCLASS_MODEM            0x03
00221 #define     PCI_IF_GENERIC_MODEM          0x00
00222 #define     PCI_IF_16450_MODEM            0x01
00223 #define     PCI_IF_16550_MODEM            0x02
00224 #define     PCI_IF_16650_MODEM            0x03
00225 #define     PCI_IF_16750_MODEM            0x04
00226 #define   PCI_SUBCLASS_SCC_OTHER        0x80
00227 
00228 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
00229 #define   PCI_SUBCLASS_PIC              0x00
00230 #define     PCI_IF_8259_PIC               0x00
00231 #define     PCI_IF_ISA_PIC                0x01
00232 #define     PCI_IF_EISA_PIC               0x02
00233 #define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
00234 #define     PCI_IF_APIC_CONTROLLER2       0x20
00235 #define   PCI_SUBCLASS_DMA              0x01
00236 #define     PCI_IF_8237_DMA               0x00
00237 #define     PCI_IF_ISA_DMA                0x01
00238 #define     PCI_IF_EISA_DMA               0x02
00239 #define   PCI_SUBCLASS_TIMER            0x02
00240 #define     PCI_IF_8254_TIMER             0x00
00241 #define     PCI_IF_ISA_TIMER              0x01
00242 #define     PCI_IF_EISA_TIMER             0x02
00243 #define   PCI_SUBCLASS_RTC              0x03
00244 #define     PCI_IF_GENERIC_RTC            0x00
00245 #define     PCI_IF_ISA_RTC                0x01
00246 #define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller
00247 #define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
00248 
00249 #define PCI_CLASS_INPUT_DEVICE        0x09
00250 #define   PCI_SUBCLASS_KEYBOARD         0x00
00251 #define   PCI_SUBCLASS_PEN              0x01
00252 #define   PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
00253 #define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03
00254 #define   PCI_SUBCLASS_GAMEPORT         0x04
00255 #define     PCI_IF_GAMEPORT               0x00
00256 #define     PCI_IF_GAMEPORT1              0x10
00257 #define   PCI_SUBCLASS_INPUT_OTHER      0x80
00258 
00259 #define PCI_CLASS_DOCKING_STATION     0x0A
00260 #define   PCI_SUBCLASS_DOCKING_GENERIC  0x00
00261 #define   PCI_SUBCLASS_DOCKING_OTHER    0x80
00262 
00263 #define PCI_CLASS_PROCESSOR           0x0B
00264 #define   PCI_SUBCLASS_PROC_386         0x00
00265 #define   PCI_SUBCLASS_PROC_486         0x01
00266 #define   PCI_SUBCLASS_PROC_PENTIUM     0x02
00267 #define   PCI_SUBCLASS_PROC_ALPHA       0x10
00268 #define   PCI_SUBCLASS_PROC_POWERPC     0x20
00269 #define   PCI_SUBCLASS_PROC_MIPS        0x30
00270 #define   PCI_SUBCLASS_PROC_CO_PORC     0x40 ///< Co-Processor
00271 
00272 #define PCI_CLASS_SERIAL              0x0C
00273 #define   PCI_CLASS_SERIAL_FIREWIRE     0x00
00274 #define     PCI_IF_1394                   0x00
00275 #define     PCI_IF_1394_OPEN_HCI          0x10
00276 #define   PCI_CLASS_SERIAL_ACCESS_BUS   0x01
00277 #define   PCI_CLASS_SERIAL_SSA          0x02
00278 #define   PCI_CLASS_SERIAL_USB          0x03
00279 #define     PCI_IF_UHCI                   0x00
00280 #define     PCI_IF_OHCI                   0x10
00281 #define     PCI_IF_USB_OTHER              0x80
00282 #define     PCI_IF_USB_DEVICE             0xFE
00283 #define   PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
00284 #define   PCI_CLASS_SERIAL_SMB          0x05
00285 
00286 #define PCI_CLASS_WIRELESS            0x0D
00287 #define   PCI_SUBCLASS_IRDA             0x00
00288 #define   PCI_SUBCLASS_IR               0x01
00289 #define   PCI_SUBCLASS_RF               0x10
00290 #define   PCI_SUBCLASS_WIRELESS_OTHER   0x80
00291 
00292 #define PCI_CLASS_INTELLIGENT_IO      0x0E
00293 
00294 #define PCI_CLASS_SATELLITE           0x0F
00295 #define   PCI_SUBCLASS_TV               0x01
00296 #define   PCI_SUBCLASS_AUDIO            0x02
00297 #define   PCI_SUBCLASS_VOICE            0x03
00298 #define   PCI_SUBCLASS_DATA             0x04
00299 
00300 #define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
00301 #define   PCI_SUBCLASS_NET_COMPUT       0x00
00302 #define   PCI_SUBCLASS_ENTERTAINMENT    0x10
00303 #define   PCI_SUBCLASS_SECURITY_OTHER   0x80
00304 
00305 #define PCI_CLASS_DPIO                0x11
00306 #define   PCI_SUBCLASS_DPIO             0x00
00307 #define   PCI_SUBCLASS_DPIO_OTHER       0x80
00308 
00309 /**
00310   Macro that checks whether the Base Class code of device matched.
00311 
00312   @param  _p      Specified device.
00313   @param  c       Base Class code needs matching.
00314 
00315   @retval TRUE    Base Class code matches the specified device.
00316   @retval FALSE   Base Class code doesn't match the specified device.
00317 
00318 **/
00319 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
00320 /**
00321   Macro that checks whether the Base Class code and Sub-Class code of device matched.
00322 
00323   @param  _p      Specified device.
00324   @param  c       Base Class code needs matching.
00325   @param  s       Sub-Class code needs matching.
00326 
00327   @retval TRUE    Base Class code and Sub-Class code match the specified device.
00328   @retval FALSE   Base Class code and Sub-Class code don't match the specified device.
00329 
00330 **/
00331 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
00332 /**
00333   Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
00334 
00335   @param  _p      Specified device.
00336   @param  c       Base Class code needs matching.
00337   @param  s       Sub-Class code needs matching.
00338   @param  p       Interface code needs matching.
00339 
00340   @retval TRUE    Base Class code, Sub-Class code and Interface code match the specified device.
00341   @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.
00342 
00343 **/
00344 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
00345 
00346 /**
00347   Macro that checks whether device is a display controller.
00348 
00349   @param  _p      Specified device.
00350 
00351   @retval TRUE    Device is a display controller.
00352   @retval FALSE   Device is not a display controller.
00353 
00354 **/
00355 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
00356 /**
00357   Macro that checks whether device is a VGA-compatible controller.
00358 
00359   @param  _p      Specified device.
00360 
00361   @retval TRUE    Device is a VGA-compatible controller.
00362   @retval FALSE   Device is not a VGA-compatible controller.
00363 
00364 **/
00365 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
00366 /**
00367   Macro that checks whether device is an 8514-compatible controller.
00368 
00369   @param  _p      Specified device.
00370 
00371   @retval TRUE    Device is an 8514-compatible controller.
00372   @retval FALSE   Device is not an 8514-compatible controller.
00373 
00374 **/
00375 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
00376 /**
00377   Macro that checks whether device is built before the Class Code field was defined.
00378 
00379   @param  _p      Specified device.
00380 
00381   @retval TRUE    Device is an old device.
00382   @retval FALSE   Device is not an old device.
00383 
00384 **/
00385 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
00386 /**
00387   Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
00388 
00389   @param  _p      Specified device.
00390 
00391   @retval TRUE    Device is an old VGA-compatible device.
00392   @retval FALSE   Device is not an old VGA-compatible device.
00393 
00394 **/
00395 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
00396 /**
00397   Macro that checks whether device is an IDE controller.
00398 
00399   @param  _p      Specified device.
00400 
00401   @retval TRUE    Device is an IDE controller.
00402   @retval FALSE   Device is not an IDE controller.
00403 
00404 **/
00405 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
00406 /**
00407   Macro that checks whether device is a SCSI bus controller.
00408 
00409   @param  _p      Specified device.
00410 
00411   @retval TRUE    Device is a SCSI bus controller.
00412   @retval FALSE   Device is not a SCSI bus controller.
00413 
00414 **/
00415 #define IS_PCI_SCSI(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
00416 /**
00417   Macro that checks whether device is a RAID controller.
00418 
00419   @param  _p      Specified device.
00420 
00421   @retval TRUE    Device is a RAID controller.
00422   @retval FALSE   Device is not a RAID controller.
00423 
00424 **/
00425 #define IS_PCI_RAID(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
00426 /**
00427   Macro that checks whether device is an ISA bridge.
00428 
00429   @param  _p      Specified device.
00430 
00431   @retval TRUE    Device is an ISA bridge.
00432   @retval FALSE   Device is not an ISA bridge.
00433 
00434 **/
00435 #define IS_PCI_LPC(_p)                IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
00436 /**
00437   Macro that checks whether device is a PCI-to-PCI bridge.
00438 
00439   @param  _p      Specified device.
00440 
00441   @retval TRUE    Device is a PCI-to-PCI bridge.
00442   @retval FALSE   Device is not a PCI-to-PCI bridge.
00443 
00444 **/
00445 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
00446 /**
00447   Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
00448 
00449   @param  _p      Specified device.
00450 
00451   @retval TRUE    Device is a Subtractive Decode PCI-to-PCI bridge.
00452   @retval FALSE   Device is not a Subtractive Decode PCI-to-PCI bridge.
00453 
00454 **/
00455 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
00456 /**
00457   Macro that checks whether device is a 16550-compatible serial controller.
00458 
00459   @param  _p      Specified device.
00460 
00461   @retval TRUE    Device is a 16550-compatible serial controller.
00462   @retval FALSE   Device is not a 16550-compatible serial controller.
00463 
00464 **/
00465 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
00466 /**
00467   Macro that checks whether device is a Universal Serial Bus controller.
00468 
00469   @param  _p      Specified device.
00470 
00471   @retval TRUE    Device is a Universal Serial Bus controller.
00472   @retval FALSE   Device is not a Universal Serial Bus controller.
00473 
00474 **/
00475 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
00476 
00477 //
00478 // the definition of Header Type
00479 //
00480 #define HEADER_TYPE_DEVICE            0x00
00481 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
00482 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
00483 #define HEADER_TYPE_MULTI_FUNCTION    0x80
00484 //
00485 // Mask of Header type
00486 //
00487 #define HEADER_LAYOUT_CODE            0x7f
00488 /**
00489   Macro that checks whether device is a PCI-PCI bridge.
00490 
00491   @param  _p      Specified device.
00492 
00493   @retval TRUE    Device is a PCI-PCI bridge.
00494   @retval FALSE   Device is not a PCI-PCI bridge.
00495 
00496 **/
00497 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
00498 /**
00499   Macro that checks whether device is a CardBus bridge.
00500 
00501   @param  _p      Specified device.
00502 
00503   @retval TRUE    Device is a CardBus bridge.
00504   @retval FALSE   Device is not a CardBus bridge.
00505 
00506 **/
00507 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
00508 /**
00509   Macro that checks whether device is a multiple functions device.
00510 
00511   @param  _p      Specified device.
00512 
00513   @retval TRUE    Device is a multiple functions device.
00514   @retval FALSE   Device is not a multiple functions device.
00515 
00516 **/
00517 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
00518 
00519 ///
00520 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
00521 ///
00522 #define PCI_BRIDGE_ROMBAR             0x38
00523 
00524 #define PCI_MAX_BAR                   0x0006
00525 #define PCI_MAX_CONFIG_OFFSET         0x0100
00526 
00527 #define PCI_VENDOR_ID_OFFSET                        0x00
00528 #define PCI_DEVICE_ID_OFFSET                        0x02
00529 #define PCI_COMMAND_OFFSET                          0x04
00530 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
00531 #define PCI_REVISION_ID_OFFSET                      0x08
00532 #define PCI_CLASSCODE_OFFSET                        0x09
00533 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
00534 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
00535 #define PCI_HEADER_TYPE_OFFSET                      0x0E
00536 #define PCI_BIST_OFFSET                             0x0F
00537 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
00538 #define PCI_CARDBUS_CIS_OFFSET                      0x28
00539 #define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id
00540 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
00541 #define PCI_SID_OFFSET                              0x2E ///< SubSystem ID
00542 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
00543 #define PCI_EXPANSION_ROM_BASE                      0x30
00544 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
00545 #define PCI_INT_LINE_OFFSET                         0x3C ///< Interrupt Line Register
00546 #define PCI_INT_PIN_OFFSET                          0x3D ///< Interrupt Pin Register
00547 #define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register
00548 #define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register
00549 
00550 //
00551 // defined in PCI-to-PCI Bridge Architecture Specification
00552 //
00553 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
00554 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
00555 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
00556 #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b
00557 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
00558 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
00559 
00560 ///
00561 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
00562 ///
00563 #define PCI_INT_LINE_UNKNOWN                        0xFF
00564 
00565 ///
00566 /// PCI Access Data Format
00567 ///
00568 typedef union {
00569   struct {
00570     UINT32  Reg : 8;
00571     UINT32  Func : 3;
00572     UINT32  Dev : 5;
00573     UINT32  Bus : 8;
00574     UINT32  Reserved : 7;
00575     UINT32  Enable : 1;
00576   } Bits;
00577   UINT32  Uint32;
00578 } PCI_CONFIG_ACCESS_CF8;
00579 
00580 #pragma pack()
00581 
00582 #define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001
00583 #define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002
00584 #define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004
00585 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   BIT3   ///< 0x0008
00586 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     BIT4   ///< 0x0010
00587 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               BIT5   ///< 0x0020
00588 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            BIT6   ///< 0x0040
00589 #define EFI_PCI_COMMAND_STEPPING_CONTROL                BIT7   ///< 0x0080
00590 #define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100
00591 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200
00592 
00593 //
00594 // defined in PCI-to-PCI Bridge Architecture Specification
00595 //
00596 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001
00597 #define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002
00598 #define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004
00599 #define EFI_PCI_BRIDGE_CONTROL_VGA                      BIT3   ///< 0x0008
00600 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   BIT4   ///< 0x0010
00601 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             BIT5   ///< 0x0020
00602 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      BIT6   ///< 0x0040
00603 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        BIT7   ///< 0x0080
00604 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    BIT8   ///< 0x0100
00605 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  BIT9   ///< 0x0200
00606 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400
00607 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800
00608 
00609 //
00610 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
00611 //
00612 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080
00613 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100
00614 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200
00615 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE     BIT10  ///< 0x0400
00616 
00617 //
00618 // Following are the PCI status control bit
00619 //
00620 #define EFI_PCI_STATUS_CAPABILITY                       BIT4   ///< 0x0010
00621 #define EFI_PCI_STATUS_66MZ_CAPABLE                     BIT5   ///< 0x0020
00622 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE               BIT7   ///< 0x0080
00623 #define EFI_PCI_MASTER_DATA_PARITY_ERROR                BIT8   ///< 0x0100
00624 
00625 ///
00626 /// defined in PC Card Standard
00627 ///
00628 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
00629 
00630 #pragma pack(1)
00631 //
00632 // PCI Capability List IDs and records
00633 //
00634 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
00635 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
00636 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
00637 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
00638 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
00639 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
00640 #define EFI_PCI_CAPABILITY_ID_SHPC    0x0C
00641 
00642 ///
00643 /// Capabilities List Header
00644 /// Section 6.7, PCI Local Bus Specification, 2.2
00645 ///
00646 typedef struct {
00647   UINT8 CapabilityID;
00648   UINT8 NextItemPtr;
00649 } EFI_PCI_CAPABILITY_HDR;
00650 
00651 ///
00652 /// PMC - Power Management Capabilities
00653 /// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
00654 ///
00655 typedef union {
00656   struct {
00657     UINT16 Version : 3;
00658     UINT16 PmeClock : 1;
00659     UINT16 Reserved : 1;
00660     UINT16 DeviceSpecificInitialization : 1;
00661     UINT16 AuxCurrent : 3;
00662     UINT16 D1Support : 1;
00663     UINT16 D2Support : 1;
00664     UINT16 PmeSupport : 5;
00665   } Bits;
00666   UINT16 Data;
00667 } EFI_PCI_PMC;
00668 
00669 #define EFI_PCI_PMC_D3_COLD_MASK    (BIT15)
00670 
00671 ///
00672 /// PMCSR - Power Management Control/Status
00673 /// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
00674 ///
00675 typedef union {
00676   struct {
00677     UINT16 PowerState : 2;
00678     UINT16 ReservedForPciExpress : 1;
00679     UINT16 NoSoftReset : 1;
00680     UINT16 Reserved : 4;
00681     UINT16 PmeEnable : 1;
00682     UINT16 DataSelect : 4;
00683     UINT16 DataScale : 2;
00684     UINT16 PmeStatus : 1;
00685   } Bits;
00686   UINT16 Data;
00687 } EFI_PCI_PMCSR;
00688 
00689 #define PCI_POWER_STATE_D0     0
00690 #define PCI_POWER_STATE_D1     1
00691 #define PCI_POWER_STATE_D2     2
00692 #define PCI_POWER_STATE_D3_HOT 3
00693 
00694 ///
00695 /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
00696 /// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
00697 ///
00698 typedef union {
00699   struct {
00700     UINT8 Reserved : 6;
00701     UINT8 B2B3 : 1;
00702     UINT8 BusPowerClockControl : 1;
00703   } Bits;
00704   UINT8   Uint8;
00705 } EFI_PCI_PMCSR_BSE;
00706 
00707 ///
00708 /// Power Management Register Block Definition
00709 /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
00710 ///
00711 typedef struct {
00712   EFI_PCI_CAPABILITY_HDR  Hdr;
00713   EFI_PCI_PMC             PMC;
00714   EFI_PCI_PMCSR           PMCSR;
00715   EFI_PCI_PMCSR_BSE       BridgeExtention;
00716   UINT8                   Data;
00717 } EFI_PCI_CAPABILITY_PMI;
00718 
00719 ///
00720 /// A.G.P Capability
00721 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
00722 ///
00723 typedef struct {
00724   EFI_PCI_CAPABILITY_HDR  Hdr;
00725   UINT8                   Rev;
00726   UINT8                   Reserved;
00727   UINT32                  Status;
00728   UINT32                  Command;
00729 } EFI_PCI_CAPABILITY_AGP;
00730 
00731 ///
00732 /// VPD Capability Structure
00733 /// Appendix I, PCI Local Bus Specification, 2.2
00734 ///
00735 typedef struct {
00736   EFI_PCI_CAPABILITY_HDR  Hdr;
00737   UINT16                  AddrReg;
00738   UINT32                  DataReg;
00739 } EFI_PCI_CAPABILITY_VPD;
00740 
00741 ///
00742 /// Slot Numbering Capabilities Register
00743 /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
00744 ///
00745 typedef struct {
00746   EFI_PCI_CAPABILITY_HDR  Hdr;
00747   UINT8                   ExpnsSlotReg;
00748   UINT8                   ChassisNo;
00749 } EFI_PCI_CAPABILITY_SLOTID;
00750 
00751 ///
00752 /// Message Capability Structure for 32-bit Message Address
00753 /// Section 6.8.1, PCI Local Bus Specification, 2.2
00754 ///
00755 typedef struct {
00756   EFI_PCI_CAPABILITY_HDR  Hdr;
00757   UINT16                  MsgCtrlReg;
00758   UINT32                  MsgAddrReg;
00759   UINT16                  MsgDataReg;
00760 } EFI_PCI_CAPABILITY_MSI32;
00761 
00762 ///
00763 /// Message Capability Structure for 64-bit Message Address
00764 /// Section 6.8.1, PCI Local Bus Specification, 2.2
00765 ///
00766 typedef struct {
00767   EFI_PCI_CAPABILITY_HDR  Hdr;
00768   UINT16                  MsgCtrlReg;
00769   UINT32                  MsgAddrRegLsdw;
00770   UINT32                  MsgAddrRegMsdw;
00771   UINT16                  MsgDataReg;
00772 } EFI_PCI_CAPABILITY_MSI64;
00773 
00774 ///
00775 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
00776 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
00777 ///
00778 typedef struct {
00779   EFI_PCI_CAPABILITY_HDR  Hdr;
00780   ///
00781   /// not finished - fields need to go here
00782   ///
00783 } EFI_PCI_CAPABILITY_HOTPLUG;
00784 
00785 #define PCI_BAR_IDX0        0x00
00786 #define PCI_BAR_IDX1        0x01
00787 #define PCI_BAR_IDX2        0x02
00788 #define PCI_BAR_IDX3        0x03
00789 #define PCI_BAR_IDX4        0x04
00790 #define PCI_BAR_IDX5        0x05
00791 
00792 ///
00793 /// EFI PCI Option ROM definitions
00794 ///
00795 #define EFI_ROOT_BRIDGE_LIST                            'eprb'
00796 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
00797 
00798 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
00799 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
00800 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
00801 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///< defined in UEFI spec.
00802 
00803 ///
00804 /// Standard PCI Expansion ROM Header
00805 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
00806 ///
00807 typedef struct {
00808   UINT16  Signature;    ///< 0xaa55
00809   UINT8   Reserved[0x16];
00810   UINT16  PcirOffset;
00811 } PCI_EXPANSION_ROM_HEADER;
00812 
00813 ///
00814 /// Legacy ROM Header Extensions
00815 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
00816 ///
00817 typedef struct {
00818   UINT16  Signature;    ///< 0xaa55
00819   UINT8   Size512;
00820   UINT8   InitEntryPoint[3];
00821   UINT8   Reserved[0x12];
00822   UINT16  PcirOffset;
00823 } EFI_LEGACY_EXPANSION_ROM_HEADER;
00824 
00825 ///
00826 /// PCI Data Structure Format
00827 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
00828 ///
00829 typedef struct {
00830   UINT32  Signature;    ///< "PCIR"
00831   UINT16  VendorId;
00832   UINT16  DeviceId;
00833   UINT16  Reserved0;
00834   UINT16  Length;
00835   UINT8   Revision;
00836   UINT8   ClassCode[3];
00837   UINT16  ImageLength;
00838   UINT16  CodeRevision;
00839   UINT8   CodeType;
00840   UINT8   Indicator;
00841   UINT16  Reserved1;
00842 } PCI_DATA_STRUCTURE;
00843 
00844 ///
00845 /// EFI PCI Expansion ROM Header
00846 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
00847 ///
00848 typedef struct {
00849   UINT16  Signature;    ///< 0xaa55
00850   UINT16  InitializationSize;
00851   UINT32  EfiSignature; ///< 0x0EF1
00852   UINT16  EfiSubsystem;
00853   UINT16  EfiMachineType;
00854   UINT16  CompressionType;
00855   UINT8   Reserved[8];
00856   UINT16  EfiImageHeaderOffset;
00857   UINT16  PcirOffset;
00858 } EFI_PCI_EXPANSION_ROM_HEADER;
00859 
00860 typedef union {
00861   UINT8                           *Raw;
00862   PCI_EXPANSION_ROM_HEADER        *Generic;
00863   EFI_PCI_EXPANSION_ROM_HEADER    *Efi;
00864   EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
00865 } EFI_PCI_ROM_HEADER;
00866 
00867 #pragma pack()
00868 
00869 #endif