iPXE
ar9002_phy.h
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Permission to use, copy, modify, and/or distribute this software for any
00005  * purpose with or without fee is hereby granted, provided that the above
00006  * copyright notice and this permission notice appear in all copies.
00007  *
00008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00015  */
00016 #ifndef AR9002_PHY_H
00017 #define AR9002_PHY_H
00018 
00019 FILE_LICENCE ( BSD2 );
00020 
00021 #define AR_PHY_TEST             0x9800
00022 #define PHY_AGC_CLR             0x10000000
00023 #define RFSILENT_BB             0x00002000
00024 
00025 #define AR_PHY_TURBO                0x9804
00026 #define AR_PHY_FC_TURBO_MODE        0x00000001
00027 #define AR_PHY_FC_TURBO_SHORT       0x00000002
00028 #define AR_PHY_FC_DYN2040_EN        0x00000004
00029 #define AR_PHY_FC_DYN2040_PRI_ONLY  0x00000008
00030 #define AR_PHY_FC_DYN2040_PRI_CH    0x00000010
00031 /* For 25 MHz channel spacing -- not used but supported by hw */
00032 #define AR_PHY_FC_DYN2040_EXT_CH    0x00000020
00033 #define AR_PHY_FC_HT_EN             0x00000040
00034 #define AR_PHY_FC_SHORT_GI_40       0x00000080
00035 #define AR_PHY_FC_WALSH             0x00000100
00036 #define AR_PHY_FC_SINGLE_HT_LTF1    0x00000200
00037 #define AR_PHY_FC_ENABLE_DAC_FIFO   0x00000800
00038 
00039 #define AR_PHY_TEST2                    0x9808
00040 
00041 #define AR_PHY_TIMING2           0x9810
00042 #define AR_PHY_TIMING3           0x9814
00043 #define AR_PHY_TIMING3_DSC_MAN   0xFFFE0000
00044 #define AR_PHY_TIMING3_DSC_MAN_S 17
00045 #define AR_PHY_TIMING3_DSC_EXP   0x0001E000
00046 #define AR_PHY_TIMING3_DSC_EXP_S 13
00047 
00048 #define AR_PHY_CHIP_ID_REV_0      0x80
00049 #define AR_PHY_CHIP_ID_REV_1      0x81
00050 #define AR_PHY_CHIP_ID_9160_REV_0 0xb0
00051 
00052 #define AR_PHY_ACTIVE       0x981C
00053 #define AR_PHY_ACTIVE_EN    0x00000001
00054 #define AR_PHY_ACTIVE_DIS   0x00000000
00055 
00056 #define AR_PHY_RF_CTL2             0x9824
00057 #define AR_PHY_TX_END_DATA_START   0x000000FF
00058 #define AR_PHY_TX_END_DATA_START_S 0
00059 #define AR_PHY_TX_END_PA_ON        0x0000FF00
00060 #define AR_PHY_TX_END_PA_ON_S      8
00061 
00062 #define AR_PHY_RF_CTL3                  0x9828
00063 #define AR_PHY_TX_END_TO_A2_RX_ON       0x00FF0000
00064 #define AR_PHY_TX_END_TO_A2_RX_ON_S     16
00065 
00066 #define AR_PHY_ADC_CTL                  0x982C
00067 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN    0x00000003
00068 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S  0
00069 #define AR_PHY_ADC_CTL_OFF_PWDDAC       0x00002000
00070 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP   0x00004000
00071 #define AR_PHY_ADC_CTL_OFF_PWDADC       0x00008000
00072 #define AR_PHY_ADC_CTL_ON_INBUFGAIN     0x00030000
00073 #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S   16
00074 
00075 #define AR_PHY_ADC_SERIAL_CTL       0x9830
00076 #define AR_PHY_SEL_INTERNAL_ADDAC   0x00000000
00077 #define AR_PHY_SEL_EXTERNAL_RADIO   0x00000001
00078 
00079 #define AR_PHY_RF_CTL4                    0x9834
00080 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF    0xFF000000
00081 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S  24
00082 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF    0x00FF0000
00083 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S  16
00084 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON      0x0000FF00
00085 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S    8
00086 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON      0x000000FF
00087 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S    0
00088 
00089 #define AR_PHY_TSTDAC_CONST               0x983c
00090 
00091 #define AR_PHY_SETTLING          0x9844
00092 #define AR_PHY_SETTLING_SWITCH   0x00003F80
00093 #define AR_PHY_SETTLING_SWITCH_S 7
00094 
00095 #define AR_PHY_RXGAIN                   0x9848
00096 #define AR_PHY_RXGAIN_TXRX_ATTEN        0x0003F000
00097 #define AR_PHY_RXGAIN_TXRX_ATTEN_S      12
00098 #define AR_PHY_RXGAIN_TXRX_RF_MAX       0x007C0000
00099 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S     18
00100 #define AR9280_PHY_RXGAIN_TXRX_ATTEN    0x00003F80
00101 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S  7
00102 #define AR9280_PHY_RXGAIN_TXRX_MARGIN   0x001FC000
00103 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
00104 
00105 #define AR_PHY_DESIRED_SZ           0x9850
00106 #define AR_PHY_DESIRED_SZ_ADC       0x000000FF
00107 #define AR_PHY_DESIRED_SZ_ADC_S     0
00108 #define AR_PHY_DESIRED_SZ_PGA       0x0000FF00
00109 #define AR_PHY_DESIRED_SZ_PGA_S     8
00110 #define AR_PHY_DESIRED_SZ_TOT_DES   0x0FF00000
00111 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
00112 
00113 #define AR_PHY_FIND_SIG           0x9858
00114 #define AR_PHY_FIND_SIG_FIRSTEP   0x0003F000
00115 #define AR_PHY_FIND_SIG_FIRSTEP_S 12
00116 #define AR_PHY_FIND_SIG_FIRPWR    0x03FC0000
00117 #define AR_PHY_FIND_SIG_FIRPWR_S  18
00118 
00119 #define AR_PHY_FIND_SIG_LOW           0x9840
00120 #define AR_PHY_FIND_SIG_FIRSTEP_LOW   0x00000FC0L
00121 #define AR_PHY_FIND_SIG_FIRSTEP_LOW_S 6
00122 
00123 #define AR_PHY_AGC_CTL1                  0x985C
00124 #define AR_PHY_AGC_CTL1_COARSE_LOW       0x00007F80
00125 #define AR_PHY_AGC_CTL1_COARSE_LOW_S     7
00126 #define AR_PHY_AGC_CTL1_COARSE_HIGH      0x003F8000
00127 #define AR_PHY_AGC_CTL1_COARSE_HIGH_S    15
00128 
00129 #define AR_PHY_CCA                  0x9864
00130 #define AR_PHY_MINCCA_PWR           0x0FF80000
00131 #define AR_PHY_MINCCA_PWR_S         19
00132 #define AR_PHY_CCA_THRESH62         0x0007F000
00133 #define AR_PHY_CCA_THRESH62_S       12
00134 #define AR9280_PHY_MINCCA_PWR       0x1FF00000
00135 #define AR9280_PHY_MINCCA_PWR_S     20
00136 #define AR9280_PHY_CCA_THRESH62     0x000FF000
00137 #define AR9280_PHY_CCA_THRESH62_S   12
00138 
00139 #define AR_PHY_SFCORR_LOW                    0x986C
00140 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW  0x00000001
00141 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW    0x00003F00
00142 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S  8
00143 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW      0x001FC000
00144 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S    14
00145 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW      0x0FE00000
00146 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S    21
00147 
00148 #define AR_PHY_SFCORR                0x9868
00149 #define AR_PHY_SFCORR_M2COUNT_THR    0x0000001F
00150 #define AR_PHY_SFCORR_M2COUNT_THR_S  0
00151 #define AR_PHY_SFCORR_M1_THRESH      0x00FE0000
00152 #define AR_PHY_SFCORR_M1_THRESH_S    17
00153 #define AR_PHY_SFCORR_M2_THRESH      0x7F000000
00154 #define AR_PHY_SFCORR_M2_THRESH_S    24
00155 
00156 #define AR_PHY_SLEEP_CTR_CONTROL    0x9870
00157 #define AR_PHY_SLEEP_CTR_LIMIT      0x9874
00158 #define AR_PHY_SYNTH_CONTROL        0x9874
00159 #define AR_PHY_SLEEP_SCAL           0x9878
00160 
00161 #define AR_PHY_PLL_CTL          0x987c
00162 #define AR_PHY_PLL_CTL_40       0xaa
00163 #define AR_PHY_PLL_CTL_40_5413  0x04
00164 #define AR_PHY_PLL_CTL_44       0xab
00165 #define AR_PHY_PLL_CTL_44_2133  0xeb
00166 #define AR_PHY_PLL_CTL_40_2133  0xea
00167 
00168 #define AR_PHY_SPECTRAL_SCAN                    0x9910  /* AR9280 spectral scan configuration register */
00169 #define AR_PHY_SPECTRAL_SCAN_ENABLE             0x1
00170 #define AR_PHY_SPECTRAL_SCAN_ENA                0x00000001  /* Enable spectral scan, reg 68, bit 0 */
00171 #define AR_PHY_SPECTRAL_SCAN_ENA_S              0  /* Enable spectral scan, reg 68, bit 0 */
00172 #define AR_PHY_SPECTRAL_SCAN_ACTIVE             0x00000002  /* Activate spectral scan reg 68, bit 1*/
00173 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S           1  /* Activate spectral scan reg 68, bit 1*/
00174 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD         0x000000F0  /* Interval for FFT reports, reg 68, bits 4-7*/
00175 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S       4
00176 #define AR_PHY_SPECTRAL_SCAN_PERIOD             0x0000FF00  /* Interval for FFT reports, reg 68, bits 8-15*/
00177 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S           8
00178 #define AR_PHY_SPECTRAL_SCAN_COUNT              0x00FF0000  /* Number of reports, reg 68, bits 16-23*/
00179 #define AR_PHY_SPECTRAL_SCAN_COUNT_S            16
00180 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT       0x01000000  /* Short repeat, reg 68, bit 24*/
00181 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S     24  /* Short repeat, reg 68, bit 24*/
00182 
00183 #define AR_PHY_RX_DELAY           0x9914
00184 #define AR_PHY_SEARCH_START_DELAY 0x9918
00185 #define AR_PHY_RX_DELAY_DELAY     0x00003FFF
00186 
00187 #define AR_PHY_TIMING_CTRL4(_i)     (0x9920 + ((_i) << 12))
00188 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
00189 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S   0
00190 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
00191 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S   5
00192 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE   0x800
00193 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
00194 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S   12
00195 #define AR_PHY_TIMING_CTRL4_DO_CAL    0x10000
00196 
00197 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI    0x80000000
00198 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER  0x40000000
00199 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK    0x20000000
00200 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK   0x10000000
00201 
00202 #define AR_PHY_TIMING5               0x9924
00203 #define AR_PHY_TIMING5_CYCPWR_THR1   0x000000FE
00204 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
00205 
00206 #define AR_PHY_POWER_TX_RATE1               0x9934
00207 #define AR_PHY_POWER_TX_RATE2               0x9938
00208 #define AR_PHY_POWER_TX_RATE_MAX            0x993c
00209 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
00210 
00211 #define AR_PHY_FRAME_CTL            0x9944
00212 #define AR_PHY_FRAME_CTL_TX_CLIP    0x00000038
00213 #define AR_PHY_FRAME_CTL_TX_CLIP_S  3
00214 
00215 #define AR_PHY_TXPWRADJ                   0x994C
00216 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA    0x00000FC0
00217 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S  6
00218 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX   0x00FC0000
00219 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
00220 
00221 #define AR_PHY_RADAR_EXT      0x9940
00222 #define AR_PHY_RADAR_EXT_ENA  0x00004000
00223 
00224 #define AR_PHY_RADAR_0          0x9954
00225 #define AR_PHY_RADAR_0_ENA      0x00000001
00226 #define AR_PHY_RADAR_0_FFT_ENA  0x80000000
00227 #define AR_PHY_RADAR_0_INBAND   0x0000003e
00228 #define AR_PHY_RADAR_0_INBAND_S 1
00229 #define AR_PHY_RADAR_0_PRSSI    0x00000FC0
00230 #define AR_PHY_RADAR_0_PRSSI_S  6
00231 #define AR_PHY_RADAR_0_HEIGHT   0x0003F000
00232 #define AR_PHY_RADAR_0_HEIGHT_S 12
00233 #define AR_PHY_RADAR_0_RRSSI    0x00FC0000
00234 #define AR_PHY_RADAR_0_RRSSI_S  18
00235 #define AR_PHY_RADAR_0_FIRPWR   0x7F000000
00236 #define AR_PHY_RADAR_0_FIRPWR_S 24
00237 
00238 #define AR_PHY_RADAR_1                  0x9958
00239 #define AR_PHY_RADAR_1_RELPWR_ENA       0x00800000
00240 #define AR_PHY_RADAR_1_USE_FIR128       0x00400000
00241 #define AR_PHY_RADAR_1_RELPWR_THRESH    0x003F0000
00242 #define AR_PHY_RADAR_1_RELPWR_THRESH_S  16
00243 #define AR_PHY_RADAR_1_BLOCK_CHECK      0x00008000
00244 #define AR_PHY_RADAR_1_MAX_RRSSI        0x00004000
00245 #define AR_PHY_RADAR_1_RELSTEP_CHECK    0x00002000
00246 #define AR_PHY_RADAR_1_RELSTEP_THRESH   0x00001F00
00247 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
00248 #define AR_PHY_RADAR_1_MAXLEN           0x000000FF
00249 #define AR_PHY_RADAR_1_MAXLEN_S         0
00250 
00251 #define AR_PHY_SWITCH_CHAIN_0     0x9960
00252 #define AR_PHY_SWITCH_COM         0x9964
00253 
00254 #define AR_PHY_SIGMA_DELTA            0x996C
00255 #define AR_PHY_SIGMA_DELTA_ADC_SEL    0x00000003
00256 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S  0
00257 #define AR_PHY_SIGMA_DELTA_FILT2      0x000000F8
00258 #define AR_PHY_SIGMA_DELTA_FILT2_S    3
00259 #define AR_PHY_SIGMA_DELTA_FILT1      0x00001F00
00260 #define AR_PHY_SIGMA_DELTA_FILT1_S    8
00261 #define AR_PHY_SIGMA_DELTA_ADC_CLIP   0x01FFE000
00262 #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
00263 
00264 #define AR_PHY_RESTART          0x9970
00265 #define AR_PHY_RESTART_DIV_GC   0x001C0000
00266 #define AR_PHY_RESTART_DIV_GC_S 18
00267 
00268 #define AR_PHY_RFBUS_REQ        0x997C
00269 #define AR_PHY_RFBUS_REQ_EN     0x00000001
00270 
00271 #define AR_PHY_TIMING7                  0x9980
00272 #define AR_PHY_TIMING8                  0x9984
00273 #define AR_PHY_TIMING8_PILOT_MASK_2     0x000FFFFF
00274 #define AR_PHY_TIMING8_PILOT_MASK_2_S   0
00275 
00276 #define AR_PHY_BIN_MASK2_1      0x9988
00277 #define AR_PHY_BIN_MASK2_2      0x998c
00278 #define AR_PHY_BIN_MASK2_3      0x9990
00279 #define AR_PHY_BIN_MASK2_4      0x9994
00280 
00281 #define AR_PHY_BIN_MASK_1       0x9900
00282 #define AR_PHY_BIN_MASK_2       0x9904
00283 #define AR_PHY_BIN_MASK_3       0x9908
00284 
00285 #define AR_PHY_MASK_CTL         0x990c
00286 
00287 #define AR_PHY_BIN_MASK2_4_MASK_4       0x00003FFF
00288 #define AR_PHY_BIN_MASK2_4_MASK_4_S     0
00289 
00290 #define AR_PHY_TIMING9                  0x9998
00291 #define AR_PHY_TIMING10                 0x999c
00292 #define AR_PHY_TIMING10_PILOT_MASK_2    0x000FFFFF
00293 #define AR_PHY_TIMING10_PILOT_MASK_2_S  0
00294 
00295 #define AR_PHY_TIMING11                         0x99a0
00296 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE        0x000FFFFF
00297 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S      0
00298 #define AR_PHY_TIMING11_USE_SPUR_IN_AGC         0x40000000
00299 #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR     0x80000000
00300 
00301 #define AR_PHY_RX_CHAINMASK     0x99a4
00302 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
00303 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
00304 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
00305 
00306 #define AR_PHY_MULTICHAIN_GAIN_CTL          0x99ac
00307 #define AR_PHY_9285_FAST_DIV_BIAS           0x00007E00
00308 #define AR_PHY_9285_FAST_DIV_BIAS_S         9
00309 #define AR_PHY_9285_ANT_DIV_CTL_ALL         0x7f000000
00310 #define AR_PHY_9285_ANT_DIV_CTL             0x01000000
00311 #define AR_PHY_9285_ANT_DIV_CTL_S           24
00312 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF     0x06000000
00313 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S   25
00314 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF    0x18000000
00315 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S  27
00316 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB      0x20000000
00317 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S    29
00318 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB     0x40000000
00319 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S   30
00320 #define AR_PHY_9285_ANT_DIV_LNA1            2
00321 #define AR_PHY_9285_ANT_DIV_LNA2            1
00322 #define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2  3
00323 #define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
00324 #define AR_PHY_9285_ANT_DIV_GAINTB_0        0
00325 #define AR_PHY_9285_ANT_DIV_GAINTB_1        1
00326 
00327 #define AR_PHY_EXT_CCA0             0x99b8
00328 #define AR_PHY_EXT_CCA0_THRESH62    0x000000FF
00329 #define AR_PHY_EXT_CCA0_THRESH62_S  0
00330 
00331 #define AR_PHY_EXT_CCA                  0x99bc
00332 #define AR_PHY_EXT_CCA_CYCPWR_THR1      0x0000FE00
00333 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S    9
00334 #define AR_PHY_EXT_CCA_THRESH62         0x007F0000
00335 #define AR_PHY_EXT_CCA_THRESH62_S       16
00336 #define AR_PHY_EXT_TIMING5_CYCPWR_THR1   0x0000FE00L
00337 #define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9
00338 
00339 #define AR_PHY_EXT_MINCCA_PWR           0xFF800000
00340 #define AR_PHY_EXT_MINCCA_PWR_S         23
00341 #define AR9280_PHY_EXT_MINCCA_PWR       0x01FF0000
00342 #define AR9280_PHY_EXT_MINCCA_PWR_S     16
00343 
00344 #define AR_PHY_SFCORR_EXT                 0x99c0
00345 #define AR_PHY_SFCORR_EXT_M1_THRESH       0x0000007F
00346 #define AR_PHY_SFCORR_EXT_M1_THRESH_S     0
00347 #define AR_PHY_SFCORR_EXT_M2_THRESH       0x00003F80
00348 #define AR_PHY_SFCORR_EXT_M2_THRESH_S     7
00349 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW   0x001FC000
00350 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
00351 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW   0x0FE00000
00352 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
00353 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S   28
00354 
00355 #define AR_PHY_HALFGI           0x99D0
00356 #define AR_PHY_HALFGI_DSC_MAN   0x0007FFF0
00357 #define AR_PHY_HALFGI_DSC_MAN_S 4
00358 #define AR_PHY_HALFGI_DSC_EXP   0x0000000F
00359 #define AR_PHY_HALFGI_DSC_EXP_S 0
00360 
00361 #define AR_PHY_CHAN_INFO_MEMORY               0x99DC
00362 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK  0x0001
00363 
00364 #define AR_PHY_HEAVY_CLIP_ENABLE         0x99E0
00365 
00366 #define AR_PHY_HEAVY_CLIP_FACTOR_RIFS    0x99EC
00367 #define AR_PHY_RIFS_INIT_DELAY         0x03ff0000
00368 
00369 #define AR_PHY_M_SLEEP      0x99f0
00370 #define AR_PHY_REFCLKDLY    0x99f4
00371 #define AR_PHY_REFCLKPD     0x99f8
00372 
00373 #define AR_PHY_CALMODE      0x99f0
00374 
00375 #define AR_PHY_CALMODE_IQ           0x00000000
00376 #define AR_PHY_CALMODE_ADC_GAIN     0x00000001
00377 #define AR_PHY_CALMODE_ADC_DC_PER   0x00000002
00378 #define AR_PHY_CALMODE_ADC_DC_INIT  0x00000003
00379 
00380 #define AR_PHY_CAL_MEAS_0(_i)     (0x9c10 + ((_i) << 12))
00381 #define AR_PHY_CAL_MEAS_1(_i)     (0x9c14 + ((_i) << 12))
00382 #define AR_PHY_CAL_MEAS_2(_i)     (0x9c18 + ((_i) << 12))
00383 #define AR_PHY_CAL_MEAS_3(_i)     (0x9c1c + ((_i) << 12))
00384 
00385 #define AR_PHY_CURRENT_RSSI 0x9c1c
00386 #define AR9280_PHY_CURRENT_RSSI 0x9c3c
00387 
00388 #define AR_PHY_RFBUS_GRANT       0x9C20
00389 #define AR_PHY_RFBUS_GRANT_EN    0x00000001
00390 
00391 #define AR_PHY_CHAN_INFO_GAIN_DIFF             0x9CF4
00392 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
00393 
00394 #define AR_PHY_CHAN_INFO_GAIN          0x9CFC
00395 
00396 #define AR_PHY_MODE         0xA200
00397 #define AR_PHY_MODE_ASYNCFIFO 0x80
00398 #define AR_PHY_MODE_AR2133  0x08
00399 #define AR_PHY_MODE_AR5111  0x00
00400 #define AR_PHY_MODE_AR5112  0x08
00401 #define AR_PHY_MODE_DYNAMIC 0x04
00402 #define AR_PHY_MODE_RF2GHZ  0x02
00403 #define AR_PHY_MODE_RF5GHZ  0x00
00404 #define AR_PHY_MODE_CCK     0x01
00405 #define AR_PHY_MODE_OFDM    0x00
00406 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
00407 
00408 #define AR_PHY_CCK_TX_CTRL       0xA204
00409 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
00410 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK         0x0000000C
00411 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S       2
00412 
00413 #define AR_PHY_CCK_DETECT                           0xA208
00414 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003F
00415 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
00416 /* [12:6] settling time for antenna switch */
00417 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001FC0
00418 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S         6
00419 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV    0x2000
00420 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S  13
00421 
00422 #define AR_PHY_GAIN_2GHZ                0xA20C
00423 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN    0x00FC0000
00424 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S  18
00425 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN     0x00003C00
00426 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S   10
00427 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN      0x0000001F
00428 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S    0
00429 
00430 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN     0x003E0000
00431 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S   17
00432 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN     0x0001F000
00433 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S   12
00434 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB         0x00000FC0
00435 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S       6
00436 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB         0x0000003F
00437 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S       0
00438 
00439 #define AR_PHY_CCK_RXCTRL4  0xA21C
00440 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT   0x01F80000
00441 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
00442 
00443 #define AR_PHY_DAG_CTRLCCK  0xA228
00444 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR  0x00000200
00445 #define AR_PHY_DAG_CTRLCCK_RSSI_THR     0x0001FC00
00446 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S   10
00447 
00448 #define AR_PHY_FORCE_CLKEN_CCK              0xA22C
00449 #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX      0x00000040
00450 
00451 #define AR_PHY_POWER_TX_RATE3   0xA234
00452 #define AR_PHY_POWER_TX_RATE4   0xA238
00453 
00454 #define AR_PHY_SCRM_SEQ_XR       0xA23C
00455 #define AR_PHY_HEADER_DETECT_XR  0xA240
00456 #define AR_PHY_CHIRP_DETECTED_XR 0xA244
00457 #define AR_PHY_BLUETOOTH         0xA254
00458 
00459 #define AR_PHY_TPCRG1   0xA258
00460 #define AR_PHY_TPCRG1_NUM_PD_GAIN   0x0000c000
00461 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
00462 
00463 #define AR_PHY_TPCRG1_PD_GAIN_1    0x00030000
00464 #define AR_PHY_TPCRG1_PD_GAIN_1_S  16
00465 #define AR_PHY_TPCRG1_PD_GAIN_2    0x000C0000
00466 #define AR_PHY_TPCRG1_PD_GAIN_2_S  18
00467 #define AR_PHY_TPCRG1_PD_GAIN_3    0x00300000
00468 #define AR_PHY_TPCRG1_PD_GAIN_3_S  20
00469 
00470 #define AR_PHY_TPCRG1_PD_CAL_ENABLE   0x00400000
00471 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
00472 
00473 #define AR_PHY_TX_PWRCTRL4       0xa264
00474 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID     0x00000001
00475 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S   0
00476 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT       0x000001FE
00477 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S     1
00478 
00479 #define AR_PHY_TX_PWRCTRL6_0     0xa270
00480 #define AR_PHY_TX_PWRCTRL6_1     0xb270
00481 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE     0x03000000
00482 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S   24
00483 
00484 #define AR_PHY_TX_PWRCTRL7       0xa274
00485 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN     0x01F80000
00486 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S   19
00487 
00488 #define AR_PHY_TX_PWRCTRL8       0xa278
00489 
00490 #define AR_PHY_TX_PWRCTRL9       0xa27C
00491 
00492 #define AR_PHY_TX_PWRCTRL10       0xa394
00493 #define AR_PHY_TX_DESIRED_SCALE_CCK        0x00007C00
00494 #define AR_PHY_TX_DESIRED_SCALE_CCK_S      10
00495 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL  0x80000000
00496 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
00497 
00498 #define AR_PHY_TX_GAIN_TBL1      0xa300
00499 #define AR_PHY_TX_GAIN                     0x0007F000
00500 #define AR_PHY_TX_GAIN_S                   12
00501 
00502 #define AR_PHY_CH0_TX_PWRCTRL11  0xa398
00503 #define AR_PHY_CH1_TX_PWRCTRL11  0xb398
00504 #define AR_PHY_CH0_TX_PWRCTRL12  0xa3dc
00505 #define AR_PHY_CH0_TX_PWRCTRL13  0xa3e0
00506 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP   0x0000FC00
00507 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
00508 
00509 #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
00510 #define AR_PHY_MASK2_M_31_45     0xa3a4
00511 #define AR_PHY_MASK2_M_16_30     0xa3a8
00512 #define AR_PHY_MASK2_M_00_15     0xa3ac
00513 #define AR_PHY_MASK2_P_15_01     0xa3b8
00514 #define AR_PHY_MASK2_P_30_16     0xa3bc
00515 #define AR_PHY_MASK2_P_45_31     0xa3c0
00516 #define AR_PHY_MASK2_P_61_45     0xa3c4
00517 #define AR_PHY_SPUR_REG          0x994c
00518 
00519 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL       (0xFF << 18)
00520 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S     18
00521 
00522 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM      0x20000
00523 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT     (0xFF << 9)
00524 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S   9
00525 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
00526 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH     0x7F
00527 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S   0
00528 
00529 #define AR_PHY_PILOT_MASK_01_30   0xa3b0
00530 #define AR_PHY_PILOT_MASK_31_60   0xa3b4
00531 
00532 #define AR_PHY_CHANNEL_MASK_01_30 0x99d4
00533 #define AR_PHY_CHANNEL_MASK_31_60 0x99d8
00534 
00535 #define AR_PHY_ANALOG_SWAP      0xa268
00536 #define AR_PHY_SWAP_ALT_CHAIN   0x00000040
00537 
00538 #define AR_PHY_TPCRG5   0xA26C
00539 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP       0x0000000F
00540 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S     0
00541 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1    0x000003F0
00542 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S  4
00543 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2    0x0000FC00
00544 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S  10
00545 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3    0x003F0000
00546 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S  16
00547 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4    0x0FC00000
00548 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S  22
00549 
00550 /* Carrier leak calibration control, do it after AGC calibration */
00551 #define AR_PHY_CL_CAL_CTL       0xA358
00552 #define AR_PHY_CL_CAL_ENABLE    0x00000002
00553 #define AR_PHY_PARALLEL_CAL_ENABLE    0x00000001
00554 
00555 #define AR_PHY_POWER_TX_RATE5   0xA38C
00556 #define AR_PHY_POWER_TX_RATE6   0xA390
00557 
00558 #define AR_PHY_CAL_CHAINMASK    0xA39C
00559 
00560 #define AR_PHY_POWER_TX_SUB     0xA3C8
00561 #define AR_PHY_POWER_TX_RATE7   0xA3CC
00562 #define AR_PHY_POWER_TX_RATE8   0xA3D0
00563 #define AR_PHY_POWER_TX_RATE9   0xA3D4
00564 
00565 #define AR_PHY_XPA_CFG          0xA3D8
00566 #define AR_PHY_FORCE_XPA_CFG    0x000000001
00567 #define AR_PHY_FORCE_XPA_CFG_S  0
00568 
00569 #define AR_PHY_CH1_CCA          0xa864
00570 #define AR_PHY_CH1_MINCCA_PWR   0x0FF80000
00571 #define AR_PHY_CH1_MINCCA_PWR_S 19
00572 #define AR9280_PHY_CH1_MINCCA_PWR   0x1FF00000
00573 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
00574 
00575 #define AR_PHY_CH2_CCA          0xb864
00576 #define AR_PHY_CH2_MINCCA_PWR   0x0FF80000
00577 #define AR_PHY_CH2_MINCCA_PWR_S 19
00578 
00579 #define AR_PHY_CH1_EXT_CCA          0xa9bc
00580 #define AR_PHY_CH1_EXT_MINCCA_PWR   0xFF800000
00581 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
00582 #define AR9280_PHY_CH1_EXT_MINCCA_PWR   0x01FF0000
00583 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
00584 
00585 #define AR_PHY_CH2_EXT_CCA          0xb9bc
00586 #define AR_PHY_CH2_EXT_MINCCA_PWR   0xFF800000
00587 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
00588 
00589 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ            -90
00590 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ            -100
00591 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ     -100
00592 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ     -110
00593 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ     -80
00594 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ     -90
00595 
00596 #define AR_PHY_CCA_NOM_VAL_9280_2GHZ         -112
00597 #define AR_PHY_CCA_NOM_VAL_9280_5GHZ         -112
00598 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ  -127
00599 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ  -122
00600 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ  -97
00601 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ  -102
00602 
00603 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ           -118
00604 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ    -127
00605 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ    -108
00606 
00607 #define AR_PHY_CCA_NOM_VAL_9271_2GHZ             -118
00608 #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ      -127
00609 #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ      -116
00610 
00611 #define AR_PHY_CCA_NOM_VAL_9287_2GHZ           -120
00612 #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ    -127
00613 #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ    -110
00614 
00615 #endif