iPXE
ar9003_mac.h
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1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef AR9003_MAC_H
21 #define AR9003_MAC_H
22 
23 #define AR_DescId 0xffff0000
24 #define AR_DescId_S 16
25 #define AR_CtrlStat 0x00004000
26 #define AR_CtrlStat_S 14
27 #define AR_TxRxDesc 0x00008000
28 #define AR_TxRxDesc_S 15
29 #define AR_TxQcuNum 0x00000f00
30 #define AR_TxQcuNum_S 8
31 
32 #define AR_BufLen 0x0fff0000
33 #define AR_BufLen_S 16
34 
35 #define AR_TxDescId 0xffff0000
36 #define AR_TxDescId_S 16
37 #define AR_TxPtrChkSum 0x0000ffff
38 
39 #define AR_LowRxChain 0x00004000
40 
41 #define AR_Not_Sounding 0x20000000
42 
43 /* ctl 12 */
44 #define AR_PAPRDChainMask 0x00000e00
45 #define AR_PAPRDChainMask_S 9
46 
47 #define MAP_ISR_S2_CST 6
48 #define MAP_ISR_S2_GTT 6
49 #define MAP_ISR_S2_TIM 3
50 #define MAP_ISR_S2_CABEND 0
51 #define MAP_ISR_S2_DTIMSYNC 7
52 #define MAP_ISR_S2_DTIM 7
53 #define MAP_ISR_S2_TSFOOR 4
54 #define MAP_ISR_S2_BB_WATCHDOG 6
55 
56 #define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
57 
58 struct ar9003_rxs {
71 } __attribute__((packed, aligned(4)));
72 
73 /* Transmit Control Descriptor */
74 struct ar9003_txc {
75  u32 info; /* descriptor information */
76  u32 link; /* link pointer */
77  u32 data0; /* data pointer to 1st buffer */
78  u32 ctl3; /* DMA control 3 */
79  u32 data1; /* data pointer to 2nd buffer */
80  u32 ctl5; /* DMA control 5 */
81  u32 data2; /* data pointer to 3rd buffer */
82  u32 ctl7; /* DMA control 7 */
83  u32 data3; /* data pointer to 4th buffer */
84  u32 ctl9; /* DMA control 9 */
85  u32 ctl10; /* DMA control 10 */
86  u32 ctl11; /* DMA control 11 */
87  u32 ctl12; /* DMA control 12 */
88  u32 ctl13; /* DMA control 13 */
89  u32 ctl14; /* DMA control 14 */
90  u32 ctl15; /* DMA control 15 */
91  u32 ctl16; /* DMA control 16 */
92  u32 ctl17; /* DMA control 17 */
93  u32 ctl18; /* DMA control 18 */
94  u32 ctl19; /* DMA control 19 */
95  u32 ctl20; /* DMA control 20 */
96  u32 ctl21; /* DMA control 21 */
97  u32 ctl22; /* DMA control 22 */
98  u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
99 } __attribute__((packed, aligned(4)));
100 
101 struct ar9003_txs {
111 } __attribute__((packed, aligned(4)));
112 
113 void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
114 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
115 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
116  enum ath9k_rx_qtype qtype);
117 
119  struct ath_rx_status *rxs,
120  void *buf_addr);
122 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
123  u32 ts_paddr_start,
124  u8 size);
125 #endif
uint16_t u16
Definition: stdint.h:21
Definition: hw.h:656
u32 pad[9]
Definition: ar9003_mac.h:98
u32 status10
Definition: ar9003_mac.h:69
u32 status3
Definition: ar9003_mac.h:62
Definition: hw.c:16
u32 status8
Definition: ar9003_mac.h:67
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
u32 status1
Definition: ar9003_mac.h:60
void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, u32 ts_paddr_start, u8 size)
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, void *buf_addr)
u32 status6
Definition: ar9003_mac.h:65
u32 status9
Definition: ar9003_mac.h:68
u32 status4
Definition: ar9003_mac.h:63
void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, enum ath9k_rx_qtype qtype)
u32 status2
Definition: ar9003_mac.h:61
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
Definition: sis900.h:32
u32 status5
Definition: ar9003_mac.h:64
uint8_t ah
Definition: registers.h:85
u32 status11
Definition: ar9003_mac.h:70
ath9k_rx_qtype
Definition: hw.h:399
u32 ds_info
Definition: ar9003_mac.h:59
u32 status7
Definition: ar9003_mac.h:66
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
struct ar9003_rxs __attribute__((packed, aligned(4)))