iPXE
ar9003_mac.h
Go to the documentation of this file.
00001 /*
00002  * Copyright (c) 2010-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #ifndef AR9003_MAC_H
00021 #define AR9003_MAC_H
00022 
00023 #define AR_DescId       0xffff0000
00024 #define AR_DescId_S     16
00025 #define AR_CtrlStat     0x00004000
00026 #define AR_CtrlStat_S   14
00027 #define AR_TxRxDesc     0x00008000
00028 #define AR_TxRxDesc_S   15
00029 #define AR_TxQcuNum     0x00000f00
00030 #define AR_TxQcuNum_S   8
00031 
00032 #define AR_BufLen       0x0fff0000
00033 #define AR_BufLen_S     16
00034 
00035 #define AR_TxDescId     0xffff0000
00036 #define AR_TxDescId_S   16
00037 #define AR_TxPtrChkSum  0x0000ffff
00038 
00039 #define AR_LowRxChain   0x00004000
00040 
00041 #define AR_Not_Sounding 0x20000000
00042 
00043 /* ctl 12 */
00044 #define AR_PAPRDChainMask       0x00000e00
00045 #define AR_PAPRDChainMask_S     9
00046 
00047 #define MAP_ISR_S2_CST          6
00048 #define MAP_ISR_S2_GTT          6
00049 #define MAP_ISR_S2_TIM          3
00050 #define MAP_ISR_S2_CABEND       0
00051 #define MAP_ISR_S2_DTIMSYNC     7
00052 #define MAP_ISR_S2_DTIM         7
00053 #define MAP_ISR_S2_TSFOOR       4
00054 #define MAP_ISR_S2_BB_WATCHDOG  6
00055 
00056 #define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
00057 
00058 struct ar9003_rxs {
00059         u32 ds_info;
00060         u32 status1;
00061         u32 status2;
00062         u32 status3;
00063         u32 status4;
00064         u32 status5;
00065         u32 status6;
00066         u32 status7;
00067         u32 status8;
00068         u32 status9;
00069         u32 status10;
00070         u32 status11;
00071 } __attribute__((packed, aligned(4)));
00072 
00073 /* Transmit Control Descriptor */
00074 struct ar9003_txc {
00075         u32 info;   /* descriptor information */
00076         u32 link;   /* link pointer */
00077         u32 data0;  /* data pointer to 1st buffer */
00078         u32 ctl3;   /* DMA control 3  */
00079         u32 data1;  /* data pointer to 2nd buffer */
00080         u32 ctl5;   /* DMA control 5  */
00081         u32 data2;  /* data pointer to 3rd buffer */
00082         u32 ctl7;   /* DMA control 7  */
00083         u32 data3;  /* data pointer to 4th buffer */
00084         u32 ctl9;   /* DMA control 9  */
00085         u32 ctl10;  /* DMA control 10 */
00086         u32 ctl11;  /* DMA control 11 */
00087         u32 ctl12;  /* DMA control 12 */
00088         u32 ctl13;  /* DMA control 13 */
00089         u32 ctl14;  /* DMA control 14 */
00090         u32 ctl15;  /* DMA control 15 */
00091         u32 ctl16;  /* DMA control 16 */
00092         u32 ctl17;  /* DMA control 17 */
00093         u32 ctl18;  /* DMA control 18 */
00094         u32 ctl19;  /* DMA control 19 */
00095         u32 ctl20;  /* DMA control 20 */
00096         u32 ctl21;  /* DMA control 21 */
00097         u32 ctl22;  /* DMA control 22 */
00098         u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
00099 } __attribute__((packed, aligned(4)));
00100 
00101 struct ar9003_txs {
00102         u32 ds_info;
00103         u32 status1;
00104         u32 status2;
00105         u32 status3;
00106         u32 status4;
00107         u32 status5;
00108         u32 status6;
00109         u32 status7;
00110         u32 status8;
00111 } __attribute__((packed, aligned(4)));
00112 
00113 void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
00114 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
00115 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
00116                             enum ath9k_rx_qtype qtype);
00117 
00118 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
00119                                  struct ath_rx_status *rxs,
00120                                  void *buf_addr);
00121 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
00122 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
00123                                u32 ts_paddr_start,
00124                                u8 size);
00125 #endif