iPXE
ar9003_phy.h
Go to the documentation of this file.
00001 /*
00002  * Copyright (c) 2010-2011 Atheros Communications, Inc.
00003  *
00004  * Permission to use, copy, modify, and/or distribute this software for any
00005  * purpose with or without fee is hereby granted, provided that the above
00006  * copyright notice and this permission notice appear in all copies.
00007  *
00008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00015  */
00016 
00017 #ifndef AR9003_PHY_H
00018 #define AR9003_PHY_H
00019 
00020 /*
00021  * Channel Register Map
00022  */
00023 #define AR_CHAN_BASE    0x9800
00024 
00025 #define AR_PHY_TIMING1      (AR_CHAN_BASE + 0x0)
00026 #define AR_PHY_TIMING2      (AR_CHAN_BASE + 0x4)
00027 #define AR_PHY_TIMING3      (AR_CHAN_BASE + 0x8)
00028 #define AR_PHY_TIMING4      (AR_CHAN_BASE + 0xc)
00029 #define AR_PHY_TIMING5      (AR_CHAN_BASE + 0x10)
00030 #define AR_PHY_TIMING6      (AR_CHAN_BASE + 0x14)
00031 #define AR_PHY_TIMING11     (AR_CHAN_BASE + 0x18)
00032 #define AR_PHY_SPUR_REG     (AR_CHAN_BASE + 0x1c)
00033 #define AR_PHY_RX_IQCAL_CORR_B0    (AR_CHAN_BASE + 0xdc)
00034 #define AR_PHY_TX_IQCAL_CONTROL_3  (AR_CHAN_BASE + 0xb0)
00035 
00036 #define AR_PHY_TIMING11_SPUR_FREQ_SD    0x3FF00000
00037 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S  20
00038 
00039 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
00040 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
00041 
00042 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
00043 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
00044 
00045 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
00046 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
00047 
00048 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT         0x4000000
00049 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S       26
00050 
00051 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM                         0x20000     /* bins move with freq offset */
00052 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S                       17
00053 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH            0x000000FF
00054 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S          0
00055 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI                        0x00000100
00056 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S                      8
00057 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL                          0x03FC0000
00058 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S                        18
00059 
00060 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN   0x20000000
00061 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S         29
00062 
00063 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN   0x80000000
00064 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S         31
00065 
00066 #define AR_PHY_FIND_SIG_LOW  (AR_CHAN_BASE + 0x20)
00067 
00068 #define AR_PHY_SFCORR           (AR_CHAN_BASE + 0x24)
00069 #define AR_PHY_SFCORR_LOW       (AR_CHAN_BASE + 0x28)
00070 #define AR_PHY_SFCORR_EXT       (AR_CHAN_BASE + 0x2c)
00071 
00072 #define AR_PHY_EXT_CCA              (AR_CHAN_BASE + 0x30)
00073 #define AR_PHY_RADAR_0              (AR_CHAN_BASE + 0x34)
00074 #define AR_PHY_RADAR_1              (AR_CHAN_BASE + 0x38)
00075 #define AR_PHY_RADAR_EXT            (AR_CHAN_BASE + 0x3c)
00076 #define AR_PHY_MULTICHAIN_CTRL      (AR_CHAN_BASE + 0x80)
00077 #define AR_PHY_PERCHAIN_CSD         (AR_CHAN_BASE + 0x84)
00078 
00079 #define AR_PHY_TX_PHASE_RAMP_0      (AR_CHAN_BASE + 0xd0)
00080 #define AR_PHY_ADC_GAIN_DC_CORR_0   (AR_CHAN_BASE + 0xd4)
00081 #define AR_PHY_IQ_ADC_MEAS_0_B0     (AR_CHAN_BASE + 0xc0)
00082 #define AR_PHY_IQ_ADC_MEAS_1_B0     (AR_CHAN_BASE + 0xc4)
00083 #define AR_PHY_IQ_ADC_MEAS_2_B0     (AR_CHAN_BASE + 0xc8)
00084 #define AR_PHY_IQ_ADC_MEAS_3_B0     (AR_CHAN_BASE + 0xcc)
00085 
00086 /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
00087 #define AR_PHY_TX_PHASE_RAMP_0_9300_10      (AR_CHAN_BASE + 0xd0 - 0x10)
00088 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10   (AR_CHAN_BASE + 0xd4 - 0x10)
00089 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10     (AR_CHAN_BASE + 0xc0 + 0x8)
00090 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10     (AR_CHAN_BASE + 0xc4 + 0x8)
00091 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10     (AR_CHAN_BASE + 0xc8 + 0x8)
00092 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10     (AR_CHAN_BASE + 0xcc + 0x8)
00093 
00094 #define AR_PHY_TX_CRC               (AR_CHAN_BASE + 0xa0)
00095 #define AR_PHY_TST_DAC_CONST        (AR_CHAN_BASE + 0xa4)
00096 #define AR_PHY_SPUR_REPORT_0        (AR_CHAN_BASE + 0xa8)
00097 #define AR_PHY_CHAN_INFO_TAB_0      (AR_CHAN_BASE + 0x300)
00098 
00099 /*
00100  * Channel Field Definitions
00101  */
00102 #define AR_PHY_TIMING2_USE_FORCE_PPM    0x00001000
00103 #define AR_PHY_TIMING2_FORCE_PPM_VAL    0x00000fff
00104 #define AR_PHY_TIMING3_DSC_MAN      0xFFFE0000
00105 #define AR_PHY_TIMING3_DSC_MAN_S    17
00106 #define AR_PHY_TIMING3_DSC_EXP      0x0001E000
00107 #define AR_PHY_TIMING3_DSC_EXP_S    13
00108 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
00109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S   12
00110 #define AR_PHY_TIMING4_DO_CAL    0x10000
00111 
00112 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK        0x10000000
00113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S      28
00114 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK         0x20000000
00115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S       29
00116 
00117 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
00118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
00119 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
00120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
00121 
00122 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
00123 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
00124 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW  0x00000001
00125 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW    0x00003F00
00126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S  8
00127 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW      0x001FC000
00128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S    14
00129 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW      0x0FE00000
00130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S    21
00131 #define AR_PHY_SFCORR_M2COUNT_THR    0x0000001F
00132 #define AR_PHY_SFCORR_M2COUNT_THR_S  0
00133 #define AR_PHY_SFCORR_M1_THRESH      0x00FE0000
00134 #define AR_PHY_SFCORR_M1_THRESH_S    17
00135 #define AR_PHY_SFCORR_M2_THRESH      0x7F000000
00136 #define AR_PHY_SFCORR_M2_THRESH_S    24
00137 #define AR_PHY_SFCORR_EXT_M1_THRESH       0x0000007F
00138 #define AR_PHY_SFCORR_EXT_M1_THRESH_S     0
00139 #define AR_PHY_SFCORR_EXT_M2_THRESH       0x00003F80
00140 #define AR_PHY_SFCORR_EXT_M2_THRESH_S     7
00141 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW   0x001FC000
00142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
00143 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW   0x0FE00000
00144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
00145 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
00146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
00147 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S   28
00148 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
00149 #define AR_PHY_EXT_CCA_THRESH62_S       16
00150 #define AR_PHY_EXT_MINCCA_PWR   0x01FF0000
00151 #define AR_PHY_EXT_MINCCA_PWR_S 16
00152 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
00153 #define AR_PHY_EXT_CYCPWR_THR1_S 9
00154 #define AR_PHY_TIMING5_CYCPWR_THR1  0x000000FE
00155 #define AR_PHY_TIMING5_CYCPWR_THR1_S    1
00156 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE  0x00000001
00157 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S    0
00158 #define AR_PHY_TIMING5_CYCPWR_THR1A  0x007F0000
00159 #define AR_PHY_TIMING5_CYCPWR_THR1A_S    16
00160 #define AR_PHY_TIMING5_RSSI_THR1A     (0x7F << 16)
00161 #define AR_PHY_TIMING5_RSSI_THR1A_S   16
00162 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
00163 #define AR_PHY_RADAR_0_ENA  0x00000001
00164 #define AR_PHY_RADAR_0_FFT_ENA  0x80000000
00165 #define AR_PHY_RADAR_0_INBAND   0x0000003e
00166 #define AR_PHY_RADAR_0_INBAND_S 1
00167 #define AR_PHY_RADAR_0_PRSSI    0x00000FC0
00168 #define AR_PHY_RADAR_0_PRSSI_S  6
00169 #define AR_PHY_RADAR_0_HEIGHT   0x0003F000
00170 #define AR_PHY_RADAR_0_HEIGHT_S 12
00171 #define AR_PHY_RADAR_0_RRSSI    0x00FC0000
00172 #define AR_PHY_RADAR_0_RRSSI_S  18
00173 #define AR_PHY_RADAR_0_FIRPWR   0x7F000000
00174 #define AR_PHY_RADAR_0_FIRPWR_S 24
00175 #define AR_PHY_RADAR_1_RELPWR_ENA       0x00800000
00176 #define AR_PHY_RADAR_1_USE_FIR128       0x00400000
00177 #define AR_PHY_RADAR_1_RELPWR_THRESH    0x003F0000
00178 #define AR_PHY_RADAR_1_RELPWR_THRESH_S  16
00179 #define AR_PHY_RADAR_1_BLOCK_CHECK      0x00008000
00180 #define AR_PHY_RADAR_1_MAX_RRSSI        0x00004000
00181 #define AR_PHY_RADAR_1_RELSTEP_CHECK    0x00002000
00182 #define AR_PHY_RADAR_1_RELSTEP_THRESH   0x00001F00
00183 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
00184 #define AR_PHY_RADAR_1_MAXLEN           0x000000FF
00185 #define AR_PHY_RADAR_1_MAXLEN_S         0
00186 #define AR_PHY_RADAR_EXT_ENA            0x00004000
00187 #define AR_PHY_RADAR_DC_PWR_THRESH      0x007f8000
00188 #define AR_PHY_RADAR_DC_PWR_THRESH_S    15
00189 #define AR_PHY_RADAR_LB_DC_CAP          0x7f800000
00190 #define AR_PHY_RADAR_LB_DC_CAP_S        23
00191 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
00192 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S   6
00193 #define AR_PHY_FIND_SIG_LOW_FIRPWR      (0x7f << 12)
00194 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S    12
00195 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
00196 #define AR_PHY_FIND_SIG_LOW_RELSTEP     0x1f
00197 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S   0
00198 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
00199 #define AR_PHY_CHAN_INFO_TAB_S2_READ    0x00000008
00200 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S           3
00201 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
00202 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S   0
00203 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
00204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S   7
00205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE   0x00004000
00206 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF   0x003f8000
00207 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
00208 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF   0x1fc00000
00209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
00210 
00211 /*
00212  * MRC Register Map
00213  */
00214 #define AR_MRC_BASE     0x9c00
00215 
00216 #define AR_PHY_TIMING_3A       (AR_MRC_BASE + 0x0)
00217 #define AR_PHY_LDPC_CNTL1      (AR_MRC_BASE + 0x4)
00218 #define AR_PHY_LDPC_CNTL2      (AR_MRC_BASE + 0x8)
00219 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
00220 #define AR_PHY_CHAN_SPUR_MASK  (AR_MRC_BASE + 0x10)
00221 #define AR_PHY_SGI_DELTA       (AR_MRC_BASE + 0x14)
00222 #define AR_PHY_ML_CNTL_1       (AR_MRC_BASE + 0x18)
00223 #define AR_PHY_ML_CNTL_2       (AR_MRC_BASE + 0x1c)
00224 #define AR_PHY_TST_ADC         (AR_MRC_BASE + 0x20)
00225 
00226 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A              0x00000FE0
00227 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S    5
00228 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A                  0x1F
00229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S                0
00230 
00231 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A        0x00000FE0
00232 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S      5
00233 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A            0x1F
00234 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S          0
00235 
00236 /*
00237  * MRC Feild Definitions
00238  */
00239 #define AR_PHY_SGI_DSC_MAN   0x0007FFF0
00240 #define AR_PHY_SGI_DSC_MAN_S 4
00241 #define AR_PHY_SGI_DSC_EXP   0x0000000F
00242 #define AR_PHY_SGI_DSC_EXP_S 0
00243 /*
00244  * BBB Register Map
00245  */
00246 #define AR_BBB_BASE     0x9d00
00247 
00248 /*
00249  * AGC Register Map
00250  */
00251 #define AR_AGC_BASE     0x9e00
00252 
00253 #define AR_PHY_SETTLING         (AR_AGC_BASE + 0x0)
00254 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
00255 #define AR_PHY_GAINS_MINOFF0    (AR_AGC_BASE + 0x8)
00256 #define AR_PHY_DESIRED_SZ       (AR_AGC_BASE + 0xc)
00257 #define AR_PHY_FIND_SIG         (AR_AGC_BASE + 0x10)
00258 #define AR_PHY_AGC              (AR_AGC_BASE + 0x14)
00259 #define AR_PHY_EXT_ATTEN_CTL_0  (AR_AGC_BASE + 0x18)
00260 #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
00261 #define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
00262 #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
00263 
00264 /*
00265  * Antenna Diversity  settings
00266  */
00267 #define AR_PHY_MC_GAIN_CTRL     (AR_AGC_BASE + 0x28)
00268 #define AR_ANT_DIV_CTRL_ALL     0x7e000000
00269 #define AR_ANT_DIV_CTRL_ALL_S   25
00270 #define AR_ANT_DIV_ENABLE       0x1000000
00271 #define AR_ANT_DIV_ENABLE_S     24
00272 
00273 
00274 #define AR_PHY_9485_ANT_FAST_DIV_BIAS                   0x00007e00
00275 #define AR_PHY_9485_ANT_FAST_DIV_BIAS_S                  9
00276 #define AR_PHY_9485_ANT_DIV_LNADIV                      0x01000000
00277 #define AR_PHY_9485_ANT_DIV_LNADIV_S                    24
00278 #define AR_PHY_9485_ANT_DIV_ALT_LNACONF                 0x06000000
00279 #define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S               25
00280 #define AR_PHY_9485_ANT_DIV_MAIN_LNACONF                0x18000000
00281 #define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S              27
00282 #define AR_PHY_9485_ANT_DIV_ALT_GAINTB                  0x20000000
00283 #define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S                29
00284 #define AR_PHY_9485_ANT_DIV_MAIN_GAINTB                 0x40000000
00285 #define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S               30
00286 
00287 #define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2             0x0
00288 #define AR_PHY_9485_ANT_DIV_LNA2                        0x1
00289 #define AR_PHY_9485_ANT_DIV_LNA1                        0x2
00290 #define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2              0x3
00291 
00292 #define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
00293 #define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
00294 #define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)
00295 #define AR_PHY_RIFS_SRCH        (AR_AGC_BASE + 0x38)
00296 #define AR_PHY_PEAK_DET_CTRL_1  (AR_AGC_BASE + 0x3c)
00297 #define AR_PHY_PEAK_DET_CTRL_2  (AR_AGC_BASE + 0x40)
00298 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
00299 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
00300 #define AR_PHY_RSSI_0           (AR_AGC_BASE + 0x180)
00301 #define AR_PHY_SPUR_CCK_REP0    (AR_AGC_BASE + 0x184)
00302 
00303 #define AR_PHY_CCK_DETECT       (AR_AGC_BASE + 0x1c0)
00304 #define AR_FAST_DIV_ENABLE      0x2000
00305 #define AR_FAST_DIV_ENABLE_S    13
00306 
00307 #define AR_PHY_DAG_CTRLCCK      (AR_AGC_BASE + 0x1c4)
00308 #define AR_PHY_IQCORR_CTRL_CCK  (AR_AGC_BASE + 0x1c8)
00309 
00310 #define AR_PHY_CCK_SPUR_MIT     (AR_AGC_BASE + 0x1cc)
00311 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR                           0x000001fe
00312 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S                                  1
00313 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE                        0x60000000
00314 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S                              29
00315 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT                        0x00000001
00316 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S                               0
00317 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ                           0x1ffffe00
00318 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S                                  9
00319 
00320 #define AR_PHY_MRC_CCK_CTRL         (AR_AGC_BASE + 0x1d0)
00321 #define AR_PHY_MRC_CCK_ENABLE       0x00000001
00322 #define AR_PHY_MRC_CCK_ENABLE_S              0
00323 #define AR_PHY_MRC_CCK_MUX_REG      0x00000002
00324 #define AR_PHY_MRC_CCK_MUX_REG_S             1
00325 
00326 #define AR_PHY_RX_OCGAIN        (AR_AGC_BASE + 0x200)
00327 
00328 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ          -110
00329 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ          -115
00330 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ     -125
00331 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ     -125
00332 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95
00333 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
00334 
00335 /*
00336  * AGC Field Definitions
00337  */
00338 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN    0x00FC0000
00339 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S  18
00340 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN     0x00003C00
00341 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S   10
00342 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN      0x0000001F
00343 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S    0
00344 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN     0x003E0000
00345 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S   17
00346 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN     0x0001F000
00347 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S   12
00348 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB         0x00000FC0
00349 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S       6
00350 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB         0x0000003F
00351 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S       0
00352 #define AR_PHY_RXGAIN_TXRX_ATTEN    0x0003F000
00353 #define AR_PHY_RXGAIN_TXRX_ATTEN_S  12
00354 #define AR_PHY_RXGAIN_TXRX_RF_MAX   0x007C0000
00355 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
00356 #define AR9280_PHY_RXGAIN_TXRX_ATTEN    0x00003F80
00357 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S  7
00358 #define AR9280_PHY_RXGAIN_TXRX_MARGIN   0x001FC000
00359 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
00360 #define AR_PHY_SETTLING_SWITCH  0x00003F80
00361 #define AR_PHY_SETTLING_SWITCH_S    7
00362 #define AR_PHY_DESIRED_SZ_ADC       0x000000FF
00363 #define AR_PHY_DESIRED_SZ_ADC_S     0
00364 #define AR_PHY_DESIRED_SZ_PGA       0x0000FF00
00365 #define AR_PHY_DESIRED_SZ_PGA_S     8
00366 #define AR_PHY_DESIRED_SZ_TOT_DES   0x0FF00000
00367 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
00368 #define AR_PHY_MINCCA_PWR       0x1FF00000
00369 #define AR_PHY_MINCCA_PWR_S     20
00370 #define AR_PHY_CCA_THRESH62     0x0007F000
00371 #define AR_PHY_CCA_THRESH62_S   12
00372 #define AR9280_PHY_MINCCA_PWR       0x1FF00000
00373 #define AR9280_PHY_MINCCA_PWR_S     20
00374 #define AR9280_PHY_CCA_THRESH62     0x000FF000
00375 #define AR9280_PHY_CCA_THRESH62_S   12
00376 #define AR_PHY_EXT_CCA0_THRESH62    0x000000FF
00377 #define AR_PHY_EXT_CCA0_THRESH62_S  0
00378 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003F
00379 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
00380 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001FC0
00381 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S         6
00382 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV    0x2000
00383 
00384 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR  0x00000200
00385 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S  9
00386 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
00387 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S   10
00388 
00389 #define AR_PHY_RIFS_INIT_DELAY         0x3ff0000
00390 #define AR_PHY_AGC_COARSE_LOW       0x00007F80
00391 #define AR_PHY_AGC_COARSE_LOW_S     7
00392 #define AR_PHY_AGC_COARSE_HIGH      0x003F8000
00393 #define AR_PHY_AGC_COARSE_HIGH_S    15
00394 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
00395 #define AR_PHY_AGC_COARSE_PWR_CONST_S   0
00396 #define AR_PHY_FIND_SIG_FIRSTEP  0x0003F000
00397 #define AR_PHY_FIND_SIG_FIRSTEP_S        12
00398 #define AR_PHY_FIND_SIG_FIRPWR   0x03FC0000
00399 #define AR_PHY_FIND_SIG_FIRPWR_S         18
00400 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT  25
00401 #define AR_PHY_FIND_SIG_RELPWR   (0x1f << 6)
00402 #define AR_PHY_FIND_SIG_RELPWR_S          6
00403 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT  11
00404 #define AR_PHY_FIND_SIG_RELSTEP        0x1f
00405 #define AR_PHY_FIND_SIG_RELSTEP_S         0
00406 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT  5
00407 #define AR_PHY_RESTART_DIV_GC   0x001C0000
00408 #define AR_PHY_RESTART_DIV_GC_S 18
00409 #define AR_PHY_RESTART_ENA      0x01
00410 #define AR_PHY_DC_RESTART_DIS   0x40000000
00411 
00412 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON       0xFF000000
00413 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S     24
00414 #define AR_PHY_TPC_OLPC_GAIN_DELTA              0x00FF0000
00415 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S            16
00416 
00417 #define AR_PHY_TPC_6_ERROR_EST_MODE             0x03000000
00418 #define AR_PHY_TPC_6_ERROR_EST_MODE_S           24
00419 
00420 /*
00421  * SM Register Map
00422  */
00423 #define AR_SM_BASE      0xa200
00424 
00425 #define AR_PHY_D2_CHIP_ID        (AR_SM_BASE + 0x0)
00426 #define AR_PHY_GEN_CTRL          (AR_SM_BASE + 0x4)
00427 #define AR_PHY_MODE              (AR_SM_BASE + 0x8)
00428 #define AR_PHY_ACTIVE            (AR_SM_BASE + 0xc)
00429 #define AR_PHY_SPUR_MASK_A       (AR_SM_BASE + 0x20)
00430 #define AR_PHY_SPUR_MASK_B       (AR_SM_BASE + 0x24)
00431 #define AR_PHY_SPECTRAL_SCAN     (AR_SM_BASE + 0x28)
00432 #define AR_PHY_RADAR_BW_FILTER   (AR_SM_BASE + 0x2c)
00433 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
00434 #define AR_PHY_MAX_RX_LEN        (AR_SM_BASE + 0x34)
00435 #define AR_PHY_FRAME_CTL         (AR_SM_BASE + 0x38)
00436 #define AR_PHY_RFBUS_REQ         (AR_SM_BASE + 0x3c)
00437 #define AR_PHY_RFBUS_GRANT       (AR_SM_BASE + 0x40)
00438 #define AR_PHY_RIFS              (AR_SM_BASE + 0x44)
00439 #define AR_PHY_RX_CLR_DELAY      (AR_SM_BASE + 0x50)
00440 #define AR_PHY_RX_DELAY          (AR_SM_BASE + 0x54)
00441 
00442 #define AR_PHY_XPA_TIMING_CTL    (AR_SM_BASE + 0x64)
00443 #define AR_PHY_MISC_PA_CTL       (AR_SM_BASE + 0x80)
00444 #define AR_PHY_SWITCH_CHAIN_0    (AR_SM_BASE + 0x84)
00445 #define AR_PHY_SWITCH_COM        (AR_SM_BASE + 0x88)
00446 #define AR_PHY_SWITCH_COM_2      (AR_SM_BASE + 0x8c)
00447 #define AR_PHY_RX_CHAINMASK      (AR_SM_BASE + 0xa0)
00448 #define AR_PHY_CAL_CHAINMASK     (AR_SM_BASE + 0xc0)
00449 #define AR_PHY_CALMODE           (AR_SM_BASE + 0xc8)
00450 #define AR_PHY_FCAL_1            (AR_SM_BASE + 0xcc)
00451 #define AR_PHY_FCAL_2_0          (AR_SM_BASE + 0xd0)
00452 #define AR_PHY_DFT_TONE_CTL_0    (AR_SM_BASE + 0xd4)
00453 #define AR_PHY_CL_CAL_CTL        (AR_SM_BASE + 0xd8)
00454 #define AR_PHY_CL_TAB_0          (AR_SM_BASE + 0x100)
00455 #define AR_PHY_SYNTH_CONTROL     (AR_SM_BASE + 0x140)
00456 #define AR_PHY_ADDAC_CLK_SEL     (AR_SM_BASE + 0x144)
00457 #define AR_PHY_PLL_CTL           (AR_SM_BASE + 0x148)
00458 #define AR_PHY_ANALOG_SWAP       (AR_SM_BASE + 0x14c)
00459 #define AR_PHY_ADDAC_PARA_CTL    (AR_SM_BASE + 0x150)
00460 #define AR_PHY_XPA_CFG           (AR_SM_BASE + 0x158)
00461 
00462 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A           0x0001FC00
00463 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S         10
00464 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A                       0x3FF
00465 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S                     0
00466 
00467 #define AR_PHY_TEST              (AR_SM_BASE + 0x160)
00468 
00469 #define AR_PHY_TEST_BBB_OBS_SEL       0x780000
00470 #define AR_PHY_TEST_BBB_OBS_SEL_S     19
00471 
00472 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
00473 #define AR_PHY_TEST_RX_OBS_SEL_BIT5   (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
00474 
00475 #define AR_PHY_TEST_CHAIN_SEL      0xC0000000
00476 #define AR_PHY_TEST_CHAIN_SEL_S    30
00477 
00478 #define AR_PHY_TEST_CTL_STATUS   (AR_SM_BASE + 0x164)
00479 #define AR_PHY_TEST_CTL_TSTDAC_EN         0x1
00480 #define AR_PHY_TEST_CTL_TSTDAC_EN_S       0
00481 #define AR_PHY_TEST_CTL_TX_OBS_SEL        0x1C
00482 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S      2
00483 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL    0x60
00484 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S  5
00485 #define AR_PHY_TEST_CTL_TSTADC_EN         0x100
00486 #define AR_PHY_TEST_CTL_TSTADC_EN_S       8
00487 #define AR_PHY_TEST_CTL_RX_OBS_SEL        0x3C00
00488 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S      10
00489 
00490 
00491 #define AR_PHY_TSTDAC            (AR_SM_BASE + 0x168)
00492 
00493 #define AR_PHY_CHAN_STATUS       (AR_SM_BASE + 0x16c)
00494 
00495 #define AR_PHY_CHAN_INFO_MEMORY                         (AR_SM_BASE + 0x170)
00496 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ     0x00000008
00497 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S   3
00498 
00499 #define AR_PHY_CHNINFO_NOISEPWR  (AR_SM_BASE + 0x174)
00500 #define AR_PHY_CHNINFO_GAINDIFF  (AR_SM_BASE + 0x178)
00501 #define AR_PHY_CHNINFO_FINETIM   (AR_SM_BASE + 0x17c)
00502 #define AR_PHY_CHAN_INFO_GAIN_0  (AR_SM_BASE + 0x180)
00503 #define AR_PHY_SCRAMBLER_SEED    (AR_SM_BASE + 0x190)
00504 #define AR_PHY_CCK_TX_CTRL       (AR_SM_BASE + 0x194)
00505 
00506 #define AR_PHY_HEAVYCLIP_CTL     (AR_SM_BASE + 0x1a4)
00507 #define AR_PHY_HEAVYCLIP_20      (AR_SM_BASE + 0x1a8)
00508 #define AR_PHY_HEAVYCLIP_40      (AR_SM_BASE + 0x1ac)
00509 #define AR_PHY_ILLEGAL_TXRATE    (AR_SM_BASE + 0x1b0)
00510 
00511 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
00512 
00513 #define AR_PHY_PWRTX_MAX         (AR_SM_BASE + 0x1f0)
00514 #define AR_PHY_POWER_TX_SUB      (AR_SM_BASE + 0x1f4)
00515 
00516 #define AR_PHY_TPC_1                            (AR_SM_BASE + 0x1f8)
00517 #define AR_PHY_TPC_1_FORCED_DAC_GAIN            0x0000003e
00518 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S          1
00519 #define AR_PHY_TPC_1_FORCE_DAC_GAIN             0x00000001
00520 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S           0
00521 
00522 #define AR_PHY_TPC_4_B0                         (AR_SM_BASE + 0x204)
00523 #define AR_PHY_TPC_5_B0                         (AR_SM_BASE + 0x208)
00524 #define AR_PHY_TPC_6_B0                         (AR_SM_BASE + 0x20c)
00525 
00526 #define AR_PHY_TPC_11_B0                        (AR_SM_BASE + 0x220)
00527 #define AR_PHY_TPC_11_B1                        (AR_SM1_BASE + 0x220)
00528 #define AR_PHY_TPC_11_B2                        (AR_SM2_BASE + 0x220)
00529 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA           0x00ff0000
00530 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S         16
00531 
00532 #define AR_PHY_TPC_12                           (AR_SM_BASE + 0x224)
00533 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5      0x3e000000
00534 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S    25
00535 
00536 #define AR_PHY_TPC_18                           (AR_SM_BASE + 0x23c)
00537 #define AR_PHY_TPC_18_THERM_CAL_VALUE           0x000000ff
00538 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S         0
00539 #define AR_PHY_TPC_18_VOLT_CAL_VALUE            0x0000ff00
00540 #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S          8
00541 
00542 #define AR_PHY_TPC_19                           (AR_SM_BASE + 0x240)
00543 #define AR_PHY_TPC_19_ALPHA_VOLT                0x001f0000
00544 #define AR_PHY_TPC_19_ALPHA_VOLT_S              16
00545 #define AR_PHY_TPC_19_ALPHA_THERM               0xff
00546 #define AR_PHY_TPC_19_ALPHA_THERM_S             0
00547 
00548 #define AR_PHY_TX_FORCED_GAIN                           (AR_SM_BASE + 0x258)
00549 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN             0x00000001
00550 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S           0
00551 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN        0x0000000e
00552 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S      1
00553 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN        0x00000030
00554 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S      4
00555 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN          0x000003c0
00556 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S        6
00557 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA           0x00003c00
00558 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S         10
00559 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB           0x0003c000
00560 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S         14
00561 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC           0x003c0000
00562 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S         18
00563 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND           0x00c00000
00564 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S         22
00565 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL         0x01000000
00566 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S       24
00567 
00568 
00569 #define AR_PHY_PDADC_TAB_0       (AR_SM_BASE + 0x280)
00570 
00571 #define AR_PHY_TXGAIN_TABLE      (AR_SM_BASE + 0x300)
00572 
00573 #define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + AR_SREV_9485(ah) ? \
00574                                                  0x3c8 : 0x448)
00575 #define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + AR_SREV_9485(ah) ? \
00576                                                  0x3c4 : 0x440)
00577 #define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + AR_SREV_9485(ah) ? \
00578                                                  0x3f0 : 0x48c)
00579 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i)    (AR_SM_BASE + \
00580                                              (AR_SREV_9485(ah) ? \
00581                                               0x3d0 : 0x450) + ((_i) << 2))
00582 
00583 #define AR_PHY_WATCHDOG_STATUS      (AR_SM_BASE + 0x5c0)
00584 #define AR_PHY_WATCHDOG_CTL_1       (AR_SM_BASE + 0x5c4)
00585 #define AR_PHY_WATCHDOG_CTL_2       (AR_SM_BASE + 0x5c8)
00586 #define AR_PHY_WATCHDOG_CTL         (AR_SM_BASE + 0x5cc)
00587 #define AR_PHY_ONLY_WARMRESET       (AR_SM_BASE + 0x5d0)
00588 #define AR_PHY_ONLY_CTL             (AR_SM_BASE + 0x5d4)
00589 #define AR_PHY_ECO_CTRL             (AR_SM_BASE + 0x5dc)
00590 
00591 #define AR_PHY_BB_THERM_ADC_1                           (AR_SM_BASE + 0x248)
00592 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM                0x000000ff
00593 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S              0
00594 
00595 #define AR_PHY_BB_THERM_ADC_4                           (AR_SM_BASE + 0x254)
00596 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE        0x000000ff
00597 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S      0
00598 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE         0x0000ff00
00599 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S       8
00600 
00601 
00602 #define AR_PHY_65NM_CH0_SYNTH4      0x1608c
00603 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   0x00000002
00604 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
00605 #define AR_PHY_65NM_CH0_SYNTH7      0x16098
00606 #define AR_PHY_65NM_CH0_BIAS1       0x160c0
00607 #define AR_PHY_65NM_CH0_BIAS2       0x160c4
00608 #define AR_PHY_65NM_CH0_BIAS4       0x160cc
00609 #define AR_PHY_65NM_CH0_RXTX4       0x1610c
00610 #define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 : 0x1628c)
00611 
00612 #define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000
00613 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
00614 #define AR_PHY_65NM_CH0_THERM_START   0x20000000
00615 #define AR_PHY_65NM_CH0_THERM_START_S 29
00616 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT   0x0000ff00
00617 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
00618 
00619 #define AR_PHY_65NM_CH0_RXTX1       0x16100
00620 #define AR_PHY_65NM_CH0_RXTX2       0x16104
00621 #define AR_PHY_65NM_CH1_RXTX1       0x16500
00622 #define AR_PHY_65NM_CH1_RXTX2       0x16504
00623 #define AR_PHY_65NM_CH2_RXTX1       0x16900
00624 #define AR_PHY_65NM_CH2_RXTX2       0x16904
00625 
00626 #define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
00627 #define AR_CH0_TOP2_XPABIASLVL          0xf000
00628 #define AR_CH0_TOP2_XPABIASLVL_S        12
00629 
00630 #define AR_CH0_XTAL             (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
00631 #define AR_CH0_XTAL_CAPINDAC    0x7f000000
00632 #define AR_CH0_XTAL_CAPINDAC_S  24
00633 #define AR_CH0_XTAL_CAPOUTDAC   0x00fe0000
00634 #define AR_CH0_XTAL_CAPOUTDAC_S 17
00635 
00636 #define AR_PHY_PMU1             0x16c40
00637 #define AR_PHY_PMU1_PWD         0x1
00638 #define AR_PHY_PMU1_PWD_S       0
00639 
00640 #define AR_PHY_PMU2             0x16c44
00641 #define AR_PHY_PMU2_PGM         0x00200000
00642 #define AR_PHY_PMU2_PGM_S       21
00643 
00644 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT          0x00380000
00645 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S        19
00646 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT          0x00c00000
00647 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S        22
00648 #define AR_PHY_LNAGAIN_LONG_SHIFT               0xe0000000
00649 #define AR_PHY_LNAGAIN_LONG_SHIFT_S             29
00650 #define AR_PHY_MXRGAIN_LONG_SHIFT               0x03000000
00651 #define AR_PHY_MXRGAIN_LONG_SHIFT_S             24
00652 #define AR_PHY_VGAGAIN_LONG_SHIFT               0x1c000000
00653 #define AR_PHY_VGAGAIN_LONG_SHIFT_S             26
00654 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT            0x00000001
00655 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S          0
00656 #define AR_PHY_MANRXGAIN_LONG_SHIFT             0x00000002
00657 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S           1
00658 
00659 /*
00660  * SM Field Definitions
00661  */
00662 #define AR_PHY_CL_CAL_ENABLE          0x00000002
00663 #define AR_PHY_PARALLEL_CAL_ENABLE    0x00000001
00664 #define AR_PHY_TPCRG1_PD_CAL_ENABLE   0x00400000
00665 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
00666 
00667 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
00668 
00669 #define AR_PHY_FCAL20_CAP_STATUS_0    0x01f00000
00670 #define AR_PHY_FCAL20_CAP_STATUS_0_S  20
00671 
00672 #define AR_PHY_RFBUS_REQ_EN     0x00000001  /* request for RF bus */
00673 #define AR_PHY_RFBUS_GRANT_EN   0x00000001  /* RF bus granted */
00674 #define AR_PHY_GC_TURBO_MODE       0x00000001  /* set turbo mode bits */
00675 #define AR_PHY_GC_TURBO_SHORT      0x00000002  /* set short symbols to turbo mode setting */
00676 #define AR_PHY_GC_DYN2040_EN       0x00000004  /* enable dyn 20/40 mode */
00677 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008  /* dyn 20/40 - primary only */
00678 #define AR_PHY_GC_DYN2040_PRI_CH   0x00000010  /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
00679 #define AR_PHY_GC_DYN2040_PRI_CH_S 4
00680 #define AR_PHY_GC_DYN2040_EXT_CH   0x00000020  /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
00681 #define AR_PHY_GC_HT_EN            0x00000040  /* ht enable */
00682 #define AR_PHY_GC_SHORT_GI_40      0x00000080  /* allow short GI for HT 40 */
00683 #define AR_PHY_GC_WALSH            0x00000100  /* walsh spatial spreading for 2 chains,2 streams TX */
00684 #define AR_PHY_GC_SINGLE_HT_LTF1   0x00000200  /* single length (4us) 1st HT long training symbol */
00685 #define AR_PHY_GC_GF_DETECT_EN     0x00000400  /* enable Green Field detection. Only affects rx, not tx */
00686 #define AR_PHY_GC_ENABLE_DAC_FIFO  0x00000800  /* fifo between bb and dac */
00687 #define AR_PHY_RX_DELAY_DELAY      0x00003FFF  /* delay from wakeup to rx ena */
00688 
00689 #define AR_PHY_CALMODE_IQ           0x00000000
00690 #define AR_PHY_CALMODE_ADC_GAIN     0x00000001
00691 #define AR_PHY_CALMODE_ADC_DC_PER   0x00000002
00692 #define AR_PHY_CALMODE_ADC_DC_INIT  0x00000003
00693 #define AR_PHY_SWAP_ALT_CHAIN       0x00000040
00694 #define AR_PHY_MODE_OFDM            0x00000000
00695 #define AR_PHY_MODE_CCK             0x00000001
00696 #define AR_PHY_MODE_DYNAMIC         0x00000004
00697 #define AR_PHY_MODE_DYNAMIC_S       2
00698 #define AR_PHY_MODE_HALF            0x00000020
00699 #define AR_PHY_MODE_QUARTER         0x00000040
00700 #define AR_PHY_MAC_CLK_MODE         0x00000080
00701 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
00702 #define AR_PHY_MODE_SVD_HALF        0x00000200
00703 #define AR_PHY_ACTIVE_EN    0x00000001
00704 #define AR_PHY_ACTIVE_DIS   0x00000000
00705 #define AR_PHY_FORCE_XPA_CFG    0x000000001
00706 #define AR_PHY_FORCE_XPA_CFG_S  0
00707 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF    0xFF000000
00708 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S  24
00709 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF    0x00FF0000
00710 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S  16
00711 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON      0x0000FF00
00712 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S    8
00713 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON      0x000000FF
00714 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S    0
00715 #define AR_PHY_TX_END_TO_A2_RX_ON       0x00FF0000
00716 #define AR_PHY_TX_END_TO_A2_RX_ON_S     16
00717 #define AR_PHY_TX_END_DATA_START  0x000000FF
00718 #define AR_PHY_TX_END_DATA_START_S  0
00719 #define AR_PHY_TX_END_PA_ON       0x0000FF00
00720 #define AR_PHY_TX_END_PA_ON_S       8
00721 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP   0x0000000F
00722 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S     0
00723 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1    0x000003F0
00724 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S  4
00725 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2    0x0000FC00
00726 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S  10
00727 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3    0x003F0000
00728 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S  16
00729 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4    0x0FC00000
00730 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S  22
00731 #define AR_PHY_TPCRG1_NUM_PD_GAIN   0x0000c000
00732 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
00733 #define AR_PHY_TPCRG1_PD_GAIN_1    0x00030000
00734 #define AR_PHY_TPCRG1_PD_GAIN_1_S  16
00735 #define AR_PHY_TPCRG1_PD_GAIN_2    0x000C0000
00736 #define AR_PHY_TPCRG1_PD_GAIN_2_S  18
00737 #define AR_PHY_TPCRG1_PD_GAIN_3    0x00300000
00738 #define AR_PHY_TPCRG1_PD_GAIN_3_S  20
00739 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN   0x0000003e
00740 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
00741 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN    0x00000001
00742 #define AR_PHY_TXGAIN_FORCE               0x00000001
00743 #define AR_PHY_TXGAIN_FORCE_S             0
00744 #define AR_PHY_TXGAIN_FORCED_PADVGNRA     0x00003c00
00745 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S   10
00746 #define AR_PHY_TXGAIN_FORCED_PADVGNRB     0x0003c000
00747 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S   14
00748 #define AR_PHY_TXGAIN_FORCED_PADVGNRD     0x00c00000
00749 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S   22
00750 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN    0x000003c0
00751 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S  6
00752 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN  0x0000000e
00753 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
00754 
00755 #define AR_PHY_POWER_TX_RATE1   0x9934
00756 #define AR_PHY_POWER_TX_RATE2   0x9938
00757 #define AR_PHY_POWER_TX_RATE_MAX    0x993c
00758 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
00759 #define PHY_AGC_CLR             0x10000000
00760 #define RFSILENT_BB             0x00002000
00761 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK          0xFFF
00762 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT    0x800
00763 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT         320
00764 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK         0x0001
00765 #define AR_PHY_RX_DELAY_DELAY   0x00003FFF
00766 #define AR_PHY_CCK_TX_CTRL_JAPAN    0x00000010
00767 #define AR_PHY_SPECTRAL_SCAN_ENABLE         0x00000001
00768 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S       0
00769 #define AR_PHY_SPECTRAL_SCAN_ACTIVE         0x00000002
00770 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S       1
00771 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD     0x000000F0
00772 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S   4
00773 #define AR_PHY_SPECTRAL_SCAN_PERIOD         0x0000FF00
00774 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S       8
00775 #define AR_PHY_SPECTRAL_SCAN_COUNT          0x00FF0000
00776 #define AR_PHY_SPECTRAL_SCAN_COUNT_S        16
00777 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT   0x01000000
00778 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
00779 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR      0x00000004
00780 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
00781 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
00782 #define AR_PHY_TX_IQCAL_START_DO_CAL        0x00000001
00783 #define AR_PHY_TX_IQCAL_START_DO_CAL_S      0
00784 
00785 #define AR_PHY_TX_IQCAL_STATUS_FAILED    0x00000001
00786 #define AR_PHY_CALIBRATED_GAINS_0        0x3e
00787 #define AR_PHY_CALIBRATED_GAINS_0_S      1
00788 
00789 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE      0x00003fff
00790 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S    0
00791 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x0fffc000
00792 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    14
00793 
00794 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON          0x10000000
00795 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S        28
00796 
00797 /*
00798  * Channel 1 Register Map
00799  */
00800 #define AR_CHAN1_BASE   0xa800
00801 
00802 #define AR_PHY_EXT_CCA_1            (AR_CHAN1_BASE + 0x30)
00803 #define AR_PHY_TX_PHASE_RAMP_1      (AR_CHAN1_BASE + 0xd0)
00804 #define AR_PHY_ADC_GAIN_DC_CORR_1   (AR_CHAN1_BASE + 0xd4)
00805 
00806 #define AR_PHY_SPUR_REPORT_1        (AR_CHAN1_BASE + 0xa8)
00807 #define AR_PHY_CHAN_INFO_TAB_1      (AR_CHAN1_BASE + 0x300)
00808 #define AR_PHY_RX_IQCAL_CORR_B1     (AR_CHAN1_BASE + 0xdc)
00809 
00810 /*
00811  * Channel 1 Field Definitions
00812  */
00813 #define AR_PHY_CH1_EXT_MINCCA_PWR   0x01FF0000
00814 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
00815 
00816 /*
00817  * AGC 1 Register Map
00818  */
00819 #define AR_AGC1_BASE    0xae00
00820 
00821 #define AR_PHY_FORCEMAX_GAINS_1      (AR_AGC1_BASE + 0x4)
00822 #define AR_PHY_EXT_ATTEN_CTL_1       (AR_AGC1_BASE + 0x18)
00823 #define AR_PHY_CCA_1                 (AR_AGC1_BASE + 0x1c)
00824 #define AR_PHY_CCA_CTRL_1            (AR_AGC1_BASE + 0x20)
00825 #define AR_PHY_RSSI_1                (AR_AGC1_BASE + 0x180)
00826 #define AR_PHY_SPUR_CCK_REP_1        (AR_AGC1_BASE + 0x184)
00827 #define AR_PHY_RX_OCGAIN_2           (AR_AGC1_BASE + 0x200)
00828 
00829 /*
00830  * AGC 1 Field Definitions
00831  */
00832 #define AR_PHY_CH1_MINCCA_PWR   0x1FF00000
00833 #define AR_PHY_CH1_MINCCA_PWR_S 20
00834 
00835 /*
00836  * SM 1 Register Map
00837  */
00838 #define AR_SM1_BASE     0xb200
00839 
00840 #define AR_PHY_SWITCH_CHAIN_1    (AR_SM1_BASE + 0x84)
00841 #define AR_PHY_FCAL_2_1          (AR_SM1_BASE + 0xd0)
00842 #define AR_PHY_DFT_TONE_CTL_1    (AR_SM1_BASE + 0xd4)
00843 #define AR_PHY_CL_TAB_1          (AR_SM1_BASE + 0x100)
00844 #define AR_PHY_CHAN_INFO_GAIN_1  (AR_SM1_BASE + 0x180)
00845 #define AR_PHY_TPC_4_B1          (AR_SM1_BASE + 0x204)
00846 #define AR_PHY_TPC_5_B1          (AR_SM1_BASE + 0x208)
00847 #define AR_PHY_TPC_6_B1          (AR_SM1_BASE + 0x20c)
00848 #define AR_PHY_TPC_11_B1         (AR_SM1_BASE + 0x220)
00849 #define AR_PHY_PDADC_TAB_1       (AR_SM1_BASE + 0x240)
00850 #define AR_PHY_TX_IQCAL_STATUS_B1   (AR_SM1_BASE + 0x48c)
00851 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM_BASE + 0x450 + ((_i) << 2))
00852 
00853 /*
00854  * Channel 2 Register Map
00855  */
00856 #define AR_CHAN2_BASE   0xb800
00857 
00858 #define AR_PHY_EXT_CCA_2            (AR_CHAN2_BASE + 0x30)
00859 #define AR_PHY_TX_PHASE_RAMP_2      (AR_CHAN2_BASE + 0xd0)
00860 #define AR_PHY_ADC_GAIN_DC_CORR_2   (AR_CHAN2_BASE + 0xd4)
00861 
00862 #define AR_PHY_SPUR_REPORT_2        (AR_CHAN2_BASE + 0xa8)
00863 #define AR_PHY_CHAN_INFO_TAB_2      (AR_CHAN2_BASE + 0x300)
00864 #define AR_PHY_RX_IQCAL_CORR_B2     (AR_CHAN2_BASE + 0xdc)
00865 
00866 /*
00867  * Channel 2 Field Definitions
00868  */
00869 #define AR_PHY_CH2_EXT_MINCCA_PWR   0x01FF0000
00870 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
00871 /*
00872  * AGC 2 Register Map
00873  */
00874 #define AR_AGC2_BASE    0xbe00
00875 
00876 #define AR_PHY_FORCEMAX_GAINS_2      (AR_AGC2_BASE + 0x4)
00877 #define AR_PHY_EXT_ATTEN_CTL_2       (AR_AGC2_BASE + 0x18)
00878 #define AR_PHY_CCA_2                 (AR_AGC2_BASE + 0x1c)
00879 #define AR_PHY_CCA_CTRL_2            (AR_AGC2_BASE + 0x20)
00880 #define AR_PHY_RSSI_2                (AR_AGC2_BASE + 0x180)
00881 
00882 /*
00883  * AGC 2 Field Definitions
00884  */
00885 #define AR_PHY_CH2_MINCCA_PWR   0x1FF00000
00886 #define AR_PHY_CH2_MINCCA_PWR_S 20
00887 
00888 /*
00889  * SM 2 Register Map
00890  */
00891 #define AR_SM2_BASE     0xc200
00892 
00893 #define AR_PHY_SWITCH_CHAIN_2    (AR_SM2_BASE + 0x84)
00894 #define AR_PHY_FCAL_2_2          (AR_SM2_BASE + 0xd0)
00895 #define AR_PHY_DFT_TONE_CTL_2    (AR_SM2_BASE + 0xd4)
00896 #define AR_PHY_CL_TAB_2          (AR_SM2_BASE + 0x100)
00897 #define AR_PHY_CHAN_INFO_GAIN_2  (AR_SM2_BASE + 0x180)
00898 #define AR_PHY_TPC_4_B2          (AR_SM2_BASE + 0x204)
00899 #define AR_PHY_TPC_5_B2          (AR_SM2_BASE + 0x208)
00900 #define AR_PHY_TPC_6_B2          (AR_SM2_BASE + 0x20c)
00901 #define AR_PHY_TPC_11_B2         (AR_SM2_BASE + 0x220)
00902 #define AR_PHY_PDADC_TAB_2       (AR_SM2_BASE + 0x240)
00903 #define AR_PHY_TX_IQCAL_STATUS_B2   (AR_SM2_BASE + 0x48c)
00904 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i)    (AR_SM2_BASE + 0x450 + ((_i) << 2))
00905 
00906 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED    0x00000001
00907 
00908 /*
00909  * AGC 3 Register Map
00910  */
00911 #define AR_AGC3_BASE    0xce00
00912 
00913 #define AR_PHY_RSSI_3            (AR_AGC3_BASE + 0x180)
00914 
00915 /*
00916  * Misc helper defines
00917  */
00918 #define AR_PHY_CHAIN_OFFSET     (AR_CHAN1_BASE - AR_CHAN_BASE)
00919 
00920 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00921 #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
00922 #define AR_PHY_SWITCH_CHAIN(_i)     (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00923 #define AR_PHY_EXT_ATTEN_CTL(_i)    (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00924 
00925 #define AR_PHY_RXGAIN(_i)           (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00926 #define AR_PHY_TPCRG5(_i)           (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00927 #define AR_PHY_PDADC_TAB(_i)        (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00928 
00929 #define AR_PHY_CAL_MEAS_0(_i)       (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00930 #define AR_PHY_CAL_MEAS_1(_i)       (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00931 #define AR_PHY_CAL_MEAS_2(_i)       (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00932 #define AR_PHY_CAL_MEAS_3(_i)       (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
00933 #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
00934 #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
00935 #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
00936 #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
00937 
00938 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE    0x00000001
00939 #define AR_PHY_WATCHDOG_IDLE_ENABLE        0x00000002
00940 #define AR_PHY_WATCHDOG_IDLE_MASK          0xFFFF0000
00941 #define AR_PHY_WATCHDOG_NON_IDLE_MASK      0x0000FFFC
00942 
00943 #define AR_PHY_WATCHDOG_RST_ENABLE         0x00000002
00944 #define AR_PHY_WATCHDOG_IRQ_ENABLE         0x00000004
00945 #define AR_PHY_WATCHDOG_CNTL2_MASK         0xFFFFFFF9
00946 
00947 #define AR_PHY_WATCHDOG_INFO               0x00000007
00948 #define AR_PHY_WATCHDOG_INFO_S             0
00949 #define AR_PHY_WATCHDOG_DET_HANG           0x00000008
00950 #define AR_PHY_WATCHDOG_DET_HANG_S         3
00951 #define AR_PHY_WATCHDOG_RADAR_SM           0x000000F0
00952 #define AR_PHY_WATCHDOG_RADAR_SM_S         4
00953 #define AR_PHY_WATCHDOG_RX_OFDM_SM         0x00000F00
00954 #define AR_PHY_WATCHDOG_RX_OFDM_SM_S       8
00955 #define AR_PHY_WATCHDOG_RX_CCK_SM          0x0000F000
00956 #define AR_PHY_WATCHDOG_RX_CCK_SM_S        12
00957 #define AR_PHY_WATCHDOG_TX_OFDM_SM         0x000F0000
00958 #define AR_PHY_WATCHDOG_TX_OFDM_SM_S       16
00959 #define AR_PHY_WATCHDOG_TX_CCK_SM          0x00F00000
00960 #define AR_PHY_WATCHDOG_TX_CCK_SM_S        20
00961 #define AR_PHY_WATCHDOG_AGC_SM             0x0F000000
00962 #define AR_PHY_WATCHDOG_AGC_SM_S           24
00963 #define AR_PHY_WATCHDOG_SRCH_SM            0xF0000000
00964 #define AR_PHY_WATCHDOG_SRCH_SM_S          28
00965 
00966 #define AR_PHY_WATCHDOG_STATUS_CLR         0x00000008
00967 
00968 /*
00969  * PAPRD registers
00970  */
00971 #define AR_PHY_XPA_TIMING_CTL           (AR_SM_BASE + 0x64)
00972 
00973 #define AR_PHY_PAPRD_AM2AM              (AR_CHAN_BASE + 0xe4)
00974 #define AR_PHY_PAPRD_AM2AM_MASK         0x01ffffff
00975 #define AR_PHY_PAPRD_AM2AM_MASK_S       0
00976 
00977 #define AR_PHY_PAPRD_AM2PM              (AR_CHAN_BASE + 0xe8)
00978 #define AR_PHY_PAPRD_AM2PM_MASK         0x01ffffff
00979 #define AR_PHY_PAPRD_AM2PM_MASK_S       0
00980 
00981 #define AR_PHY_PAPRD_HT40               (AR_CHAN_BASE + 0xec)
00982 #define AR_PHY_PAPRD_HT40_MASK          0x01ffffff
00983 #define AR_PHY_PAPRD_HT40_MASK_S        0
00984 
00985 #define AR_PHY_PAPRD_CTRL0_B0                           (AR_CHAN_BASE + 0xf0)
00986 #define AR_PHY_PAPRD_CTRL0_B1                           (AR_CHAN1_BASE + 0xf0)
00987 #define AR_PHY_PAPRD_CTRL0_B2                           (AR_CHAN2_BASE + 0xf0)
00988 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE                 0x00000001
00989 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S               0
00990 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK        0x00000002
00991 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S      1
00992 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH              0xf8000000
00993 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S            27
00994 
00995 #define AR_PHY_PAPRD_CTRL1_B0                           (AR_CHAN_BASE + 0xf4)
00996 #define AR_PHY_PAPRD_CTRL1_B1                           (AR_CHAN1_BASE + 0xf4)
00997 #define AR_PHY_PAPRD_CTRL1_B2                           (AR_CHAN2_BASE + 0xf4)
00998 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA         0x00000001
00999 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S       0
01000 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE        0x00000002
01001 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S      1
01002 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE        0x00000004
01003 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S      2
01004 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL     0x000001f8
01005 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S   3
01006 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK      0x0001fe00
01007 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S    9
01008 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT         0x0ffe0000
01009 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S       17
01010 
01011 #define AR_PHY_PAPRD_TRAINER_CNTL1                              (AR_SM_BASE + \
01012                                                                  (AR_SREV_9485(ah) ? \
01013                                                                   0x580 : 0x490))
01014 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE     0x00000001
01015 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S   0
01016 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING       0x0000007e
01017 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S     1
01018 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE       0x00000100
01019 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S     8
01020 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE    0x00000200
01021 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S  9
01022 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE       0x00000400
01023 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S     10
01024 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE           0x00000800
01025 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S         11
01026 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP             0x0003f000
01027 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S           12
01028 
01029 #define AR_PHY_PAPRD_TRAINER_CNTL2                              (AR_SM_BASE + \
01030                                                                  (AR_SREV_9485(ah) ? \
01031                                                                   0x584 : 0x494))
01032 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN     0xFFFFFFFF
01033 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S   0
01034 
01035 #define AR_PHY_PAPRD_TRAINER_CNTL3                              (AR_SM_BASE + \
01036                                                                  (AR_SREV_9485(ah) ? \
01037                                                                   0x588 : 0x498))
01038 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE    0x0000003f
01039 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S  0
01040 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP          0x00000fc0
01041 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S        6
01042 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL    0x0001f000
01043 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S  12
01044 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES     0x000e0000
01045 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S   17
01046 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN     0x00f00000
01047 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S   20
01048 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN       0x0f000000
01049 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S     24
01050 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE     0x20000000
01051 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S   29
01052 
01053 #define AR_PHY_PAPRD_TRAINER_CNTL4                              (AR_SM_BASE + \
01054                                                                  (AR_SREV_9485(ah) ? \
01055                                                                   0x58c : 0x49c))
01056 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES   0x03ff0000
01057 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
01058 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA        0x0000f000
01059 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S      12
01060 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR            0x00000fff
01061 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S          0
01062 
01063 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0                        (AR_CHAN_BASE + 0x100)
01064 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0                        (AR_CHAN_BASE + 0x104)
01065 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0                        (AR_CHAN_BASE + 0x108)
01066 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0                        (AR_CHAN_BASE + 0x10c)
01067 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0                        (AR_CHAN_BASE + 0x110)
01068 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0                        (AR_CHAN_BASE + 0x114)
01069 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0                        (AR_CHAN_BASE + 0x118)
01070 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0                        (AR_CHAN_BASE + 0x11c)
01071 #define AR_PHY_PAPRD_PRE_POST_SCALING                           0x3FFFF
01072 #define AR_PHY_PAPRD_PRE_POST_SCALING_S                         0
01073 
01074 #define AR_PHY_PAPRD_TRAINER_STAT1                              (AR_SM_BASE + 0x4a0)
01075 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE             0x00000001
01076 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S           0
01077 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE       0x00000002
01078 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S     1
01079 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR               0x00000004
01080 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S             2
01081 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE           0x00000008
01082 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S         3
01083 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX            0x000001f0
01084 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S          4
01085 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR               0x0001fe00
01086 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S             9
01087 
01088 #define AR_PHY_PAPRD_TRAINER_STAT2                              (AR_SM_BASE + 0x4a4)
01089 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL               0x0000ffff
01090 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S             0
01091 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX             0x001f0000
01092 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S           16
01093 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX               0x00600000
01094 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S             21
01095 
01096 #define AR_PHY_PAPRD_TRAINER_STAT3                              (AR_SM_BASE + 0x4a8)
01097 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT      0x000fffff
01098 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S    0
01099 
01100 #define AR_PHY_PAPRD_MEM_TAB_B0                 (AR_CHAN_BASE + 0x120)
01101 #define AR_PHY_PAPRD_MEM_TAB_B1                 (AR_CHAN1_BASE + 0x120)
01102 #define AR_PHY_PAPRD_MEM_TAB_B2                 (AR_CHAN2_BASE + 0x120)
01103 
01104 #define AR_PHY_PA_GAIN123_B0                    (AR_CHAN_BASE + 0xf8)
01105 #define AR_PHY_PA_GAIN123_B1                    (AR_CHAN1_BASE + 0xf8)
01106 #define AR_PHY_PA_GAIN123_B2                    (AR_CHAN2_BASE + 0xf8)
01107 #define AR_PHY_PA_GAIN123_PA_GAIN1              0x3FF
01108 #define AR_PHY_PA_GAIN123_PA_GAIN1_S            0
01109 
01110 #define AR_PHY_POWERTX_RATE5                    (AR_SM_BASE + 0x1d0)
01111 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0      0x3F
01112 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S    0
01113 
01114 #define AR_PHY_POWERTX_RATE6                    (AR_SM_BASE + 0x1d4)
01115 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5      0x3F00
01116 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S    8
01117 
01118 #define AR_PHY_POWERTX_RATE8                    (AR_SM_BASE + 0x1dc)
01119 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5      0x3F00
01120 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S    8
01121 
01122 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
01123 
01124 #endif  /* AR9003_PHY_H */