iPXE
arch-arm.h
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00001 /******************************************************************************
00002  * arch-arm.h
00003  *
00004  * Guest OS interface to ARM Xen.
00005  *
00006  * Permission is hereby granted, free of charge, to any person obtaining a copy
00007  * of this software and associated documentation files (the "Software"), to
00008  * deal in the Software without restriction, including without limitation the
00009  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
00010  * sell copies of the Software, and to permit persons to whom the Software is
00011  * furnished to do so, subject to the following conditions:
00012  *
00013  * The above copyright notice and this permission notice shall be included in
00014  * all copies or substantial portions of the Software.
00015  *
00016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00019  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00020  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
00021  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
00022  * DEALINGS IN THE SOFTWARE.
00023  *
00024  * Copyright 2011 (C) Citrix Systems
00025  */
00026 
00027 #ifndef __XEN_PUBLIC_ARCH_ARM_H__
00028 #define __XEN_PUBLIC_ARCH_ARM_H__
00029 
00030 FILE_LICENCE ( MIT );
00031 
00032 /*
00033  * `incontents 50 arm_abi Hypercall Calling Convention
00034  *
00035  * A hypercall is issued using the ARM HVC instruction.
00036  *
00037  * A hypercall can take up to 5 arguments. These are passed in
00038  * registers, the first argument in x0/r0 (for arm64/arm32 guests
00039  * respectively irrespective of whether the underlying hypervisor is
00040  * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2,
00041  * the forth in x3/r3 and the fifth in x4/r4.
00042  *
00043  * The hypercall number is passed in r12 (arm) or x16 (arm64). In both
00044  * cases the relevant ARM procedure calling convention specifies this
00045  * is an inter-procedure-call scratch register (e.g. for use in linker
00046  * stubs). This use does not conflict with use during a hypercall.
00047  *
00048  * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG.
00049  *
00050  * The return value is in x0/r0.
00051  *
00052  * The hypercall will clobber x16/r12 and the argument registers used
00053  * by that hypercall (except r0 which is the return value) i.e. in
00054  * addition to x16/r12 a 2 argument hypercall will clobber x1/r1 and a
00055  * 4 argument hypercall will clobber x1/r1, x2/r2 and x3/r3.
00056  *
00057  * Parameter structs passed to hypercalls are laid out according to
00058  * the Procedure Call Standard for the ARM Architecture (AAPCS, AKA
00059  * EABI) and Procedure Call Standard for the ARM 64-bit Architecture
00060  * (AAPCS64). Where there is a conflict the 64-bit standard should be
00061  * used regardless of guest type. Structures which are passed as
00062  * hypercall arguments are always little endian.
00063  *
00064  * All memory which is shared with other entities in the system
00065  * (including the hypervisor and other guests) must reside in memory
00066  * which is mapped as Normal Inner-cacheable. This applies to:
00067  *  - hypercall arguments passed via a pointer to guest memory.
00068  *  - memory shared via the grant table mechanism (including PV I/O
00069  *    rings etc).
00070  *  - memory shared with the hypervisor (struct shared_info, struct
00071  *    vcpu_info, the grant table, etc).
00072  *
00073  * Any Inner cache allocation strategy (Write-Back, Write-Through etc)
00074  * is acceptable. There is no restriction on the Outer-cacheability.
00075  */
00076 
00077 /*
00078  * `incontents 55 arm_hcall Supported Hypercalls
00079  *
00080  * Xen on ARM makes extensive use of hardware facilities and therefore
00081  * only a subset of the potential hypercalls are required.
00082  *
00083  * Since ARM uses second stage paging any machine/physical addresses
00084  * passed to hypercalls are Guest Physical Addresses (Intermediate
00085  * Physical Addresses) unless otherwise noted.
00086  *
00087  * The following hypercalls (and sub operations) are supported on the
00088  * ARM platform. Other hypercalls should be considered
00089  * unavailable/unsupported.
00090  *
00091  *  HYPERVISOR_memory_op
00092  *   All generic sub-operations.
00093  *
00094  *   In addition the following arch specific sub-ops:
00095  *    * XENMEM_add_to_physmap
00096  *    * XENMEM_add_to_physmap_batch
00097  *
00098  *  HYPERVISOR_domctl
00099  *   All generic sub-operations, with the exception of:
00100  *    * XEN_DOMCTL_iomem_permission (not yet implemented)
00101  *    * XEN_DOMCTL_irq_permission (not yet implemented)
00102  *
00103  *  HYPERVISOR_sched_op
00104  *   All generic sub-operations, with the exception of:
00105  *    * SCHEDOP_block -- prefer wfi hardware instruction
00106  *
00107  *  HYPERVISOR_console_io
00108  *   All generic sub-operations
00109  *
00110  *  HYPERVISOR_xen_version
00111  *   All generic sub-operations
00112  *
00113  *  HYPERVISOR_event_channel_op
00114  *   All generic sub-operations
00115  *
00116  *  HYPERVISOR_physdev_op
00117  *   No sub-operations are currenty supported
00118  *
00119  *  HYPERVISOR_sysctl
00120  *   All generic sub-operations, with the exception of:
00121  *    * XEN_SYSCTL_page_offline_op
00122  *    * XEN_SYSCTL_get_pmstat
00123  *    * XEN_SYSCTL_pm_op
00124  *
00125  *  HYPERVISOR_hvm_op
00126  *   Exactly these sub-operations are supported:
00127  *    * HVMOP_set_param
00128  *    * HVMOP_get_param
00129  *
00130  *  HYPERVISOR_grant_table_op
00131  *   All generic sub-operations
00132  *
00133  *  HYPERVISOR_vcpu_op
00134  *   Exactly these sub-operations are supported:
00135  *    * VCPUOP_register_vcpu_info
00136  *    * VCPUOP_register_runstate_memory_area
00137  *
00138  *
00139  * Other notes on the ARM ABI:
00140  *
00141  * - struct start_info is not exported to ARM guests.
00142  *
00143  * - struct shared_info is mapped by ARM guests using the
00144  *   HYPERVISOR_memory_op sub-op XENMEM_add_to_physmap, passing
00145  *   XENMAPSPACE_shared_info as space parameter.
00146  *
00147  * - All the per-cpu struct vcpu_info are mapped by ARM guests using the
00148  *   HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0
00149  *   struct vcpu_info.
00150  *
00151  * - The grant table is mapped using the HYPERVISOR_memory_op sub-op
00152  *   XENMEM_add_to_physmap, passing XENMAPSPACE_grant_table as space
00153  *   parameter. The memory range specified under the Xen compatible
00154  *   hypervisor node on device tree can be used as target gpfn for the
00155  *   mapping.
00156  *
00157  * - Xenstore is initialized by using the two hvm_params
00158  *   HVM_PARAM_STORE_PFN and HVM_PARAM_STORE_EVTCHN. They can be read
00159  *   with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.
00160  *
00161  * - The paravirtualized console is initialized by using the two
00162  *   hvm_params HVM_PARAM_CONSOLE_PFN and HVM_PARAM_CONSOLE_EVTCHN. They
00163  *   can be read with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.
00164  *
00165  * - Event channel notifications are delivered using the percpu GIC
00166  *   interrupt specified under the Xen compatible hypervisor node on
00167  *   device tree.
00168  *
00169  * - The device tree Xen compatible node is fully described under Linux
00170  *   at Documentation/devicetree/bindings/arm/xen.txt.
00171  */
00172 
00173 #define XEN_HYPERCALL_TAG   0XEA1
00174 
00175 #define uint64_aligned_t uint64_t __attribute__((aligned(8)))
00176 
00177 #ifndef __ASSEMBLY__
00178 #define ___DEFINE_XEN_GUEST_HANDLE(name, type)                  \
00179     typedef union { type *p; unsigned long q; }                 \
00180         __guest_handle_ ## name;                                \
00181     typedef union { type *p; uint64_aligned_t q; }              \
00182         __guest_handle_64_ ## name;
00183 
00184 /*
00185  * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field
00186  * in a struct in memory. On ARM is always 8 bytes sizes and 8 bytes
00187  * aligned.
00188  * XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an
00189  * hypercall argument. It is 4 bytes on aarch and 8 bytes on aarch64.
00190  */
00191 #define __DEFINE_XEN_GUEST_HANDLE(name, type) \
00192     ___DEFINE_XEN_GUEST_HANDLE(name, type);   \
00193     ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type)
00194 #define DEFINE_XEN_GUEST_HANDLE(name)   __DEFINE_XEN_GUEST_HANDLE(name, name)
00195 #define __XEN_GUEST_HANDLE(name)        __guest_handle_64_ ## name
00196 #define XEN_GUEST_HANDLE(name)          __XEN_GUEST_HANDLE(name)
00197 /* this is going to be changed on 64 bit */
00198 #define XEN_GUEST_HANDLE_PARAM(name)    __guest_handle_ ## name
00199 #define set_xen_guest_handle_raw(hnd, val)                  \
00200     do {                                                    \
00201         typeof(&(hnd)) _sxghr_tmp = &(hnd);                 \
00202         _sxghr_tmp->q = 0;                                  \
00203         _sxghr_tmp->p = val;                                \
00204     } while ( 0 )
00205 #ifdef __XEN_TOOLS__
00206 #define get_xen_guest_handle(val, hnd)  do { val = (hnd).p; } while (0)
00207 #endif
00208 #define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
00209 
00210 #if defined(__GNUC__) && !defined(__STRICT_ANSI__)
00211 /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */
00212 # define __DECL_REG(n64, n32) union {          \
00213         uint64_t n64;                          \
00214         uint32_t n32;                          \
00215     }
00216 #else
00217 /* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */
00218 #define __DECL_REG(n64, n32) uint64_t n64
00219 #endif
00220 
00221 struct vcpu_guest_core_regs
00222 {
00223     /*         Aarch64       Aarch32 */
00224     __DECL_REG(x0,           r0_usr);
00225     __DECL_REG(x1,           r1_usr);
00226     __DECL_REG(x2,           r2_usr);
00227     __DECL_REG(x3,           r3_usr);
00228     __DECL_REG(x4,           r4_usr);
00229     __DECL_REG(x5,           r5_usr);
00230     __DECL_REG(x6,           r6_usr);
00231     __DECL_REG(x7,           r7_usr);
00232     __DECL_REG(x8,           r8_usr);
00233     __DECL_REG(x9,           r9_usr);
00234     __DECL_REG(x10,          r10_usr);
00235     __DECL_REG(x11,          r11_usr);
00236     __DECL_REG(x12,          r12_usr);
00237 
00238     __DECL_REG(x13,          sp_usr);
00239     __DECL_REG(x14,          lr_usr);
00240 
00241     __DECL_REG(x15,          __unused_sp_hyp);
00242 
00243     __DECL_REG(x16,          lr_irq);
00244     __DECL_REG(x17,          sp_irq);
00245 
00246     __DECL_REG(x18,          lr_svc);
00247     __DECL_REG(x19,          sp_svc);
00248 
00249     __DECL_REG(x20,          lr_abt);
00250     __DECL_REG(x21,          sp_abt);
00251 
00252     __DECL_REG(x22,          lr_und);
00253     __DECL_REG(x23,          sp_und);
00254 
00255     __DECL_REG(x24,          r8_fiq);
00256     __DECL_REG(x25,          r9_fiq);
00257     __DECL_REG(x26,          r10_fiq);
00258     __DECL_REG(x27,          r11_fiq);
00259     __DECL_REG(x28,          r12_fiq);
00260 
00261     __DECL_REG(x29,          sp_fiq);
00262     __DECL_REG(x30,          lr_fiq);
00263 
00264     /* Return address and mode */
00265     __DECL_REG(pc64,         pc32);             /* ELR_EL2 */
00266     uint32_t cpsr;                              /* SPSR_EL2 */
00267 
00268     union {
00269         uint32_t spsr_el1;       /* AArch64 */
00270         uint32_t spsr_svc;       /* AArch32 */
00271     };
00272 
00273     /* AArch32 guests only */
00274     uint32_t spsr_fiq, spsr_irq, spsr_und, spsr_abt;
00275 
00276     /* AArch64 guests only */
00277     uint64_t sp_el0;
00278     uint64_t sp_el1, elr_el1;
00279 };
00280 typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t;
00281 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t);
00282 
00283 #undef __DECL_REG
00284 
00285 typedef uint64_t xen_pfn_t;
00286 #define PRI_xen_pfn PRIx64
00287 
00288 /* Maximum number of virtual CPUs in legacy multi-processor guests. */
00289 /* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */
00290 #define XEN_LEGACY_MAX_VCPUS 1
00291 
00292 typedef uint64_t xen_ulong_t;
00293 #define PRI_xen_ulong PRIx64
00294 
00295 #if defined(__XEN__) || defined(__XEN_TOOLS__)
00296 struct vcpu_guest_context {
00297 #define _VGCF_online                   0
00298 #define VGCF_online                    (1<<_VGCF_online)
00299     uint32_t flags;                         /* VGCF_* */
00300 
00301     struct vcpu_guest_core_regs user_regs;  /* Core CPU registers */
00302 
00303     uint32_t sctlr;
00304     uint64_t ttbcr, ttbr0, ttbr1;
00305 };
00306 typedef struct vcpu_guest_context vcpu_guest_context_t;
00307 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
00308 #endif
00309 
00310 struct arch_vcpu_info {
00311 };
00312 typedef struct arch_vcpu_info arch_vcpu_info_t;
00313 
00314 struct arch_shared_info {
00315 };
00316 typedef struct arch_shared_info arch_shared_info_t;
00317 typedef uint64_t xen_callback_t;
00318 
00319 #endif
00320 
00321 #if defined(__XEN__) || defined(__XEN_TOOLS__)
00322 
00323 /* PSR bits (CPSR, SPSR)*/
00324 
00325 #define PSR_THUMB       (1<<5)        /* Thumb Mode enable */
00326 #define PSR_FIQ_MASK    (1<<6)        /* Fast Interrupt mask */
00327 #define PSR_IRQ_MASK    (1<<7)        /* Interrupt mask */
00328 #define PSR_ABT_MASK    (1<<8)        /* Asynchronous Abort mask */
00329 #define PSR_BIG_ENDIAN  (1<<9)        /* arm32: Big Endian Mode */
00330 #define PSR_DBG_MASK    (1<<9)        /* arm64: Debug Exception mask */
00331 #define PSR_IT_MASK     (0x0600fc00)  /* Thumb If-Then Mask */
00332 #define PSR_JAZELLE     (1<<24)       /* Jazelle Mode */
00333 
00334 /* 32 bit modes */
00335 #define PSR_MODE_USR 0x10
00336 #define PSR_MODE_FIQ 0x11
00337 #define PSR_MODE_IRQ 0x12
00338 #define PSR_MODE_SVC 0x13
00339 #define PSR_MODE_MON 0x16
00340 #define PSR_MODE_ABT 0x17
00341 #define PSR_MODE_HYP 0x1a
00342 #define PSR_MODE_UND 0x1b
00343 #define PSR_MODE_SYS 0x1f
00344 
00345 /* 64 bit modes */
00346 #define PSR_MODE_BIT  0x10 /* Set iff AArch32 */
00347 #define PSR_MODE_EL3h 0x0d
00348 #define PSR_MODE_EL3t 0x0c
00349 #define PSR_MODE_EL2h 0x09
00350 #define PSR_MODE_EL2t 0x08
00351 #define PSR_MODE_EL1h 0x05
00352 #define PSR_MODE_EL1t 0x04
00353 #define PSR_MODE_EL0t 0x00
00354 
00355 #define PSR_GUEST32_INIT  (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
00356 #define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
00357 
00358 #define SCTLR_GUEST_INIT    0x00c50078
00359 
00360 /*
00361  * Virtual machine platform (memory layout, interrupts)
00362  *
00363  * These are defined for consistency between the tools and the
00364  * hypervisor. Guests must not rely on these hardcoded values but
00365  * should instead use the FDT.
00366  */
00367 
00368 /* Physical Address Space */
00369 #define GUEST_GICD_BASE   0x03001000ULL
00370 #define GUEST_GICD_SIZE   0x00001000ULL
00371 #define GUEST_GICC_BASE   0x03002000ULL
00372 #define GUEST_GICC_SIZE   0x00000100ULL
00373 
00374 /* 16MB == 4096 pages reserved for guest to use as a region to map its
00375  * grant table in.
00376  */
00377 #define GUEST_GNTTAB_BASE 0x38000000ULL
00378 #define GUEST_GNTTAB_SIZE 0x01000000ULL
00379 
00380 #define GUEST_MAGIC_BASE  0x39000000ULL
00381 #define GUEST_MAGIC_SIZE  0x01000000ULL
00382 
00383 #define GUEST_RAM_BANKS   2
00384 
00385 #define GUEST_RAM0_BASE   0x40000000ULL /* 3GB of low RAM @ 1GB */
00386 #define GUEST_RAM0_SIZE   0xc0000000ULL
00387 
00388 #define GUEST_RAM1_BASE   0x0200000000ULL /* 1016GB of RAM @ 8GB */
00389 #define GUEST_RAM1_SIZE   0xfe00000000ULL
00390 
00391 #define GUEST_RAM_BASE    GUEST_RAM0_BASE /* Lowest RAM address */
00392 /* Largest amount of actual RAM, not including holes */
00393 #define GUEST_RAM_MAX     (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE)
00394 /* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */
00395 #define GUEST_RAM_BANK_BASES   { GUEST_RAM0_BASE, GUEST_RAM1_BASE }
00396 #define GUEST_RAM_BANK_SIZES   { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }
00397 
00398 /* Interrupts */
00399 #define GUEST_TIMER_VIRT_PPI    27
00400 #define GUEST_TIMER_PHYS_S_PPI  29
00401 #define GUEST_TIMER_PHYS_NS_PPI 30
00402 #define GUEST_EVTCHN_PPI        31
00403 
00404 /* PSCI functions */
00405 #define PSCI_cpu_suspend 0
00406 #define PSCI_cpu_off     1
00407 #define PSCI_cpu_on      2
00408 #define PSCI_migrate     3
00409 
00410 #endif
00411 
00412 #endif /*  __XEN_PUBLIC_ARCH_ARM_H__ */
00413 
00414 /*
00415  * Local variables:
00416  * mode: C
00417  * c-file-style: "BSD"
00418  * c-basic-offset: 4
00419  * tab-width: 4
00420  * indent-tabs-mode: nil
00421  * End:
00422  */