iPXE
eeprom.h
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00001 /*
00002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
00003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
00004  *
00005  * Permission to use, copy, modify, and distribute this software for any
00006  * purpose with or without fee is hereby granted, provided that the above
00007  * copyright notice and this permission notice appear in all copies.
00008  *
00009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00016  *
00017  */
00018 
00019 /*
00020  * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
00021  */
00022 #define AR5K_EEPROM_MAGIC               0x003d  /* EEPROM Magic number */
00023 #define AR5K_EEPROM_MAGIC_VALUE         0x5aa5  /* Default - found on EEPROM */
00024 #define AR5K_EEPROM_MAGIC_5212          0x0000145c /* 5212 */
00025 #define AR5K_EEPROM_MAGIC_5211          0x0000145b /* 5211 */
00026 #define AR5K_EEPROM_MAGIC_5210          0x0000145a /* 5210 */
00027 
00028 #define AR5K_EEPROM_IS_HB63             0x000b  /* Talon detect */
00029 
00030 #define AR5K_EEPROM_RFKILL              0x0f
00031 #define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
00032 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
00033 #define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
00034 #define AR5K_EEPROM_RFKILL_POLARITY_S   1
00035 
00036 #define AR5K_EEPROM_REG_DOMAIN          0x00bf  /* EEPROM regdom */
00037 #define AR5K_EEPROM_CHECKSUM            0x00c0  /* EEPROM checksum */
00038 #define AR5K_EEPROM_INFO_BASE           0x00c0  /* EEPROM header */
00039 #define AR5K_EEPROM_INFO_MAX            (0x400 - AR5K_EEPROM_INFO_BASE)
00040 #define AR5K_EEPROM_INFO_CKSUM          0xffff
00041 #define AR5K_EEPROM_INFO(_n)            (AR5K_EEPROM_INFO_BASE + (_n))
00042 
00043 #define AR5K_EEPROM_VERSION             AR5K_EEPROM_INFO(1)     /* EEPROM Version */
00044 #define AR5K_EEPROM_VERSION_3_0         0x3000  /* No idea what's going on before this version */
00045 #define AR5K_EEPROM_VERSION_3_1         0x3001  /* ob/db values for 2Ghz (ar5211_rfregs) */
00046 #define AR5K_EEPROM_VERSION_3_2         0x3002  /* different frequency representation (eeprom_bin2freq) */
00047 #define AR5K_EEPROM_VERSION_3_3         0x3003  /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
00048 #define AR5K_EEPROM_VERSION_3_4         0x3004  /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
00049 #define AR5K_EEPROM_VERSION_4_0         0x4000  /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
00050 #define AR5K_EEPROM_VERSION_4_1         0x4001  /* has ee_margin_tx_rx (eeprom_init) */
00051 #define AR5K_EEPROM_VERSION_4_2         0x4002  /* has ee_cck_ofdm_gain_delta (eeprom_init) */
00052 #define AR5K_EEPROM_VERSION_4_3         0x4003  /* power calibration changes */
00053 #define AR5K_EEPROM_VERSION_4_4         0x4004
00054 #define AR5K_EEPROM_VERSION_4_5         0x4005
00055 #define AR5K_EEPROM_VERSION_4_6         0x4006  /* has ee_scaled_cck_delta */
00056 #define AR5K_EEPROM_VERSION_4_7         0x3007  /* 4007 ? */
00057 #define AR5K_EEPROM_VERSION_4_9         0x4009  /* EAR futureproofing */
00058 #define AR5K_EEPROM_VERSION_5_0         0x5000  /* Has 2413 PDADC calibration etc */
00059 #define AR5K_EEPROM_VERSION_5_1         0x5001  /* Has capability values */
00060 #define AR5K_EEPROM_VERSION_5_3         0x5003  /* Has spur mitigation tables */
00061 
00062 #define AR5K_EEPROM_MODE_11A            0
00063 #define AR5K_EEPROM_MODE_11B            1
00064 #define AR5K_EEPROM_MODE_11G            2
00065 
00066 #define AR5K_EEPROM_HDR                 AR5K_EEPROM_INFO(2)     /* Header that contains the device caps */
00067 #define AR5K_EEPROM_HDR_11A(_v)         (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
00068 #define AR5K_EEPROM_HDR_11B(_v)         (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
00069 #define AR5K_EEPROM_HDR_11G(_v)         (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
00070 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)  (((_v) >> 3) & 0x1)     /* Disable turbo for 2Ghz (?) */
00071 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)  (((_v) >> 4) & 0x7f)    /* Max turbo power for a/XR mode (eeprom_init) */
00072 #define AR5K_EEPROM_HDR_DEVICE(_v)      (((_v) >> 11) & 0x7)
00073 #define AR5K_EEPROM_HDR_RFKILL(_v)      (((_v) >> 14) & 0x1)    /* Device has RFKill support */
00074 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)  (((_v) >> 15) & 0x1)    /* Disable turbo for 5Ghz */
00075 
00076 #define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
00077 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
00078 #define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
00079 #define AR5K_EEPROM_RFKILL_POLARITY_S   1
00080 
00081 /* Newer EEPROMs are using a different offset */
00082 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
00083         (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
00084 
00085 #define AR5K_EEPROM_ANT_GAIN(_v)        AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
00086 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)   ((s8)(((_v) >> 8) & 0xff))
00087 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)   ((s8)((_v) & 0xff))
00088 
00089 /* Misc values available since EEPROM 4.0 */
00090 #define AR5K_EEPROM_MISC0               AR5K_EEPROM_INFO(4)
00091 #define AR5K_EEPROM_EARSTART(_v)        ((_v) & 0xfff)
00092 #define AR5K_EEPROM_HDR_XR2_DIS(_v)     (((_v) >> 12) & 0x1)
00093 #define AR5K_EEPROM_HDR_XR5_DIS(_v)     (((_v) >> 13) & 0x1)
00094 #define AR5K_EEPROM_EEMAP(_v)           (((_v) >> 14) & 0x3)
00095 
00096 #define AR5K_EEPROM_MISC1                       AR5K_EEPROM_INFO(5)
00097 #define AR5K_EEPROM_TARGET_PWRSTART(_v)         ((_v) & 0xfff)
00098 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v)         (((_v) >> 14) & 0x1)
00099 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v)     (((_v) >> 15) & 0x1)
00100 
00101 #define AR5K_EEPROM_MISC2                       AR5K_EEPROM_INFO(6)
00102 #define AR5K_EEPROM_EEP_FILE_VERSION(_v)        (((_v) >> 8) & 0xff)
00103 #define AR5K_EEPROM_EAR_FILE_VERSION(_v)        ((_v) & 0xff)
00104 
00105 #define AR5K_EEPROM_MISC3               AR5K_EEPROM_INFO(7)
00106 #define AR5K_EEPROM_ART_BUILD_NUM(_v)   (((_v) >> 10) & 0x3f)
00107 #define AR5K_EEPROM_EAR_FILE_ID(_v)     ((_v) & 0xff)
00108 
00109 #define AR5K_EEPROM_MISC4               AR5K_EEPROM_INFO(8)
00110 #define AR5K_EEPROM_CAL_DATA_START(_v)  (((_v) >> 4) & 0xfff)
00111 #define AR5K_EEPROM_MASK_R0(_v)         (((_v) >> 2) & 0x3)
00112 #define AR5K_EEPROM_MASK_R1(_v)         ((_v) & 0x3)
00113 
00114 #define AR5K_EEPROM_MISC5               AR5K_EEPROM_INFO(9)
00115 #define AR5K_EEPROM_COMP_DIS(_v)        ((_v) & 0x1)
00116 #define AR5K_EEPROM_AES_DIS(_v)         (((_v) >> 1) & 0x1)
00117 #define AR5K_EEPROM_FF_DIS(_v)          (((_v) >> 2) & 0x1)
00118 #define AR5K_EEPROM_BURST_DIS(_v)       (((_v) >> 3) & 0x1)
00119 #define AR5K_EEPROM_MAX_QCU(_v)         (((_v) >> 4) & 0xf)
00120 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v)   (((_v) >> 8) & 0x1)
00121 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v)  (((_v) >> 12) & 0xf)
00122 
00123 #define AR5K_EEPROM_MISC6               AR5K_EEPROM_INFO(10)
00124 #define AR5K_EEPROM_TX_CHAIN_DIS        ((_v) & 0x8)
00125 #define AR5K_EEPROM_RX_CHAIN_DIS        (((_v) >> 3) & 0x8)
00126 #define AR5K_EEPROM_FCC_MID_EN          (((_v) >> 6) & 0x1)
00127 #define AR5K_EEPROM_JAP_U1EVEN_EN       (((_v) >> 7) & 0x1)
00128 #define AR5K_EEPROM_JAP_U2_EN           (((_v) >> 8) & 0x1)
00129 #define AR5K_EEPROM_JAP_U1ODD_EN        (((_v) >> 9) & 0x1)
00130 #define AR5K_EEPROM_JAP_11A_NEW_EN      (((_v) >> 10) & 0x1)
00131 
00132 /* calibration settings */
00133 #define AR5K_EEPROM_MODES_11A(_v)       AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
00134 #define AR5K_EEPROM_MODES_11B(_v)       AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
00135 #define AR5K_EEPROM_MODES_11G(_v)       AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
00136 #define AR5K_EEPROM_CTL(_v)             AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)     /* Conformance test limits */
00137 #define AR5K_EEPROM_GROUPS_START(_v)    AR5K_EEPROM_OFF(_v, 0x0100, 0x0150)     /* Start of Groups */
00138 #define AR5K_EEPROM_GROUP1_OFFSET       0x0
00139 #define AR5K_EEPROM_GROUP2_OFFSET       0x5
00140 #define AR5K_EEPROM_GROUP3_OFFSET       0x37
00141 #define AR5K_EEPROM_GROUP4_OFFSET       0x46
00142 #define AR5K_EEPROM_GROUP5_OFFSET       0x55
00143 #define AR5K_EEPROM_GROUP6_OFFSET       0x65
00144 #define AR5K_EEPROM_GROUP7_OFFSET       0x69
00145 #define AR5K_EEPROM_GROUP8_OFFSET       0x6f
00146 
00147 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
00148                                                                 AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
00149 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
00150                                                                 AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
00151 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
00152                                                                 AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
00153 
00154 /* [3.1 - 3.3] */
00155 #define AR5K_EEPROM_OBDB0_2GHZ          0x00ec
00156 #define AR5K_EEPROM_OBDB1_2GHZ          0x00ed
00157 
00158 #define AR5K_EEPROM_PROTECT             0x003f  /* EEPROM protect status */
00159 #define AR5K_EEPROM_PROTECT_RD_0_31     0x0001  /* Read protection bit for offsets 0x0 - 0x1f */
00160 #define AR5K_EEPROM_PROTECT_WR_0_31     0x0002  /* Write protection bit for offsets 0x0 - 0x1f */
00161 #define AR5K_EEPROM_PROTECT_RD_32_63    0x0004  /* 0x20 - 0x3f */
00162 #define AR5K_EEPROM_PROTECT_WR_32_63    0x0008
00163 #define AR5K_EEPROM_PROTECT_RD_64_127   0x0010  /* 0x40 - 0x7f */
00164 #define AR5K_EEPROM_PROTECT_WR_64_127   0x0020
00165 #define AR5K_EEPROM_PROTECT_RD_128_191  0x0040  /* 0x80 - 0xbf (regdom) */
00166 #define AR5K_EEPROM_PROTECT_WR_128_191  0x0080
00167 #define AR5K_EEPROM_PROTECT_RD_192_207  0x0100  /* 0xc0 - 0xcf */
00168 #define AR5K_EEPROM_PROTECT_WR_192_207  0x0200
00169 #define AR5K_EEPROM_PROTECT_RD_208_223  0x0400  /* 0xd0 - 0xdf */
00170 #define AR5K_EEPROM_PROTECT_WR_208_223  0x0800
00171 #define AR5K_EEPROM_PROTECT_RD_224_239  0x1000  /* 0xe0 - 0xef */
00172 #define AR5K_EEPROM_PROTECT_WR_224_239  0x2000
00173 #define AR5K_EEPROM_PROTECT_RD_240_255  0x4000  /* 0xf0 - 0xff */
00174 #define AR5K_EEPROM_PROTECT_WR_240_255  0x8000
00175 
00176 /* Some EEPROM defines */
00177 #define AR5K_EEPROM_EEP_SCALE           100
00178 #define AR5K_EEPROM_EEP_DELTA           10
00179 #define AR5K_EEPROM_N_MODES             3
00180 #define AR5K_EEPROM_N_5GHZ_CHAN         10
00181 #define AR5K_EEPROM_N_2GHZ_CHAN         3
00182 #define AR5K_EEPROM_N_2GHZ_CHAN_2413    4
00183 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX     4
00184 #define AR5K_EEPROM_MAX_CHAN            10
00185 #define AR5K_EEPROM_N_PWR_POINTS_5111   11
00186 #define AR5K_EEPROM_N_PCDAC             11
00187 #define AR5K_EEPROM_N_PHASE_CAL         5
00188 #define AR5K_EEPROM_N_TEST_FREQ         8
00189 #define AR5K_EEPROM_N_EDGES             8
00190 #define AR5K_EEPROM_N_INTERCEPTS        11
00191 #define AR5K_EEPROM_FREQ_M(_v)          AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
00192 #define AR5K_EEPROM_PCDAC_M             0x3f
00193 #define AR5K_EEPROM_PCDAC_START         1
00194 #define AR5K_EEPROM_PCDAC_STOP          63
00195 #define AR5K_EEPROM_PCDAC_STEP          1
00196 #define AR5K_EEPROM_NON_EDGE_M          0x40
00197 #define AR5K_EEPROM_CHANNEL_POWER       8
00198 #define AR5K_EEPROM_N_OBDB              4
00199 #define AR5K_EEPROM_OBDB_DIS            0xffff
00200 #define AR5K_EEPROM_CHANNEL_DIS         0xff
00201 #define AR5K_EEPROM_SCALE_OC_DELTA(_x)  (((_x) * 2) / 10)
00202 #define AR5K_EEPROM_N_CTLS(_v)          AR5K_EEPROM_OFF(_v, 16, 32)
00203 #define AR5K_EEPROM_MAX_CTLS            32
00204 #define AR5K_EEPROM_N_PD_CURVES         4
00205 #define AR5K_EEPROM_N_XPD0_POINTS       4
00206 #define AR5K_EEPROM_N_XPD3_POINTS       3
00207 #define AR5K_EEPROM_N_PD_GAINS          4
00208 #define AR5K_EEPROM_N_PD_POINTS         5
00209 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
00210 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
00211 #define AR5K_EEPROM_POWER_M             0x3f
00212 #define AR5K_EEPROM_POWER_MIN           0
00213 #define AR5K_EEPROM_POWER_MAX           3150
00214 #define AR5K_EEPROM_POWER_STEP          50
00215 #define AR5K_EEPROM_POWER_TABLE_SIZE    64
00216 #define AR5K_EEPROM_N_POWER_LOC_11B     4
00217 #define AR5K_EEPROM_N_POWER_LOC_11G     6
00218 #define AR5K_EEPROM_I_GAIN              10
00219 #define AR5K_EEPROM_CCK_OFDM_DELTA      15
00220 #define AR5K_EEPROM_N_IQ_CAL            2
00221 
00222 #define AR5K_EEPROM_READ(_o, _v) do {                   \
00223         ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
00224         if (ret)                                        \
00225                 return ret;                             \
00226 } while (0)
00227 
00228 #define AR5K_EEPROM_READ_HDR(_o, _v)                                    \
00229         AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v);        \
00230 
00231 enum ath5k_ant_setting {
00232         AR5K_ANT_VARIABLE       = 0,    /* variable by programming */
00233         AR5K_ANT_FIXED_A        = 1,    /* fixed to 11a frequencies */
00234         AR5K_ANT_FIXED_B        = 2,    /* fixed to 11b frequencies */
00235         AR5K_ANT_MAX            = 3,
00236 };
00237 
00238 enum ath5k_ctl_mode {
00239         AR5K_CTL_11A = 0,
00240         AR5K_CTL_11B = 1,
00241         AR5K_CTL_11G = 2,
00242         AR5K_CTL_TURBO = 3,
00243         AR5K_CTL_TURBOG = 4,
00244         AR5K_CTL_2GHT20 = 5,
00245         AR5K_CTL_5GHT20 = 6,
00246         AR5K_CTL_2GHT40 = 7,
00247         AR5K_CTL_5GHT40 = 8,
00248         AR5K_CTL_MODE_M = 15,
00249 };
00250 
00251 /* Default CTL ids for the 3 main reg domains.
00252  * Atheros only uses these by default but vendors
00253  * can have up to 32 different CTLs for different
00254  * scenarios. Note that theese values are ORed with
00255  * the mode id (above) so we can have up to 24 CTL
00256  * datasets out of these 3 main regdomains. That leaves
00257  * 8 ids that can be used by vendors and since 0x20 is
00258  * missing from HAL sources i guess this is the set of
00259  * custom CTLs vendors can use. */
00260 #define AR5K_CTL_FCC    0x10
00261 #define AR5K_CTL_CUSTOM 0x20
00262 #define AR5K_CTL_ETSI   0x30
00263 #define AR5K_CTL_MKK    0x40
00264 
00265 /* Indicates a CTL with only mode set and
00266  * no reg domain mapping, such CTLs are used
00267  * for world roaming domains or simply when
00268  * a reg domain is not set */
00269 #define AR5K_CTL_NO_REGDOMAIN   0xf0
00270 
00271 /* Indicates an empty (invalid) CTL */
00272 #define AR5K_CTL_NO_CTL         0xff
00273 
00274 /* Per channel calibration data, used for power table setup */
00275 struct ath5k_chan_pcal_info_rf5111 {
00276         /* Power levels in half dbm units
00277          * for one power curve. */
00278         u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
00279         /* PCDAC table steps
00280          * for the above values */
00281         u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
00282         /* Starting PCDAC step */
00283         u8 pcdac_min;
00284         /* Final PCDAC step */
00285         u8 pcdac_max;
00286 };
00287 
00288 struct ath5k_chan_pcal_info_rf5112 {
00289         /* Power levels in quarter dBm units
00290          * for lower (0) and higher (3)
00291          * level curves in 0.25dB units */
00292         s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
00293         s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
00294         /* PCDAC table steps
00295          * for the above values */
00296         u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
00297         u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
00298 };
00299 
00300 struct ath5k_chan_pcal_info_rf2413 {
00301         /* Starting pwr/pddac values */
00302         s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
00303         u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
00304         /* (pwr,pddac) points
00305          * power levels in 0.5dB units */
00306         s8 pwr[AR5K_EEPROM_N_PD_GAINS]
00307                 [AR5K_EEPROM_N_PD_POINTS];
00308         u8 pddac[AR5K_EEPROM_N_PD_GAINS]
00309                 [AR5K_EEPROM_N_PD_POINTS];
00310 };
00311 
00312 enum ath5k_powertable_type {
00313         AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
00314         AR5K_PWRTABLE_LINEAR_PCDAC = 1,
00315         AR5K_PWRTABLE_PWR_TO_PDADC = 2,
00316 };
00317 
00318 struct ath5k_pdgain_info {
00319         u8 pd_points;
00320         u8 *pd_step;
00321         /* Power values are in
00322          * 0.25dB units */
00323         s16 *pd_pwr;
00324 };
00325 
00326 struct ath5k_chan_pcal_info {
00327         /* Frequency */
00328         u16     freq;
00329         /* Tx power boundaries */
00330         s16     max_pwr;
00331         s16     min_pwr;
00332         union {
00333                 struct ath5k_chan_pcal_info_rf5111 rf5111_info;
00334                 struct ath5k_chan_pcal_info_rf5112 rf5112_info;
00335                 struct ath5k_chan_pcal_info_rf2413 rf2413_info;
00336         };
00337         /* Raw values used by phy code
00338          * Curves are stored in order from lower
00339          * gain to higher gain (max txpower -> min txpower) */
00340         struct ath5k_pdgain_info *pd_curves;
00341 };
00342 
00343 /* Per rate calibration data for each mode,
00344  * used for rate power table setup.
00345  * Note: Values in 0.5dB units */
00346 struct ath5k_rate_pcal_info {
00347         u16     freq; /* Frequency */
00348         /* Power level for 6-24Mbit/s rates or
00349          * 1Mb rate */
00350         u16     target_power_6to24;
00351         /* Power level for 36Mbit rate or
00352          * 2Mb rate */
00353         u16     target_power_36;
00354         /* Power level for 48Mbit rate or
00355          * 5.5Mbit rate */
00356         u16     target_power_48;
00357         /* Power level for 54Mbit rate or
00358          * 11Mbit rate */
00359         u16     target_power_54;
00360 };
00361 
00362 /* Power edges for conformance test limits */
00363 struct ath5k_edge_power {
00364         u16 freq;
00365         u16 edge; /* in half dBm */
00366         int flag;
00367 };
00368 
00369 /* EEPROM calibration data */
00370 struct ath5k_eeprom_info {
00371 
00372         /* Header information */
00373         u16     ee_magic;
00374         u16     ee_protect;
00375         u16     ee_regdomain;
00376         u16     ee_version;
00377         u16     ee_header;
00378         u16     ee_ant_gain;
00379         u8      ee_rfkill_pin;
00380         int     ee_rfkill_pol;
00381         int     ee_is_hb63;
00382         u16     ee_misc0;
00383         u16     ee_misc1;
00384         u16     ee_misc2;
00385         u16     ee_misc3;
00386         u16     ee_misc4;
00387         u16     ee_misc5;
00388         u16     ee_misc6;
00389         u16     ee_cck_ofdm_gain_delta;
00390         u16     ee_cck_ofdm_power_delta;
00391         u16     ee_scaled_cck_delta;
00392 
00393         /* RF Calibration settings (reset, rfregs) */
00394         u16     ee_i_cal[AR5K_EEPROM_N_MODES];
00395         u16     ee_q_cal[AR5K_EEPROM_N_MODES];
00396         u16     ee_fixed_bias[AR5K_EEPROM_N_MODES];
00397         u16     ee_turbo_max_power[AR5K_EEPROM_N_MODES];
00398         u16     ee_xr_power[AR5K_EEPROM_N_MODES];
00399         u16     ee_switch_settling[AR5K_EEPROM_N_MODES];
00400         u16     ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
00401         u16     ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
00402         u16     ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
00403         u16     ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
00404         u16     ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
00405         u16     ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
00406         u16     ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
00407         u16     ee_thr_62[AR5K_EEPROM_N_MODES];
00408         u16     ee_xlna_gain[AR5K_EEPROM_N_MODES];
00409         u16     ee_xpd[AR5K_EEPROM_N_MODES];
00410         u16     ee_x_gain[AR5K_EEPROM_N_MODES];
00411         u16     ee_i_gain[AR5K_EEPROM_N_MODES];
00412         u16     ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
00413         u16     ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
00414         u16     ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
00415         u16     ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
00416 
00417         /* Power calibration data */
00418         u16     ee_false_detect[AR5K_EEPROM_N_MODES];
00419 
00420         /* Number of pd gain curves per mode */
00421         u8      ee_pd_gains[AR5K_EEPROM_N_MODES];
00422         /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */
00423         u8      ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
00424 
00425         u8      ee_n_piers[AR5K_EEPROM_N_MODES];
00426         struct ath5k_chan_pcal_info     ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
00427         struct ath5k_chan_pcal_info     ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00428         struct ath5k_chan_pcal_info     ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00429 
00430         /* Per rate target power levels */
00431         u8      ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
00432         struct ath5k_rate_pcal_info     ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
00433         struct ath5k_rate_pcal_info     ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00434         struct ath5k_rate_pcal_info     ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00435 
00436         /* Conformance test limits (Unused) */
00437         u8      ee_ctls;
00438         u8      ee_ctl[AR5K_EEPROM_MAX_CTLS];
00439         struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
00440 
00441         /* Noise Floor Calibration settings */
00442         s16     ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
00443         s8      ee_adc_desired_size[AR5K_EEPROM_N_MODES];
00444         s8      ee_pga_desired_size[AR5K_EEPROM_N_MODES];
00445         s8      ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
00446         s8      ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
00447         s8      ee_pd_gain_overlap;
00448 
00449         u32     ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
00450 };
00451