iPXE
reg.h
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00001 /*
00002  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
00003  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
00004  * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
00005  *
00006  * Permission to use, copy, modify, and distribute this software for any
00007  * purpose with or without fee is hereby granted, provided that the above
00008  * copyright notice and this permission notice appear in all copies.
00009  *
00010  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00011  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00012  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00013  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00014  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00015  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00016  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00017  *
00018  */
00019 
00020 /*
00021  * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
00022  * maintained by Reyk Floeter
00023  *
00024  * I tried to document those registers by looking at ar5k code, some
00025  * 802.11 (802.11e mostly) papers and by reading various public available
00026  * Atheros presentations and papers like these:
00027  *
00028  * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
00029  *        http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf
00030  *
00031  * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
00032  *
00033  * This file also contains register values found on a memory dump of
00034  * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
00035  * released by Atheros and on various debug messages found on the net.
00036  */
00037 
00038 
00039 
00040 /*====MAC DMA REGISTERS====*/
00041 
00042 /*
00043  * AR5210-Specific TXDP registers
00044  * 5210 has only 2 transmit queues so no DCU/QCU, just
00045  * 2 transmit descriptor pointers...
00046  */
00047 #define AR5K_NOQCU_TXDP0        0x0000          /* Queue 0 - data */
00048 #define AR5K_NOQCU_TXDP1        0x0004          /* Queue 1 - beacons */
00049 
00050 /*
00051  * Mac Control Register
00052  */
00053 #define AR5K_CR         0x0008                  /* Register Address */
00054 #define AR5K_CR_TXE0    0x00000001      /* TX Enable for queue 0 on 5210 */
00055 #define AR5K_CR_TXE1    0x00000002      /* TX Enable for queue 1 on 5210 */
00056 #define AR5K_CR_RXE     0x00000004      /* RX Enable */
00057 #define AR5K_CR_TXD0    0x00000008      /* TX Disable for queue 0 on 5210 */
00058 #define AR5K_CR_TXD1    0x00000010      /* TX Disable for queue 1 on 5210 */
00059 #define AR5K_CR_RXD     0x00000020      /* RX Disable */
00060 #define AR5K_CR_SWI     0x00000040      /* Software Interrupt */
00061 
00062 /*
00063  * RX Descriptor Pointer register
00064  */
00065 #define AR5K_RXDP       0x000c
00066 
00067 /*
00068  * Configuration and status register
00069  */
00070 #define AR5K_CFG                0x0014                  /* Register Address */
00071 #define AR5K_CFG_SWTD           0x00000001      /* Byte-swap TX descriptor (for big endian archs) */
00072 #define AR5K_CFG_SWTB           0x00000002      /* Byte-swap TX buffer */
00073 #define AR5K_CFG_SWRD           0x00000004      /* Byte-swap RX descriptor */
00074 #define AR5K_CFG_SWRB           0x00000008      /* Byte-swap RX buffer */
00075 #define AR5K_CFG_SWRG           0x00000010      /* Byte-swap Register access */
00076 #define AR5K_CFG_IBSS           0x00000020      /* 0-BSS, 1-IBSS [5211+] */
00077 #define AR5K_CFG_PHY_OK         0x00000100      /* [5211+] */
00078 #define AR5K_CFG_EEBS           0x00000200      /* EEPROM is busy */
00079 #define AR5K_CFG_CLKGD          0x00000400      /* Clock gated (Disable dynamic clock) */
00080 #define AR5K_CFG_TXCNT          0x00007800      /* Tx frame count (?) [5210] */
00081 #define AR5K_CFG_TXCNT_S        11
00082 #define AR5K_CFG_TXFSTAT        0x00008000      /* Tx frame status (?) [5210] */
00083 #define AR5K_CFG_TXFSTRT        0x00010000      /* [5210] */
00084 #define AR5K_CFG_PCI_THRES      0x00060000      /* PCI Master req q threshold [5211+] */
00085 #define AR5K_CFG_PCI_THRES_S    17
00086 
00087 /*
00088  * Interrupt enable register
00089  */
00090 #define AR5K_IER                0x0024          /* Register Address */
00091 #define AR5K_IER_DISABLE        0x00000000      /* Disable card interrupts */
00092 #define AR5K_IER_ENABLE         0x00000001      /* Enable card interrupts */
00093 
00094 
00095 /*
00096  * 0x0028 is Beacon Control Register on 5210
00097  * and first RTS duration register on 5211
00098  */
00099 
00100 /*
00101  * Beacon control register [5210]
00102  */
00103 #define AR5K_BCR                0x0028          /* Register Address */
00104 #define AR5K_BCR_AP             0x00000000      /* AP mode */
00105 #define AR5K_BCR_ADHOC          0x00000001      /* Ad-Hoc mode */
00106 #define AR5K_BCR_BDMAE          0x00000002      /* DMA enable */
00107 #define AR5K_BCR_TQ1FV          0x00000004      /* Use Queue1 for CAB traffic */
00108 #define AR5K_BCR_TQ1V           0x00000008      /* Use Queue1 for Beacon traffic */
00109 #define AR5K_BCR_BCGET          0x00000010
00110 
00111 /*
00112  * First RTS duration register [5211]
00113  */
00114 #define AR5K_RTSD0              0x0028          /* Register Address */
00115 #define AR5K_RTSD0_6            0x000000ff      /* 6Mb RTS duration mask (?) */
00116 #define AR5K_RTSD0_6_S          0               /* 6Mb RTS duration shift (?) */
00117 #define AR5K_RTSD0_9            0x0000ff00      /* 9Mb*/
00118 #define AR5K_RTSD0_9_S          8
00119 #define AR5K_RTSD0_12           0x00ff0000      /* 12Mb*/
00120 #define AR5K_RTSD0_12_S         16
00121 #define AR5K_RTSD0_18           0xff000000      /* 16Mb*/
00122 #define AR5K_RTSD0_18_S         24
00123 
00124 
00125 /*
00126  * 0x002c is Beacon Status Register on 5210
00127  * and second RTS duration register on 5211
00128  */
00129 
00130 /*
00131  * Beacon status register [5210]
00132  *
00133  * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
00134  * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
00135  * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
00136  * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i
00137  * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what
00138  * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
00139  */
00140 #define AR5K_BSR                0x002c                  /* Register Address */
00141 #define AR5K_BSR_BDLYSW         0x00000001      /* SW Beacon delay (?) */
00142 #define AR5K_BSR_BDLYDMA        0x00000002      /* DMA Beacon delay (?) */
00143 #define AR5K_BSR_TXQ1F          0x00000004      /* Beacon queue (1) finished */
00144 #define AR5K_BSR_ATIMDLY        0x00000008      /* ATIM delay (?) */
00145 #define AR5K_BSR_SNPADHOC       0x00000100      /* Ad-hoc mode set (?) */
00146 #define AR5K_BSR_SNPBDMAE       0x00000200      /* Beacon DMA enabled (?) */
00147 #define AR5K_BSR_SNPTQ1FV       0x00000400      /* Queue1 is used for CAB traffic (?) */
00148 #define AR5K_BSR_SNPTQ1V        0x00000800      /* Queue1 is used for Beacon traffic (?) */
00149 #define AR5K_BSR_SNAPSHOTSVALID 0x00001000      /* BCR snapshots are valid (?) */
00150 #define AR5K_BSR_SWBA_CNT       0x00ff0000
00151 
00152 /*
00153  * Second RTS duration register [5211]
00154  */
00155 #define AR5K_RTSD1              0x002c                  /* Register Address */
00156 #define AR5K_RTSD1_24           0x000000ff      /* 24Mb */
00157 #define AR5K_RTSD1_24_S         0
00158 #define AR5K_RTSD1_36           0x0000ff00      /* 36Mb */
00159 #define AR5K_RTSD1_36_S         8
00160 #define AR5K_RTSD1_48           0x00ff0000      /* 48Mb */
00161 #define AR5K_RTSD1_48_S         16
00162 #define AR5K_RTSD1_54           0xff000000      /* 54Mb */
00163 #define AR5K_RTSD1_54_S         24
00164 
00165 
00166 /*
00167  * Transmit configuration register
00168  */
00169 #define AR5K_TXCFG                      0x0030                  /* Register Address */
00170 #define AR5K_TXCFG_SDMAMR               0x00000007      /* DMA size (read) */
00171 #define AR5K_TXCFG_SDMAMR_S             0
00172 #define AR5K_TXCFG_B_MODE               0x00000008      /* Set b mode for 5111 (enable 2111) */
00173 #define AR5K_TXCFG_TXFSTP               0x00000008      /* TX DMA full Stop [5210] */
00174 #define AR5K_TXCFG_TXFULL               0x000003f0      /* TX Triger level mask */
00175 #define AR5K_TXCFG_TXFULL_S             4
00176 #define AR5K_TXCFG_TXFULL_0B            0x00000000
00177 #define AR5K_TXCFG_TXFULL_64B           0x00000010
00178 #define AR5K_TXCFG_TXFULL_128B          0x00000020
00179 #define AR5K_TXCFG_TXFULL_192B          0x00000030
00180 #define AR5K_TXCFG_TXFULL_256B          0x00000040
00181 #define AR5K_TXCFG_TXCONT_EN            0x00000080
00182 #define AR5K_TXCFG_DMASIZE              0x00000100      /* Flag for passing DMA size [5210] */
00183 #define AR5K_TXCFG_JUMBO_DESC_EN        0x00000400      /* Enable jumbo tx descriptors [5211+] */
00184 #define AR5K_TXCFG_ADHOC_BCN_ATIM       0x00000800      /* Adhoc Beacon ATIM Policy */
00185 #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS  0x00001000      /* Disable ATIM window defer [5211+] */
00186 #define AR5K_TXCFG_RTSRND               0x00001000      /* [5211+] */
00187 #define AR5K_TXCFG_FRMPAD_DIS           0x00002000      /* [5211+] */
00188 #define AR5K_TXCFG_RDY_CBR_DIS          0x00004000      /* Ready time CBR disable [5211+] */
00189 #define AR5K_TXCFG_JUMBO_FRM_MODE       0x00008000      /* Jumbo frame mode [5211+] */
00190 #define AR5K_TXCFG_DCU_DBL_BUF_DIS      0x00008000      /* Disable double buffering on DCU */
00191 #define AR5K_TXCFG_DCU_CACHING_DIS      0x00010000      /* Disable DCU caching */
00192 
00193 /*
00194  * Receive configuration register
00195  */
00196 #define AR5K_RXCFG              0x0034                  /* Register Address */
00197 #define AR5K_RXCFG_SDMAMW       0x00000007      /* DMA size (write) */
00198 #define AR5K_RXCFG_SDMAMW_S     0
00199 #define AR5K_RXCFG_ZLFDMA       0x00000008      /* Enable Zero-length frame DMA */
00200 #define AR5K_RXCFG_DEF_ANTENNA  0x00000010      /* Default antenna (?) */
00201 #define AR5K_RXCFG_JUMBO_RXE    0x00000020      /* Enable jumbo rx descriptors [5211+] */
00202 #define AR5K_RXCFG_JUMBO_WRAP   0x00000040      /* Wrap jumbo frames [5211+] */
00203 #define AR5K_RXCFG_SLE_ENTRY    0x00000080      /* Sleep entry policy */
00204 
00205 /*
00206  * Receive jumbo descriptor last address register
00207  * Only found in 5211 (?)
00208  */
00209 #define AR5K_RXJLA              0x0038
00210 
00211 /*
00212  * MIB control register
00213  */
00214 #define AR5K_MIBC               0x0040                  /* Register Address */
00215 #define AR5K_MIBC_COW           0x00000001      /* Warn test indicator */
00216 #define AR5K_MIBC_FMC           0x00000002      /* Freeze MIB Counters  */
00217 #define AR5K_MIBC_CMC           0x00000004      /* Clean MIB Counters  */
00218 #define AR5K_MIBC_MCS           0x00000008      /* MIB counter strobe */
00219 
00220 /*
00221  * Timeout prescale register
00222  */
00223 #define AR5K_TOPS               0x0044
00224 #define AR5K_TOPS_M             0x0000ffff
00225 
00226 /*
00227  * Receive timeout register (no frame received)
00228  */
00229 #define AR5K_RXNOFRM            0x0048
00230 #define AR5K_RXNOFRM_M          0x000003ff
00231 
00232 /*
00233  * Transmit timeout register (no frame sent)
00234  */
00235 #define AR5K_TXNOFRM            0x004c
00236 #define AR5K_TXNOFRM_M          0x000003ff
00237 #define AR5K_TXNOFRM_QCU        0x000ffc00
00238 #define AR5K_TXNOFRM_QCU_S      10
00239 
00240 /*
00241  * Receive frame gap timeout register
00242  */
00243 #define AR5K_RPGTO              0x0050
00244 #define AR5K_RPGTO_M            0x000003ff
00245 
00246 /*
00247  * Receive frame count limit register
00248  */
00249 #define AR5K_RFCNT              0x0054
00250 #define AR5K_RFCNT_M            0x0000001f      /* [5211+] (?) */
00251 #define AR5K_RFCNT_RFCL         0x0000000f      /* [5210] */
00252 
00253 /*
00254  * Misc settings register
00255  * (reserved0-3)
00256  */
00257 #define AR5K_MISC               0x0058                  /* Register Address */
00258 #define AR5K_MISC_DMA_OBS_M     0x000001e0
00259 #define AR5K_MISC_DMA_OBS_S     5
00260 #define AR5K_MISC_MISC_OBS_M    0x00000e00
00261 #define AR5K_MISC_MISC_OBS_S    9
00262 #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
00263 #define AR5K_MISC_MAC_OBS_LSB_S 12
00264 #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
00265 #define AR5K_MISC_MAC_OBS_MSB_S 15
00266 #define AR5K_MISC_LED_DECAY     0x001c0000      /* [5210] */
00267 #define AR5K_MISC_LED_BLINK     0x00e00000      /* [5210] */
00268 
00269 /*
00270  * QCU/DCU clock gating register (5311)
00271  * (reserved4-5)
00272  */
00273 #define AR5K_QCUDCU_CLKGT       0x005c                  /* Register Address (?) */
00274 #define AR5K_QCUDCU_CLKGT_QCU   0x0000ffff      /* Mask for QCU clock */
00275 #define AR5K_QCUDCU_CLKGT_DCU   0x07ff0000      /* Mask for DCU clock */
00276 
00277 /*
00278  * Interrupt Status Registers
00279  *
00280  * For 5210 there is only one status register but for
00281  * 5211/5212 we have one primary and 4 secondary registers.
00282  * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
00283  * Most of these bits are common for all chipsets.
00284  */
00285 #define AR5K_ISR                0x001c                  /* Register Address [5210] */
00286 #define AR5K_PISR               0x0080                  /* Register Address [5211+] */
00287 #define AR5K_ISR_RXOK           0x00000001      /* Frame successfuly recieved */
00288 #define AR5K_ISR_RXDESC         0x00000002      /* RX descriptor request */
00289 #define AR5K_ISR_RXERR          0x00000004      /* Receive error */
00290 #define AR5K_ISR_RXNOFRM        0x00000008      /* No frame received (receive timeout) */
00291 #define AR5K_ISR_RXEOL          0x00000010      /* Empty RX descriptor */
00292 #define AR5K_ISR_RXORN          0x00000020      /* Receive FIFO overrun */
00293 #define AR5K_ISR_TXOK           0x00000040      /* Frame successfuly transmited */
00294 #define AR5K_ISR_TXDESC         0x00000080      /* TX descriptor request */
00295 #define AR5K_ISR_TXERR          0x00000100      /* Transmit error */
00296 #define AR5K_ISR_TXNOFRM        0x00000200      /* No frame transmited (transmit timeout) */
00297 #define AR5K_ISR_TXEOL          0x00000400      /* Empty TX descriptor */
00298 #define AR5K_ISR_TXURN          0x00000800      /* Transmit FIFO underrun */
00299 #define AR5K_ISR_MIB            0x00001000      /* Update MIB counters */
00300 #define AR5K_ISR_SWI            0x00002000      /* Software interrupt */
00301 #define AR5K_ISR_RXPHY          0x00004000      /* PHY error */
00302 #define AR5K_ISR_RXKCM          0x00008000      /* RX Key cache miss */
00303 #define AR5K_ISR_SWBA           0x00010000      /* Software beacon alert */
00304 #define AR5K_ISR_BRSSI          0x00020000      /* Beacon rssi below threshold (?) */
00305 #define AR5K_ISR_BMISS          0x00040000      /* Beacon missed */
00306 #define AR5K_ISR_HIUERR         0x00080000      /* Host Interface Unit error [5211+] */
00307 #define AR5K_ISR_BNR            0x00100000      /* Beacon not ready [5211+] */
00308 #define AR5K_ISR_MCABT          0x00100000      /* Master Cycle Abort [5210] */
00309 #define AR5K_ISR_RXCHIRP        0x00200000      /* CHIRP Received [5212+] */
00310 #define AR5K_ISR_SSERR          0x00200000      /* Signaled System Error [5210] */
00311 #define AR5K_ISR_DPERR          0x00400000      /* Det par Error (?) [5210] */
00312 #define AR5K_ISR_RXDOPPLER      0x00400000      /* Doppler chirp received [5212+] */
00313 #define AR5K_ISR_TIM            0x00800000      /* [5211+] */
00314 #define AR5K_ISR_BCNMISC        0x00800000      /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
00315                                                 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
00316 #define AR5K_ISR_GPIO           0x01000000      /* GPIO (rf kill) */
00317 #define AR5K_ISR_QCBRORN        0x02000000      /* QCU CBR overrun [5211+] */
00318 #define AR5K_ISR_QCBRURN        0x04000000      /* QCU CBR underrun [5211+] */
00319 #define AR5K_ISR_QTRIG          0x08000000      /* QCU scheduling trigger [5211+] */
00320 
00321 /*
00322  * Secondary status registers [5211+] (0 - 4)
00323  *
00324  * These give the status for each QCU, only QCUs 0-9 are
00325  * represented.
00326  */
00327 #define AR5K_SISR0              0x0084                  /* Register Address [5211+] */
00328 #define AR5K_SISR0_QCU_TXOK     0x000003ff      /* Mask for QCU_TXOK */
00329 #define AR5K_SISR0_QCU_TXOK_S   0
00330 #define AR5K_SISR0_QCU_TXDESC   0x03ff0000      /* Mask for QCU_TXDESC */
00331 #define AR5K_SISR0_QCU_TXDESC_S 16
00332 
00333 #define AR5K_SISR1              0x0088                  /* Register Address [5211+] */
00334 #define AR5K_SISR1_QCU_TXERR    0x000003ff      /* Mask for QCU_TXERR */
00335 #define AR5K_SISR1_QCU_TXERR_S  0
00336 #define AR5K_SISR1_QCU_TXEOL    0x03ff0000      /* Mask for QCU_TXEOL */
00337 #define AR5K_SISR1_QCU_TXEOL_S  16
00338 
00339 #define AR5K_SISR2              0x008c                  /* Register Address [5211+] */
00340 #define AR5K_SISR2_QCU_TXURN    0x000003ff      /* Mask for QCU_TXURN */
00341 #define AR5K_SISR2_QCU_TXURN_S  0
00342 #define AR5K_SISR2_MCABT        0x00100000      /* Master Cycle Abort */
00343 #define AR5K_SISR2_SSERR        0x00200000      /* Signaled System Error */
00344 #define AR5K_SISR2_DPERR        0x00400000      /* Bus parity error */
00345 #define AR5K_SISR2_TIM          0x01000000      /* [5212+] */
00346 #define AR5K_SISR2_CAB_END      0x02000000      /* [5212+] */
00347 #define AR5K_SISR2_DTIM_SYNC    0x04000000      /* DTIM sync lost [5212+] */
00348 #define AR5K_SISR2_BCN_TIMEOUT  0x08000000      /* Beacon Timeout [5212+] */
00349 #define AR5K_SISR2_CAB_TIMEOUT  0x10000000      /* CAB Timeout [5212+] */
00350 #define AR5K_SISR2_DTIM         0x20000000      /* [5212+] */
00351 #define AR5K_SISR2_TSFOOR       0x80000000      /* TSF OOR (?) */
00352 
00353 #define AR5K_SISR3              0x0090                  /* Register Address [5211+] */
00354 #define AR5K_SISR3_QCBRORN      0x000003ff      /* Mask for QCBRORN */
00355 #define AR5K_SISR3_QCBRORN_S    0
00356 #define AR5K_SISR3_QCBRURN      0x03ff0000      /* Mask for QCBRURN */
00357 #define AR5K_SISR3_QCBRURN_S    16
00358 
00359 #define AR5K_SISR4              0x0094                  /* Register Address [5211+] */
00360 #define AR5K_SISR4_QTRIG        0x000003ff      /* Mask for QTRIG */
00361 #define AR5K_SISR4_QTRIG_S      0
00362 
00363 /*
00364  * Shadow read-and-clear interrupt status registers [5211+]
00365  */
00366 #define AR5K_RAC_PISR           0x00c0          /* Read and clear PISR */
00367 #define AR5K_RAC_SISR0          0x00c4          /* Read and clear SISR0 */
00368 #define AR5K_RAC_SISR1          0x00c8          /* Read and clear SISR1 */
00369 #define AR5K_RAC_SISR2          0x00cc          /* Read and clear SISR2 */
00370 #define AR5K_RAC_SISR3          0x00d0          /* Read and clear SISR3 */
00371 #define AR5K_RAC_SISR4          0x00d4          /* Read and clear SISR4 */
00372 
00373 /*
00374  * Interrupt Mask Registers
00375  *
00376  * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
00377  * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.
00378  */
00379 #define AR5K_IMR                0x0020                  /* Register Address [5210] */
00380 #define AR5K_PIMR               0x00a0                  /* Register Address [5211+] */
00381 #define AR5K_IMR_RXOK           0x00000001      /* Frame successfuly recieved*/
00382 #define AR5K_IMR_RXDESC         0x00000002      /* RX descriptor request*/
00383 #define AR5K_IMR_RXERR          0x00000004      /* Receive error*/
00384 #define AR5K_IMR_RXNOFRM        0x00000008      /* No frame received (receive timeout)*/
00385 #define AR5K_IMR_RXEOL          0x00000010      /* Empty RX descriptor*/
00386 #define AR5K_IMR_RXORN          0x00000020      /* Receive FIFO overrun*/
00387 #define AR5K_IMR_TXOK           0x00000040      /* Frame successfuly transmited*/
00388 #define AR5K_IMR_TXDESC         0x00000080      /* TX descriptor request*/
00389 #define AR5K_IMR_TXERR          0x00000100      /* Transmit error*/
00390 #define AR5K_IMR_TXNOFRM        0x00000200      /* No frame transmited (transmit timeout)*/
00391 #define AR5K_IMR_TXEOL          0x00000400      /* Empty TX descriptor*/
00392 #define AR5K_IMR_TXURN          0x00000800      /* Transmit FIFO underrun*/
00393 #define AR5K_IMR_MIB            0x00001000      /* Update MIB counters*/
00394 #define AR5K_IMR_SWI            0x00002000      /* Software interrupt */
00395 #define AR5K_IMR_RXPHY          0x00004000      /* PHY error*/
00396 #define AR5K_IMR_RXKCM          0x00008000      /* RX Key cache miss */
00397 #define AR5K_IMR_SWBA           0x00010000      /* Software beacon alert*/
00398 #define AR5K_IMR_BRSSI          0x00020000      /* Beacon rssi below threshold (?) */
00399 #define AR5K_IMR_BMISS          0x00040000      /* Beacon missed*/
00400 #define AR5K_IMR_HIUERR         0x00080000      /* Host Interface Unit error [5211+] */
00401 #define AR5K_IMR_BNR            0x00100000      /* Beacon not ready [5211+] */
00402 #define AR5K_IMR_MCABT          0x00100000      /* Master Cycle Abort [5210] */
00403 #define AR5K_IMR_RXCHIRP        0x00200000      /* CHIRP Received [5212+]*/
00404 #define AR5K_IMR_SSERR          0x00200000      /* Signaled System Error [5210] */
00405 #define AR5K_IMR_DPERR          0x00400000      /* Det par Error (?) [5210] */
00406 #define AR5K_IMR_RXDOPPLER      0x00400000      /* Doppler chirp received [5212+] */
00407 #define AR5K_IMR_TIM            0x00800000      /* [5211+] */
00408 #define AR5K_IMR_BCNMISC        0x00800000      /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
00409                                                 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
00410 #define AR5K_IMR_GPIO           0x01000000      /* GPIO (rf kill)*/
00411 #define AR5K_IMR_QCBRORN        0x02000000      /* QCU CBR overrun (?) [5211+] */
00412 #define AR5K_IMR_QCBRURN        0x04000000      /* QCU CBR underrun (?) [5211+] */
00413 #define AR5K_IMR_QTRIG          0x08000000      /* QCU scheduling trigger [5211+] */
00414 
00415 /*
00416  * Secondary interrupt mask registers [5211+] (0 - 4)
00417  */
00418 #define AR5K_SIMR0              0x00a4                  /* Register Address [5211+] */
00419 #define AR5K_SIMR0_QCU_TXOK     0x000003ff      /* Mask for QCU_TXOK */
00420 #define AR5K_SIMR0_QCU_TXOK_S   0
00421 #define AR5K_SIMR0_QCU_TXDESC   0x03ff0000      /* Mask for QCU_TXDESC */
00422 #define AR5K_SIMR0_QCU_TXDESC_S 16
00423 
00424 #define AR5K_SIMR1              0x00a8                  /* Register Address [5211+] */
00425 #define AR5K_SIMR1_QCU_TXERR    0x000003ff      /* Mask for QCU_TXERR */
00426 #define AR5K_SIMR1_QCU_TXERR_S  0
00427 #define AR5K_SIMR1_QCU_TXEOL    0x03ff0000      /* Mask for QCU_TXEOL */
00428 #define AR5K_SIMR1_QCU_TXEOL_S  16
00429 
00430 #define AR5K_SIMR2              0x00ac                  /* Register Address [5211+] */
00431 #define AR5K_SIMR2_QCU_TXURN    0x000003ff      /* Mask for QCU_TXURN */
00432 #define AR5K_SIMR2_QCU_TXURN_S  0
00433 #define AR5K_SIMR2_MCABT        0x00100000      /* Master Cycle Abort */
00434 #define AR5K_SIMR2_SSERR        0x00200000      /* Signaled System Error */
00435 #define AR5K_SIMR2_DPERR        0x00400000      /* Bus parity error */
00436 #define AR5K_SIMR2_TIM          0x01000000      /* [5212+] */
00437 #define AR5K_SIMR2_CAB_END      0x02000000      /* [5212+] */
00438 #define AR5K_SIMR2_DTIM_SYNC    0x04000000      /* DTIM Sync lost [5212+] */
00439 #define AR5K_SIMR2_BCN_TIMEOUT  0x08000000      /* Beacon Timeout [5212+] */
00440 #define AR5K_SIMR2_CAB_TIMEOUT  0x10000000      /* CAB Timeout [5212+] */
00441 #define AR5K_SIMR2_DTIM         0x20000000      /* [5212+] */
00442 #define AR5K_SIMR2_TSFOOR       0x80000000      /* TSF OOR (?) */
00443 
00444 #define AR5K_SIMR3              0x00b0                  /* Register Address [5211+] */
00445 #define AR5K_SIMR3_QCBRORN      0x000003ff      /* Mask for QCBRORN */
00446 #define AR5K_SIMR3_QCBRORN_S    0
00447 #define AR5K_SIMR3_QCBRURN      0x03ff0000      /* Mask for QCBRURN */
00448 #define AR5K_SIMR3_QCBRURN_S    16
00449 
00450 #define AR5K_SIMR4              0x00b4                  /* Register Address [5211+] */
00451 #define AR5K_SIMR4_QTRIG        0x000003ff      /* Mask for QTRIG */
00452 #define AR5K_SIMR4_QTRIG_S      0
00453 
00454 /*
00455  * DMA Debug registers 0-7
00456  * 0xe0 - 0xfc
00457  */
00458 
00459 /*
00460  * Decompression mask registers [5212+]
00461  */
00462 #define AR5K_DCM_ADDR           0x0400          /*Decompression mask address (index) */
00463 #define AR5K_DCM_DATA           0x0404          /*Decompression mask data */
00464 
00465 /*
00466  * Wake On Wireless pattern control register [5212+]
00467  */
00468 #define AR5K_WOW_PCFG                   0x0410                  /* Register Address */
00469 #define AR5K_WOW_PCFG_PAT_MATCH_EN      0x00000001      /* Pattern match enable */
00470 #define AR5K_WOW_PCFG_LONG_FRAME_POL    0x00000002      /* Long frame policy */
00471 #define AR5K_WOW_PCFG_WOBMISS           0x00000004      /* Wake on bea(con) miss (?) */
00472 #define AR5K_WOW_PCFG_PAT_0_EN          0x00000100      /* Enable pattern 0 */
00473 #define AR5K_WOW_PCFG_PAT_1_EN          0x00000200      /* Enable pattern 1 */
00474 #define AR5K_WOW_PCFG_PAT_2_EN          0x00000400      /* Enable pattern 2 */
00475 #define AR5K_WOW_PCFG_PAT_3_EN          0x00000800      /* Enable pattern 3 */
00476 #define AR5K_WOW_PCFG_PAT_4_EN          0x00001000      /* Enable pattern 4 */
00477 #define AR5K_WOW_PCFG_PAT_5_EN          0x00002000      /* Enable pattern 5 */
00478 
00479 /*
00480  * Wake On Wireless pattern index register (?) [5212+]
00481  */
00482 #define AR5K_WOW_PAT_IDX        0x0414
00483 
00484 /*
00485  * Wake On Wireless pattern data register [5212+]
00486  */
00487 #define AR5K_WOW_PAT_DATA       0x0418                  /* Register Address */
00488 #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001      /* Pattern 0, 3 value */
00489 #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100      /* Pattern 1, 4 value */
00490 #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000      /* Pattern 2, 5 value */
00491 #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000      /* Pattern 0, 3 mask */
00492 #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000      /* Pattern 1, 4 mask */
00493 #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000      /* Pattern 2, 5 mask */
00494 
00495 /*
00496  * Decompression configuration registers [5212+]
00497  */
00498 #define AR5K_DCCFG              0x0420                  /* Register Address */
00499 #define AR5K_DCCFG_GLOBAL_EN    0x00000001      /* Enable decompression on all queues */
00500 #define AR5K_DCCFG_BYPASS_EN    0x00000002      /* Bypass decompression */
00501 #define AR5K_DCCFG_BCAST_EN     0x00000004      /* Enable decompression for bcast frames */
00502 #define AR5K_DCCFG_MCAST_EN     0x00000008      /* Enable decompression for mcast frames */
00503 
00504 /*
00505  * Compression configuration registers [5212+]
00506  */
00507 #define AR5K_CCFG               0x0600                  /* Register Address */
00508 #define AR5K_CCFG_WINDOW_SIZE   0x00000007      /* Compression window size */
00509 #define AR5K_CCFG_CPC_EN        0x00000008      /* Enable performance counters */
00510 
00511 #define AR5K_CCFG_CCU           0x0604                  /* Register Address */
00512 #define AR5K_CCFG_CCU_CUP_EN    0x00000001      /* CCU Catchup enable */
00513 #define AR5K_CCFG_CCU_CREDIT    0x00000002      /* CCU Credit (field) */
00514 #define AR5K_CCFG_CCU_CD_THRES  0x00000080      /* CCU Cyc(lic?) debt threshold (field) */
00515 #define AR5K_CCFG_CCU_CUP_LCNT  0x00010000      /* CCU Catchup lit(?) count */
00516 #define AR5K_CCFG_CCU_INIT      0x00100200      /* Initial value during reset */
00517 
00518 /*
00519  * Compression performance counter registers [5212+]
00520  */
00521 #define AR5K_CPC0               0x0610          /* Compression performance counter 0 */
00522 #define AR5K_CPC1               0x0614          /* Compression performance counter 1*/
00523 #define AR5K_CPC2               0x0618          /* Compression performance counter 2 */
00524 #define AR5K_CPC3               0x061c          /* Compression performance counter 3 */
00525 #define AR5K_CPCOVF             0x0620          /* Compression performance overflow */
00526 
00527 
00528 /*
00529  * Queue control unit (QCU) registers [5211+]
00530  *
00531  * Card has 12 TX Queues but i see that only 0-9 are used (?)
00532  * both in binary HAL (see ah.h) and ar5k. Each queue has it's own
00533  * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
00534  * configuration register (0x08c0 - 0x08ec), a ready time configuration
00535  * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
00536  * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
00537  * global registers, QCU transmit enable/disable and "one shot arm (?)"
00538  * set/clear, which contain status for all queues (we shift by 1 for each
00539  * queue). To access these registers easily we define some macros here
00540  * that are used inside HAL. For more infos check out *_tx_queue functs.
00541  */
00542 
00543 /*
00544  * Generic QCU Register access macros
00545  */
00546 #define AR5K_QUEUE_REG(_r, _q)          (((_q) << 2) + _r)
00547 #define AR5K_QCU_GLOBAL_READ(_r, _q)    (AR5K_REG_READ(_r) & (1 << _q))
00548 #define AR5K_QCU_GLOBAL_WRITE(_r, _q)   AR5K_REG_WRITE(_r, (1 << _q))
00549 
00550 /*
00551  * QCU Transmit descriptor pointer registers
00552  */
00553 #define AR5K_QCU_TXDP_BASE      0x0800          /* Register Address - Queue0 TXDP */
00554 #define AR5K_QUEUE_TXDP(_q)     AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
00555 
00556 /*
00557  * QCU Transmit enable register
00558  */
00559 #define AR5K_QCU_TXE            0x0840
00560 #define AR5K_ENABLE_QUEUE(_q)   AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
00561 #define AR5K_QUEUE_ENABLED(_q)  AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
00562 
00563 /*
00564  * QCU Transmit disable register
00565  */
00566 #define AR5K_QCU_TXD            0x0880
00567 #define AR5K_DISABLE_QUEUE(_q)  AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
00568 #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
00569 
00570 /*
00571  * QCU Constant Bit Rate configuration registers
00572  */
00573 #define AR5K_QCU_CBRCFG_BASE            0x08c0  /* Register Address - Queue0 CBRCFG */
00574 #define AR5K_QCU_CBRCFG_INTVAL          0x00ffffff      /* CBR Interval mask */
00575 #define AR5K_QCU_CBRCFG_INTVAL_S        0
00576 #define AR5K_QCU_CBRCFG_ORN_THRES       0xff000000      /* CBR overrun threshold mask */
00577 #define AR5K_QCU_CBRCFG_ORN_THRES_S     24
00578 #define AR5K_QUEUE_CBRCFG(_q)           AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
00579 
00580 /*
00581  * QCU Ready time configuration registers
00582  */
00583 #define AR5K_QCU_RDYTIMECFG_BASE        0x0900  /* Register Address - Queue0 RDYTIMECFG */
00584 #define AR5K_QCU_RDYTIMECFG_INTVAL      0x00ffffff      /* Ready time interval mask */
00585 #define AR5K_QCU_RDYTIMECFG_INTVAL_S    0
00586 #define AR5K_QCU_RDYTIMECFG_ENABLE      0x01000000      /* Ready time enable mask */
00587 #define AR5K_QUEUE_RDYTIMECFG(_q)       AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
00588 
00589 /*
00590  * QCU one shot arm set registers
00591  */
00592 #define AR5K_QCU_ONESHOTARM_SET         0x0940  /* Register Address -QCU "one shot arm set (?)" */
00593 #define AR5K_QCU_ONESHOTARM_SET_M       0x0000ffff
00594 
00595 /*
00596  * QCU one shot arm clear registers
00597  */
00598 #define AR5K_QCU_ONESHOTARM_CLEAR       0x0980  /* Register Address -QCU "one shot arm clear (?)" */
00599 #define AR5K_QCU_ONESHOTARM_CLEAR_M     0x0000ffff
00600 
00601 /*
00602  * QCU misc registers
00603  */
00604 #define AR5K_QCU_MISC_BASE              0x09c0                  /* Register Address -Queue0 MISC */
00605 #define AR5K_QCU_MISC_FRSHED_M          0x0000000f      /* Frame sheduling mask */
00606 #define AR5K_QCU_MISC_FRSHED_ASAP               0       /* ASAP */
00607 #define AR5K_QCU_MISC_FRSHED_CBR                1       /* Constant Bit Rate */
00608 #define AR5K_QCU_MISC_FRSHED_DBA_GT             2       /* DMA Beacon alert gated */
00609 #define AR5K_QCU_MISC_FRSHED_TIM_GT             3       /* TIMT gated */
00610 #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT        4       /* Beacon sent gated */
00611 #define AR5K_QCU_MISC_ONESHOT_ENABLE    0x00000010      /* Oneshot enable */
00612 #define AR5K_QCU_MISC_CBREXP_DIS        0x00000020      /* Disable CBR expired counter (normal queue) */
00613 #define AR5K_QCU_MISC_CBREXP_BCN_DIS    0x00000040      /* Disable CBR expired counter (beacon queue) */
00614 #define AR5K_QCU_MISC_BCN_ENABLE        0x00000080      /* Enable Beacon use */
00615 #define AR5K_QCU_MISC_CBR_THRES_ENABLE  0x00000100      /* CBR expired threshold enabled */
00616 #define AR5K_QCU_MISC_RDY_VEOL_POLICY   0x00000200      /* TXE reset when RDYTIME expired or VEOL */
00617 #define AR5K_QCU_MISC_CBR_RESET_CNT     0x00000400      /* CBR threshold (counter) reset */
00618 #define AR5K_QCU_MISC_DCU_EARLY         0x00000800      /* DCU early termination */
00619 #define AR5K_QCU_MISC_DCU_CMP_EN        0x00001000      /* Enable frame compression */
00620 #define AR5K_QUEUE_MISC(_q)             AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
00621 
00622 
00623 /*
00624  * QCU status registers
00625  */
00626 #define AR5K_QCU_STS_BASE       0x0a00                  /* Register Address - Queue0 STS */
00627 #define AR5K_QCU_STS_FRMPENDCNT 0x00000003      /* Frames pending counter */
00628 #define AR5K_QCU_STS_CBREXPCNT  0x0000ff00      /* CBR expired counter */
00629 #define AR5K_QUEUE_STATUS(_q)   AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
00630 
00631 /*
00632  * QCU ready time shutdown register
00633  */
00634 #define AR5K_QCU_RDYTIMESHDN    0x0a40
00635 #define AR5K_QCU_RDYTIMESHDN_M  0x000003ff
00636 
00637 /*
00638  * QCU compression buffer base registers [5212+]
00639  */
00640 #define AR5K_QCU_CBB_SELECT     0x0b00
00641 #define AR5K_QCU_CBB_ADDR       0x0b04
00642 #define AR5K_QCU_CBB_ADDR_S     9
00643 
00644 /*
00645  * QCU compression buffer configuration register [5212+]
00646  * (buffer size)
00647  */
00648 #define AR5K_QCU_CBCFG          0x0b08
00649 
00650 
00651 
00652 /*
00653  * Distributed Coordination Function (DCF) control unit (DCU)
00654  * registers [5211+]
00655  *
00656  * These registers control the various characteristics of each queue
00657  * for 802.11e (WME) combatibility so they go together with
00658  * QCU registers in pairs. For each queue we have a QCU mask register,
00659  * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
00660  * a retry limit register (0x1080 - 0x10ac), a channel time register
00661  * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
00662  * a sequence number register (0x1140 - 0x116c). It seems that "global"
00663  * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).
00664  * We use the same macros here for easier register access.
00665  *
00666  */
00667 
00668 /*
00669  * DCU QCU mask registers
00670  */
00671 #define AR5K_DCU_QCUMASK_BASE   0x1000          /* Register Address -Queue0 DCU_QCUMASK */
00672 #define AR5K_DCU_QCUMASK_M      0x000003ff
00673 #define AR5K_QUEUE_QCUMASK(_q)  AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
00674 
00675 /*
00676  * DCU local Inter Frame Space settings register
00677  */
00678 #define AR5K_DCU_LCL_IFS_BASE           0x1040                  /* Register Address -Queue0 DCU_LCL_IFS */
00679 #define AR5K_DCU_LCL_IFS_CW_MIN         0x000003ff      /* Minimum Contention Window */
00680 #define AR5K_DCU_LCL_IFS_CW_MIN_S       0
00681 #define AR5K_DCU_LCL_IFS_CW_MAX         0x000ffc00      /* Maximum Contention Window */
00682 #define AR5K_DCU_LCL_IFS_CW_MAX_S       10
00683 #define AR5K_DCU_LCL_IFS_AIFS           0x0ff00000      /* Arbitrated Interframe Space */
00684 #define AR5K_DCU_LCL_IFS_AIFS_S         20
00685 #define AR5K_DCU_LCL_IFS_AIFS_MAX       0xfc            /* Anything above that can cause DCU to hang */
00686 #define AR5K_QUEUE_DFS_LOCAL_IFS(_q)    AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
00687 
00688 /*
00689  * DCU retry limit registers
00690  */
00691 #define AR5K_DCU_RETRY_LMT_BASE         0x1080                  /* Register Address -Queue0 DCU_RETRY_LMT */
00692 #define AR5K_DCU_RETRY_LMT_SH_RETRY     0x0000000f      /* Short retry limit mask */
00693 #define AR5K_DCU_RETRY_LMT_SH_RETRY_S   0
00694 #define AR5K_DCU_RETRY_LMT_LG_RETRY     0x000000f0      /* Long retry limit mask */
00695 #define AR5K_DCU_RETRY_LMT_LG_RETRY_S   4
00696 #define AR5K_DCU_RETRY_LMT_SSH_RETRY    0x00003f00      /* Station short retry limit mask (?) */
00697 #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S  8
00698 #define AR5K_DCU_RETRY_LMT_SLG_RETRY    0x000fc000      /* Station long retry limit mask (?) */
00699 #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S  14
00700 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q)  AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
00701 
00702 /*
00703  * DCU channel time registers
00704  */
00705 #define AR5K_DCU_CHAN_TIME_BASE         0x10c0                  /* Register Address -Queue0 DCU_CHAN_TIME */
00706 #define AR5K_DCU_CHAN_TIME_DUR          0x000fffff      /* Channel time duration */
00707 #define AR5K_DCU_CHAN_TIME_DUR_S        0
00708 #define AR5K_DCU_CHAN_TIME_ENABLE       0x00100000      /* Enable channel time */
00709 #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
00710 
00711 /*
00712  * DCU misc registers [5211+]
00713  *
00714  * Note: Arbiter lockout control controls the
00715  * behaviour on low priority queues when we have multiple queues
00716  * with pending frames. Intra-frame lockout means we wait until
00717  * the queue's current frame transmits (with post frame backoff and bursting)
00718  * before we transmit anything else and global lockout means we
00719  * wait for the whole queue to finish before higher priority queues
00720  * can transmit (this is used on beacon and CAB queues).
00721  * No lockout means there is no special handling.
00722  */
00723 #define AR5K_DCU_MISC_BASE              0x1100                  /* Register Address -Queue0 DCU_MISC */
00724 #define AR5K_DCU_MISC_BACKOFF           0x0000003f      /* Mask for backoff threshold */
00725 #define AR5K_DCU_MISC_ETS_RTS_POL       0x00000040      /* End of transmission series
00726                                                         station RTS/data failure count
00727                                                         reset policy (?) */
00728 #define AR5K_DCU_MISC_ETS_CW_POL        0x00000080      /* End of transmission series
00729                                                         CW reset policy */
00730 #define AR5K_DCU_MISC_FRAG_WAIT         0x00000100      /* Wait for next fragment */
00731 #define AR5K_DCU_MISC_BACKOFF_FRAG      0x00000200      /* Enable backoff while bursting */
00732 #define AR5K_DCU_MISC_HCFPOLL_ENABLE    0x00000800      /* CF - Poll enable */
00733 #define AR5K_DCU_MISC_BACKOFF_PERSIST   0x00001000      /* Persistent backoff */
00734 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE  0x00002000      /* Enable frame pre-fetch */
00735 #define AR5K_DCU_MISC_VIRTCOL           0x0000c000      /* Mask for Virtual Collision (?) */
00736 #define AR5K_DCU_MISC_VIRTCOL_NORMAL    0
00737 #define AR5K_DCU_MISC_VIRTCOL_IGNORE    1
00738 #define AR5K_DCU_MISC_BCN_ENABLE        0x00010000      /* Enable Beacon use */
00739 #define AR5K_DCU_MISC_ARBLOCK_CTL       0x00060000      /* Arbiter lockout control mask */
00740 #define AR5K_DCU_MISC_ARBLOCK_CTL_S     17
00741 #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE          0       /* No arbiter lockout */
00742 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM        1       /* Intra-frame lockout */
00743 #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL        2       /* Global lockout */
00744 #define AR5K_DCU_MISC_ARBLOCK_IGNORE    0x00080000      /* Ignore Arbiter lockout */
00745 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS  0x00100000      /* Disable sequence number increment */
00746 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000      /* Disable post-frame backoff */
00747 #define AR5K_DCU_MISC_VIRT_COLL_POLICY  0x00400000      /* Virtual Collision cw policy */
00748 #define AR5K_DCU_MISC_BLOWN_IFS_POLICY  0x00800000      /* Blown IFS policy (?) */
00749 #define AR5K_DCU_MISC_SEQNUM_CTL        0x01000000      /* Sequence number control (?) */
00750 #define AR5K_QUEUE_DFS_MISC(_q)         AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
00751 
00752 /*
00753  * DCU frame sequence number registers
00754  */
00755 #define AR5K_DCU_SEQNUM_BASE            0x1140
00756 #define AR5K_DCU_SEQNUM_M               0x00000fff
00757 #define AR5K_QUEUE_DCU_SEQNUM(_q)       AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
00758 
00759 /*
00760  * DCU global IFS SIFS register
00761  */
00762 #define AR5K_DCU_GBL_IFS_SIFS   0x1030
00763 #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
00764 
00765 /*
00766  * DCU global IFS slot interval register
00767  */
00768 #define AR5K_DCU_GBL_IFS_SLOT   0x1070
00769 #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
00770 
00771 /*
00772  * DCU global IFS EIFS register
00773  */
00774 #define AR5K_DCU_GBL_IFS_EIFS   0x10b0
00775 #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
00776 
00777 /*
00778  * DCU global IFS misc register
00779  *
00780  * LFSR stands for Linear Feedback Shift Register
00781  * and it's used for generating pseudo-random
00782  * number sequences.
00783  *
00784  * (If i understand corectly, random numbers are
00785  * used for idle sensing -multiplied with cwmin/max etc-)
00786  */
00787 #define AR5K_DCU_GBL_IFS_MISC                   0x10f0                  /* Register Address */
00788 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE        0x00000007      /* LFSR Slice Select */
00789 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE        0x00000008      /* Turbo mode */
00790 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC     0x000003f0      /* SIFS Duration mask */
00791 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR          0x000ffc00      /* USEC Duration mask */
00792 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S        10
00793 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY     0x00300000      /* DCU Arbiter delay mask */
00794 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST      0x00400000      /* SIFS cnt reset policy (?) */
00795 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST      0x00800000      /* AIFS cnt reset policy (?) */
00796 #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS   0x01000000      /* Disable random LFSR slice */
00797 
00798 /*
00799  * DCU frame prefetch control register
00800  */
00801 #define AR5K_DCU_FP                     0x1230                  /* Register Address */
00802 #define AR5K_DCU_FP_NOBURST_DCU_EN      0x00000001      /* Enable non-burst prefetch on DCU (?) */
00803 #define AR5K_DCU_FP_NOBURST_EN          0x00000010      /* Enable non-burst prefetch (?) */
00804 #define AR5K_DCU_FP_BURST_DCU_EN        0x00000020      /* Enable burst prefetch on DCU (?) */
00805 
00806 /*
00807  * DCU transmit pause control/status register
00808  */
00809 #define AR5K_DCU_TXP            0x1270                  /* Register Address */
00810 #define AR5K_DCU_TXP_M          0x000003ff      /* Tx pause mask */
00811 #define AR5K_DCU_TXP_STATUS     0x00010000      /* Tx pause status */
00812 
00813 /*
00814  * DCU transmit filter table 0 (32 entries)
00815  * each entry contains a 32bit slice of the
00816  * 128bit tx filter for each DCU (4 slices per DCU)
00817  */
00818 #define AR5K_DCU_TX_FILTER_0_BASE       0x1038
00819 #define AR5K_DCU_TX_FILTER_0(_n)        (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
00820 
00821 /*
00822  * DCU transmit filter table 1 (16 entries)
00823  */
00824 #define AR5K_DCU_TX_FILTER_1_BASE       0x103c
00825 #define AR5K_DCU_TX_FILTER_1(_n)        (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
00826 
00827 /*
00828  * DCU clear transmit filter register
00829  */
00830 #define AR5K_DCU_TX_FILTER_CLR  0x143c
00831 
00832 /*
00833  * DCU set transmit filter register
00834  */
00835 #define AR5K_DCU_TX_FILTER_SET  0x147c
00836 
00837 /*
00838  * Reset control register
00839  */
00840 #define AR5K_RESET_CTL          0x4000                  /* Register Address */
00841 #define AR5K_RESET_CTL_PCU      0x00000001      /* Protocol Control Unit reset */
00842 #define AR5K_RESET_CTL_DMA      0x00000002      /* DMA (Rx/Tx) reset [5210] */
00843 #define AR5K_RESET_CTL_BASEBAND 0x00000002      /* Baseband reset [5211+] */
00844 #define AR5K_RESET_CTL_MAC      0x00000004      /* MAC reset (PCU+Baseband ?) [5210] */
00845 #define AR5K_RESET_CTL_PHY      0x00000008      /* PHY reset [5210] */
00846 #define AR5K_RESET_CTL_PCI      0x00000010      /* PCI Core reset (interrupts etc) */
00847 
00848 /*
00849  * Sleep control register
00850  */
00851 #define AR5K_SLEEP_CTL                  0x4004                  /* Register Address */
00852 #define AR5K_SLEEP_CTL_SLDUR            0x0000ffff      /* Sleep duration mask */
00853 #define AR5K_SLEEP_CTL_SLDUR_S          0
00854 #define AR5K_SLEEP_CTL_SLE              0x00030000      /* Sleep enable mask */
00855 #define AR5K_SLEEP_CTL_SLE_S            16
00856 #define AR5K_SLEEP_CTL_SLE_WAKE         0x00000000      /* Force chip awake */
00857 #define AR5K_SLEEP_CTL_SLE_SLP          0x00010000      /* Force chip sleep */
00858 #define AR5K_SLEEP_CTL_SLE_ALLOW        0x00020000      /* Normal sleep policy */
00859 #define AR5K_SLEEP_CTL_SLE_UNITS        0x00000008      /* [5211+] */
00860 #define AR5K_SLEEP_CTL_DUR_TIM_POL      0x00040000      /* Sleep duration timing policy */
00861 #define AR5K_SLEEP_CTL_DUR_WRITE_POL    0x00080000      /* Sleep duration write policy */
00862 #define AR5K_SLEEP_CTL_SLE_POL          0x00100000      /* Sleep policy mode */
00863 
00864 /*
00865  * Interrupt pending register
00866  */
00867 #define AR5K_INTPEND    0x4008
00868 #define AR5K_INTPEND_M  0x00000001
00869 
00870 /*
00871  * Sleep force register
00872  */
00873 #define AR5K_SFR        0x400c
00874 #define AR5K_SFR_EN     0x00000001
00875 
00876 /*
00877  * PCI configuration register
00878  * TODO: Fix LED stuff
00879  */
00880 #define AR5K_PCICFG                     0x4010                  /* Register Address */
00881 #define AR5K_PCICFG_EEAE                0x00000001      /* Eeprom access enable [5210] */
00882 #define AR5K_PCICFG_SLEEP_CLOCK_EN      0x00000002      /* Enable sleep clock */
00883 #define AR5K_PCICFG_CLKRUNEN            0x00000004      /* CLKRUN enable [5211+] */
00884 #define AR5K_PCICFG_EESIZE              0x00000018      /* Mask for EEPROM size [5211+] */
00885 #define AR5K_PCICFG_EESIZE_S            3
00886 #define AR5K_PCICFG_EESIZE_4K           0               /* 4K */
00887 #define AR5K_PCICFG_EESIZE_8K           1               /* 8K */
00888 #define AR5K_PCICFG_EESIZE_16K          2               /* 16K */
00889 #define AR5K_PCICFG_EESIZE_FAIL         3               /* Failed to get size [5211+] */
00890 #define AR5K_PCICFG_LED                 0x00000060      /* Led status [5211+] */
00891 #define AR5K_PCICFG_LED_NONE            0x00000000      /* Default [5211+] */
00892 #define AR5K_PCICFG_LED_PEND            0x00000020      /* Scan / Auth pending */
00893 #define AR5K_PCICFG_LED_ASSOC           0x00000040      /* Associated */
00894 #define AR5K_PCICFG_BUS_SEL             0x00000380      /* Mask for "bus select" [5211+] (?) */
00895 #define AR5K_PCICFG_CBEFIX_DIS          0x00000400      /* Disable CBE fix */
00896 #define AR5K_PCICFG_SL_INTEN            0x00000800      /* Enable interrupts when asleep */
00897 #define AR5K_PCICFG_LED_BCTL            0x00001000      /* Led blink (?) [5210] */
00898 #define AR5K_PCICFG_RETRY_FIX           0x00001000      /* Enable pci core retry fix */
00899 #define AR5K_PCICFG_SL_INPEN            0x00002000      /* Sleep even whith pending interrupts*/
00900 #define AR5K_PCICFG_SPWR_DN             0x00010000      /* Mask for power status */
00901 #define AR5K_PCICFG_LEDMODE             0x000e0000      /* Ledmode [5211+] */
00902 #define AR5K_PCICFG_LEDMODE_PROP        0x00000000      /* Blink on standard traffic [5211+] */
00903 #define AR5K_PCICFG_LEDMODE_PROM        0x00020000      /* Default mode (blink on any traffic) [5211+] */
00904 #define AR5K_PCICFG_LEDMODE_PWR         0x00040000      /* Some other blinking mode  (?) [5211+] */
00905 #define AR5K_PCICFG_LEDMODE_RAND        0x00060000      /* Random blinking (?) [5211+] */
00906 #define AR5K_PCICFG_LEDBLINK            0x00700000      /* Led blink rate */
00907 #define AR5K_PCICFG_LEDBLINK_S          20
00908 #define AR5K_PCICFG_LEDSLOW             0x00800000      /* Slowest led blink rate [5211+] */
00909 #define AR5K_PCICFG_LEDSTATE                            \
00910         (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE |        \
00911         AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
00912 #define AR5K_PCICFG_SLEEP_CLOCK_RATE    0x03000000      /* Sleep clock rate */
00913 #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S  24
00914 
00915 /*
00916  * "General Purpose Input/Output" (GPIO) control register
00917  *
00918  * I'm not sure about this but after looking at the code
00919  * for all chipsets here is what i got.
00920  *
00921  * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits)
00922  * Mode 0 -> always input
00923  * Mode 1 -> output when GPIODO for this GPIO is set to 0
00924  * Mode 2 -> output when GPIODO for this GPIO is set to 1
00925  * Mode 3 -> always output
00926  *
00927  * For more infos check out get_gpio/set_gpio and
00928  * set_gpio_input/set_gpio_output functs.
00929  * For more infos on gpio interrupt check out set_gpio_intr.
00930  */
00931 #define AR5K_NUM_GPIO   6
00932 
00933 #define AR5K_GPIOCR             0x4014                          /* Register Address */
00934 #define AR5K_GPIOCR_INT_ENA     0x00008000              /* Enable GPIO interrupt */
00935 #define AR5K_GPIOCR_INT_SELL    0x00000000              /* Generate interrupt when pin is low */
00936 #define AR5K_GPIOCR_INT_SELH    0x00010000              /* Generate interrupt when pin is high */
00937 #define AR5K_GPIOCR_IN(n)       (0 << ((n) * 2))        /* Mode 0 for pin n */
00938 #define AR5K_GPIOCR_OUT0(n)     (1 << ((n) * 2))        /* Mode 1 for pin n */
00939 #define AR5K_GPIOCR_OUT1(n)     (2 << ((n) * 2))        /* Mode 2 for pin n */
00940 #define AR5K_GPIOCR_OUT(n)      (3 << ((n) * 2))        /* Mode 3 for pin n */
00941 #define AR5K_GPIOCR_INT_SEL(n)  ((n) << 12)             /* Interrupt for GPIO pin n */
00942 
00943 /*
00944  * "General Purpose Input/Output" (GPIO) data output register
00945  */
00946 #define AR5K_GPIODO     0x4018
00947 
00948 /*
00949  * "General Purpose Input/Output" (GPIO) data input register
00950  */
00951 #define AR5K_GPIODI     0x401c
00952 #define AR5K_GPIODI_M   0x0000002f
00953 
00954 /*
00955  * Silicon revision register
00956  */
00957 #define AR5K_SREV               0x4020                  /* Register Address */
00958 #define AR5K_SREV_REV           0x0000000f      /* Mask for revision */
00959 #define AR5K_SREV_REV_S         0
00960 #define AR5K_SREV_VER           0x000000ff      /* Mask for version */
00961 #define AR5K_SREV_VER_S         4
00962 
00963 /*
00964  * TXE write posting register
00965  */
00966 #define AR5K_TXEPOST    0x4028
00967 
00968 /*
00969  * QCU sleep mask
00970  */
00971 #define AR5K_QCU_SLEEP_MASK     0x402c
00972 
00973 /* 0x4068 is compression buffer configuration
00974  * register on 5414 and pm configuration register
00975  * on 5424 and newer pci-e chips. */
00976 
00977 /*
00978  * Compression buffer configuration
00979  * register (enable/disable) [5414]
00980  */
00981 #define AR5K_5414_CBCFG         0x4068
00982 #define AR5K_5414_CBCFG_BUF_DIS 0x10    /* Disable buffer */
00983 
00984 /*
00985  * PCI-E Power managment configuration
00986  * and status register [5424+]
00987  */
00988 #define AR5K_PCIE_PM_CTL                0x4068                  /* Register address */
00989 /* Only 5424 */
00990 #define AR5K_PCIE_PM_CTL_L1_WHEN_D2     0x00000001      /* enable PCIe core enter L1
00991                                                         when d2_sleep_en is asserted */
00992 #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR   0x00000002      /* Clear L0 and L0S counters */
00993 #define AR5K_PCIE_PM_CTL_L0_L0S_EN      0x00000004      /* Start L0 nd L0S counters */
00994 #define AR5K_PCIE_PM_CTL_LDRESET_EN     0x00000008      /* Enable reset when link goes
00995                                                         down */
00996 /* Wake On Wireless */
00997 #define AR5K_PCIE_PM_CTL_PME_EN         0x00000010      /* PME Enable */
00998 #define AR5K_PCIE_PM_CTL_AUX_PWR_DET    0x00000020      /* Aux power detect */
00999 #define AR5K_PCIE_PM_CTL_PME_CLEAR      0x00000040      /* Clear PME */
01000 #define AR5K_PCIE_PM_CTL_PSM_D0         0x00000080
01001 #define AR5K_PCIE_PM_CTL_PSM_D1         0x00000100
01002 #define AR5K_PCIE_PM_CTL_PSM_D2         0x00000200
01003 #define AR5K_PCIE_PM_CTL_PSM_D3         0x00000400
01004 
01005 /*
01006  * PCI-E Workaround enable register
01007  */
01008 #define AR5K_PCIE_WAEN  0x407c
01009 
01010 /*
01011  * PCI-E Serializer/Desirializer
01012  * registers
01013  */
01014 #define AR5K_PCIE_SERDES        0x4080
01015 #define AR5K_PCIE_SERDES_RESET  0x4084
01016 
01017 /*====EEPROM REGISTERS====*/
01018 
01019 /*
01020  * EEPROM access registers
01021  *
01022  * Here we got a difference between 5210/5211-12
01023  * read data register for 5210 is at 0x6800 and
01024  * status register is at 0x6c00. There is also
01025  * no eeprom command register on 5210 and the
01026  * offsets are different.
01027  *
01028  * To read eeprom data for a specific offset:
01029  * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
01030  *        read AR5K_EEPROM_BASE +(4 * offset)
01031  *        check the eeprom status register
01032  *        and read eeprom data register.
01033  *
01034  * 5211 - write offset to AR5K_EEPROM_BASE
01035  * 5212   write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD
01036  *        check the eeprom status register
01037  *        and read eeprom data register.
01038  *
01039  * To write eeprom data for a specific offset:
01040  * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
01041  *        write data to AR5K_EEPROM_BASE +(4 * offset)
01042  *        check the eeprom status register
01043  * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
01044  * 5212   write offset to AR5K_EEPROM_BASE
01045  *        write data to data register
01046  *        write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD
01047  *        check the eeprom status register
01048  *
01049  * For more infos check eeprom_* functs and the ar5k.c
01050  * file posted in madwifi-devel mailing list.
01051  * http://sourceforge.net/mailarchive/message.php?msg_id=8966525
01052  *
01053  */
01054 #define AR5K_EEPROM_BASE        0x6000
01055 
01056 /*
01057  * EEPROM data register
01058  */
01059 #define AR5K_EEPROM_DATA_5211   0x6004
01060 #define AR5K_EEPROM_DATA_5210   0x6800
01061 #define AR5K_EEPROM_DATA        (ah->ah_version == AR5K_AR5210 ? \
01062                                 AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
01063 
01064 /*
01065  * EEPROM command register
01066  */
01067 #define AR5K_EEPROM_CMD         0x6008                  /* Register Addres */
01068 #define AR5K_EEPROM_CMD_READ    0x00000001      /* EEPROM read */
01069 #define AR5K_EEPROM_CMD_WRITE   0x00000002      /* EEPROM write */
01070 #define AR5K_EEPROM_CMD_RESET   0x00000004      /* EEPROM reset */
01071 
01072 /*
01073  * EEPROM status register
01074  */
01075 #define AR5K_EEPROM_STAT_5210   0x6c00                  /* Register Address [5210] */
01076 #define AR5K_EEPROM_STAT_5211   0x600c                  /* Register Address [5211+] */
01077 #define AR5K_EEPROM_STATUS      (ah->ah_version == AR5K_AR5210 ? \
01078                                 AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
01079 #define AR5K_EEPROM_STAT_RDERR  0x00000001      /* EEPROM read failed */
01080 #define AR5K_EEPROM_STAT_RDDONE 0x00000002      /* EEPROM read successful */
01081 #define AR5K_EEPROM_STAT_WRERR  0x00000004      /* EEPROM write failed */
01082 #define AR5K_EEPROM_STAT_WRDONE 0x00000008      /* EEPROM write successful */
01083 
01084 /*
01085  * EEPROM config register
01086  */
01087 #define AR5K_EEPROM_CFG                 0x6010                  /* Register Addres */
01088 #define AR5K_EEPROM_CFG_SIZE            0x00000003              /* Size determination override */
01089 #define AR5K_EEPROM_CFG_SIZE_AUTO       0
01090 #define AR5K_EEPROM_CFG_SIZE_4KBIT      1
01091 #define AR5K_EEPROM_CFG_SIZE_8KBIT      2
01092 #define AR5K_EEPROM_CFG_SIZE_16KBIT     3
01093 #define AR5K_EEPROM_CFG_WR_WAIT_DIS     0x00000004      /* Disable write wait */
01094 #define AR5K_EEPROM_CFG_CLK_RATE        0x00000018      /* Clock rate */
01095 #define AR5K_EEPROM_CFG_CLK_RATE_S              3
01096 #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
01097 #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
01098 #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
01099 #define AR5K_EEPROM_CFG_PROT_KEY        0x00ffff00      /* Protection key */
01100 #define AR5K_EEPROM_CFG_PROT_KEY_S      8
01101 #define AR5K_EEPROM_CFG_LIND_EN         0x01000000      /* Enable length indicator (?) */
01102 
01103 
01104 /*
01105  * TODO: Wake On Wireless registers
01106  * Range 0x7000 - 0x7ce0
01107  */
01108 
01109 /*
01110  * Protocol Control Unit (PCU) registers
01111  */
01112 /*
01113  * Used for checking initial register writes
01114  * during channel reset (see reset func)
01115  */
01116 #define AR5K_PCU_MIN    0x8000
01117 #define AR5K_PCU_MAX    0x8fff
01118 
01119 /*
01120  * First station id register (Lower 32 bits of MAC address)
01121  */
01122 #define AR5K_STA_ID0            0x8000
01123 #define AR5K_STA_ID0_ARRD_L32   0xffffffff
01124 
01125 /*
01126  * Second station id register (Upper 16 bits of MAC address + PCU settings)
01127  */
01128 #define AR5K_STA_ID1                    0x8004                  /* Register Address */
01129 #define AR5K_STA_ID1_ADDR_U16           0x0000ffff      /* Upper 16 bits of MAC addres */
01130 #define AR5K_STA_ID1_AP                 0x00010000      /* Set AP mode */
01131 #define AR5K_STA_ID1_ADHOC              0x00020000      /* Set Ad-Hoc mode */
01132 #define AR5K_STA_ID1_PWR_SV             0x00040000      /* Power save reporting */
01133 #define AR5K_STA_ID1_NO_KEYSRCH         0x00080000      /* No key search */
01134 #define AR5K_STA_ID1_NO_PSPOLL          0x00100000      /* No power save polling [5210] */
01135 #define AR5K_STA_ID1_PCF_5211           0x00100000      /* Enable PCF on [5211+] */
01136 #define AR5K_STA_ID1_PCF_5210           0x00200000      /* Enable PCF on [5210]*/
01137 #define AR5K_STA_ID1_PCF                (ah->ah_version == AR5K_AR5210 ? \
01138                                         AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
01139 #define AR5K_STA_ID1_DEFAULT_ANTENNA    0x00200000      /* Use default antenna */
01140 #define AR5K_STA_ID1_DESC_ANTENNA       0x00400000      /* Update antenna from descriptor */
01141 #define AR5K_STA_ID1_RTS_DEF_ANTENNA    0x00800000      /* Use default antenna for RTS */
01142 #define AR5K_STA_ID1_ACKCTS_6MB         0x01000000      /* Use 6Mbit/s for ACK/CTS */
01143 #define AR5K_STA_ID1_BASE_RATE_11B      0x02000000      /* Use 11b base rate for ACK/CTS [5211+] */
01144 #define AR5K_STA_ID1_SELFGEN_DEF_ANT    0x04000000      /* Use def. antenna for self generated frames */
01145 #define AR5K_STA_ID1_CRYPT_MIC_EN       0x08000000      /* Enable MIC */
01146 #define AR5K_STA_ID1_KEYSRCH_MODE       0x10000000      /* Look up key when key id != 0 */
01147 #define AR5K_STA_ID1_PRESERVE_SEQ_NUM   0x20000000      /* Preserve sequence number */
01148 #define AR5K_STA_ID1_CBCIV_ENDIAN       0x40000000      /* ??? */
01149 #define AR5K_STA_ID1_KEYSRCH_MCAST      0x80000000      /* Do key cache search for mcast frames */
01150 
01151 /*
01152  * First BSSID register (MAC address, lower 32bits)
01153  */
01154 #define AR5K_BSS_ID0    0x8008
01155 
01156 /*
01157  * Second BSSID register (MAC address in upper 16 bits)
01158  *
01159  * AID: Association ID
01160  */
01161 #define AR5K_BSS_ID1            0x800c
01162 #define AR5K_BSS_ID1_AID        0xffff0000
01163 #define AR5K_BSS_ID1_AID_S      16
01164 
01165 /*
01166  * Backoff slot time register
01167  */
01168 #define AR5K_SLOT_TIME  0x8010
01169 
01170 /*
01171  * ACK/CTS timeout register
01172  */
01173 #define AR5K_TIME_OUT           0x8014                  /* Register Address */
01174 #define AR5K_TIME_OUT_ACK       0x00001fff      /* ACK timeout mask */
01175 #define AR5K_TIME_OUT_ACK_S     0
01176 #define AR5K_TIME_OUT_CTS       0x1fff0000      /* CTS timeout mask */
01177 #define AR5K_TIME_OUT_CTS_S     16
01178 
01179 /*
01180  * RSSI threshold register
01181  */
01182 #define AR5K_RSSI_THR                   0x8018          /* Register Address */
01183 #define AR5K_RSSI_THR_M                 0x000000ff      /* Mask for RSSI threshold [5211+] */
01184 #define AR5K_RSSI_THR_BMISS_5210        0x00000700      /* Mask for Beacon Missed threshold [5210] */
01185 #define AR5K_RSSI_THR_BMISS_5210_S      8
01186 #define AR5K_RSSI_THR_BMISS_5211        0x0000ff00      /* Mask for Beacon Missed threshold [5211+] */
01187 #define AR5K_RSSI_THR_BMISS_5211_S      8
01188 #define AR5K_RSSI_THR_BMISS             (ah->ah_version == AR5K_AR5210 ? \
01189                                         AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
01190 #define AR5K_RSSI_THR_BMISS_S           8
01191 
01192 /*
01193  * 5210 has more PCU registers because there is no QCU/DCU
01194  * so queue parameters are set here, this way a lot common
01195  * registers have different address for 5210. To make things
01196  * easier we define a macro based on ah->ah_version for common
01197  * registers with different addresses and common flags.
01198  */
01199 
01200 /*
01201  * Retry limit register
01202  *
01203  * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
01204  */
01205 #define AR5K_NODCU_RETRY_LMT            0x801c                  /* Register Address */
01206 #define AR5K_NODCU_RETRY_LMT_SH_RETRY   0x0000000f      /* Short retry limit mask */
01207 #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
01208 #define AR5K_NODCU_RETRY_LMT_LG_RETRY   0x000000f0      /* Long retry mask */
01209 #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
01210 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY  0x00003f00      /* Station short retry limit mask */
01211 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S        8
01212 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY  0x000fc000      /* Station long retry limit mask */
01213 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S        14
01214 #define AR5K_NODCU_RETRY_LMT_CW_MIN     0x3ff00000      /* Minimum contention window mask */
01215 #define AR5K_NODCU_RETRY_LMT_CW_MIN_S   20
01216 
01217 /*
01218  * Transmit latency register
01219  */
01220 #define AR5K_USEC_5210                  0x8020                  /* Register Address [5210] */
01221 #define AR5K_USEC_5211                  0x801c                  /* Register Address [5211+] */
01222 #define AR5K_USEC                       (ah->ah_version == AR5K_AR5210 ? \
01223                                         AR5K_USEC_5210 : AR5K_USEC_5211)
01224 #define AR5K_USEC_1                     0x0000007f      /* clock cycles for 1us */
01225 #define AR5K_USEC_1_S                   0
01226 #define AR5K_USEC_32                    0x00003f80      /* clock cycles for 1us while on 32Mhz clock */
01227 #define AR5K_USEC_32_S                  7
01228 #define AR5K_USEC_TX_LATENCY_5211       0x007fc000
01229 #define AR5K_USEC_TX_LATENCY_5211_S     14
01230 #define AR5K_USEC_RX_LATENCY_5211       0x1f800000
01231 #define AR5K_USEC_RX_LATENCY_5211_S     23
01232 #define AR5K_USEC_TX_LATENCY_5210       0x000fc000      /* also for 5311 */
01233 #define AR5K_USEC_TX_LATENCY_5210_S     14
01234 #define AR5K_USEC_RX_LATENCY_5210       0x03f00000      /* also for 5311 */
01235 #define AR5K_USEC_RX_LATENCY_5210_S     20
01236 
01237 /*
01238  * PCU beacon control register
01239  */
01240 #define AR5K_BEACON_5210        0x8024                  /*Register Address [5210] */
01241 #define AR5K_BEACON_5211        0x8020                  /*Register Address [5211+] */
01242 #define AR5K_BEACON             (ah->ah_version == AR5K_AR5210 ? \
01243                                 AR5K_BEACON_5210 : AR5K_BEACON_5211)
01244 #define AR5K_BEACON_PERIOD      0x0000ffff      /* Mask for beacon period */
01245 #define AR5K_BEACON_PERIOD_S    0
01246 #define AR5K_BEACON_TIM         0x007f0000      /* Mask for TIM offset */
01247 #define AR5K_BEACON_TIM_S       16
01248 #define AR5K_BEACON_ENABLE      0x00800000      /* Enable beacons */
01249 #define AR5K_BEACON_RESET_TSF   0x01000000      /* Force TSF reset */
01250 
01251 /*
01252  * CFP period register
01253  */
01254 #define AR5K_CFP_PERIOD_5210    0x8028
01255 #define AR5K_CFP_PERIOD_5211    0x8024
01256 #define AR5K_CFP_PERIOD         (ah->ah_version == AR5K_AR5210 ? \
01257                                 AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)
01258 
01259 /*
01260  * Next beacon time register
01261  */
01262 #define AR5K_TIMER0_5210        0x802c
01263 #define AR5K_TIMER0_5211        0x8028
01264 #define AR5K_TIMER0             (ah->ah_version == AR5K_AR5210 ? \
01265                                 AR5K_TIMER0_5210 : AR5K_TIMER0_5211)
01266 
01267 /*
01268  * Next DMA beacon alert register
01269  */
01270 #define AR5K_TIMER1_5210        0x8030
01271 #define AR5K_TIMER1_5211        0x802c
01272 #define AR5K_TIMER1             (ah->ah_version == AR5K_AR5210 ? \
01273                                 AR5K_TIMER1_5210 : AR5K_TIMER1_5211)
01274 
01275 /*
01276  * Next software beacon alert register
01277  */
01278 #define AR5K_TIMER2_5210        0x8034
01279 #define AR5K_TIMER2_5211        0x8030
01280 #define AR5K_TIMER2             (ah->ah_version == AR5K_AR5210 ? \
01281                                 AR5K_TIMER2_5210 : AR5K_TIMER2_5211)
01282 
01283 /*
01284  * Next ATIM window time register
01285  */
01286 #define AR5K_TIMER3_5210        0x8038
01287 #define AR5K_TIMER3_5211        0x8034
01288 #define AR5K_TIMER3             (ah->ah_version == AR5K_AR5210 ? \
01289                                 AR5K_TIMER3_5210 : AR5K_TIMER3_5211)
01290 
01291 
01292 /*
01293  * 5210 First inter frame spacing register (IFS)
01294  */
01295 #define AR5K_IFS0               0x8040
01296 #define AR5K_IFS0_SIFS          0x000007ff
01297 #define AR5K_IFS0_SIFS_S        0
01298 #define AR5K_IFS0_DIFS          0x007ff800
01299 #define AR5K_IFS0_DIFS_S        11
01300 
01301 /*
01302  * 5210 Second inter frame spacing register (IFS)
01303  */
01304 #define AR5K_IFS1               0x8044
01305 #define AR5K_IFS1_PIFS          0x00000fff
01306 #define AR5K_IFS1_PIFS_S        0
01307 #define AR5K_IFS1_EIFS          0x03fff000
01308 #define AR5K_IFS1_EIFS_S        12
01309 #define AR5K_IFS1_CS_EN         0x04000000
01310 
01311 
01312 /*
01313  * CFP duration register
01314  */
01315 #define AR5K_CFP_DUR_5210       0x8048
01316 #define AR5K_CFP_DUR_5211       0x8038
01317 #define AR5K_CFP_DUR            (ah->ah_version == AR5K_AR5210 ? \
01318                                 AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)
01319 
01320 /*
01321  * Receive filter register
01322  */
01323 #define AR5K_RX_FILTER_5210     0x804c                  /* Register Address [5210] */
01324 #define AR5K_RX_FILTER_5211     0x803c                  /* Register Address [5211+] */
01325 #define AR5K_RX_FILTER          (ah->ah_version == AR5K_AR5210 ? \
01326                                 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
01327 #define AR5K_RX_FILTER_UCAST    0x00000001      /* Don't filter unicast frames */
01328 #define AR5K_RX_FILTER_MCAST    0x00000002      /* Don't filter multicast frames */
01329 #define AR5K_RX_FILTER_BCAST    0x00000004      /* Don't filter broadcast frames */
01330 #define AR5K_RX_FILTER_CONTROL  0x00000008      /* Don't filter control frames */
01331 #define AR5K_RX_FILTER_BEACON   0x00000010      /* Don't filter beacon frames */
01332 #define AR5K_RX_FILTER_PROM     0x00000020      /* Set promiscuous mode */
01333 #define AR5K_RX_FILTER_XRPOLL   0x00000040      /* Don't filter XR poll frame [5212+] */
01334 #define AR5K_RX_FILTER_PROBEREQ 0x00000080      /* Don't filter probe requests [5212+] */
01335 #define AR5K_RX_FILTER_PHYERR_5212      0x00000100      /* Don't filter phy errors [5212+] */
01336 #define AR5K_RX_FILTER_RADARERR_5212    0x00000200      /* Don't filter phy radar errors [5212+] */
01337 #define AR5K_RX_FILTER_PHYERR_5211      0x00000040      /* [5211] */
01338 #define AR5K_RX_FILTER_RADARERR_5211    0x00000080      /* [5211] */
01339 #define AR5K_RX_FILTER_PHYERR  \
01340         ((ah->ah_version == AR5K_AR5211 ? \
01341         AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))
01342 #define        AR5K_RX_FILTER_RADARERR \
01343         ((ah->ah_version == AR5K_AR5211 ? \
01344         AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))
01345 
01346 /*
01347  * Multicast filter register (lower 32 bits)
01348  */
01349 #define AR5K_MCAST_FILTER0_5210 0x8050
01350 #define AR5K_MCAST_FILTER0_5211 0x8040
01351 #define AR5K_MCAST_FILTER0      (ah->ah_version == AR5K_AR5210 ? \
01352                                 AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)
01353 
01354 /*
01355  * Multicast filter register (higher 16 bits)
01356  */
01357 #define AR5K_MCAST_FILTER1_5210 0x8054
01358 #define AR5K_MCAST_FILTER1_5211 0x8044
01359 #define AR5K_MCAST_FILTER1      (ah->ah_version == AR5K_AR5210 ? \
01360                                 AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)
01361 
01362 
01363 /*
01364  * Transmit mask register (lower 32 bits) [5210]
01365  */
01366 #define AR5K_TX_MASK0   0x8058
01367 
01368 /*
01369  * Transmit mask register (higher 16 bits) [5210]
01370  */
01371 #define AR5K_TX_MASK1   0x805c
01372 
01373 /*
01374  * Clear transmit mask [5210]
01375  */
01376 #define AR5K_CLR_TMASK  0x8060
01377 
01378 /*
01379  * Trigger level register (before transmission) [5210]
01380  */
01381 #define AR5K_TRIG_LVL   0x8064
01382 
01383 
01384 /*
01385  * PCU control register
01386  *
01387  * Only DIS_RX is used in the code, the rest i guess are
01388  * for tweaking/diagnostics.
01389  */
01390 #define AR5K_DIAG_SW_5210               0x8068                  /* Register Address [5210] */
01391 #define AR5K_DIAG_SW_5211               0x8048                  /* Register Address [5211+] */
01392 #define AR5K_DIAG_SW                    (ah->ah_version == AR5K_AR5210 ? \
01393                                         AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
01394 #define AR5K_DIAG_SW_DIS_WEP_ACK        0x00000001      /* Disable ACKs if WEP key is invalid */
01395 #define AR5K_DIAG_SW_DIS_ACK            0x00000002      /* Disable ACKs */
01396 #define AR5K_DIAG_SW_DIS_CTS            0x00000004      /* Disable CTSs */
01397 #define AR5K_DIAG_SW_DIS_ENC            0x00000008      /* Disable encryption */
01398 #define AR5K_DIAG_SW_DIS_DEC            0x00000010      /* Disable decryption */
01399 #define AR5K_DIAG_SW_DIS_TX             0x00000020      /* Disable transmit [5210] */
01400 #define AR5K_DIAG_SW_DIS_RX_5210        0x00000040      /* Disable recieve */
01401 #define AR5K_DIAG_SW_DIS_RX_5211        0x00000020
01402 #define AR5K_DIAG_SW_DIS_RX             (ah->ah_version == AR5K_AR5210 ? \
01403                                         AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
01404 #define AR5K_DIAG_SW_LOOP_BACK_5210     0x00000080      /* Loopback (i guess it goes with DIS_TX) [5210] */
01405 #define AR5K_DIAG_SW_LOOP_BACK_5211     0x00000040
01406 #define AR5K_DIAG_SW_LOOP_BACK          (ah->ah_version == AR5K_AR5210 ? \
01407                                         AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
01408 #define AR5K_DIAG_SW_CORR_FCS_5210      0x00000100      /* Corrupted FCS */
01409 #define AR5K_DIAG_SW_CORR_FCS_5211      0x00000080
01410 #define AR5K_DIAG_SW_CORR_FCS           (ah->ah_version == AR5K_AR5210 ? \
01411                                         AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
01412 #define AR5K_DIAG_SW_CHAN_INFO_5210     0x00000200      /* Dump channel info */
01413 #define AR5K_DIAG_SW_CHAN_INFO_5211     0x00000100
01414 #define AR5K_DIAG_SW_CHAN_INFO          (ah->ah_version == AR5K_AR5210 ? \
01415                                         AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
01416 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400      /* Enable fixed scrambler seed */
01417 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
01418 #define AR5K_DIAG_SW_EN_SCRAM_SEED      (ah->ah_version == AR5K_AR5210 ? \
01419                                         AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
01420 #define AR5K_DIAG_SW_ECO_ENABLE         0x00000400      /* [5211+] */
01421 #define AR5K_DIAG_SW_SCVRAM_SEED        0x0003f800      /* [5210] */
01422 #define AR5K_DIAG_SW_SCRAM_SEED_M       0x0001fc00      /* Scrambler seed mask */
01423 #define AR5K_DIAG_SW_SCRAM_SEED_S       10
01424 #define AR5K_DIAG_SW_DIS_SEQ_INC        0x00040000      /* Disable seqnum increment (?)[5210] */
01425 #define AR5K_DIAG_SW_FRAME_NV0_5210     0x00080000
01426 #define AR5K_DIAG_SW_FRAME_NV0_5211     0x00020000      /* Accept frames of non-zero protocol number */
01427 #define AR5K_DIAG_SW_FRAME_NV0          (ah->ah_version == AR5K_AR5210 ? \
01428                                         AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
01429 #define AR5K_DIAG_SW_OBSPT_M            0x000c0000      /* Observation point select (?) */
01430 #define AR5K_DIAG_SW_OBSPT_S            18
01431 #define AR5K_DIAG_SW_RX_CLEAR_HIGH      0x0010000       /* Force RX Clear high */
01432 #define AR5K_DIAG_SW_IGNORE_CARR_SENSE  0x0020000       /* Ignore virtual carrier sense */
01433 #define AR5K_DIAG_SW_CHANEL_IDLE_HIGH   0x0040000       /* Force channel idle high */
01434 #define AR5K_DIAG_SW_PHEAR_ME           0x0080000       /* ??? */
01435 
01436 /*
01437  * TSF (clock) register (lower 32 bits)
01438  */
01439 #define AR5K_TSF_L32_5210       0x806c
01440 #define AR5K_TSF_L32_5211       0x804c
01441 #define AR5K_TSF_L32            (ah->ah_version == AR5K_AR5210 ? \
01442                                 AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)
01443 
01444 /*
01445  * TSF (clock) register (higher 32 bits)
01446  */
01447 #define AR5K_TSF_U32_5210       0x8070
01448 #define AR5K_TSF_U32_5211       0x8050
01449 #define AR5K_TSF_U32            (ah->ah_version == AR5K_AR5210 ? \
01450                                 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
01451 
01452 /*
01453  * Last beacon timestamp register (Read Only)
01454  */
01455 #define AR5K_LAST_TSTP  0x8080
01456 
01457 /*
01458  * ADDAC test register [5211+]
01459  */
01460 #define AR5K_ADDAC_TEST                 0x8054                  /* Register Address */
01461 #define AR5K_ADDAC_TEST_TXCONT          0x00000001      /* Test continuous tx */
01462 #define AR5K_ADDAC_TEST_TST_MODE        0x00000002      /* Test mode */
01463 #define AR5K_ADDAC_TEST_LOOP_EN         0x00000004      /* Enable loop */
01464 #define AR5K_ADDAC_TEST_LOOP_LEN        0x00000008      /* Loop length (field) */
01465 #define AR5K_ADDAC_TEST_USE_U8          0x00004000      /* Use upper 8 bits */
01466 #define AR5K_ADDAC_TEST_MSB             0x00008000      /* State of MSB */
01467 #define AR5K_ADDAC_TEST_TRIG_SEL        0x00010000      /* Trigger select */
01468 #define AR5K_ADDAC_TEST_TRIG_PTY        0x00020000      /* Trigger polarity */
01469 #define AR5K_ADDAC_TEST_RXCONT          0x00040000      /* Continuous capture */
01470 #define AR5K_ADDAC_TEST_CAPTURE         0x00080000      /* Begin capture */
01471 #define AR5K_ADDAC_TEST_TST_ARM         0x00100000      /* ARM rx buffer for capture */
01472 
01473 /*
01474  * Default antenna register [5211+]
01475  */
01476 #define AR5K_DEFAULT_ANTENNA    0x8058
01477 
01478 /*
01479  * Frame control QoS mask register (?) [5211+]
01480  * (FC_QOS_MASK)
01481  */
01482 #define AR5K_FRAME_CTL_QOSM     0x805c
01483 
01484 /*
01485  * Seq mask register (?) [5211+]
01486  */
01487 #define AR5K_SEQ_MASK   0x8060
01488 
01489 /*
01490  * Retry count register [5210]
01491  */
01492 #define AR5K_RETRY_CNT          0x8084                  /* Register Address [5210] */
01493 #define AR5K_RETRY_CNT_SSH      0x0000003f      /* Station short retry count (?) */
01494 #define AR5K_RETRY_CNT_SLG      0x00000fc0      /* Station long retry count (?) */
01495 
01496 /*
01497  * Back-off status register [5210]
01498  */
01499 #define AR5K_BACKOFF            0x8088                  /* Register Address [5210] */
01500 #define AR5K_BACKOFF_CW         0x000003ff      /* Backoff Contention Window (?) */
01501 #define AR5K_BACKOFF_CNT        0x03ff0000      /* Backoff count (?) */
01502 
01503 
01504 
01505 /*
01506  * NAV register (current)
01507  */
01508 #define AR5K_NAV_5210           0x808c
01509 #define AR5K_NAV_5211           0x8084
01510 #define AR5K_NAV                (ah->ah_version == AR5K_AR5210 ? \
01511                                 AR5K_NAV_5210 : AR5K_NAV_5211)
01512 
01513 /*
01514  * RTS success register
01515  */
01516 #define AR5K_RTS_OK_5210        0x8090
01517 #define AR5K_RTS_OK_5211        0x8088
01518 #define AR5K_RTS_OK             (ah->ah_version == AR5K_AR5210 ? \
01519                                 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
01520 
01521 /*
01522  * RTS failure register
01523  */
01524 #define AR5K_RTS_FAIL_5210      0x8094
01525 #define AR5K_RTS_FAIL_5211      0x808c
01526 #define AR5K_RTS_FAIL           (ah->ah_version == AR5K_AR5210 ? \
01527                                 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
01528 
01529 /*
01530  * ACK failure register
01531  */
01532 #define AR5K_ACK_FAIL_5210      0x8098
01533 #define AR5K_ACK_FAIL_5211      0x8090
01534 #define AR5K_ACK_FAIL           (ah->ah_version == AR5K_AR5210 ? \
01535                                 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
01536 
01537 /*
01538  * FCS failure register
01539  */
01540 #define AR5K_FCS_FAIL_5210      0x809c
01541 #define AR5K_FCS_FAIL_5211      0x8094
01542 #define AR5K_FCS_FAIL           (ah->ah_version == AR5K_AR5210 ? \
01543                                 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)
01544 
01545 /*
01546  * Beacon count register
01547  */
01548 #define AR5K_BEACON_CNT_5210    0x80a0
01549 #define AR5K_BEACON_CNT_5211    0x8098
01550 #define AR5K_BEACON_CNT         (ah->ah_version == AR5K_AR5210 ? \
01551                                 AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)
01552 
01553 
01554 /*===5212 Specific PCU registers===*/
01555 
01556 /*
01557  * Transmit power control register
01558  */
01559 #define AR5K_TPC                        0x80e8
01560 #define AR5K_TPC_ACK                    0x0000003f      /* ack frames */
01561 #define AR5K_TPC_ACK_S                  0
01562 #define AR5K_TPC_CTS                    0x00003f00      /* cts frames */
01563 #define AR5K_TPC_CTS_S                  8
01564 #define AR5K_TPC_CHIRP                  0x003f0000      /* chirp frames */
01565 #define AR5K_TPC_CHIRP_S                16
01566 #define AR5K_TPC_DOPPLER                0x0f000000      /* doppler chirp span */
01567 #define AR5K_TPC_DOPPLER_S              24
01568 
01569 /*
01570  * XR (eXtended Range) mode register
01571  */
01572 #define AR5K_XRMODE                     0x80c0                  /* Register Address */
01573 #define AR5K_XRMODE_POLL_TYPE_M         0x0000003f      /* Mask for Poll type (?) */
01574 #define AR5K_XRMODE_POLL_TYPE_S         0
01575 #define AR5K_XRMODE_POLL_SUBTYPE_M      0x0000003c      /* Mask for Poll subtype (?) */
01576 #define AR5K_XRMODE_POLL_SUBTYPE_S      2
01577 #define AR5K_XRMODE_POLL_WAIT_ALL       0x00000080      /* Wait for poll */
01578 #define AR5K_XRMODE_SIFS_DELAY          0x000fff00      /* Mask for SIFS delay */
01579 #define AR5K_XRMODE_FRAME_HOLD_M        0xfff00000      /* Mask for frame hold (?) */
01580 #define AR5K_XRMODE_FRAME_HOLD_S        20
01581 
01582 /*
01583  * XR delay register
01584  */
01585 #define AR5K_XRDELAY                    0x80c4                  /* Register Address */
01586 #define AR5K_XRDELAY_SLOT_DELAY_M       0x0000ffff      /* Mask for slot delay */
01587 #define AR5K_XRDELAY_SLOT_DELAY_S       0
01588 #define AR5K_XRDELAY_CHIRP_DELAY_M      0xffff0000      /* Mask for CHIRP data delay */
01589 #define AR5K_XRDELAY_CHIRP_DELAY_S      16
01590 
01591 /*
01592  * XR timeout register
01593  */
01594 #define AR5K_XRTIMEOUT                  0x80c8                  /* Register Address */
01595 #define AR5K_XRTIMEOUT_CHIRP_M          0x0000ffff      /* Mask for CHIRP timeout */
01596 #define AR5K_XRTIMEOUT_CHIRP_S          0
01597 #define AR5K_XRTIMEOUT_POLL_M           0xffff0000      /* Mask for Poll timeout */
01598 #define AR5K_XRTIMEOUT_POLL_S           16
01599 
01600 /*
01601  * XR chirp register
01602  */
01603 #define AR5K_XRCHIRP                    0x80cc                  /* Register Address */
01604 #define AR5K_XRCHIRP_SEND               0x00000001      /* Send CHIRP */
01605 #define AR5K_XRCHIRP_GAP                0xffff0000      /* Mask for CHIRP gap (?) */
01606 
01607 /*
01608  * XR stomp register
01609  */
01610 #define AR5K_XRSTOMP                    0x80d0                  /* Register Address */
01611 #define AR5K_XRSTOMP_TX                 0x00000001      /* Stomp Tx (?) */
01612 #define AR5K_XRSTOMP_RX                 0x00000002      /* Stomp Rx (?) */
01613 #define AR5K_XRSTOMP_TX_RSSI            0x00000004      /* Stomp Tx RSSI (?) */
01614 #define AR5K_XRSTOMP_TX_BSSID           0x00000008      /* Stomp Tx BSSID (?) */
01615 #define AR5K_XRSTOMP_DATA               0x00000010      /* Stomp data (?)*/
01616 #define AR5K_XRSTOMP_RSSI_THRES         0x0000ff00      /* Mask for XR RSSI threshold */
01617 
01618 /*
01619  * First enhanced sleep register
01620  */
01621 #define AR5K_SLEEP0                     0x80d4                  /* Register Address */
01622 #define AR5K_SLEEP0_NEXT_DTIM           0x0007ffff      /* Mask for next DTIM (?) */
01623 #define AR5K_SLEEP0_NEXT_DTIM_S         0
01624 #define AR5K_SLEEP0_ASSUME_DTIM         0x00080000      /* Assume DTIM */
01625 #define AR5K_SLEEP0_ENH_SLEEP_EN        0x00100000      /* Enable enchanced sleep control */
01626 #define AR5K_SLEEP0_CABTO               0xff000000      /* Mask for CAB Time Out */
01627 #define AR5K_SLEEP0_CABTO_S             24
01628 
01629 /*
01630  * Second enhanced sleep register
01631  */
01632 #define AR5K_SLEEP1                     0x80d8                  /* Register Address */
01633 #define AR5K_SLEEP1_NEXT_TIM            0x0007ffff      /* Mask for next TIM (?) */
01634 #define AR5K_SLEEP1_NEXT_TIM_S          0
01635 #define AR5K_SLEEP1_BEACON_TO           0xff000000      /* Mask for Beacon Time Out */
01636 #define AR5K_SLEEP1_BEACON_TO_S         24
01637 
01638 /*
01639  * Third enhanced sleep register
01640  */
01641 #define AR5K_SLEEP2                     0x80dc                  /* Register Address */
01642 #define AR5K_SLEEP2_TIM_PER             0x0000ffff      /* Mask for TIM period (?) */
01643 #define AR5K_SLEEP2_TIM_PER_S           0
01644 #define AR5K_SLEEP2_DTIM_PER            0xffff0000      /* Mask for DTIM period (?) */
01645 #define AR5K_SLEEP2_DTIM_PER_S          16
01646 
01647 /*
01648  * BSSID mask registers
01649  */
01650 #define AR5K_BSS_IDM0                   0x80e0  /* Upper bits */
01651 #define AR5K_BSS_IDM1                   0x80e4  /* Lower bits */
01652 
01653 /*
01654  * TX power control (TPC) register
01655  *
01656  * XXX: PCDAC steps (0.5dbm) or DBM ?
01657  *
01658  */
01659 #define AR5K_TXPC                       0x80e8                  /* Register Address */
01660 #define AR5K_TXPC_ACK_M                 0x0000003f      /* ACK tx power */
01661 #define AR5K_TXPC_ACK_S                 0
01662 #define AR5K_TXPC_CTS_M                 0x00003f00      /* CTS tx power */
01663 #define AR5K_TXPC_CTS_S                 8
01664 #define AR5K_TXPC_CHIRP_M               0x003f0000      /* CHIRP tx power */
01665 #define AR5K_TXPC_CHIRP_S               16
01666 #define AR5K_TXPC_DOPPLER               0x0f000000      /* Doppler chirp span (?) */
01667 #define AR5K_TXPC_DOPPLER_S             24
01668 
01669 /*
01670  * Profile count registers
01671  */
01672 #define AR5K_PROFCNT_TX                 0x80ec  /* Tx count */
01673 #define AR5K_PROFCNT_RX                 0x80f0  /* Rx count */
01674 #define AR5K_PROFCNT_RXCLR              0x80f4  /* Clear Rx count */
01675 #define AR5K_PROFCNT_CYCLE              0x80f8  /* Cycle count (?) */
01676 
01677 /*
01678  * Quiet period control registers
01679  */
01680 #define AR5K_QUIET_CTL1                 0x80fc                  /* Register Address */
01681 #define AR5K_QUIET_CTL1_NEXT_QT_TSF     0x0000ffff      /* Next quiet period TSF (TU) */
01682 #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S   0
01683 #define AR5K_QUIET_CTL1_QT_EN           0x00010000      /* Enable quiet period */
01684 #define AR5K_QUIET_CTL1_ACK_CTS_EN      0x00020000      /* Send ACK/CTS during quiet period */
01685 
01686 #define AR5K_QUIET_CTL2                 0x8100                  /* Register Address */
01687 #define AR5K_QUIET_CTL2_QT_PER          0x0000ffff      /* Mask for quiet period periodicity */
01688 #define AR5K_QUIET_CTL2_QT_PER_S        0
01689 #define AR5K_QUIET_CTL2_QT_DUR          0xffff0000      /* Mask for quiet period duration */
01690 #define AR5K_QUIET_CTL2_QT_DUR_S        16
01691 
01692 /*
01693  * TSF parameter register
01694  */
01695 #define AR5K_TSF_PARM                   0x8104                  /* Register Address */
01696 #define AR5K_TSF_PARM_INC               0x000000ff      /* Mask for TSF increment */
01697 #define AR5K_TSF_PARM_INC_S             0
01698 
01699 /*
01700  * QoS NOACK policy
01701  */
01702 #define AR5K_QOS_NOACK                  0x8108                  /* Register Address */
01703 #define AR5K_QOS_NOACK_2BIT_VALUES      0x0000000f      /* ??? */
01704 #define AR5K_QOS_NOACK_2BIT_VALUES_S    0
01705 #define AR5K_QOS_NOACK_BIT_OFFSET       0x00000070      /* ??? */
01706 #define AR5K_QOS_NOACK_BIT_OFFSET_S     4
01707 #define AR5K_QOS_NOACK_BYTE_OFFSET      0x00000180      /* ??? */
01708 #define AR5K_QOS_NOACK_BYTE_OFFSET_S    7
01709 
01710 /*
01711  * PHY error filter register
01712  */
01713 #define AR5K_PHY_ERR_FIL                0x810c
01714 #define AR5K_PHY_ERR_FIL_RADAR          0x00000020      /* Radar signal */
01715 #define AR5K_PHY_ERR_FIL_OFDM           0x00020000      /* OFDM false detect (ANI) */
01716 #define AR5K_PHY_ERR_FIL_CCK            0x02000000      /* CCK false detect (ANI) */
01717 
01718 /*
01719  * XR latency register
01720  */
01721 #define AR5K_XRLAT_TX           0x8110
01722 
01723 /*
01724  * ACK SIFS register
01725  */
01726 #define AR5K_ACKSIFS            0x8114                  /* Register Address */
01727 #define AR5K_ACKSIFS_INC        0x00000000      /* ACK SIFS Increment (field) */
01728 
01729 /*
01730  * MIC QoS control register (?)
01731  */
01732 #define AR5K_MIC_QOS_CTL                0x8118                  /* Register Address */
01733 #define AR5K_MIC_QOS_CTL_OFF(_n)        (1 << (_n * 2))
01734 #define AR5K_MIC_QOS_CTL_MQ_EN          0x00010000      /* Enable MIC QoS */
01735 
01736 /*
01737  * MIC QoS select register (?)
01738  */
01739 #define AR5K_MIC_QOS_SEL                0x811c
01740 #define AR5K_MIC_QOS_SEL_OFF(_n)        (1 << (_n * 4))
01741 
01742 /*
01743  * Misc mode control register (?)
01744  */
01745 #define AR5K_MISC_MODE                  0x8120                  /* Register Address */
01746 #define AR5K_MISC_MODE_FBSSID_MATCH     0x00000001      /* Force BSSID match */
01747 #define AR5K_MISC_MODE_ACKSIFS_MEM      0x00000002      /* ACK SIFS memory (?) */
01748 #define AR5K_MISC_MODE_COMBINED_MIC     0x00000004      /* use rx/tx MIC key */
01749 /* more bits */
01750 
01751 /*
01752  * OFDM Filter counter
01753  */
01754 #define AR5K_OFDM_FIL_CNT               0x8124
01755 
01756 /*
01757  * CCK Filter counter
01758  */
01759 #define AR5K_CCK_FIL_CNT                0x8128
01760 
01761 /*
01762  * PHY Error Counters (?)
01763  */
01764 #define AR5K_PHYERR_CNT1                0x812c
01765 #define AR5K_PHYERR_CNT1_MASK           0x8130
01766 
01767 #define AR5K_PHYERR_CNT2                0x8134
01768 #define AR5K_PHYERR_CNT2_MASK           0x8138
01769 
01770 /*
01771  * TSF Threshold register (?)
01772  */
01773 #define AR5K_TSF_THRES                  0x813c
01774 
01775 /*
01776  * TODO: Wake On Wireless registers
01777  * Range: 0x8147 - 0x818c
01778  */
01779 
01780 /*
01781  * Rate -> ACK SIFS mapping table (32 entries)
01782  */
01783 #define AR5K_RATE_ACKSIFS_BASE          0x8680                  /* Register Address */
01784 #define AR5K_RATE_ACKSIFS(_n)           (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))
01785 #define AR5K_RATE_ACKSIFS_NORMAL        0x00000001      /* Normal SIFS (field) */
01786 #define AR5K_RATE_ACKSIFS_TURBO         0x00000400      /* Turbo SIFS (field) */
01787 
01788 /*
01789  * Rate -> duration mapping table (32 entries)
01790  */
01791 #define AR5K_RATE_DUR_BASE              0x8700
01792 #define AR5K_RATE_DUR(_n)               (AR5K_RATE_DUR_BASE + ((_n) << 2))
01793 
01794 /*
01795  * Rate -> db mapping table
01796  * (8 entries, each one has 4 8bit fields)
01797  */
01798 #define AR5K_RATE2DB_BASE               0x87c0
01799 #define AR5K_RATE2DB(_n)                (AR5K_RATE2DB_BASE + ((_n) << 2))
01800 
01801 /*
01802  * db -> Rate mapping table
01803  * (8 entries, each one has 4 8bit fields)
01804  */
01805 #define AR5K_DB2RATE_BASE               0x87e0
01806 #define AR5K_DB2RATE(_n)                (AR5K_DB2RATE_BASE + ((_n) << 2))
01807 
01808 /*===5212 end===*/
01809 
01810 /*
01811  * Key table (WEP) register
01812  */
01813 #define AR5K_KEYTABLE_0_5210            0x9000
01814 #define AR5K_KEYTABLE_0_5211            0x8800
01815 #define AR5K_KEYTABLE_5210(_n)          (AR5K_KEYTABLE_0_5210 + ((_n) << 5))
01816 #define AR5K_KEYTABLE_5211(_n)          (AR5K_KEYTABLE_0_5211 + ((_n) << 5))
01817 #define AR5K_KEYTABLE(_n)               (ah->ah_version == AR5K_AR5210 ? \
01818                                         AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))
01819 #define AR5K_KEYTABLE_OFF(_n, x)        (AR5K_KEYTABLE(_n) + (x << 2))
01820 #define AR5K_KEYTABLE_TYPE(_n)          AR5K_KEYTABLE_OFF(_n, 5)
01821 #define AR5K_KEYTABLE_TYPE_40           0x00000000
01822 #define AR5K_KEYTABLE_TYPE_104          0x00000001
01823 #define AR5K_KEYTABLE_TYPE_128          0x00000003
01824 #define AR5K_KEYTABLE_TYPE_TKIP         0x00000004      /* [5212+] */
01825 #define AR5K_KEYTABLE_TYPE_AES          0x00000005      /* [5211+] */
01826 #define AR5K_KEYTABLE_TYPE_CCM          0x00000006      /* [5212+] */
01827 #define AR5K_KEYTABLE_TYPE_NULL         0x00000007      /* [5211+] */
01828 #define AR5K_KEYTABLE_ANTENNA           0x00000008      /* [5212+] */
01829 #define AR5K_KEYTABLE_MAC0(_n)          AR5K_KEYTABLE_OFF(_n, 6)
01830 #define AR5K_KEYTABLE_MAC1(_n)          AR5K_KEYTABLE_OFF(_n, 7)
01831 #define AR5K_KEYTABLE_VALID             0x00008000
01832 
01833 /* If key type is TKIP and MIC is enabled
01834  * MIC key goes in offset entry + 64 */
01835 #define AR5K_KEYTABLE_MIC_OFFSET        64
01836 
01837 /* WEP 40-bit   = 40-bit  entered key + 24 bit IV = 64-bit
01838  * WEP 104-bit  = 104-bit entered key + 24-bit IV = 128-bit
01839  * WEP 128-bit  = 128-bit entered key + 24 bit IV = 152-bit
01840  *
01841  * Some vendors have introduced bigger WEP keys to address
01842  * security vulnerabilities in WEP. This includes:
01843  *
01844  * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit
01845  *
01846  * We can expand this if we find ar5k Atheros cards with a larger
01847  * key table size.
01848  */
01849 #define AR5K_KEYTABLE_SIZE_5210         64
01850 #define AR5K_KEYTABLE_SIZE_5211         128
01851 #define AR5K_KEYTABLE_SIZE              (ah->ah_version == AR5K_AR5210 ? \
01852                                         AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)
01853 
01854 
01855 /*===PHY REGISTERS===*/
01856 
01857 /*
01858  * PHY registers start
01859  */
01860 #define AR5K_PHY_BASE                   0x9800
01861 #define AR5K_PHY(_n)                    (AR5K_PHY_BASE + ((_n) << 2))
01862 
01863 /*
01864  * TST_2 (Misc config parameters)
01865  */
01866 #define AR5K_PHY_TST2                   0x9800                  /* Register Address */
01867 #define AR5K_PHY_TST2_TRIG_SEL          0x00000007      /* Trigger select (?)*/
01868 #define AR5K_PHY_TST2_TRIG              0x00000010      /* Trigger (?) */
01869 #define AR5K_PHY_TST2_CBUS_MODE         0x00000060      /* Cardbus mode (?) */
01870 #define AR5K_PHY_TST2_CLK32             0x00000400      /* CLK_OUT is CLK32 (32Khz external) */
01871 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN   0x00000800      /* Enable Chancor dump (?) */
01872 #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000      /* Even Chancor dump (?) */
01873 #define AR5K_PHY_TST2_RFSILENT_EN       0x00002000      /* Enable RFSILENT */
01874 #define AR5K_PHY_TST2_ALT_RFDATA        0x00004000      /* Alternate RFDATA (5-2GHz switch ?) */
01875 #define AR5K_PHY_TST2_MINI_OBS_EN       0x00008000      /* Enable mini OBS (?) */
01876 #define AR5K_PHY_TST2_RX2_IS_RX5_INV    0x00010000      /* 2GHz rx path is the 5GHz path inverted (?) */
01877 #define AR5K_PHY_TST2_SLOW_CLK160       0x00020000      /* Slow CLK160 (?) */
01878 #define AR5K_PHY_TST2_AGC_OBS_SEL_3     0x00040000      /* AGC OBS Select 3 (?) */
01879 #define AR5K_PHY_TST2_BBB_OBS_SEL       0x00080000      /* BB OBS Select (field ?) */
01880 #define AR5K_PHY_TST2_ADC_OBS_SEL       0x00800000      /* ADC OBS Select (field ?) */
01881 #define AR5K_PHY_TST2_RX_CLR_SEL        0x08000000      /* RX Clear Select (?) */
01882 #define AR5K_PHY_TST2_FORCE_AGC_CLR     0x10000000      /* Force AGC clear (?) */
01883 #define AR5K_PHY_SHIFT_2GHZ             0x00004007      /* Used to access 2GHz radios */
01884 #define AR5K_PHY_SHIFT_5GHZ             0x00000007      /* Used to access 5GHz radios (default) */
01885 
01886 /*
01887  * PHY frame control register [5110] /turbo mode register [5111+]
01888  *
01889  * There is another frame control register for [5111+]
01890  * at address 0x9944 (see below) but the 2 first flags
01891  * are common here between 5110 frame control register
01892  * and [5111+] turbo mode register, so this also works as
01893  * a "turbo mode register" for 5110. We treat this one as
01894  * a frame control register for 5110 below.
01895  */
01896 #define AR5K_PHY_TURBO                  0x9804                  /* Register Address */
01897 #define AR5K_PHY_TURBO_MODE             0x00000001      /* Enable turbo mode */
01898 #define AR5K_PHY_TURBO_SHORT            0x00000002      /* Set short symbols to turbo mode */
01899 #define AR5K_PHY_TURBO_MIMO             0x00000004      /* Set turbo for mimo mimo */
01900 
01901 /*
01902  * PHY agility command register
01903  * (aka TST_1)
01904  */
01905 #define AR5K_PHY_AGC                    0x9808                  /* Register Address */
01906 #define AR5K_PHY_TST1                   0x9808
01907 #define AR5K_PHY_AGC_DISABLE            0x08000000      /* Disable AGC to A2 (?)*/
01908 #define AR5K_PHY_TST1_TXHOLD            0x00003800      /* Set tx hold (?) */
01909 #define AR5K_PHY_TST1_TXSRC_SRC         0x00000002      /* Used with bit 7 (?) */
01910 #define AR5K_PHY_TST1_TXSRC_SRC_S       1
01911 #define AR5K_PHY_TST1_TXSRC_ALT         0x00000080      /* Set input to tsdac (?) */
01912 #define AR5K_PHY_TST1_TXSRC_ALT_S       7
01913 
01914 
01915 /*
01916  * PHY timing register 3 [5112+]
01917  */
01918 #define AR5K_PHY_TIMING_3               0x9814
01919 #define AR5K_PHY_TIMING_3_DSC_MAN       0xfffe0000
01920 #define AR5K_PHY_TIMING_3_DSC_MAN_S     17
01921 #define AR5K_PHY_TIMING_3_DSC_EXP       0x0001e000
01922 #define AR5K_PHY_TIMING_3_DSC_EXP_S     13
01923 
01924 /*
01925  * PHY chip revision register
01926  */
01927 #define AR5K_PHY_CHIP_ID                0x9818
01928 
01929 /*
01930  * PHY activation register
01931  */
01932 #define AR5K_PHY_ACT                    0x981c                  /* Register Address */
01933 #define AR5K_PHY_ACT_ENABLE             0x00000001      /* Activate PHY */
01934 #define AR5K_PHY_ACT_DISABLE            0x00000002      /* Deactivate PHY */
01935 
01936 /*
01937  * PHY RF control registers
01938  */
01939 #define AR5K_PHY_RF_CTL2                0x9824                  /* Register Address */
01940 #define AR5K_PHY_RF_CTL2_TXF2TXD_START  0x0000000f      /* TX frame to TX data start */
01941 #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S        0
01942 
01943 #define AR5K_PHY_RF_CTL3                0x9828                  /* Register Address */
01944 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON    0x0000ff00      /* TX end to XLNA on */
01945 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S  8
01946 
01947 #define AR5K_PHY_ADC_CTL                        0x982c
01948 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF          0x00000003
01949 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S        0
01950 #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF            0x00002000
01951 #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF       0x00004000
01952 #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF            0x00008000
01953 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON           0x00030000
01954 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S         16
01955 
01956 #define AR5K_PHY_RF_CTL4                0x9834                  /* Register Address */
01957 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON   0x00000001      /* TX frame to XPA A on (field) */
01958 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON   0x00000100      /* TX frame to XPA B on (field) */
01959 #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF  0x00010000      /* TX end to XPA A off (field) */
01960 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF  0x01000000      /* TX end to XPA B off (field) */
01961 
01962 /*
01963  * Pre-Amplifier control register
01964  * (XPA -> external pre-amplifier)
01965  */
01966 #define AR5K_PHY_PA_CTL                 0x9838                  /* Register Address */
01967 #define AR5K_PHY_PA_CTL_XPA_A_HI        0x00000001      /* XPA A high (?) */
01968 #define AR5K_PHY_PA_CTL_XPA_B_HI        0x00000002      /* XPA B high (?) */
01969 #define AR5K_PHY_PA_CTL_XPA_A_EN        0x00000004      /* Enable XPA A */
01970 #define AR5K_PHY_PA_CTL_XPA_B_EN        0x00000008      /* Enable XPA B */
01971 
01972 /*
01973  * PHY settling register
01974  */
01975 #define AR5K_PHY_SETTLING               0x9844                  /* Register Address */
01976 #define AR5K_PHY_SETTLING_AGC           0x0000007f      /* AGC settling time */
01977 #define AR5K_PHY_SETTLING_AGC_S         0
01978 #define AR5K_PHY_SETTLING_SWITCH        0x00003f80      /* Switch settlig time */
01979 #define AR5K_PHY_SETTLING_SWITCH_S      7
01980 
01981 /*
01982  * PHY Gain registers
01983  */
01984 #define AR5K_PHY_GAIN                   0x9848                  /* Register Address */
01985 #define AR5K_PHY_GAIN_TXRX_ATTEN        0x0003f000      /* TX-RX Attenuation */
01986 #define AR5K_PHY_GAIN_TXRX_ATTEN_S      12
01987 #define AR5K_PHY_GAIN_TXRX_RF_MAX       0x007c0000
01988 #define AR5K_PHY_GAIN_TXRX_RF_MAX_S     18
01989 
01990 #define AR5K_PHY_GAIN_OFFSET            0x984c                  /* Register Address */
01991 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG  0x00020000      /* RX-TX flag (?) */
01992 
01993 /*
01994  * Desired ADC/PGA size register
01995  * (for more infos read ANI patent)
01996  */
01997 #define AR5K_PHY_DESIRED_SIZE           0x9850                  /* Register Address */
01998 #define AR5K_PHY_DESIRED_SIZE_ADC       0x000000ff      /* ADC desired size */
01999 #define AR5K_PHY_DESIRED_SIZE_ADC_S     0
02000 #define AR5K_PHY_DESIRED_SIZE_PGA       0x0000ff00      /* PGA desired size */
02001 #define AR5K_PHY_DESIRED_SIZE_PGA_S     8
02002 #define AR5K_PHY_DESIRED_SIZE_TOT       0x0ff00000      /* Total desired size */
02003 #define AR5K_PHY_DESIRED_SIZE_TOT_S     20
02004 
02005 /*
02006  * PHY signal register
02007  * (for more infos read ANI patent)
02008  */
02009 #define AR5K_PHY_SIG                    0x9858                  /* Register Address */
02010 #define AR5K_PHY_SIG_FIRSTEP            0x0003f000      /* FIRSTEP */
02011 #define AR5K_PHY_SIG_FIRSTEP_S          12
02012 #define AR5K_PHY_SIG_FIRPWR             0x03fc0000      /* FIPWR */
02013 #define AR5K_PHY_SIG_FIRPWR_S           18
02014 
02015 /*
02016  * PHY coarse agility control register
02017  * (for more infos read ANI patent)
02018  */
02019 #define AR5K_PHY_AGCCOARSE              0x985c                  /* Register Address */
02020 #define AR5K_PHY_AGCCOARSE_LO           0x00007f80      /* AGC Coarse low */
02021 #define AR5K_PHY_AGCCOARSE_LO_S         7
02022 #define AR5K_PHY_AGCCOARSE_HI           0x003f8000      /* AGC Coarse high */
02023 #define AR5K_PHY_AGCCOARSE_HI_S         15
02024 
02025 /*
02026  * PHY agility control register
02027  */
02028 #define AR5K_PHY_AGCCTL                 0x9860                  /* Register address */
02029 #define AR5K_PHY_AGCCTL_CAL             0x00000001      /* Enable PHY calibration */
02030 #define AR5K_PHY_AGCCTL_NF              0x00000002      /* Enable Noise Floor calibration */
02031 #define AR5K_PHY_AGCCTL_NF_EN           0x00008000      /* Enable nf calibration to happen (?) */
02032 #define AR5K_PHY_AGCCTL_NF_NOUPDATE     0x00020000      /* Don't update nf automaticaly */
02033 
02034 /*
02035  * PHY noise floor status register
02036  */
02037 #define AR5K_PHY_NF                     0x9864                  /* Register address */
02038 #define AR5K_PHY_NF_M                   0x000001ff      /* Noise floor mask */
02039 #define AR5K_PHY_NF_ACTIVE              0x00000100      /* Noise floor calibration still active */
02040 #define AR5K_PHY_NF_RVAL(_n)            (((_n) >> 19) & AR5K_PHY_NF_M)
02041 #define AR5K_PHY_NF_AVAL(_n)            (-((_n) ^ AR5K_PHY_NF_M) + 1)
02042 #define AR5K_PHY_NF_SVAL(_n)            (((_n) & AR5K_PHY_NF_M) | (1 << 9))
02043 #define AR5K_PHY_NF_THRESH62            0x0007f000      /* Thresh62 -check ANI patent- (field) */
02044 #define AR5K_PHY_NF_THRESH62_S          12
02045 #define AR5K_PHY_NF_MINCCA_PWR          0x0ff80000      /* ??? */
02046 #define AR5K_PHY_NF_MINCCA_PWR_S        19
02047 
02048 /*
02049  * PHY ADC saturation register [5110]
02050  */
02051 #define AR5K_PHY_ADCSAT                 0x9868
02052 #define AR5K_PHY_ADCSAT_ICNT            0x0001f800
02053 #define AR5K_PHY_ADCSAT_ICNT_S          11
02054 #define AR5K_PHY_ADCSAT_THR             0x000007e0
02055 #define AR5K_PHY_ADCSAT_THR_S           5
02056 
02057 /*
02058  * PHY Weak ofdm signal detection threshold registers (ANI) [5212+]
02059  */
02060 
02061 /* High thresholds */
02062 #define AR5K_PHY_WEAK_OFDM_HIGH_THR             0x9868
02063 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT    0x0000001f
02064 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S  0
02065 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1          0x00fe0000
02066 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S        17
02067 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2          0x7f000000
02068 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S        24
02069 
02070 /* Low thresholds */
02071 #define AR5K_PHY_WEAK_OFDM_LOW_THR              0x986c
02072 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN   0x00000001
02073 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT     0x00003f00
02074 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S   8
02075 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1           0x001fc000
02076 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S         14
02077 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2           0x0fe00000
02078 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S         21
02079 
02080 
02081 /*
02082  * PHY sleep registers [5112+]
02083  */
02084 #define AR5K_PHY_SCR                    0x9870
02085 
02086 #define AR5K_PHY_SLMT                   0x9874
02087 #define AR5K_PHY_SLMT_32MHZ             0x0000007f
02088 
02089 #define AR5K_PHY_SCAL                   0x9878
02090 #define AR5K_PHY_SCAL_32MHZ             0x0000000e
02091 #define AR5K_PHY_SCAL_32MHZ_2417        0x0000000a
02092 #define AR5K_PHY_SCAL_32MHZ_HB63        0x00000032
02093 
02094 /*
02095  * PHY PLL (Phase Locked Loop) control register
02096  */
02097 #define AR5K_PHY_PLL                    0x987c
02098 #define AR5K_PHY_PLL_20MHZ              0x00000013      /* For half rate (?) */
02099 /* 40MHz -> 5GHz band */
02100 #define AR5K_PHY_PLL_40MHZ_5211         0x00000018
02101 #define AR5K_PHY_PLL_40MHZ_5212         0x000000aa
02102 #define AR5K_PHY_PLL_40MHZ_5413         0x00000004
02103 #define AR5K_PHY_PLL_40MHZ              (ah->ah_version == AR5K_AR5211 ? \
02104                                         AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
02105 /* 44MHz -> 2.4GHz band */
02106 #define AR5K_PHY_PLL_44MHZ_5211         0x00000019
02107 #define AR5K_PHY_PLL_44MHZ_5212         0x000000ab
02108 #define AR5K_PHY_PLL_44MHZ              (ah->ah_version == AR5K_AR5211 ? \
02109                                         AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
02110 
02111 #define AR5K_PHY_PLL_RF5111             0x00000000
02112 #define AR5K_PHY_PLL_RF5112             0x00000040
02113 #define AR5K_PHY_PLL_HALF_RATE          0x00000100
02114 #define AR5K_PHY_PLL_QUARTER_RATE       0x00000200
02115 
02116 /*
02117  * RF Buffer register
02118  *
02119  * It's obvious from the code that 0x989c is the buffer register but
02120  * for the other special registers that we write to after sending each
02121  * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers
02122  * for now. It's interesting that they are also used for some other operations.
02123  */
02124 
02125 #define AR5K_RF_BUFFER                  0x989c
02126 #define AR5K_RF_BUFFER_CONTROL_0        0x98c0  /* Channel on 5110 */
02127 #define AR5K_RF_BUFFER_CONTROL_1        0x98c4  /* Bank 7 on 5112 */
02128 #define AR5K_RF_BUFFER_CONTROL_2        0x98cc  /* Bank 7 on 5111 */
02129 
02130 #define AR5K_RF_BUFFER_CONTROL_3        0x98d0  /* Bank 2 on 5112 */
02131                                                 /* Channel set on 5111 */
02132                                                 /* Used to read radio revision*/
02133 
02134 #define AR5K_RF_BUFFER_CONTROL_4        0x98d4  /* RF Stage register on 5110 */
02135                                                 /* Bank 0,1,2,6 on 5111 */
02136                                                 /* Bank 1 on 5112 */
02137                                                 /* Used during activation on 5111 */
02138 
02139 #define AR5K_RF_BUFFER_CONTROL_5        0x98d8  /* Bank 3 on 5111 */
02140                                                 /* Used during activation on 5111 */
02141                                                 /* Channel on 5112 */
02142                                                 /* Bank 6 on 5112 */
02143 
02144 #define AR5K_RF_BUFFER_CONTROL_6        0x98dc  /* Bank 3 on 5112 */
02145 
02146 /*
02147  * PHY RF stage register [5210]
02148  */
02149 #define AR5K_PHY_RFSTG                  0x98d4
02150 #define AR5K_PHY_RFSTG_DISABLE          0x00000021
02151 
02152 /*
02153  * BIN masks (?)
02154  */
02155 #define AR5K_PHY_BIN_MASK_1     0x9900
02156 #define AR5K_PHY_BIN_MASK_2     0x9904
02157 #define AR5K_PHY_BIN_MASK_3     0x9908
02158 
02159 #define AR5K_PHY_BIN_MASK_CTL           0x990c
02160 #define AR5K_PHY_BIN_MASK_CTL_MASK_4    0x00003fff
02161 #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S  0
02162 #define AR5K_PHY_BIN_MASK_CTL_RATE      0xff000000
02163 #define AR5K_PHY_BIN_MASK_CTL_RATE_S    24
02164 
02165 /*
02166  * PHY Antenna control register
02167  */
02168 #define AR5K_PHY_ANT_CTL                0x9910                  /* Register Address */
02169 #define AR5K_PHY_ANT_CTL_TXRX_EN        0x00000001      /* Enable TX/RX (?) */
02170 #define AR5K_PHY_ANT_CTL_SECTORED_ANT   0x00000004      /* Sectored Antenna */
02171 #define AR5K_PHY_ANT_CTL_HITUNE5        0x00000008      /* Hitune5 (?) */
02172 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE   0x000003f0      /* Switch table idle (?) */
02173 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
02174 
02175 /*
02176  * PHY receiver delay register [5111+]
02177  */
02178 #define AR5K_PHY_RX_DELAY               0x9914                  /* Register Address */
02179 #define AR5K_PHY_RX_DELAY_M             0x00003fff      /* Mask for RX activate to receive delay (/100ns) */
02180 
02181 /*
02182  * PHY max rx length register (?) [5111]
02183  */
02184 #define AR5K_PHY_MAX_RX_LEN             0x991c
02185 
02186 /*
02187  * PHY timing register 4
02188  * I(nphase)/Q(adrature) calibration register [5111+]
02189  */
02190 #define AR5K_PHY_IQ                     0x9920                  /* Register Address */
02191 #define AR5K_PHY_IQ_CORR_Q_Q_COFF       0x0000001f      /* Mask for q correction info */
02192 #define AR5K_PHY_IQ_CORR_Q_I_COFF       0x000007e0      /* Mask for i correction info */
02193 #define AR5K_PHY_IQ_CORR_Q_I_COFF_S     5
02194 #define AR5K_PHY_IQ_CORR_ENABLE         0x00000800      /* Enable i/q correction */
02195 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX     0x0000f000      /* Mask for max number of samples in log scale */
02196 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S   12
02197 #define AR5K_PHY_IQ_RUN                 0x00010000      /* Run i/q calibration */
02198 #define AR5K_PHY_IQ_USE_PT_DF           0x00020000      /* Use pilot track df (?) */
02199 #define AR5K_PHY_IQ_EARLY_TRIG_THR      0x00200000      /* Early trigger threshold (?) (field) */
02200 #define AR5K_PHY_IQ_PILOT_MASK_EN       0x10000000      /* Enable pilot mask (?) */
02201 #define AR5K_PHY_IQ_CHAN_MASK_EN        0x20000000      /* Enable channel mask (?) */
02202 #define AR5K_PHY_IQ_SPUR_FILT_EN        0x40000000      /* Enable spur filter */
02203 #define AR5K_PHY_IQ_SPUR_RSSI_EN        0x80000000      /* Enable spur rssi */
02204 
02205 /*
02206  * PHY timing register 5
02207  * OFDM Self-correlator Cyclic RSSI threshold params
02208  * (Check out bb_cycpwr_thr1 on ANI patent)
02209  */
02210 #define AR5K_PHY_OFDM_SELFCORR                  0x9924                  /* Register Address */
02211 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN    0x00000001      /* Enable cyclic RSSI thr 1 */
02212 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1       0x000000fe      /* Mask for Cyclic RSSI threshold 1 */
02213 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S     1
02214 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3       0x00000100      /* Cyclic RSSI threshold 3 (field) (?) */
02215 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN    0x00008000      /* Enable 1A RSSI threshold (?) */
02216 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR       0x00010000      /* 1A RSSI threshold (field) (?) */
02217 #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI    0x00800000      /* Long sc threshold hi rssi (?) */
02218 
02219 /*
02220  * PHY-only warm reset register
02221  */
02222 #define AR5K_PHY_WARM_RESET             0x9928
02223 
02224 /*
02225  * PHY-only control register
02226  */
02227 #define AR5K_PHY_CTL                    0x992c                  /* Register Address */
02228 #define AR5K_PHY_CTL_RX_DRAIN_RATE      0x00000001      /* RX drain rate (?) */
02229 #define AR5K_PHY_CTL_LATE_TX_SIG_SYM    0x00000002      /* Late tx signal symbol (?) */
02230 #define AR5K_PHY_CTL_GEN_SCRAMBLER      0x00000004      /* Generate scrambler */
02231 #define AR5K_PHY_CTL_TX_ANT_SEL         0x00000008      /* TX antenna select */
02232 #define AR5K_PHY_CTL_TX_ANT_STATIC      0x00000010      /* Static TX antenna */
02233 #define AR5K_PHY_CTL_RX_ANT_SEL         0x00000020      /* RX antenna select */
02234 #define AR5K_PHY_CTL_RX_ANT_STATIC      0x00000040      /* Static RX antenna */
02235 #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN    0x00000080      /* Enable low freq sleep */
02236 
02237 /*
02238  * PHY PAPD probe register [5111+]
02239  */
02240 #define AR5K_PHY_PAPD_PROBE             0x9930
02241 #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR   0x00000001
02242 #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS  0x00000002
02243 #define AR5K_PHY_PAPD_PROBE_COMP_GAIN   0x00000040
02244 #define AR5K_PHY_PAPD_PROBE_TXPOWER     0x00007e00
02245 #define AR5K_PHY_PAPD_PROBE_TXPOWER_S   9
02246 #define AR5K_PHY_PAPD_PROBE_TX_NEXT     0x00008000
02247 #define AR5K_PHY_PAPD_PROBE_PREDIST_EN  0x00010000
02248 #define AR5K_PHY_PAPD_PROBE_TYPE        0x01800000      /* [5112+] */
02249 #define AR5K_PHY_PAPD_PROBE_TYPE_S      23
02250 #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM   0
02251 #define AR5K_PHY_PAPD_PROBE_TYPE_XR     1
02252 #define AR5K_PHY_PAPD_PROBE_TYPE_CCK    2
02253 #define AR5K_PHY_PAPD_PROBE_GAINF       0xfe000000
02254 #define AR5K_PHY_PAPD_PROBE_GAINF_S     25
02255 #define AR5K_PHY_PAPD_PROBE_INI_5111    0x00004883      /* [5212+] */
02256 #define AR5K_PHY_PAPD_PROBE_INI_5112    0x00004882      /* [5212+] */
02257 
02258 /*
02259  * PHY TX rate power registers [5112+]
02260  */
02261 #define AR5K_PHY_TXPOWER_RATE1                  0x9934
02262 #define AR5K_PHY_TXPOWER_RATE2                  0x9938
02263 #define AR5K_PHY_TXPOWER_RATE_MAX               0x993c
02264 #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE    0x00000040
02265 #define AR5K_PHY_TXPOWER_RATE3                  0xa234
02266 #define AR5K_PHY_TXPOWER_RATE4                  0xa238
02267 
02268 /*
02269  * PHY frame control register [5111+]
02270  */
02271 #define AR5K_PHY_FRAME_CTL_5210         0x9804
02272 #define AR5K_PHY_FRAME_CTL_5211         0x9944
02273 #define AR5K_PHY_FRAME_CTL              (ah->ah_version == AR5K_AR5210 ? \
02274                                         AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
02275 /*---[5111+]---*/
02276 #define AR5K_PHY_FRAME_CTL_TX_CLIP      0x00000038      /* Mask for tx clip (?) */
02277 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S    3
02278 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO  0x00010000      /* Prepend chan info */
02279 #define AR5K_PHY_FRAME_CTL_EMU          0x80000000
02280 #define AR5K_PHY_FRAME_CTL_EMU_S        31
02281 /*---[5110/5111]---*/
02282 #define AR5K_PHY_FRAME_CTL_TIMING_ERR   0x01000000      /* PHY timing error */
02283 #define AR5K_PHY_FRAME_CTL_PARITY_ERR   0x02000000      /* Parity error */
02284 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR  0x04000000      /* Illegal rate */
02285 #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR   0x08000000      /* Illegal length */
02286 #define AR5K_PHY_FRAME_CTL_SERVICE_ERR  0x20000000
02287 #define AR5K_PHY_FRAME_CTL_TXURN_ERR    0x40000000      /* TX underrun */
02288 #define AR5K_PHY_FRAME_CTL_INI          AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
02289                         AR5K_PHY_FRAME_CTL_TXURN_ERR | \
02290                         AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
02291                         AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
02292                         AR5K_PHY_FRAME_CTL_PARITY_ERR | \
02293                         AR5K_PHY_FRAME_CTL_TIMING_ERR
02294 
02295 /*
02296  * PHY Tx Power adjustment register [5212A+]
02297  */
02298 #define AR5K_PHY_TX_PWR_ADJ                     0x994c
02299 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA      0x00000fc0
02300 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S    6
02301 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX     0x00fc0000
02302 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S   18
02303 
02304 /*
02305  * PHY radar detection register [5111+]
02306  */
02307 #define AR5K_PHY_RADAR                  0x9954
02308 #define AR5K_PHY_RADAR_ENABLE           0x00000001
02309 #define AR5K_PHY_RADAR_DISABLE          0x00000000
02310 #define AR5K_PHY_RADAR_INBANDTHR        0x0000003e      /* Inband threshold
02311                                                         5-bits, units unknown {0..31}
02312                                                         (? MHz ?) */
02313 #define AR5K_PHY_RADAR_INBANDTHR_S      1
02314 
02315 #define AR5K_PHY_RADAR_PRSSI_THR        0x00000fc0      /* Pulse RSSI/SNR threshold
02316                                                         6-bits, dBm range {0..63}
02317                                                         in dBm units. */
02318 #define AR5K_PHY_RADAR_PRSSI_THR_S      6
02319 
02320 #define AR5K_PHY_RADAR_PHEIGHT_THR      0x0003f000      /* Pulse height threshold
02321                                                         6-bits, dBm range {0..63}
02322                                                         in dBm units. */
02323 #define AR5K_PHY_RADAR_PHEIGHT_THR_S    12
02324 
02325 #define AR5K_PHY_RADAR_RSSI_THR         0x00fc0000      /* Radar RSSI/SNR threshold.
02326                                                         6-bits, dBm range {0..63}
02327                                                         in dBm units. */
02328 #define AR5K_PHY_RADAR_RSSI_THR_S       18
02329 
02330 #define AR5K_PHY_RADAR_FIRPWR_THR       0x7f000000      /* Finite Impulse Response
02331                                                         filter power out threshold.
02332                                                         7-bits, standard power range
02333                                                         {0..127} in 1/2 dBm units. */
02334 #define AR5K_PHY_RADAR_FIRPWR_THRS      24
02335 
02336 /*
02337  * PHY antenna switch table registers
02338  */
02339 #define AR5K_PHY_ANT_SWITCH_TABLE_0     0x9960
02340 #define AR5K_PHY_ANT_SWITCH_TABLE_1     0x9964
02341 
02342 /*
02343  * PHY Noise floor threshold
02344  */
02345 #define AR5K_PHY_NFTHRES                0x9968
02346 
02347 /*
02348  * Sigma Delta register (?) [5213]
02349  */
02350 #define AR5K_PHY_SIGMA_DELTA            0x996C
02351 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL    0x00000003
02352 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S  0
02353 #define AR5K_PHY_SIGMA_DELTA_FILT2      0x000000f8
02354 #define AR5K_PHY_SIGMA_DELTA_FILT2_S    3
02355 #define AR5K_PHY_SIGMA_DELTA_FILT1      0x00001f00
02356 #define AR5K_PHY_SIGMA_DELTA_FILT1_S    8
02357 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP   0x01ffe000
02358 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
02359 
02360 /*
02361  * RF restart register [5112+] (?)
02362  */
02363 #define AR5K_PHY_RESTART                0x9970          /* restart */
02364 #define AR5K_PHY_RESTART_DIV_GC         0x001c0000      /* Fast diversity gc_limit (?) */
02365 #define AR5K_PHY_RESTART_DIV_GC_S       18
02366 
02367 /*
02368  * RF Bus access request register (for synth-oly channel switching)
02369  */
02370 #define AR5K_PHY_RFBUS_REQ              0x997C
02371 #define AR5K_PHY_RFBUS_REQ_REQUEST      0x00000001
02372 
02373 /*
02374  * Spur mitigation masks (?)
02375  */
02376 #define AR5K_PHY_TIMING_7               0x9980
02377 #define AR5K_PHY_TIMING_8               0x9984
02378 #define AR5K_PHY_TIMING_8_PILOT_MASK_2          0x000fffff
02379 #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S        0
02380 
02381 #define AR5K_PHY_BIN_MASK2_1            0x9988
02382 #define AR5K_PHY_BIN_MASK2_2            0x998c
02383 #define AR5K_PHY_BIN_MASK2_3            0x9990
02384 
02385 #define AR5K_PHY_BIN_MASK2_4            0x9994
02386 #define AR5K_PHY_BIN_MASK2_4_MASK_4     0x00003fff
02387 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S   0
02388 
02389 #define AR5K_PHY_TIMING_9                       0x9998
02390 #define AR5K_PHY_TIMING_10                      0x999c
02391 #define AR5K_PHY_TIMING_10_PILOT_MASK_2         0x000fffff
02392 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S       0
02393 
02394 /*
02395  * Spur mitigation control
02396  */
02397 #define AR5K_PHY_TIMING_11                      0x99a0          /* Register address */
02398 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE     0x000fffff      /* Spur delta phase */
02399 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S   0
02400 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD         0x3ff00000      /* Freq sigma delta */
02401 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S       20
02402 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC      0x40000000      /* Spur filter in AGC detector */
02403 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR  0x80000000      /* Spur filter in OFDM self correlator */
02404 
02405 /*
02406  * Gain tables
02407  */
02408 #define AR5K_BB_GAIN_BASE               0x9b00  /* BaseBand Amplifier Gain table base address */
02409 #define AR5K_BB_GAIN(_n)                (AR5K_BB_GAIN_BASE + ((_n) << 2))
02410 #define AR5K_RF_GAIN_BASE               0x9a00  /* RF Amplrifier Gain table base address */
02411 #define AR5K_RF_GAIN(_n)                (AR5K_RF_GAIN_BASE + ((_n) << 2))
02412 
02413 /*
02414  * PHY timing IQ calibration result register [5111+]
02415  */
02416 #define AR5K_PHY_IQRES_CAL_PWR_I        0x9c10  /* I (Inphase) power value */
02417 #define AR5K_PHY_IQRES_CAL_PWR_Q        0x9c14  /* Q (Quadrature) power value */
02418 #define AR5K_PHY_IQRES_CAL_CORR         0x9c18  /* I/Q Correlation */
02419 
02420 /*
02421  * PHY current RSSI register [5111+]
02422  */
02423 #define AR5K_PHY_CURRENT_RSSI   0x9c1c
02424 
02425 /*
02426  * PHY RF Bus grant register
02427  */
02428 #define AR5K_PHY_RFBUS_GRANT    0x9c20
02429 #define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
02430 
02431 /*
02432  * PHY ADC test register
02433  */
02434 #define AR5K_PHY_ADC_TEST       0x9c24
02435 #define AR5K_PHY_ADC_TEST_I     0x00000001
02436 #define AR5K_PHY_ADC_TEST_Q     0x00000200
02437 
02438 /*
02439  * PHY DAC test register
02440  */
02441 #define AR5K_PHY_DAC_TEST       0x9c28
02442 #define AR5K_PHY_DAC_TEST_I     0x00000001
02443 #define AR5K_PHY_DAC_TEST_Q     0x00000200
02444 
02445 /*
02446  * PHY PTAT register (?)
02447  */
02448 #define AR5K_PHY_PTAT           0x9c2c
02449 
02450 /*
02451  * PHY Illegal TX rate register [5112+]
02452  */
02453 #define AR5K_PHY_BAD_TX_RATE    0x9c30
02454 
02455 /*
02456  * PHY SPUR Power register [5112+]
02457  */
02458 #define AR5K_PHY_SPUR_PWR       0x9c34                  /* Register Address */
02459 #define AR5K_PHY_SPUR_PWR_I     0x00000001      /* SPUR Power estimate for I (field) */
02460 #define AR5K_PHY_SPUR_PWR_Q     0x00000100      /* SPUR Power estimate for Q (field) */
02461 #define AR5K_PHY_SPUR_PWR_FILT  0x00010000      /* Power with SPUR removed (field) */
02462 
02463 /*
02464  * PHY Channel status register [5112+] (?)
02465  */
02466 #define AR5K_PHY_CHAN_STATUS            0x9c38
02467 #define AR5K_PHY_CHAN_STATUS_BT_ACT     0x00000001
02468 #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002
02469 #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004
02470 #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
02471 
02472 /*
02473  * Heavy clip enable register
02474  */
02475 #define AR5K_PHY_HEAVY_CLIP_ENABLE      0x99e0
02476 
02477 /*
02478  * PHY clock sleep registers [5112+]
02479  */
02480 #define AR5K_PHY_SCLOCK                 0x99f0
02481 #define AR5K_PHY_SCLOCK_32MHZ           0x0000000c
02482 #define AR5K_PHY_SDELAY                 0x99f4
02483 #define AR5K_PHY_SDELAY_32MHZ           0x000000ff
02484 #define AR5K_PHY_SPENDING               0x99f8
02485 
02486 
02487 /*
02488  * PHY PAPD I (power?) table (?)
02489  * (92! entries)
02490  */
02491 #define AR5K_PHY_PAPD_I_BASE    0xa000
02492 #define AR5K_PHY_PAPD_I(_n)     (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))
02493 
02494 /*
02495  * PHY PCDAC TX power table
02496  */
02497 #define AR5K_PHY_PCDAC_TXPOWER_BASE     0xa180
02498 #define AR5K_PHY_PCDAC_TXPOWER(_n)      (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
02499 
02500 /*
02501  * PHY mode register [5111+]
02502  */
02503 #define AR5K_PHY_MODE                   0x0a200                 /* Register Address */
02504 #define AR5K_PHY_MODE_MOD               0x00000001      /* PHY Modulation bit */
02505 #define AR5K_PHY_MODE_MOD_OFDM          0
02506 #define AR5K_PHY_MODE_MOD_CCK           1
02507 #define AR5K_PHY_MODE_FREQ              0x00000002      /* Freq mode bit */
02508 #define AR5K_PHY_MODE_FREQ_5GHZ         0
02509 #define AR5K_PHY_MODE_FREQ_2GHZ         2
02510 #define AR5K_PHY_MODE_MOD_DYN           0x00000004      /* Enable Dynamic OFDM/CCK mode [5112+] */
02511 #define AR5K_PHY_MODE_RAD               0x00000008      /* [5212+] */
02512 #define AR5K_PHY_MODE_RAD_RF5111        0
02513 #define AR5K_PHY_MODE_RAD_RF5112        8
02514 #define AR5K_PHY_MODE_XR                0x00000010      /* Enable XR mode [5112+] */
02515 #define AR5K_PHY_MODE_HALF_RATE         0x00000020      /* Enable Half rate (test) */
02516 #define AR5K_PHY_MODE_QUARTER_RATE      0x00000040      /* Enable Quarter rat (test) */
02517 
02518 /*
02519  * PHY CCK transmit control register [5111+ (?)]
02520  */
02521 #define AR5K_PHY_CCKTXCTL               0xa204
02522 #define AR5K_PHY_CCKTXCTL_WORLD         0x00000000
02523 #define AR5K_PHY_CCKTXCTL_JAPAN         0x00000010
02524 #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001
02525 #define AR5K_PHY_CCKTXCTK_DAC_SCALE     0x00000004
02526 
02527 /*
02528  * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]
02529  */
02530 #define AR5K_PHY_CCK_CROSSCORR                  0xa208
02531 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR     0x0000000f
02532 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S   0
02533 
02534 /* Same address is used for antenna diversity activation */
02535 #define AR5K_PHY_FAST_ANT_DIV           0xa208
02536 #define AR5K_PHY_FAST_ANT_DIV_EN        0x00002000
02537 
02538 /*
02539  * PHY 2GHz gain register [5111+]
02540  */
02541 #define AR5K_PHY_GAIN_2GHZ                      0xa20c
02542 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX          0x00fc0000
02543 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S        18
02544 #define AR5K_PHY_GAIN_2GHZ_INI_5111             0x6480416c
02545 
02546 #define AR5K_PHY_CCK_RX_CTL_4                   0xa21c
02547 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT    0x01f80000
02548 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S  19
02549 
02550 #define AR5K_PHY_DAG_CCK_CTL                    0xa228
02551 #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR        0x00000200
02552 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR           0x0001fc00
02553 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S         10
02554 
02555 #define AR5K_PHY_FAST_ADC       0xa24c
02556 
02557 #define AR5K_PHY_BLUETOOTH      0xa254
02558 
02559 /*
02560  * Transmit Power Control register
02561  * [2413+]
02562  */
02563 #define AR5K_PHY_TPC_RG1                0xa258
02564 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN    0x0000c000
02565 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S  14
02566 #define AR5K_PHY_TPC_RG1_PDGAIN_1       0x00030000
02567 #define AR5K_PHY_TPC_RG1_PDGAIN_1_S     16
02568 #define AR5K_PHY_TPC_RG1_PDGAIN_2       0x000c0000
02569 #define AR5K_PHY_TPC_RG1_PDGAIN_2_S     18
02570 #define AR5K_PHY_TPC_RG1_PDGAIN_3       0x00300000
02571 #define AR5K_PHY_TPC_RG1_PDGAIN_3_S     20
02572 
02573 #define AR5K_PHY_TPC_RG5                        0xa26C
02574 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP        0x0000000F
02575 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S      0
02576 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1     0x000003F0
02577 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S   4
02578 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2     0x0000FC00
02579 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S   10
02580 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3     0x003F0000
02581 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S   16
02582 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4     0x0FC00000
02583 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S   22
02584 
02585 /*
02586  * PHY PDADC Tx power table
02587  */
02588 #define AR5K_PHY_PDADC_TXPOWER_BASE     0xa280
02589 #define AR5K_PHY_PDADC_TXPOWER(_n)      (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))