iPXE
Data Structures | Defines | Enumerations | Functions
ath5k.h File Reference
#include <stddef.h>
#include <byteswap.h>
#include <ipxe/io.h>
#include <ipxe/netdevice.h>
#include <ipxe/net80211.h>
#include <errno.h>
#include "desc.h"
#include "eeprom.h"

Go to the source code of this file.

Data Structures

struct  ath5k_srev_name
struct  ath5k_tx_status
struct  ath5k_txq_info
struct  ath5k_rx_status
struct  ath5k_gain
struct  ath5k_athchan_2ghz
struct  ath5k_capabilities
struct  ath5k_hw
 ath5k_hw_get_isr - Get interrupt status More...

Defines

#define ERRFILE   ERRFILE_ath5k
#define PCI_DEVICE_ID_ATHEROS_AR5210   0x0007 /* AR5210 */
#define PCI_DEVICE_ID_ATHEROS_AR5311   0x0011 /* AR5311 */
#define PCI_DEVICE_ID_ATHEROS_AR5211   0x0012 /* AR5211 */
#define PCI_DEVICE_ID_ATHEROS_AR5212   0x0013 /* AR5212 */
#define PCI_DEVICE_ID_3COM_3CRDAG675   0x0013 /* 3CRDAG675 (Atheros AR5212) */
#define PCI_DEVICE_ID_3COM_2_3CRPAG175   0x0013 /* 3CRPAG175 (Atheros AR5212) */
#define PCI_DEVICE_ID_ATHEROS_AR5210_AP   0x0207 /* AR5210 (Early) */
#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM   0x1014 /* AR5212 (IBM MiniPCI) */
#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT   0x1107 /* AR5210 (no eeprom) */
#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT   0x1113 /* AR5212 (no eeprom) */
#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT   0x1112 /* AR5211 (no eeprom) */
#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA   0xf013 /* AR5212 (emulation board) */
#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY   0xff12 /* AR5211 (emulation board) */
#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B   0xf11b /* AR5211 (emulation board) */
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2   0x0052 /* AR5312 WMAC (AP31) */
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7   0x0057 /* AR5312 WMAC (AP30-040) */
#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8   0x0058 /* AR5312 WMAC (AP43-030) */
#define PCI_DEVICE_ID_ATHEROS_AR5212_0014   0x0014 /* AR5212 compatible */
#define PCI_DEVICE_ID_ATHEROS_AR5212_0015   0x0015 /* AR5212 compatible */
#define PCI_DEVICE_ID_ATHEROS_AR5212_0016   0x0016 /* AR5212 compatible */
#define PCI_DEVICE_ID_ATHEROS_AR5212_0017   0x0017 /* AR5212 compatible */
#define PCI_DEVICE_ID_ATHEROS_AR5212_0018   0x0018 /* AR5212 compatible */
#define PCI_DEVICE_ID_ATHEROS_AR5212_0019   0x0019 /* AR5212 compatible */
#define PCI_DEVICE_ID_ATHEROS_AR2413   0x001a /* AR2413 (Griffin-lite) */
#define PCI_DEVICE_ID_ATHEROS_AR5413   0x001b /* AR5413 (Eagle) */
#define PCI_DEVICE_ID_ATHEROS_AR5424   0x001c /* AR5424 (Condor PCI-E) */
#define PCI_DEVICE_ID_ATHEROS_AR5416   0x0023 /* AR5416 */
#define PCI_DEVICE_ID_ATHEROS_AR5418   0x0024 /* AR5418 */
#define AR5K_REG_SM(_val, _flags)   (((_val) << _flags##_S) & (_flags))
#define AR5K_REG_MS(_val, _flags)   (((_val) & (_flags)) >> _flags##_S)
#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)   ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)   ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
#define AR5K_PHY_READ(ah, _reg)   ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
#define AR5K_PHY_WRITE(ah, _reg, _val)   ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
#define AR5K_REG_READ_Q(ah, _reg, _queue)   (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
#define AR5K_REG_WRITE_Q(ah, _reg, _queue)   ath5k_hw_reg_write(ah, (1 << _queue), _reg)
#define AR5K_Q_ENABLE_BITS(_reg, _queue)
#define AR5K_Q_DISABLE_BITS(_reg, _queue)
#define AR5K_REG_WAIT(_i)
#define AR5K_INI_RFGAIN_5GHZ   0
#define AR5K_INI_RFGAIN_2GHZ   1
#define AR5K_INI_VAL_11A   0
#define AR5K_INI_VAL_11A_TURBO   1
#define AR5K_INI_VAL_11B   2
#define AR5K_INI_VAL_11G   3
#define AR5K_INI_VAL_11G_TURBO   4
#define AR5K_INI_VAL_XR   0
#define AR5K_INI_VAL_MAX   5
#define AR5K_LOW_ID(_a)
#define AR5K_HIGH_ID(_a)   ((_a)[4] | (_a)[5] << 8)
#define IEEE80211_MAX_LEN   2352
#define AR5K_TUNE_DMA_BEACON_RESP   2
#define AR5K_TUNE_SW_BEACON_RESP   10
#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF   0
#define AR5K_TUNE_RADAR_ALERT   0
#define AR5K_TUNE_MIN_TX_FIFO_THRES   1
#define AR5K_TUNE_MAX_TX_FIFO_THRES   ((IEEE80211_MAX_LEN / 64) + 1)
#define AR5K_TUNE_REGISTER_TIMEOUT   20000
#define AR5K_TUNE_RSSI_THRES   129
#define AR5K_TUNE_BMISS_THRES   7
#define AR5K_TUNE_REGISTER_DWELL_TIME   20000
#define AR5K_TUNE_BEACON_INTERVAL   100
#define AR5K_TUNE_AIFS   2
#define AR5K_TUNE_AIFS_11B   2
#define AR5K_TUNE_AIFS_XR   0
#define AR5K_TUNE_CWMIN   15
#define AR5K_TUNE_CWMIN_11B   31
#define AR5K_TUNE_CWMIN_XR   3
#define AR5K_TUNE_CWMAX   1023
#define AR5K_TUNE_CWMAX_11B   1023
#define AR5K_TUNE_CWMAX_XR   7
#define AR5K_TUNE_NOISE_FLOOR   -72
#define AR5K_TUNE_MAX_TXPOWER   63
#define AR5K_TUNE_DEFAULT_TXPOWER   25
#define AR5K_TUNE_TPC_TXPOWER   0
#define AR5K_TUNE_ANT_DIVERSITY   1
#define AR5K_TUNE_HWTXTRIES   4
#define AR5K_INIT_CARR_SENSE_EN   1
#define AR5K_INIT_CFG   0x00000000
#define AR5K_INIT_CYCRSSI_THR1   2
#define AR5K_INIT_TX_LATENCY   502
#define AR5K_INIT_USEC   39
#define AR5K_INIT_USEC_TURBO   79
#define AR5K_INIT_USEC_32   31
#define AR5K_INIT_SLOT_TIME   396
#define AR5K_INIT_SLOT_TIME_TURBO   480
#define AR5K_INIT_ACK_CTS_TIMEOUT   1024
#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO   0x08000800
#define AR5K_INIT_PROG_IFS   920
#define AR5K_INIT_PROG_IFS_TURBO   960
#define AR5K_INIT_EIFS   3440
#define AR5K_INIT_EIFS_TURBO   6880
#define AR5K_INIT_SIFS   560
#define AR5K_INIT_SIFS_TURBO   480
#define AR5K_INIT_SH_RETRY   10
#define AR5K_INIT_LG_RETRY   AR5K_INIT_SH_RETRY
#define AR5K_INIT_SSH_RETRY   32
#define AR5K_INIT_SLG_RETRY   AR5K_INIT_SSH_RETRY
#define AR5K_INIT_TX_RETRY   10
#define AR5K_INIT_TRANSMIT_LATENCY
#define AR5K_INIT_TRANSMIT_LATENCY_TURBO
#define AR5K_INIT_PROTO_TIME_CNTRL
#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO
#define AR5K_TXQ_USEDEFAULT   ((u32) -1)
#define AR5K_SREV_UNKNOWN   0xffff
#define AR5K_SREV_AR5210   0x00 /* Crete */
#define AR5K_SREV_AR5311   0x10 /* Maui 1 */
#define AR5K_SREV_AR5311A   0x20 /* Maui 2 */
#define AR5K_SREV_AR5311B   0x30 /* Spirit */
#define AR5K_SREV_AR5211   0x40 /* Oahu */
#define AR5K_SREV_AR5212   0x50 /* Venice */
#define AR5K_SREV_AR5213   0x55 /* ??? */
#define AR5K_SREV_AR5213A   0x59 /* Hainan */
#define AR5K_SREV_AR2413   0x78 /* Griffin lite */
#define AR5K_SREV_AR2414   0x70 /* Griffin */
#define AR5K_SREV_AR5424   0x90 /* Condor */
#define AR5K_SREV_AR5413   0xa4 /* Eagle lite */
#define AR5K_SREV_AR5414   0xa0 /* Eagle */
#define AR5K_SREV_AR2415   0xb0 /* Talon */
#define AR5K_SREV_AR5416   0xc0 /* PCI-E */
#define AR5K_SREV_AR5418   0xca /* PCI-E */
#define AR5K_SREV_AR2425   0xe0 /* Swan */
#define AR5K_SREV_AR2417   0xf0 /* Nala */
#define AR5K_SREV_RAD_5110   0x00
#define AR5K_SREV_RAD_5111   0x10
#define AR5K_SREV_RAD_5111A   0x15
#define AR5K_SREV_RAD_2111   0x20
#define AR5K_SREV_RAD_5112   0x30
#define AR5K_SREV_RAD_5112A   0x35
#define AR5K_SREV_RAD_5112B   0x36
#define AR5K_SREV_RAD_2112   0x40
#define AR5K_SREV_RAD_2112A   0x45
#define AR5K_SREV_RAD_2112B   0x46
#define AR5K_SREV_RAD_2413   0x50
#define AR5K_SREV_RAD_5413   0x60
#define AR5K_SREV_RAD_2316   0x70 /* Cobra SoC */
#define AR5K_SREV_RAD_2317   0x80
#define AR5K_SREV_RAD_5424   0xa0 /* Mostly same as 5413 */
#define AR5K_SREV_RAD_2425   0xa2
#define AR5K_SREV_RAD_5133   0xc0
#define AR5K_SREV_PHY_5211   0x30
#define AR5K_SREV_PHY_5212   0x41
#define AR5K_SREV_PHY_5212A   0x42
#define AR5K_SREV_PHY_5212B   0x43
#define AR5K_SREV_PHY_2413   0x45
#define AR5K_SREV_PHY_5413   0x61
#define AR5K_SREV_PHY_2425   0x70
#define MODULATION_XR   0x00000200
#define MODULATION_TURBO   0x00000080
#define AR5K_TXSTAT_ALTRATE   0x80
#define AR5K_TXERR_XRETRY   0x01
#define AR5K_TXERR_FILT   0x02
#define AR5K_TXERR_FIFO   0x04
#define AR5K_TXQ_FLAG_TXOKINT_ENABLE   0x0001 /* Enable TXOK interrupt */
#define AR5K_TXQ_FLAG_TXERRINT_ENABLE   0x0002 /* Enable TXERR interrupt */
#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE   0x0004 /* Enable TXEOL interrupt -not used- */
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE   0x0008 /* Enable TXDESC interrupt -not used- */
#define AR5K_TXQ_FLAG_TXURNINT_ENABLE   0x0010 /* Enable TXURN interrupt */
#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE   0x0020 /* Enable CBRORN interrupt */
#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE   0x0040 /* Enable CBRURN interrupt */
#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE   0x0080 /* Enable QTRIG interrupt */
#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE   0x0100 /* Enable TXNOFRM interrupt */
#define AR5K_TXQ_FLAG_BACKOFF_DISABLE   0x0200 /* Disable random post-backoff */
#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE   0x0300 /* Enable ready time expiry policy (?)*/
#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE   0x0800 /* Enable backoff while bursting */
#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS   0x1000 /* Disable backoff while bursting */
#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE   0x2000 /* Enable hw compression -not implemented-*/
#define AR5K_TXPOWER_OFDM(_r, _v)
#define AR5K_TXPOWER_CCK(_r, _v)
#define AR5K_RXERR_CRC   0x01
#define AR5K_RXERR_PHY   0x02
#define AR5K_RXERR_FIFO   0x04
#define AR5K_RXERR_DECRYPT   0x08
#define AR5K_RXERR_MIC   0x10
#define AR5K_RXKEYIX_INVALID   ((u8) - 1)
#define AR5K_TXKEYIX_INVALID   ((u32) - 1)
#define TSF_TO_TU(_tsf)   (u32)((_tsf) >> 10)
#define AR5K_SLOT_TIME_9   396
#define AR5K_SLOT_TIME_20   880
#define AR5K_SLOT_TIME_MAX   0xffff
#define CHANNEL_CW_INT   0x0008 /* Contention Window interference detected */
#define CHANNEL_TURBO   0x0010 /* Turbo Channel */
#define CHANNEL_CCK   0x0020 /* CCK channel */
#define CHANNEL_OFDM   0x0040 /* OFDM channel */
#define CHANNEL_2GHZ   0x0080 /* 2GHz channel. */
#define CHANNEL_5GHZ   0x0100 /* 5GHz channel */
#define CHANNEL_PASSIVE   0x0200 /* Only passive scan allowed */
#define CHANNEL_DYN   0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
#define CHANNEL_XR   0x0800 /* XR channel */
#define CHANNEL_A   (CHANNEL_5GHZ|CHANNEL_OFDM)
#define CHANNEL_B   (CHANNEL_2GHZ|CHANNEL_CCK)
#define CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_OFDM)
#define CHANNEL_T   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
#define CHANNEL_TG   (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
#define CHANNEL_108A   CHANNEL_T
#define CHANNEL_108G   CHANNEL_TG
#define CHANNEL_X   (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
#define CHANNEL_ALL
#define CHANNEL_ALL_NOTURBO   (CHANNEL_ALL & ~CHANNEL_TURBO)
#define CHANNEL_MODES   CHANNEL_ALL
#define IS_CHAN_XR(_c)   ((_c->hw_value & CHANNEL_XR) != 0)
#define IS_CHAN_B(_c)   ((_c->hw_value & CHANNEL_B) != 0)
#define AR5K_MAX_RATES   32
 Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
#define ATH5K_RATE_CODE_1M   0x1B
#define ATH5K_RATE_CODE_2M   0x1A
#define ATH5K_RATE_CODE_5_5M   0x19
#define ATH5K_RATE_CODE_11M   0x18
#define ATH5K_RATE_CODE_6M   0x0B
#define ATH5K_RATE_CODE_9M   0x0F
#define ATH5K_RATE_CODE_12M   0x0A
#define ATH5K_RATE_CODE_18M   0x0E
#define ATH5K_RATE_CODE_24M   0x09
#define ATH5K_RATE_CODE_36M   0x0D
#define ATH5K_RATE_CODE_48M   0x08
#define ATH5K_RATE_CODE_54M   0x0C
#define ATH5K_RATE_CODE_XR_500K   0x07
#define ATH5K_RATE_CODE_XR_1M   0x02
#define ATH5K_RATE_CODE_XR_2M   0x06
#define ATH5K_RATE_CODE_XR_3M   0x01
#define AR5K_SET_SHORT_PREAMBLE   0x04
#define AR5K_KEYCACHE_SIZE   8
#define AR5K_RSSI_EP_MULTIPLIER   (1<<7)
#define AR5K_ASSERT_ENTRY(_e, _s)
#define AR5K_SOFTLED_PIN   0
#define AR5K_SOFTLED_ON   0
#define AR5K_SOFTLED_OFF   1
#define AR5K_MAX_GPIO   10
#define AR5K_MAX_RF_BANKS   8
#define ah_regdomain   ah_capabilities.cap_regdomain.reg_current
#define ah_regdomain_hw   ah_capabilities.cap_regdomain.reg_hw
#define ah_modes   ah_capabilities.cap_mode
#define ah_ee_version   ah_capabilities.cap_eeprom.ee_version

Enumerations

enum  ath5k_version { AR5K_AR5210 = 0, AR5K_AR5211 = 1, AR5K_AR5212 = 2 }
enum  ath5k_radio {
  AR5K_RF5110 = 0, AR5K_RF5111 = 1, AR5K_RF5112 = 2, AR5K_RF2413 = 3,
  AR5K_RF5413 = 4, AR5K_RF2316 = 5, AR5K_RF2317 = 6, AR5K_RF2425 = 7
}
enum  ath5k_srev_type { AR5K_VERSION_MAC, AR5K_VERSION_RAD }
enum  ath5k_driver_mode {
  AR5K_MODE_11A = 0, AR5K_MODE_11A_TURBO = 1, AR5K_MODE_11B = 2, AR5K_MODE_11G = 3,
  AR5K_MODE_11G_TURBO = 4, AR5K_MODE_XR = 5
}
enum  {
  AR5K_MODE_BIT_11A = (1 << AR5K_MODE_11A), AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO), AR5K_MODE_BIT_11B = (1 << AR5K_MODE_11B), AR5K_MODE_BIT_11G = (1 << AR5K_MODE_11G),
  AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO), AR5K_MODE_BIT_XR = (1 << AR5K_MODE_XR)
}
enum  ath5k_tx_queue {
  AR5K_TX_QUEUE_INACTIVE = 0, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_XR_DATA, AR5K_TX_QUEUE_BEACON,
  AR5K_TX_QUEUE_CAB, AR5K_TX_QUEUE_UAPSD
}
 enum ath5k_tx_queue - Queue types used to classify tx queues. More...
enum  ath5k_tx_queue_subtype { AR5K_WME_AC_BK = 0, AR5K_WME_AC_BE, AR5K_WME_AC_VI, AR5K_WME_AC_VO }
enum  ath5k_tx_queue_id {
  AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, AR5K_TX_QUEUE_ID_DATA_MIN = 0, AR5K_TX_QUEUE_ID_DATA_MAX = 4,
  AR5K_TX_QUEUE_ID_DATA_SVP = 5, AR5K_TX_QUEUE_ID_CAB = 6, AR5K_TX_QUEUE_ID_BEACON = 7, AR5K_TX_QUEUE_ID_UAPSD = 8,
  AR5K_TX_QUEUE_ID_XR_DATA = 9
}
enum  ath5k_pkt_type {
  AR5K_PKT_TYPE_NORMAL = 0, AR5K_PKT_TYPE_ATIM = 1, AR5K_PKT_TYPE_PSPOLL = 2, AR5K_PKT_TYPE_BEACON = 3,
  AR5K_PKT_TYPE_PROBE_RESP = 4, AR5K_PKT_TYPE_PIFS = 5
}
enum  ath5k_dmasize {
  AR5K_DMASIZE_4B = 0, AR5K_DMASIZE_8B, AR5K_DMASIZE_16B, AR5K_DMASIZE_32B,
  AR5K_DMASIZE_64B, AR5K_DMASIZE_128B, AR5K_DMASIZE_256B, AR5K_DMASIZE_512B
}
enum  ath5k_rfgain { AR5K_RFGAIN_INACTIVE = 0, AR5K_RFGAIN_ACTIVE, AR5K_RFGAIN_READ_REQUESTED, AR5K_RFGAIN_NEED_CHANGE }
enum  ath5k_int {
  AR5K_INT_RXOK = 0x00000001, AR5K_INT_RXDESC = 0x00000002, AR5K_INT_RXERR = 0x00000004, AR5K_INT_RXNOFRM = 0x00000008,
  AR5K_INT_RXEOL = 0x00000010, AR5K_INT_RXORN = 0x00000020, AR5K_INT_TXOK = 0x00000040, AR5K_INT_TXDESC = 0x00000080,
  AR5K_INT_TXERR = 0x00000100, AR5K_INT_TXNOFRM = 0x00000200, AR5K_INT_TXEOL = 0x00000400, AR5K_INT_TXURN = 0x00000800,
  AR5K_INT_MIB = 0x00001000, AR5K_INT_SWI = 0x00002000, AR5K_INT_RXPHY = 0x00004000, AR5K_INT_RXKCM = 0x00008000,
  AR5K_INT_SWBA = 0x00010000, AR5K_INT_BRSSI = 0x00020000, AR5K_INT_BMISS = 0x00040000, AR5K_INT_FATAL = 0x00080000,
  AR5K_INT_BNR = 0x00100000, AR5K_INT_TIM = 0x00200000, AR5K_INT_DTIM = 0x00400000, AR5K_INT_DTIM_SYNC = 0x00800000,
  AR5K_INT_GPIO = 0x01000000, AR5K_INT_BCN_TIMEOUT = 0x02000000, AR5K_INT_CAB_TIMEOUT = 0x04000000, AR5K_INT_RX_DOPPLER = 0x08000000,
  AR5K_INT_QCBRORN = 0x10000000, AR5K_INT_QCBRURN = 0x20000000, AR5K_INT_QTRIG = 0x40000000, AR5K_INT_GLOBAL = 0x80000000,
  AR5K_INT_COMMON, AR5K_INT_NOCARD = 0xffffffff
}
 enum ath5k_int - Hardware interrupt masks helpers More...
enum  ath5k_power_mode {
  AR5K_PM_UNDEFINED = 0, AR5K_PM_AUTO, AR5K_PM_AWAKE, AR5K_PM_FULL_SLEEP,
  AR5K_PM_NETWORK_SLEEP
}
enum  ath5k_capability_type {
  AR5K_CAP_REG_DMN = 0, AR5K_CAP_TKIP_MIC = 2, AR5K_CAP_TKIP_SPLIT = 3, AR5K_CAP_PHYCOUNTERS = 4,
  AR5K_CAP_DIVERSITY = 5, AR5K_CAP_NUM_TXQUEUES = 6, AR5K_CAP_VEOL = 7, AR5K_CAP_COMPRESSION = 8,
  AR5K_CAP_BURST = 9, AR5K_CAP_FASTFRAME = 10, AR5K_CAP_TXPOW = 11, AR5K_CAP_TPC = 12,
  AR5K_CAP_BSSIDMASK = 13, AR5K_CAP_MCAST_KEYSRCH = 14, AR5K_CAP_TSF_ADJUST = 15, AR5K_CAP_XR = 16,
  AR5K_CAP_WME_TKIPMIC = 17, AR5K_CAP_CHAN_HALFRATE = 18, AR5K_CAP_CHAN_QUARTERRATE = 19, AR5K_CAP_RFSILENT = 20
}

Functions

 FILE_LICENCE (MIT)
int ath5k_bitrate_to_hw_rix (int bitrate)
int ath5k_hw_attach (struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah)
 ath5k_hw_attach - Check if hw is supported and init the needed structs
void ath5k_hw_detach (struct ath5k_hw *ah)
 ath5k_hw_detach - Free the ath5k_hw struct
int ath5k_init_leds (struct ath5k_softc *sc)
void ath5k_led_enable (struct ath5k_softc *sc)
void ath5k_led_off (struct ath5k_softc *sc)
void ath5k_unregister_leds (struct ath5k_softc *sc)
int ath5k_hw_nic_wakeup (struct ath5k_hw *ah, int flags, int initial)
int ath5k_hw_reset (struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel)
int ath5k_hw_set_power (struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration)
void ath5k_hw_start_rx_dma (struct ath5k_hw *ah)
 ath5k_hw_start_rx_dma - Start DMA receive
int ath5k_hw_stop_rx_dma (struct ath5k_hw *ah)
 ath5k_hw_stop_rx_dma - Stop DMA receive
u32 ath5k_hw_get_rxdp (struct ath5k_hw *ah)
 ath5k_hw_get_rxdp - Get RX Descriptor's address
void ath5k_hw_set_rxdp (struct ath5k_hw *ah, u32 phys_addr)
 ath5k_hw_set_rxdp - Set RX Descriptor's address
int ath5k_hw_start_tx_dma (struct ath5k_hw *ah, unsigned int queue)
 ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
int ath5k_hw_stop_tx_dma (struct ath5k_hw *ah, unsigned int queue)
 ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
u32 ath5k_hw_get_txdp (struct ath5k_hw *ah, unsigned int queue)
 ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
int ath5k_hw_set_txdp (struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
 ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
int ath5k_hw_update_tx_triglevel (struct ath5k_hw *ah, int increase)
 ath5k_hw_update_tx_triglevel - Update tx trigger level
int ath5k_hw_is_intr_pending (struct ath5k_hw *ah)
 ath5k_hw_is_intr_pending - Check if we have pending interrupts
int ath5k_hw_get_isr (struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
enum ath5k_int ath5k_hw_set_imr (struct ath5k_hw *ah, enum ath5k_int new_mask)
 ath5k_hw_set_imr - Set interrupt mask
int ath5k_eeprom_init (struct ath5k_hw *ah)
void ath5k_eeprom_detach (struct ath5k_hw *ah)
int ath5k_eeprom_read_mac (struct ath5k_hw *ah, u8 *mac)
int ath5k_eeprom_is_hb63 (struct ath5k_hw *ah)
int ath5k_hw_set_opmode (struct ath5k_hw *ah)
 ath5k_hw_set_opmode - Set PCU operating mode
void ath5k_hw_get_lladdr (struct ath5k_hw *ah, u8 *mac)
 ath5k_hw_get_lladdr - Get station id
int ath5k_hw_set_lladdr (struct ath5k_hw *ah, const u8 *mac)
 ath5k_hw_set_lladdr - Set station id
void ath5k_hw_set_associd (struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
 ath5k_hw_set_associd - Set BSSID for association
int ath5k_hw_set_bssid_mask (struct ath5k_hw *ah, const u8 *mask)
 ath5k_hw_set_bssid_mask - filter out bssids we listen
void ath5k_hw_start_rx_pcu (struct ath5k_hw *ah)
 ath5k_hw_start_rx_pcu - Start RX engine
void ath5k_hw_stop_rx_pcu (struct ath5k_hw *ah)
 at5k_hw_stop_rx_pcu - Stop RX engine
void ath5k_hw_set_mcast_filter (struct ath5k_hw *ah, u32 filter0, u32 filter1)
u32 ath5k_hw_get_rx_filter (struct ath5k_hw *ah)
 ath5k_hw_get_rx_filter - Get current rx filter
void ath5k_hw_set_rx_filter (struct ath5k_hw *ah, u32 filter)
 ath5k_hw_set_rx_filter - Set rx filter
void ath5k_hw_set_ack_bitrate_high (struct ath5k_hw *ah, int high)
 ath5k_hw_set_ack_bitrate - set bitrate for ACKs
int ath5k_hw_set_ack_timeout (struct ath5k_hw *ah, unsigned int timeout)
 ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
unsigned int ath5k_hw_get_ack_timeout (struct ath5k_hw *ah)
 ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
int ath5k_hw_set_cts_timeout (struct ath5k_hw *ah, unsigned int timeout)
 ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
unsigned int ath5k_hw_get_cts_timeout (struct ath5k_hw *ah)
 ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
int ath5k_hw_reset_key (struct ath5k_hw *ah, u16 entry)
int ath5k_hw_set_tx_queueprops (struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info)
int ath5k_hw_setup_tx_queue (struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info)
u32 ath5k_hw_num_tx_pending (struct ath5k_hw *ah)
void ath5k_hw_release_tx_queue (struct ath5k_hw *ah)
int ath5k_hw_reset_tx_queue (struct ath5k_hw *ah)
int ath5k_hw_set_slot_time (struct ath5k_hw *ah, unsigned int slot_time)
int ath5k_hw_init_desc_functions (struct ath5k_hw *ah)
int ath5k_hw_set_gpio_input (struct ath5k_hw *ah, u32 gpio)
int ath5k_hw_set_gpio_output (struct ath5k_hw *ah, u32 gpio)
u32 ath5k_hw_get_gpio (struct ath5k_hw *ah, u32 gpio)
int ath5k_hw_set_gpio (struct ath5k_hw *ah, u32 gpio, u32 val)
void ath5k_hw_set_gpio_intr (struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level)
void ath5k_rfkill_hw_start (struct ath5k_hw *ah)
void ath5k_rfkill_hw_stop (struct ath5k_hw *ah)
int ath5k_hw_set_capabilities (struct ath5k_hw *ah)
int ath5k_hw_get_capability (struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result)
int ath5k_hw_enable_pspoll (struct ath5k_hw *ah, u8 *bssid, u16 assoc_id)
int ath5k_hw_disable_pspoll (struct ath5k_hw *ah)
int ath5k_hw_write_initvals (struct ath5k_hw *ah, u8 mode, int change_channel)
int ath5k_hw_rfregs_init (struct ath5k_hw *ah, struct net80211_channel *channel, unsigned int mode)
int ath5k_hw_rfgain_init (struct ath5k_hw *ah, unsigned int freq)
enum ath5k_rfgain ath5k_hw_gainf_calibrate (struct ath5k_hw *ah)
int ath5k_hw_rfgain_opt_init (struct ath5k_hw *ah)
int ath5k_channel_ok (struct ath5k_hw *ah, u16 freq, unsigned int flags)
int ath5k_hw_channel (struct ath5k_hw *ah, struct net80211_channel *channel)
int ath5k_hw_phy_calibrate (struct ath5k_hw *ah, struct net80211_channel *channel)
int ath5k_hw_noise_floor_calibration (struct ath5k_hw *ah, short freq)
 ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
u16 ath5k_hw_radio_revision (struct ath5k_hw *ah, unsigned int chan)
void ath5k_hw_set_def_antenna (struct ath5k_hw *ah, unsigned int ant)
unsigned int ath5k_hw_get_def_antenna (struct ath5k_hw *ah)
int ath5k_hw_phy_disable (struct ath5k_hw *ah)
int ath5k_hw_txpower (struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower)
int ath5k_hw_set_txpower_limit (struct ath5k_hw *ah, u8 ee_mode, u8 txpower)
static unsigned int ath5k_hw_htoclock (unsigned int usec, int turbo)
static unsigned int ath5k_hw_clocktoh (unsigned int clock, int turbo)
static u32 ath5k_hw_reg_read (struct ath5k_hw *ah, u16 reg)
static void ath5k_hw_reg_write (struct ath5k_hw *ah, u32 val, u16 reg)
static u32 ath5k_hw_bitswap (u32 val, unsigned int bits)

Define Documentation

#define ERRFILE   ERRFILE_ath5k

Definition at line 35 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5210   0x0007 /* AR5210 */

Definition at line 44 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5311   0x0011 /* AR5311 */

Definition at line 45 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211   0x0012 /* AR5211 */

Definition at line 46 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212   0x0013 /* AR5212 */

Definition at line 47 of file ath5k.h.

#define PCI_DEVICE_ID_3COM_3CRDAG675   0x0013 /* 3CRDAG675 (Atheros AR5212) */

Definition at line 48 of file ath5k.h.

#define PCI_DEVICE_ID_3COM_2_3CRPAG175   0x0013 /* 3CRPAG175 (Atheros AR5212) */

Definition at line 49 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5210_AP   0x0207 /* AR5210 (Early) */

Definition at line 50 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM   0x1014 /* AR5212 (IBM MiniPCI) */

Definition at line 51 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT   0x1107 /* AR5210 (no eeprom) */

Definition at line 52 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT   0x1113 /* AR5212 (no eeprom) */

Definition at line 53 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT   0x1112 /* AR5211 (no eeprom) */

Definition at line 54 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA   0xf013 /* AR5212 (emulation board) */

Definition at line 55 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY   0xff12 /* AR5211 (emulation board) */

Definition at line 56 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B   0xf11b /* AR5211 (emulation board) */

Definition at line 57 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2   0x0052 /* AR5312 WMAC (AP31) */

Definition at line 58 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7   0x0057 /* AR5312 WMAC (AP30-040) */

Definition at line 59 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8   0x0058 /* AR5312 WMAC (AP43-030) */

Definition at line 60 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0014   0x0014 /* AR5212 compatible */

Definition at line 61 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0015   0x0015 /* AR5212 compatible */

Definition at line 62 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0016   0x0016 /* AR5212 compatible */

Definition at line 63 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0017   0x0017 /* AR5212 compatible */

Definition at line 64 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0018   0x0018 /* AR5212 compatible */

Definition at line 65 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5212_0019   0x0019 /* AR5212 compatible */

Definition at line 66 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR2413   0x001a /* AR2413 (Griffin-lite) */

Definition at line 67 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5413   0x001b /* AR5413 (Eagle) */

Definition at line 68 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5424   0x001c /* AR5424 (Condor PCI-E) */

Definition at line 69 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5416   0x0023 /* AR5416 */

Definition at line 70 of file ath5k.h.

#define PCI_DEVICE_ID_ATHEROS_AR5418   0x0024 /* AR5418 */

Definition at line 71 of file ath5k.h.

#define AR5K_REG_SM (   _val,
  _flags 
)    (((_val) << _flags##_S) & (_flags))
#define AR5K_REG_MS (   _val,
  _flags 
)    (((_val) & (_flags)) >> _flags##_S)
#define AR5K_REG_WRITE_BITS (   ah,
  _reg,
  _flags,
  _val 
)
#define AR5K_REG_MASKED_BITS (   ah,
  _reg,
  _flags,
  _mask 
)
Value:
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) &           \
                        (_mask)) | (_flags), _reg)

Definition at line 100 of file ath5k.h.

#define AR5K_REG_ENABLE_BITS (   ah,
  _reg,
  _flags 
)    ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
#define AR5K_REG_DISABLE_BITS (   ah,
  _reg,
  _flags 
)    ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
#define AR5K_PHY_READ (   ah,
  _reg 
)    ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))

Definition at line 111 of file ath5k.h.

#define AR5K_PHY_WRITE (   ah,
  _reg,
  _val 
)    ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))

Definition at line 114 of file ath5k.h.

#define AR5K_REG_READ_Q (   ah,
  _reg,
  _queue 
)    (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \

Definition at line 118 of file ath5k.h.

Referenced by ath5k_hw_set_txdp(), and ath5k_hw_start_tx_dma().

#define AR5K_REG_WRITE_Q (   ah,
  _reg,
  _queue 
)    ath5k_hw_reg_write(ah, (1 << _queue), _reg)

Definition at line 121 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue(), ath5k_hw_start_tx_dma(), and ath5k_hw_stop_tx_dma().

#define AR5K_Q_ENABLE_BITS (   _reg,
  _queue 
)
Value:
do {                            \
        _reg |= 1 << _queue;                                            \
} while (0)

Definition at line 124 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue(), and ath5k_hw_setup_tx_queue().

#define AR5K_Q_DISABLE_BITS (   _reg,
  _queue 
)
Value:
do {                            \
        _reg &= ~(1 << _queue);                                         \
} while (0)

Definition at line 128 of file ath5k.h.

Referenced by ath5k_hw_release_tx_queue().

#define AR5K_REG_WAIT (   _i)
Value:
do {                                            \
        if (_i % 64)                                                    \
                udelay(1);                                              \
} while (0)

Definition at line 133 of file ath5k.h.

Referenced by ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_rfgain_init(), and ath5k_hw_rfregs_init().

#define AR5K_INI_RFGAIN_5GHZ   0

Definition at line 139 of file ath5k.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_rfgain_init().

#define AR5K_INI_RFGAIN_2GHZ   1

Definition at line 140 of file ath5k.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_rfgain_init().

#define AR5K_INI_VAL_11A   0

Definition at line 143 of file ath5k.h.

#define AR5K_INI_VAL_11A_TURBO   1

Definition at line 144 of file ath5k.h.

#define AR5K_INI_VAL_11B   2

Definition at line 145 of file ath5k.h.

#define AR5K_INI_VAL_11G   3

Definition at line 146 of file ath5k.h.

#define AR5K_INI_VAL_11G_TURBO   4

Definition at line 147 of file ath5k.h.

#define AR5K_INI_VAL_XR   0

Definition at line 148 of file ath5k.h.

#define AR5K_INI_VAL_MAX   5

Definition at line 149 of file ath5k.h.

#define AR5K_LOW_ID (   _a)
Value:
(                               \
(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24  \
)

Definition at line 152 of file ath5k.h.

Referenced by ath5k_hw_reset(), ath5k_hw_set_associd(), ath5k_hw_set_bssid_mask(), ath5k_hw_set_lladdr(), and ath5k_hw_set_opmode().

#define AR5K_HIGH_ID (   _a)    ((_a)[4] | (_a)[5] << 8)
#define IEEE80211_MAX_LEN   2352

Definition at line 158 of file ath5k.h.

Referenced by ath5k_rx_start().

#define AR5K_TUNE_DMA_BEACON_RESP   2

Definition at line 163 of file ath5k.h.

#define AR5K_TUNE_SW_BEACON_RESP   10

Definition at line 164 of file ath5k.h.

Definition at line 165 of file ath5k.h.

#define AR5K_TUNE_RADAR_ALERT   0

Definition at line 166 of file ath5k.h.

Definition at line 167 of file ath5k.h.

Referenced by ath5k_hw_update_tx_triglevel().

Definition at line 168 of file ath5k.h.

Referenced by ath5k_hw_update_tx_triglevel().

#define AR5K_TUNE_REGISTER_TIMEOUT   20000

Definition at line 169 of file ath5k.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_TUNE_RSSI_THRES   129

Definition at line 172 of file ath5k.h.

Referenced by ath5k_hw_reset().

#define AR5K_TUNE_BMISS_THRES   7

Definition at line 178 of file ath5k.h.

Referenced by ath5k_hw_reset().

#define AR5K_TUNE_REGISTER_DWELL_TIME   20000

Definition at line 179 of file ath5k.h.

#define AR5K_TUNE_BEACON_INTERVAL   100

Definition at line 180 of file ath5k.h.

#define AR5K_TUNE_AIFS   2

Definition at line 181 of file ath5k.h.

Referenced by ath5k_hw_attach(), and ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_AIFS_11B   2

Definition at line 182 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_AIFS_XR   0

Definition at line 183 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_CWMIN   15

Definition at line 184 of file ath5k.h.

Referenced by ath5k_hw_attach(), and ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_CWMIN_11B   31

Definition at line 185 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_CWMIN_XR   3

Definition at line 186 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_CWMAX   1023

Definition at line 187 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_CWMAX_11B   1023

Definition at line 188 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_CWMAX_XR   7

Definition at line 189 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TUNE_NOISE_FLOOR   -72

Definition at line 190 of file ath5k.h.

Referenced by ath5k_hw_noise_floor_calibration().

#define AR5K_TUNE_MAX_TXPOWER   63
#define AR5K_TUNE_DEFAULT_TXPOWER   25

Definition at line 192 of file ath5k.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_txpower().

#define AR5K_TUNE_TPC_TXPOWER   0

Definition at line 193 of file ath5k.h.

Referenced by ath5k_hw_txpower().

#define AR5K_TUNE_ANT_DIVERSITY   1

Definition at line 194 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_TUNE_HWTXTRIES   4

Definition at line 195 of file ath5k.h.

Referenced by ath5k_hw_setup_4word_tx_desc().

#define AR5K_INIT_CARR_SENSE_EN   1

Definition at line 197 of file ath5k.h.

#define AR5K_INIT_CFG   0x00000000

Definition at line 205 of file ath5k.h.

Referenced by ath5k_hw_nic_reset().

#define AR5K_INIT_CYCRSSI_THR1   2

Definition at line 209 of file ath5k.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_INIT_TX_LATENCY   502

Definition at line 210 of file ath5k.h.

#define AR5K_INIT_USEC   39

Definition at line 211 of file ath5k.h.

#define AR5K_INIT_USEC_TURBO   79

Definition at line 212 of file ath5k.h.

#define AR5K_INIT_USEC_32   31

Definition at line 213 of file ath5k.h.

#define AR5K_INIT_SLOT_TIME   396

Definition at line 214 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_SLOT_TIME_TURBO   480

Definition at line 215 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_ACK_CTS_TIMEOUT   1024

Definition at line 216 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO   0x08000800

Definition at line 217 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_PROG_IFS   920

Definition at line 218 of file ath5k.h.

#define AR5K_INIT_PROG_IFS_TURBO   960

Definition at line 219 of file ath5k.h.

#define AR5K_INIT_EIFS   3440

Definition at line 220 of file ath5k.h.

#define AR5K_INIT_EIFS_TURBO   6880

Definition at line 221 of file ath5k.h.

#define AR5K_INIT_SIFS   560

Definition at line 222 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_SIFS_TURBO   480

Definition at line 223 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_SH_RETRY   10

Definition at line 224 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

Definition at line 225 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_SSH_RETRY   32

Definition at line 226 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

Definition at line 227 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_INIT_TX_RETRY   10

Definition at line 228 of file ath5k.h.

Referenced by ath5k_hw_attach().

Value:
(                       \
        (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
        (AR5K_INIT_USEC)                                                \
)

Definition at line 230 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

Value:

Definition at line 234 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

Value:

Definition at line 238 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

Value:

Definition at line 242 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_USEDEFAULT   ((u32) -1)

Definition at line 248 of file ath5k.h.

Referenced by ath5k_txq_setup().

#define AR5K_SREV_UNKNOWN   0xffff

Definition at line 286 of file ath5k.h.

#define AR5K_SREV_AR5210   0x00 /* Crete */

Definition at line 288 of file ath5k.h.

#define AR5K_SREV_AR5311   0x10 /* Maui 1 */

Definition at line 289 of file ath5k.h.

#define AR5K_SREV_AR5311A   0x20 /* Maui 2 */

Definition at line 290 of file ath5k.h.

#define AR5K_SREV_AR5311B   0x30 /* Spirit */

Definition at line 291 of file ath5k.h.

#define AR5K_SREV_AR5211   0x40 /* Oahu */
#define AR5K_SREV_AR5212   0x50 /* Venice */

Definition at line 293 of file ath5k.h.

#define AR5K_SREV_AR5213   0x55 /* ??? */

Definition at line 294 of file ath5k.h.

#define AR5K_SREV_AR5213A   0x59 /* Hainan */

Definition at line 295 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_AR2413   0x78 /* Griffin lite */

Definition at line 296 of file ath5k.h.

Referenced by ath5k_hw_reset().

#define AR5K_SREV_AR2414   0x70 /* Griffin */

Definition at line 297 of file ath5k.h.

Referenced by ath5k_hw_attach(), and ath5k_hw_stop_tx_dma().

#define AR5K_SREV_AR5424   0x90 /* Condor */

Definition at line 298 of file ath5k.h.

Referenced by ath5k_hw_rfregs_init().

#define AR5K_SREV_AR5413   0xa4 /* Eagle lite */

Definition at line 299 of file ath5k.h.

Referenced by ath5k_hw_rfregs_init().

#define AR5K_SREV_AR5414   0xa0 /* Eagle */

Definition at line 300 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_AR2415   0xb0 /* Talon */

Definition at line 301 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_AR5416   0xc0 /* PCI-E */

Definition at line 302 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_AR5418   0xca /* PCI-E */

Definition at line 303 of file ath5k.h.

#define AR5K_SREV_AR2425   0xe0 /* Swan */

Definition at line 304 of file ath5k.h.

Referenced by ath5k_eeprom_init_header(), ath5k_eeprom_is_hb63(), and ath5k_hw_attach().

#define AR5K_SREV_AR2417   0xf0 /* Nala */
#define AR5K_SREV_RAD_5110   0x00

Definition at line 307 of file ath5k.h.

#define AR5K_SREV_RAD_5111   0x10

Definition at line 308 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_5111A   0x15

Definition at line 309 of file ath5k.h.

#define AR5K_SREV_RAD_2111   0x20

Definition at line 310 of file ath5k.h.

#define AR5K_SREV_RAD_5112   0x30

Definition at line 311 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_5112A   0x35
#define AR5K_SREV_RAD_5112B   0x36

Definition at line 313 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_2112   0x40

Definition at line 314 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_2112A   0x45

Definition at line 315 of file ath5k.h.

#define AR5K_SREV_RAD_2112B   0x46

Definition at line 316 of file ath5k.h.

#define AR5K_SREV_RAD_2413   0x50

Definition at line 317 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_5413   0x60

Definition at line 318 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_2316   0x70 /* Cobra SoC */

Definition at line 319 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_2317   0x80

Definition at line 320 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_5424   0xa0 /* Mostly same as 5413 */

Definition at line 321 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_2425   0xa2

Definition at line 322 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_RAD_5133   0xc0

Definition at line 323 of file ath5k.h.

#define AR5K_SREV_PHY_5211   0x30

Definition at line 325 of file ath5k.h.

#define AR5K_SREV_PHY_5212   0x41

Definition at line 326 of file ath5k.h.

#define AR5K_SREV_PHY_5212A   0x42
#define AR5K_SREV_PHY_5212B   0x43

Definition at line 328 of file ath5k.h.

Referenced by ath5k_hw_attach(), and ath5k_hw_tweak_initval_settings().

#define AR5K_SREV_PHY_2413   0x45

Definition at line 329 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_PHY_5413   0x61

Definition at line 330 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_PHY_2425   0x70

Definition at line 331 of file ath5k.h.

Referenced by ath5k_hw_attach().

#define MODULATION_XR   0x00000200

Definition at line 349 of file ath5k.h.

#define MODULATION_TURBO   0x00000080

Definition at line 389 of file ath5k.h.

#define AR5K_TXSTAT_ALTRATE   0x80

Definition at line 430 of file ath5k.h.

#define AR5K_TXERR_XRETRY   0x01

Definition at line 431 of file ath5k.h.

Referenced by ath5k_hw_proc_2word_tx_status(), and ath5k_hw_proc_4word_tx_status().

#define AR5K_TXERR_FILT   0x02

Definition at line 432 of file ath5k.h.

Referenced by ath5k_hw_proc_2word_tx_status(), and ath5k_hw_proc_4word_tx_status().

#define AR5K_TXERR_FIFO   0x04

Definition at line 433 of file ath5k.h.

Referenced by ath5k_hw_proc_2word_tx_status(), and ath5k_hw_proc_4word_tx_status().

#define AR5K_TXQ_FLAG_TXOKINT_ENABLE   0x0001 /* Enable TXOK interrupt */

Definition at line 488 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_TXERRINT_ENABLE   0x0002 /* Enable TXERR interrupt */

Definition at line 489 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE   0x0004 /* Enable TXEOL interrupt -not used- */

Definition at line 490 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue(), and ath5k_txq_setup().

#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE   0x0008 /* Enable TXDESC interrupt -not used- */

Definition at line 491 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue(), and ath5k_txq_setup().

#define AR5K_TXQ_FLAG_TXURNINT_ENABLE   0x0010 /* Enable TXURN interrupt */

Definition at line 492 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE   0x0020 /* Enable CBRORN interrupt */

Definition at line 493 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE   0x0040 /* Enable CBRURN interrupt */

Definition at line 494 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE   0x0080 /* Enable QTRIG interrupt */

Definition at line 495 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE   0x0100 /* Enable TXNOFRM interrupt */

Definition at line 496 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_BACKOFF_DISABLE   0x0200 /* Disable random post-backoff */

Definition at line 497 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE   0x0300 /* Enable ready time expiry policy (?)*/

Definition at line 498 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE   0x0800 /* Enable backoff while bursting */

Definition at line 499 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS   0x1000 /* Disable backoff while bursting */

Definition at line 500 of file ath5k.h.

Referenced by ath5k_hw_set_tx_queueprops().

#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE   0x2000 /* Enable hw compression -not implemented-*/

Definition at line 501 of file ath5k.h.

#define AR5K_TXPOWER_OFDM (   _r,
  _v 
)
Value:
(                       \
        ((0 & 1) << ((_v) + 6)) |                               \
        (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
)

Definition at line 536 of file ath5k.h.

Referenced by ath5k_hw_txpower().

#define AR5K_TXPOWER_CCK (   _r,
  _v 
)
Value:
(                       \
        (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v)     \
)

Definition at line 541 of file ath5k.h.

Referenced by ath5k_hw_txpower().

#define AR5K_RXERR_CRC   0x01
#define AR5K_RXERR_PHY   0x02
#define AR5K_RXERR_FIFO   0x04

Definition at line 581 of file ath5k.h.

Referenced by ath5k_hw_proc_5210_rx_status().

#define AR5K_RXERR_DECRYPT   0x08
#define AR5K_RXERR_MIC   0x10

Definition at line 583 of file ath5k.h.

Referenced by ath5k_hw_proc_5212_rx_status().

#define AR5K_RXKEYIX_INVALID   ((u8) - 1)
#define AR5K_TXKEYIX_INVALID   ((u32) - 1)

Definition at line 585 of file ath5k.h.

Referenced by ath5k_txbuf_setup().

#define TSF_TO_TU (   _tsf)    (u32)((_tsf) >> 10)

Definition at line 595 of file ath5k.h.

#define AR5K_SLOT_TIME_9   396

Definition at line 623 of file ath5k.h.

#define AR5K_SLOT_TIME_20   880

Definition at line 624 of file ath5k.h.

#define AR5K_SLOT_TIME_MAX   0xffff

Definition at line 625 of file ath5k.h.

Referenced by ath5k_hw_set_slot_time().

#define CHANNEL_CW_INT   0x0008 /* Contention Window interference detected */

Definition at line 628 of file ath5k.h.

Referenced by ath9k_hw_getnf(), ath9k_hw_reset(), and ath9k_init_nfcal_hist_buffer().

#define CHANNEL_TURBO   0x0010 /* Turbo Channel */
#define CHANNEL_CCK   0x0020 /* CCK channel */
#define CHANNEL_OFDM   0x0040 /* OFDM channel */
#define CHANNEL_2GHZ   0x0080 /* 2GHz channel. */
#define CHANNEL_5GHZ   0x0100 /* 5GHz channel */
#define CHANNEL_PASSIVE   0x0200 /* Only passive scan allowed */

Definition at line 634 of file ath5k.h.

#define CHANNEL_DYN   0x0400 /* Dynamic CCK-OFDM channel (for g operation) */

Definition at line 635 of file ath5k.h.

#define CHANNEL_XR   0x0800 /* XR channel */

Definition at line 636 of file ath5k.h.

Referenced by ath5k_get_max_ctl_power(), and ath5k_hw_reset().

Definition at line 641 of file ath5k.h.

Referenced by ath5k_get_max_ctl_power(), ath5k_hw_channel(), and ath5k_hw_reset().

Definition at line 642 of file ath5k.h.

Referenced by ath5k_get_max_ctl_power(), and ath5k_hw_reset().

#define CHANNEL_108A   CHANNEL_T

Definition at line 643 of file ath5k.h.

#define CHANNEL_108G   CHANNEL_TG

Definition at line 644 of file ath5k.h.

Definition at line 645 of file ath5k.h.

#define CHANNEL_ALL
Value:

Definition at line 647 of file ath5k.h.

Referenced by ath9k_hw_reset().

Definition at line 650 of file ath5k.h.

#define CHANNEL_MODES   CHANNEL_ALL

Definition at line 651 of file ath5k.h.

Referenced by ath5k_get_max_ctl_power(), and ath5k_hw_reset().

#define IS_CHAN_XR (   _c)    ((_c->hw_value & CHANNEL_XR) != 0)

Definition at line 657 of file ath5k.h.

Referenced by ath5k_hw_reset_tx_queue().

#define IS_CHAN_B (   _c)    ((_c->hw_value & CHANNEL_B) != 0)
#define AR5K_MAX_RATES   32

Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.

The rate code is used to get the RX rate or set the TX rate on the hardware descriptors. It is also used for internal modulation control and settings.

This is the hardware rate map we are aware of:

rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 rate_kbps 3000 1000 ? ? ? 2000 500 48000

rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?

rate_code 17 18 19 20 21 22 23 24 rate_kbps ? ? ? ? ? ? ? 11000

rate_code 25 26 27 28 29 30 31 32 rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?

"S" indicates CCK rates with short preamble.

AR5211 has different rate codes for CCK (802.11B) rates. It only uses the lowest 4 bits, so they are the same as below with a 0xF mask. (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). We handle this in ath5k_setup_bands().

Definition at line 703 of file ath5k.h.

#define ATH5K_RATE_CODE_1M   0x1B

Definition at line 706 of file ath5k.h.

Referenced by ath5k_bitrate_to_hw_rix().

#define ATH5K_RATE_CODE_2M   0x1A

Definition at line 707 of file ath5k.h.

#define ATH5K_RATE_CODE_5_5M   0x19

Definition at line 708 of file ath5k.h.

#define ATH5K_RATE_CODE_11M   0x18

Definition at line 709 of file ath5k.h.

#define ATH5K_RATE_CODE_6M   0x0B

Definition at line 711 of file ath5k.h.

#define ATH5K_RATE_CODE_9M   0x0F

Definition at line 712 of file ath5k.h.

#define ATH5K_RATE_CODE_12M   0x0A

Definition at line 713 of file ath5k.h.

#define ATH5K_RATE_CODE_18M   0x0E

Definition at line 714 of file ath5k.h.

#define ATH5K_RATE_CODE_24M   0x09

Definition at line 715 of file ath5k.h.

#define ATH5K_RATE_CODE_36M   0x0D

Definition at line 716 of file ath5k.h.

#define ATH5K_RATE_CODE_48M   0x08

Definition at line 717 of file ath5k.h.

#define ATH5K_RATE_CODE_54M   0x0C

Definition at line 718 of file ath5k.h.

#define ATH5K_RATE_CODE_XR_500K   0x07

Definition at line 720 of file ath5k.h.

#define ATH5K_RATE_CODE_XR_1M   0x02

Definition at line 721 of file ath5k.h.

#define ATH5K_RATE_CODE_XR_2M   0x06

Definition at line 722 of file ath5k.h.

#define ATH5K_RATE_CODE_XR_3M   0x01

Definition at line 723 of file ath5k.h.

#define AR5K_SET_SHORT_PREAMBLE   0x04

Definition at line 726 of file ath5k.h.

Referenced by ath5k_hw_write_rate_duration().

#define AR5K_KEYCACHE_SIZE   8

Definition at line 732 of file ath5k.h.

Referenced by ath5k_hw_reset_key().

#define AR5K_RSSI_EP_MULTIPLIER   (1<<7)

Definition at line 741 of file ath5k.h.

#define AR5K_ASSERT_ENTRY (   _e,
  _s 
)
Value:
do {            \
        if (_e >= _s)                           \
                return 0;                       \
} while (0)

Definition at line 743 of file ath5k.h.

#define AR5K_SOFTLED_PIN   0

Definition at line 875 of file ath5k.h.

#define AR5K_SOFTLED_ON   0

Definition at line 876 of file ath5k.h.

#define AR5K_SOFTLED_OFF   1

Definition at line 877 of file ath5k.h.

#define AR5K_MAX_GPIO   10

Definition at line 949 of file ath5k.h.

#define AR5K_MAX_RF_BANKS   8

Definition at line 950 of file ath5k.h.

Referenced by ath5k_hw_rfregs_init().

#define ah_regdomain   ah_capabilities.cap_regdomain.reg_current

Definition at line 981 of file ath5k.h.

#define ah_regdomain_hw   ah_capabilities.cap_regdomain.reg_hw

Definition at line 982 of file ath5k.h.

#define ah_modes   ah_capabilities.cap_mode

Definition at line 983 of file ath5k.h.

#define ah_ee_version   ah_capabilities.cap_eeprom.ee_version

Definition at line 984 of file ath5k.h.


Enumeration Type Documentation

Enumerator:
AR5K_AR5210 
AR5K_AR5211 
AR5K_AR5212 

Definition at line 253 of file ath5k.h.

                   {
        AR5K_AR5210     = 0,
        AR5K_AR5211     = 1,
        AR5K_AR5212     = 2,
};
Enumerator:
AR5K_RF5110 
AR5K_RF5111 
AR5K_RF5112 
AR5K_RF2413 
AR5K_RF5413 
AR5K_RF2316 
AR5K_RF2317 
AR5K_RF2425 

Definition at line 260 of file ath5k.h.

Enumerator:
AR5K_VERSION_MAC 
AR5K_VERSION_RAD 

Definition at line 275 of file ath5k.h.

Enumerator:
AR5K_MODE_11A 
AR5K_MODE_11A_TURBO 
AR5K_MODE_11B 
AR5K_MODE_11G 
AR5K_MODE_11G_TURBO 
AR5K_MODE_XR 

Definition at line 391 of file ath5k.h.

anonymous enum
Enumerator:
AR5K_MODE_BIT_11A 
AR5K_MODE_BIT_11A_TURBO 
AR5K_MODE_BIT_11B 
AR5K_MODE_BIT_11G 
AR5K_MODE_BIT_11G_TURBO 
AR5K_MODE_BIT_XR 

Definition at line 400 of file ath5k.h.

enum ath5k_tx_queue - Queue types used to classify tx queues.

: q is unused -- see ath5k_hw_release_tx_queue : A normal data queue : An XR-data queue : The beacon queue : The after-beacon queue : Unscheduled Automatic Power Save Delivery queue

Enumerator:
AR5K_TX_QUEUE_INACTIVE 
AR5K_TX_QUEUE_DATA 
AR5K_TX_QUEUE_XR_DATA 
AR5K_TX_QUEUE_BEACON 
AR5K_TX_QUEUE_CAB 
AR5K_TX_QUEUE_UAPSD 

Definition at line 444 of file ath5k.h.

Enumerator:
AR5K_WME_AC_BK 
AR5K_WME_AC_BE 
AR5K_WME_AC_VI 
AR5K_WME_AC_VO 

Definition at line 460 of file ath5k.h.

                            {
        AR5K_WME_AC_BK = 0,     /*Background traffic*/
        AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
        AR5K_WME_AC_VI,         /*Video traffic*/
        AR5K_WME_AC_VO,         /*Voice traffic*/
};
Enumerator:
AR5K_TX_QUEUE_ID_NOQCU_DATA 
AR5K_TX_QUEUE_ID_NOQCU_BEACON 
AR5K_TX_QUEUE_ID_DATA_MIN 
AR5K_TX_QUEUE_ID_DATA_MAX 
AR5K_TX_QUEUE_ID_DATA_SVP 
AR5K_TX_QUEUE_ID_CAB 
AR5K_TX_QUEUE_ID_BEACON 
AR5K_TX_QUEUE_ID_UAPSD 
AR5K_TX_QUEUE_ID_XR_DATA 

Definition at line 473 of file ath5k.h.

                       {
        AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
        AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
        AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
        AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
        AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
        AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
        AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
        AR5K_TX_QUEUE_ID_UAPSD          = 8,
        AR5K_TX_QUEUE_ID_XR_DATA        = 9,
};
Enumerator:
AR5K_PKT_TYPE_NORMAL 
AR5K_PKT_TYPE_ATIM 
AR5K_PKT_TYPE_PSPOLL 
AR5K_PKT_TYPE_BEACON 
AR5K_PKT_TYPE_PROBE_RESP 
AR5K_PKT_TYPE_PIFS 

Definition at line 524 of file ath5k.h.

Enumerator:
AR5K_DMASIZE_4B 
AR5K_DMASIZE_8B 
AR5K_DMASIZE_16B 
AR5K_DMASIZE_32B 
AR5K_DMASIZE_64B 
AR5K_DMASIZE_128B 
AR5K_DMASIZE_256B 
AR5K_DMASIZE_512B 

Definition at line 548 of file ath5k.h.

Enumerator:
AR5K_RFGAIN_INACTIVE 
AR5K_RFGAIN_ACTIVE 
AR5K_RFGAIN_READ_REQUESTED 
AR5K_RFGAIN_NEED_CHANGE 

Definition at line 602 of file ath5k.h.

enum ath5k_int

enum ath5k_int - Hardware interrupt masks helpers

: mask to identify received frame interrupts, of type AR5K_ISR_RXOK or AR5K_ISR_RXERR : Request RX descriptor/Read RX descriptor (?) : No frame received (?) : received End Of List for VEOL (Virtual End Of List). The Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's LinkPtr is NULL. For more details, refer to: http://www.freepatentsonline.com/20030225739.html : Indicates we got RX overrun (eg. no more descriptors). Note that Rx overrun is not always fatal, on some chips we can continue operation without reseting the card, that's why int_fatal is not common for all chips. : mask to identify received frame interrupts, of type AR5K_ISR_TXOK or AR5K_ISR_TXERR : Request TX descriptor/Read TX status descriptor (?) : received when we should increase the TX trigger threshold We currently do increments on interrupt by (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 : Indicates the Management Information Base counters should be checked. We should do this with ath5k_hw_update_mib_counters() but it seems we should also then do some noise immunity work. : RX PHY Error : RX Key cache miss : SoftWare Beacon Alert - indicates its time to send a beacon that must be handled in software. The alternative is if you have VEOL support, in that case you let the hardware deal with things. : If in STA mode this indicates we have stopped seeing beacons from the AP have associated with, we should probably try to reassociate. When in IBSS mode this might mean we have not received any beacons from any local stations. Note that every station in an IBSS schedules to send beacons at the Target Beacon Transmission Time (TBTT) with a random backoff. : Beacon Not Ready interrupt - ?? : GPIO interrupt is used for RF Kill, disabled for now until properly handled : Fatal errors were encountered, typically caused by DMA errors. These types of errors we can enable seem to be of type AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. : Used to clear and set the IER : signals the card has been removed : common interrupts shared amogst MACs with the same bit value

These are mapped to take advantage of some common bits between the MACs, to be able to set intr properties easier. Some of them are not used yet inside hw.c. Most map to the respective hw interrupt value as they are common amogst different MACs.

Enumerator:
AR5K_INT_RXOK 
AR5K_INT_RXDESC 
AR5K_INT_RXERR 
AR5K_INT_RXNOFRM 
AR5K_INT_RXEOL 
AR5K_INT_RXORN 
AR5K_INT_TXOK 
AR5K_INT_TXDESC 
AR5K_INT_TXERR 
AR5K_INT_TXNOFRM 
AR5K_INT_TXEOL 
AR5K_INT_TXURN 
AR5K_INT_MIB 
AR5K_INT_SWI 
AR5K_INT_RXPHY 
AR5K_INT_RXKCM 
AR5K_INT_SWBA 
AR5K_INT_BRSSI 
AR5K_INT_BMISS 
AR5K_INT_FATAL 
AR5K_INT_BNR 
AR5K_INT_TIM 
AR5K_INT_DTIM 
AR5K_INT_DTIM_SYNC 
AR5K_INT_GPIO 
AR5K_INT_BCN_TIMEOUT 
AR5K_INT_CAB_TIMEOUT 
AR5K_INT_RX_DOPPLER 
AR5K_INT_QCBRORN 
AR5K_INT_QCBRURN 
AR5K_INT_QTRIG 
AR5K_INT_GLOBAL 
AR5K_INT_COMMON 
AR5K_INT_NOCARD 

Definition at line 804 of file ath5k.h.

               {
        AR5K_INT_RXOK   = 0x00000001,
        AR5K_INT_RXDESC = 0x00000002,
        AR5K_INT_RXERR  = 0x00000004,
        AR5K_INT_RXNOFRM = 0x00000008,
        AR5K_INT_RXEOL  = 0x00000010,
        AR5K_INT_RXORN  = 0x00000020,
        AR5K_INT_TXOK   = 0x00000040,
        AR5K_INT_TXDESC = 0x00000080,
        AR5K_INT_TXERR  = 0x00000100,
        AR5K_INT_TXNOFRM = 0x00000200,
        AR5K_INT_TXEOL  = 0x00000400,
        AR5K_INT_TXURN  = 0x00000800,
        AR5K_INT_MIB    = 0x00001000,
        AR5K_INT_SWI    = 0x00002000,
        AR5K_INT_RXPHY  = 0x00004000,
        AR5K_INT_RXKCM  = 0x00008000,
        AR5K_INT_SWBA   = 0x00010000,
        AR5K_INT_BRSSI  = 0x00020000,
        AR5K_INT_BMISS  = 0x00040000,
        AR5K_INT_FATAL  = 0x00080000, /* Non common */
        AR5K_INT_BNR    = 0x00100000, /* Non common */
        AR5K_INT_TIM    = 0x00200000, /* Non common */
        AR5K_INT_DTIM   = 0x00400000, /* Non common */
        AR5K_INT_DTIM_SYNC =    0x00800000, /* Non common */
        AR5K_INT_GPIO   =       0x01000000,
        AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
        AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
        AR5K_INT_RX_DOPPLER =   0x08000000, /* Non common */
        AR5K_INT_QCBRORN =      0x10000000, /* Non common */
        AR5K_INT_QCBRURN =      0x20000000, /* Non common */
        AR5K_INT_QTRIG  =       0x40000000, /* Non common */
        AR5K_INT_GLOBAL =       0x80000000,

        AR5K_INT_COMMON  = AR5K_INT_RXOK
                | AR5K_INT_RXDESC
                | AR5K_INT_RXERR
                | AR5K_INT_RXNOFRM
                | AR5K_INT_RXEOL
                | AR5K_INT_RXORN
                | AR5K_INT_TXOK
                | AR5K_INT_TXDESC
                | AR5K_INT_TXERR
                | AR5K_INT_TXNOFRM
                | AR5K_INT_TXEOL
                | AR5K_INT_TXURN
                | AR5K_INT_MIB
                | AR5K_INT_SWI
                | AR5K_INT_RXPHY
                | AR5K_INT_RXKCM
                | AR5K_INT_SWBA
                | AR5K_INT_BRSSI
                | AR5K_INT_BMISS
                | AR5K_INT_GPIO
                | AR5K_INT_GLOBAL,

        AR5K_INT_NOCARD = 0xffffffff
};
Enumerator:
AR5K_PM_UNDEFINED 
AR5K_PM_AUTO 
AR5K_PM_AWAKE 
AR5K_PM_FULL_SLEEP 
AR5K_PM_NETWORK_SLEEP 

Definition at line 866 of file ath5k.h.

Enumerator:
AR5K_CAP_REG_DMN 
AR5K_CAP_TKIP_MIC 
AR5K_CAP_TKIP_SPLIT 
AR5K_CAP_PHYCOUNTERS 
AR5K_CAP_DIVERSITY 
AR5K_CAP_NUM_TXQUEUES 
AR5K_CAP_VEOL 
AR5K_CAP_COMPRESSION 
AR5K_CAP_BURST 
AR5K_CAP_FASTFRAME 
AR5K_CAP_TXPOW 
AR5K_CAP_TPC 
AR5K_CAP_BSSIDMASK 
AR5K_CAP_MCAST_KEYSRCH 
AR5K_CAP_TSF_ADJUST 
AR5K_CAP_XR 
AR5K_CAP_WME_TKIPMIC 
AR5K_CAP_CHAN_HALFRATE 
AR5K_CAP_CHAN_QUARTERRATE 
AR5K_CAP_RFSILENT 

Definition at line 885 of file ath5k.h.

                           {
        AR5K_CAP_REG_DMN                = 0,    /* Used to get current reg. domain id */
        AR5K_CAP_TKIP_MIC               = 2,    /* Can handle TKIP MIC in hardware */
        AR5K_CAP_TKIP_SPLIT             = 3,    /* TKIP uses split keys */
        AR5K_CAP_PHYCOUNTERS            = 4,    /* PHY error counters */
        AR5K_CAP_DIVERSITY              = 5,    /* Supports fast diversity */
        AR5K_CAP_NUM_TXQUEUES           = 6,    /* Used to get max number of hw txqueues */
        AR5K_CAP_VEOL                   = 7,    /* Supports virtual EOL */
        AR5K_CAP_COMPRESSION            = 8,    /* Supports compression */
        AR5K_CAP_BURST                  = 9,    /* Supports packet bursting */
        AR5K_CAP_FASTFRAME              = 10,   /* Supports fast frames */
        AR5K_CAP_TXPOW                  = 11,   /* Used to get global tx power limit */
        AR5K_CAP_TPC                    = 12,   /* Can do per-packet tx power control (needed for 802.11a) */
        AR5K_CAP_BSSIDMASK              = 13,   /* Supports bssid mask */
        AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
        AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
        AR5K_CAP_XR                     = 16,   /* Supports XR mode */
        AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
        AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
        AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
        AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
};

Function Documentation

FILE_LICENCE ( MIT  )
int ath5k_bitrate_to_hw_rix ( int  bitrate)

Definition at line 718 of file ath5k.c.

References ATH5K_NR_RATES, ATH5K_RATE_CODE_1M, ath5k_rates, and DBG.

Referenced by ath5k_hw_write_rate_duration().

{
        int i;

        for (i = 0; i < ATH5K_NR_RATES; i++) {
                if (ath5k_rates[i].bitrate == bitrate)
                        return ath5k_rates[i].hw_code;
        }

        DBG("ath5k: invalid bitrate %d\n", bitrate);
        return ATH5K_RATE_CODE_1M; /* use lowest rate */
}
int ath5k_hw_attach ( struct ath5k_softc sc,
u8  mac_version,
struct ath5k_hw **  hw 
)

ath5k_hw_attach - Check if hw is supported and init the needed structs

: The &struct ath5k_softc we got from the driver's attach function : The mac version id (check out ath5k.h) based on pci id : Returned newly allocated hardware structure, on success

Check if the device is supported, perform a POST and initialize the needed structs. Returns -ENOMEM if we don't have memory for the needed structs, -ENODEV if the device is not supported or prints an error msg if something else went wrong.

Definition at line 112 of file ath5k_attach.c.

References ah, ath5k_hw::ah_aifs, ath5k_hw::ah_ant_diversity, ath5k_hw::ah_atim_window, ath5k_hw::ah_bssid, ath5k_hw::ah_combined_mic, ath5k_hw::ah_cw_min, ath5k_hw::ah_imr, ath5k_hw::ah_iobase, ath5k_hw::ah_limit_tx_retries, ath5k_hw::ah_mac_revision, ath5k_hw::ah_mac_srev, ath5k_hw::ah_mac_version, ath5k_hw::ah_phy, ath5k_hw::ah_phy_revision, ath5k_hw::ah_radio, ath5k_hw::ah_radio_2ghz_revision, ath5k_hw::ah_radio_5ghz_revision, ath5k_hw::ah_sc, ath5k_hw::ah_single_chip, ath5k_hw::ah_software_retry, ath5k_hw::ah_turbo, ath5k_hw::ah_txpower, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_INIT_TX_RETRY, AR5K_MISC_MODE, AR5K_MISC_MODE_COMBINED_MIC, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX, AR5K_PCIE_SERDES, AR5K_PCIE_SERDES_RESET, AR5K_PHY, AR5K_PHY_CHIP_ID, AR5K_REG_ENABLE_BITS, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_SREV, AR5K_SREV_AR2414, AR5K_SREV_AR2415, AR5K_SREV_AR2417, AR5K_SREV_AR2425, AR5K_SREV_AR5213A, AR5K_SREV_AR5414, AR5K_SREV_AR5416, AR5K_SREV_PHY_2413, AR5K_SREV_PHY_2425, AR5K_SREV_PHY_5212B, AR5K_SREV_PHY_5413, AR5K_SREV_RAD_2112, AR5K_SREV_RAD_2316, AR5K_SREV_RAD_2317, AR5K_SREV_RAD_2413, AR5K_SREV_RAD_2425, AR5K_SREV_RAD_5111, AR5K_SREV_RAD_5112, AR5K_SREV_RAD_5112B, AR5K_SREV_RAD_5413, AR5K_SREV_RAD_5424, AR5K_SREV_REV, AR5K_SREV_VER, AR5K_TUNE_AIFS, AR5K_TUNE_ANT_DIVERSITY, AR5K_TUNE_CWMIN, ath5k_eeprom_init(), ath5k_hw_init_desc_functions(), ath5k_hw_nic_wakeup(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_rfgain_opt_init(), ath5k_hw_set_associd(), ath5k_hw_set_capabilities(), ath5k_hw_set_opmode(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_B, DBG, pci_device::device, ENOMEM, ENOTSUP, ETH_ALEN, free, ath5k_softc::iobase, mdelay(), memset(), NULL, PCI_CAP_ID_EXP, pci_find_capability(), ath5k_softc::pdev, ret, ath5k_hw::txp_tpc, and zalloc().

Referenced by ath5k_probe().

{
        struct ath5k_hw *ah;
        struct pci_device *pdev = sc->pdev;
        int ret;
        u32 srev;

        ah = zalloc(sizeof(struct ath5k_hw));
        if (ah == NULL) {
                ret = -ENOMEM;
                DBG("ath5k: out of memory\n");
                goto err;
        }

        ah->ah_sc = sc;
        ah->ah_iobase = sc->iobase;

        /*
         * HW information
         */
        ah->ah_turbo = 0;
        ah->ah_txpower.txp_tpc = 0;
        ah->ah_imr = 0;
        ah->ah_atim_window = 0;
        ah->ah_aifs = AR5K_TUNE_AIFS;
        ah->ah_cw_min = AR5K_TUNE_CWMIN;
        ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
        ah->ah_software_retry = 0;
        ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;

        /*
         * Set the mac version based on the pci id
         */
        ah->ah_version = mac_version;

        /*Fill the ath5k_hw struct with the needed functions*/
        ret = ath5k_hw_init_desc_functions(ah);
        if (ret)
                goto err_free;

        /* Bring device out of sleep and reset it's units */
        ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, 1);
        if (ret)
                goto err_free;

        /* Get MAC, PHY and RADIO revisions */
        srev = ath5k_hw_reg_read(ah, AR5K_SREV);
        ah->ah_mac_srev = srev;
        ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
        ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
        ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID);
        ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, CHANNEL_5GHZ);
        ah->ah_phy = AR5K_PHY(0);

        /* Try to identify radio chip based on it's srev */
        switch (ah->ah_radio_5ghz_revision & 0xf0) {
        case AR5K_SREV_RAD_5111:
                ah->ah_radio = AR5K_RF5111;
                ah->ah_single_chip = 0;
                ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
                                                        CHANNEL_2GHZ);
                break;
        case AR5K_SREV_RAD_5112:
        case AR5K_SREV_RAD_2112:
                ah->ah_radio = AR5K_RF5112;
                ah->ah_single_chip = 0;
                ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
                                                        CHANNEL_2GHZ);
                break;
        case AR5K_SREV_RAD_2413:
                ah->ah_radio = AR5K_RF2413;
                ah->ah_single_chip = 1;
                break;
        case AR5K_SREV_RAD_5413:
                ah->ah_radio = AR5K_RF5413;
                ah->ah_single_chip = 1;
                break;
        case AR5K_SREV_RAD_2316:
                ah->ah_radio = AR5K_RF2316;
                ah->ah_single_chip = 1;
                break;
        case AR5K_SREV_RAD_2317:
                ah->ah_radio = AR5K_RF2317;
                ah->ah_single_chip = 1;
                break;
        case AR5K_SREV_RAD_5424:
                if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
                    ah->ah_mac_version == AR5K_SREV_AR2417) {
                        ah->ah_radio = AR5K_RF2425;
                } else {
                        ah->ah_radio = AR5K_RF5413;
                }
                ah->ah_single_chip = 1;
                break;
        default:
                /* Identify radio based on mac/phy srev */
                if (ah->ah_version == AR5K_AR5210) {
                        ah->ah_radio = AR5K_RF5110;
                        ah->ah_single_chip = 0;
                } else if (ah->ah_version == AR5K_AR5211) {
                        ah->ah_radio = AR5K_RF5111;
                        ah->ah_single_chip = 0;
                        ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
                                                                CHANNEL_2GHZ);
                } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
                           ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
                           ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
                        ah->ah_radio = AR5K_RF2425;
                        ah->ah_single_chip = 1;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
                } else if (srev == AR5K_SREV_AR5213A &&
                           ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
                        ah->ah_radio = AR5K_RF5112;
                        ah->ah_single_chip = 0;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
                } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
                        ah->ah_radio = AR5K_RF2316;
                        ah->ah_single_chip = 1;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
                } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
                           ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
                        ah->ah_radio = AR5K_RF5413;
                        ah->ah_single_chip = 1;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
                } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
                           ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
                        ah->ah_radio = AR5K_RF2413;
                        ah->ah_single_chip = 1;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
                } else {
                        DBG("ath5k: Couldn't identify radio revision.\n");
                        ret = -ENOTSUP;
                        goto err_free;
                }
        }

        /* Return on unsuported chips (unsupported eeprom etc) */
        if ((srev >= AR5K_SREV_AR5416) &&
            (srev < AR5K_SREV_AR2425)) {
                DBG("ath5k: Device not yet supported.\n");
                ret = -ENOTSUP;
                goto err_free;
        }

        /*
         * Write PCI-E power save settings
         */
        if ((ah->ah_version == AR5K_AR5212) &&
            pci_find_capability(pdev, PCI_CAP_ID_EXP)) {
                ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
                ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
                /* Shut off RX when elecidle is asserted */
                ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
                ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
                /* TODO: EEPROM work */
                ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
                /* Shut off PLL and CLKREQ active in L1 */
                ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
                /* Preserce other settings */
                ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
                ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
                ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
                /* Reset SERDES to load new settings */
                ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
                mdelay(1);
        }

        /*
         * POST
         */
        ret = ath5k_hw_post(ah);
        if (ret)
                goto err_free;

        /* Enable pci core retry fix on Hainan (5213A) and later chips */
        if (srev >= AR5K_SREV_AR5213A)
                ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);

        /*
         * Get card capabilities, calibration values etc
         * TODO: EEPROM work
         */
        ret = ath5k_eeprom_init(ah);
        if (ret) {
                DBG("ath5k: unable to init EEPROM\n");
                goto err_free;
        }

        /* Get misc capabilities */
        ret = ath5k_hw_set_capabilities(ah);
        if (ret) {
                DBG("ath5k: unable to get device capabilities: 0x%04x\n",
                    sc->pdev->device);
                goto err_free;
        }

        if (srev >= AR5K_SREV_AR2414) {
                ah->ah_combined_mic = 1;
                AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
                                     AR5K_MISC_MODE_COMBINED_MIC);
        }

        /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
        memset(ah->ah_bssid, 0xff, ETH_ALEN);
        ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
        ath5k_hw_set_opmode(ah);

        ath5k_hw_rfgain_opt_init(ah);

        *hw = ah;
        return 0;
err_free:
        free(ah);
err:
        return ret;
}
void ath5k_hw_detach ( struct ath5k_hw ah)

ath5k_hw_detach - Free the ath5k_hw struct

: The &struct ath5k_hw

Definition at line 335 of file ath5k_attach.c.

References ath5k_hw::ah_rf_banks, ath5k_eeprom_detach(), and free.

Referenced by ath5k_probe(), and ath5k_remove().

int ath5k_init_leds ( struct ath5k_softc sc)
void ath5k_led_enable ( struct ath5k_softc sc)
void ath5k_led_off ( struct ath5k_softc sc)
void ath5k_unregister_leds ( struct ath5k_softc sc)
int ath5k_hw_nic_wakeup ( struct ath5k_hw ah,
int  flags,
int  initial 
)

Definition at line 282 of file ath5k_reset.c.

References ath5k_hw::ah_radio, ath5k_hw::ah_sc, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_PHY_MODE, AR5K_PHY_MODE_FREQ_2GHZ, AR5K_PHY_MODE_FREQ_5GHZ, AR5K_PHY_MODE_MOD_CCK, AR5K_PHY_MODE_MOD_DYN, AR5K_PHY_MODE_MOD_OFDM, AR5K_PHY_MODE_RAD_RF5111, AR5K_PHY_MODE_RAD_RF5112, AR5K_PHY_PLL, AR5K_PHY_PLL_40MHZ, AR5K_PHY_PLL_40MHZ_5413, AR5K_PHY_PLL_44MHZ, AR5K_PHY_PLL_RF5111, AR5K_PHY_PLL_RF5112, AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_RESET_CTL_BASEBAND, AR5K_RESET_CTL_DMA, AR5K_RESET_CTL_MAC, AR5K_RESET_CTL_PCI, AR5K_RESET_CTL_PCU, AR5K_RESET_CTL_PHY, AR5K_RF5112, AR5K_RF5413, ath5k_hw_nic_reset(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_wake(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, CHANNEL_TURBO, DBG, EINVAL, EIO, mdelay(), PCI_CAP_ID_EXP, pci_find_capability(), ath5k_softc::pdev, ret, and udelay().

Referenced by ath5k_hw_attach(), and ath5k_hw_reset().

{
        struct pci_device *pdev = ah->ah_sc->pdev;
        u32 turbo, mode, clock, bus_flags;
        int ret;

        turbo = 0;
        mode = 0;
        clock = 0;

        /* Wakeup the device */
        ret = ath5k_hw_wake(ah);
        if (ret) {
                DBG("ath5k: failed to wake up the MAC chip\n");
                return ret;
        }

        if (ah->ah_version != AR5K_AR5210) {
                /*
                 * Get channel mode flags
                 */

                if (ah->ah_radio >= AR5K_RF5112) {
                        mode = AR5K_PHY_MODE_RAD_RF5112;
                        clock = AR5K_PHY_PLL_RF5112;
                } else {
                        mode = AR5K_PHY_MODE_RAD_RF5111;        /*Zero*/
                        clock = AR5K_PHY_PLL_RF5111;            /*Zero*/
                }

                if (flags & CHANNEL_2GHZ) {
                        mode |= AR5K_PHY_MODE_FREQ_2GHZ;
                        clock |= AR5K_PHY_PLL_44MHZ;

                        if (flags & CHANNEL_CCK) {
                                mode |= AR5K_PHY_MODE_MOD_CCK;
                        } else if (flags & CHANNEL_OFDM) {
                                /* XXX Dynamic OFDM/CCK is not supported by the
                                 * AR5211 so we set MOD_OFDM for plain g (no
                                 * CCK headers) operation. We need to test
                                 * this, 5211 might support ofdm-only g after
                                 * all, there are also initial register values
                                 * in the code for g mode (see initvals.c). */
                                if (ah->ah_version == AR5K_AR5211)
                                        mode |= AR5K_PHY_MODE_MOD_OFDM;
                                else
                                        mode |= AR5K_PHY_MODE_MOD_DYN;
                        } else {
                                DBG("ath5k: invalid radio modulation mode\n");
                                return -EINVAL;
                        }
                } else if (flags & CHANNEL_5GHZ) {
                        mode |= AR5K_PHY_MODE_FREQ_5GHZ;

                        if (ah->ah_radio == AR5K_RF5413)
                                clock = AR5K_PHY_PLL_40MHZ_5413;
                        else
                                clock |= AR5K_PHY_PLL_40MHZ;

                        if (flags & CHANNEL_OFDM)
                                mode |= AR5K_PHY_MODE_MOD_OFDM;
                        else {
                                DBG("ath5k: invalid radio modulation mode\n");
                                return -EINVAL;
                        }
                } else {
                        DBG("ath5k: invalid radio frequency mode\n");
                        return -EINVAL;
                }

                if (flags & CHANNEL_TURBO)
                        turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
        } else { /* Reset the device */

                /* ...enable Atheros turbo mode if requested */
                if (flags & CHANNEL_TURBO)
                        ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
                                        AR5K_PHY_TURBO);
        }

        /* reseting PCI on PCI-E cards results card to hang
         * and always return 0xffff... so we ingore that flag
         * for PCI-E cards */
        if (pci_find_capability(pdev, PCI_CAP_ID_EXP))
                bus_flags = 0;
        else
                bus_flags = AR5K_RESET_CTL_PCI;

        /* Reset chipset */
        if (ah->ah_version == AR5K_AR5210) {
                ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
                        AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
                        AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
                mdelay(2);
        } else {
                ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
                        AR5K_RESET_CTL_BASEBAND | bus_flags);
        }
        if (ret) {
                DBG("ath5k: failed to reset the MAC chip\n");
                return -EIO;
        }

        /* ...wakeup again!*/
        ret = ath5k_hw_wake(ah);
        if (ret) {
                DBG("ath5k: failed to resume the MAC chip\n");
                return ret;
        }

        /* ...final warm reset */
        if (ath5k_hw_nic_reset(ah, 0)) {
                DBG("ath5k: failed to warm reset the MAC chip\n");
                return -EIO;
        }

        if (ah->ah_version != AR5K_AR5210) {

                /* ...update PLL if needed */
                if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
                        ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
                        udelay(300);
                }

                /* ...set the PHY operating mode */
                ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
                ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
        }

        return 0;
}
int ath5k_hw_reset ( struct ath5k_hw ah,
struct net80211_channel channel,
int  change_channel 
)

Definition at line 690 of file ath5k_reset.c.

References ath5k_hw::ah_bssid, ath5k_hw::ah_calibration, ath5k_hw::ah_capabilities, ath5k_hw::ah_gpio, ath5k_hw::ah_imr, ath5k_hw::ah_mac_srev, ath5k_hw::ah_radio, ath5k_hw::ah_rf_banks, ath5k_hw::ah_sta_id, ath5k_hw::ah_version, AR5K_ANT_FIXED_A, AR5K_ANT_FIXED_B, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_BEACON, AR5K_BEACON_ENABLE, AR5K_BEACON_RESET_TSF, AR5K_DEFAULT_ANTENNA, AR5K_DMASIZE_128B, AR5K_EEPROM_HDR_RFKILL, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_GPIOCR, AR5K_GPIODO, AR5K_HIGH_ID, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_LOW_ID, AR5K_MIC_QOS_CTL, AR5K_MIC_QOS_SEL, AR5K_MODE_11A, AR5K_MODE_11A_TURBO, AR5K_MODE_11B, AR5K_MODE_11G, AR5K_MODE_11G_TURBO, AR5K_MODE_XR, AR5K_PCICFG, AR5K_PCICFG_LEDSTATE, AR5K_PHY, AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ADC_TEST, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL, AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, AR5K_PHY_IQ_RUN, AR5K_PHY_RX_DELAY, AR5K_PHY_RX_DELAY_M, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY_TST1, AR5K_PHY_TST1_TXHOLD, AR5K_PISR, AR5K_QOS_NOACK, AR5K_QOS_NOACK_2BIT_VALUES, AR5K_QOS_NOACK_BIT_OFFSET, AR5K_QOS_NOACK_BYTE_OFFSET, AR5K_QUEUE_DCU_SEQNUM, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_BITS, AR5K_RF5111, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS_S, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_SREV_AR2413, AR5K_SREV_AR5211, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, AR5K_STA_ID1_DEFAULT_ANTENNA, AR5K_STA_ID1_DESC_ANTENNA, AR5K_STA_ID1_RTS_DEF_ANTENNA, AR5K_STA_ID1_SELFGEN_DEF_ANT, AR5K_TUNE_BMISS_THRES, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_RSSI_THRES, AR5K_TXCFG, AR5K_TXCFG_B_MODE, AR5K_TXCFG_SDMAMR, ath5k_hw_channel(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_gpio(), ath5k_hw_nic_wakeup(), ath5k_hw_noise_floor_calibration(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_reset_tx_queue(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_associd(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_imr(), ath5k_hw_set_opmode(), ath5k_hw_tweak_initval_settings(), ath5k_hw_txpower(), ath5k_hw_write_initvals(), ath5k_hw_write_ofdm_timings(), ath5k_hw_write_rate_duration(), ath5k_capabilities::cap_eeprom, net80211_channel::center_freq, CHANNEL_A, CHANNEL_B, CHANNEL_CCK, CHANNEL_G, CHANNEL_MODES, CHANNEL_OFDM, CHANNEL_T, CHANNEL_TG, CHANNEL_XR, DBG, delay, ath5k_eeprom_info::ee_header, EINVAL, net80211_channel::hw_value, mdelay(), NULL, ret, and udelay().

Referenced by ath5k_reset().

{
        u32 s_seq[10], s_ant, s_led[3], staid1_flags;
        u32 phy_tst1;
        u8 mode, freq, ee_mode, ant[2];
        int i, ret;

        s_ant = 0;
        ee_mode = 0;
        staid1_flags = 0;
        freq = 0;
        mode = 0;

        /*
         * Save some registers before a reset
         */
        /*DCU/Antenna selection not available on 5210*/
        if (ah->ah_version != AR5K_AR5210) {

                switch (channel->hw_value & CHANNEL_MODES) {
                case CHANNEL_A:
                        mode = AR5K_MODE_11A;
                        freq = AR5K_INI_RFGAIN_5GHZ;
                        ee_mode = AR5K_EEPROM_MODE_11A;
                        break;
                case CHANNEL_G:
                        mode = AR5K_MODE_11G;
                        freq = AR5K_INI_RFGAIN_2GHZ;
                        ee_mode = AR5K_EEPROM_MODE_11G;
                        break;
                case CHANNEL_B:
                        mode = AR5K_MODE_11B;
                        freq = AR5K_INI_RFGAIN_2GHZ;
                        ee_mode = AR5K_EEPROM_MODE_11B;
                        break;
                case CHANNEL_T:
                        mode = AR5K_MODE_11A_TURBO;
                        freq = AR5K_INI_RFGAIN_5GHZ;
                        ee_mode = AR5K_EEPROM_MODE_11A;
                        break;
                case CHANNEL_TG:
                        if (ah->ah_version == AR5K_AR5211) {
                                DBG("ath5k: TurboG not available on 5211\n");
                                return -EINVAL;
                        }
                        mode = AR5K_MODE_11G_TURBO;
                        freq = AR5K_INI_RFGAIN_2GHZ;
                        ee_mode = AR5K_EEPROM_MODE_11G;
                        break;
                case CHANNEL_XR:
                        if (ah->ah_version == AR5K_AR5211) {
                                DBG("ath5k: XR mode not available on 5211\n");
                                return -EINVAL;
                        }
                        mode = AR5K_MODE_XR;
                        freq = AR5K_INI_RFGAIN_5GHZ;
                        ee_mode = AR5K_EEPROM_MODE_11A;
                        break;
                default:
                        DBG("ath5k: invalid channel (%d MHz)\n",
                            channel->center_freq);
                        return -EINVAL;
                }

                if (change_channel) {
                        /*
                         * Save frame sequence count
                         * For revs. after Oahu, only save
                         * seq num for DCU 0 (Global seq num)
                         */
                        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {

                                for (i = 0; i < 10; i++)
                                        s_seq[i] = ath5k_hw_reg_read(ah,
                                                AR5K_QUEUE_DCU_SEQNUM(i));

                        } else {
                                s_seq[0] = ath5k_hw_reg_read(ah,
                                                AR5K_QUEUE_DCU_SEQNUM(0));
                        }
                }

                /* Save default antenna */
                s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);

                if (ah->ah_version == AR5K_AR5212) {
                        /* Since we are going to write rf buffer
                         * check if we have any pending gain_F
                         * optimization settings */
                        if (change_channel && ah->ah_rf_banks != NULL)
                                ath5k_hw_gainf_calibrate(ah);
                }
        }

        /*GPIOs*/
        s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
                                        AR5K_PCICFG_LEDSTATE;
        s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
        s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);

        /* AR5K_STA_ID1 flags, only preserve antenna
         * settings and ack/cts rate mode */
        staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
                        (AR5K_STA_ID1_DEFAULT_ANTENNA |
                        AR5K_STA_ID1_DESC_ANTENNA |
                        AR5K_STA_ID1_RTS_DEF_ANTENNA |
                        AR5K_STA_ID1_ACKCTS_6MB |
                        AR5K_STA_ID1_BASE_RATE_11B |
                        AR5K_STA_ID1_SELFGEN_DEF_ANT);

        /* Wakeup the device */
        ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, 0);
        if (ret)
                return ret;

        /* PHY access enable */
        if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
        else
                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
                                                        AR5K_PHY(0));

        /* Write initial settings */
        ret = ath5k_hw_write_initvals(ah, mode, change_channel);
        if (ret)
                return ret;

        /*
         * 5211/5212 Specific
         */
        if (ah->ah_version != AR5K_AR5210) {

                /*
                 * Write initial RF gain settings
                 * This should work for both 5111/5112
                 */
                ret = ath5k_hw_rfgain_init(ah, freq);
                if (ret)
                        return ret;

                mdelay(1);

                /*
                 * Tweak initval settings for revised
                 * chipsets and add some more config
                 * bits
                 */
                ath5k_hw_tweak_initval_settings(ah, channel);

                /*
                 * Set TX power (FIXME)
                 */
                ret = ath5k_hw_txpower(ah, channel, ee_mode,
                                        AR5K_TUNE_DEFAULT_TXPOWER);
                if (ret)
                        return ret;

                /* Write rate duration table only on AR5212 */
                if (ah->ah_version == AR5K_AR5212)
                        ath5k_hw_write_rate_duration(ah, mode);

                /*
                 * Write RF buffer
                 */
                ret = ath5k_hw_rfregs_init(ah, channel, mode);
                if (ret)
                        return ret;


                /* Write OFDM timings on 5212*/
                if (ah->ah_version == AR5K_AR5212 &&
                        channel->hw_value & CHANNEL_OFDM) {
                        ret = ath5k_hw_write_ofdm_timings(ah, channel);
                        if (ret)
                                return ret;
                }

                /*Enable/disable 802.11b mode on 5111
                (enable 2111 frequency converter + CCK)*/
                if (ah->ah_radio == AR5K_RF5111) {
                        if (mode == AR5K_MODE_11B)
                                AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
                                    AR5K_TXCFG_B_MODE);
                        else
                                AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
                                    AR5K_TXCFG_B_MODE);
                }

                /*
                 * In case a fixed antenna was set as default
                 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
                 * registers.
                 */
                if (s_ant != 0) {
                        if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
                                ant[0] = ant[1] = AR5K_ANT_FIXED_A;
                        else    /* 2 - Aux */
                                ant[0] = ant[1] = AR5K_ANT_FIXED_B;
                } else {
                        ant[0] = AR5K_ANT_FIXED_A;
                        ant[1] = AR5K_ANT_FIXED_B;
                }

                /* Commit values from EEPROM */
                ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode);

        } else {
                /*
                 * For 5210 we do all initialization using
                 * initvals, so we don't have to modify
                 * any settings (5210 also only supports
                 * a/aturbo modes)
                 */
                mdelay(1);
                /* Disable phy and wait */
                ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
                mdelay(1);
        }

        /*
         * Restore saved values
         */

        /*DCU/Antenna selection not available on 5210*/
        if (ah->ah_version != AR5K_AR5210) {

                if (change_channel) {
                        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
                                for (i = 0; i < 10; i++)
                                        ath5k_hw_reg_write(ah, s_seq[i],
                                                AR5K_QUEUE_DCU_SEQNUM(i));
                        } else {
                                ath5k_hw_reg_write(ah, s_seq[0],
                                        AR5K_QUEUE_DCU_SEQNUM(0));
                        }
                }

                ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
        }

        /* Ledstate */
        AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);

        /* Gpio settings */
        ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
        ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);

        /* Restore sta_id flags and preserve our mac address*/
        ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id),
                                                AR5K_STA_ID0);
        ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id),
                                                AR5K_STA_ID1);


        /*
         * Configure PCU
         */

        /* Restore bssid and bssid mask */
        /* XXX: add ah->aid once mac80211 gives this to us */
        ath5k_hw_set_associd(ah, ah->ah_bssid, 0);

        /* Set PCU config */
        ath5k_hw_set_opmode(ah);

        /* Clear any pending interrupts
         * PISR/SISR Not available on 5210 */
        if (ah->ah_version != AR5K_AR5210)
                ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);

        /* Set RSSI/BRSSI thresholds
         *
         * Note: If we decide to set this value
         * dynamicaly, have in mind that when AR5K_RSSI_THR
         * register is read it might return 0x40 if we haven't
         * wrote anything to it plus BMISS RSSI threshold is zeroed.
         * So doing a save/restore procedure here isn't the right
         * choice. Instead store it on ath5k_hw */
        ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
                                AR5K_TUNE_BMISS_THRES <<
                                AR5K_RSSI_THR_BMISS_S),
                                AR5K_RSSI_THR);

        /* MIC QoS support */
        if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
                ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
                ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
        }

        /* QoS NOACK Policy */
        if (ah->ah_version == AR5K_AR5212) {
                ath5k_hw_reg_write(ah,
                        AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
                        AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
                        AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
                        AR5K_QOS_NOACK);
        }


        /*
         * Configure PHY
         */

        /* Set channel on PHY */
        ret = ath5k_hw_channel(ah, channel);
        if (ret)
                return ret;

        /*
         * Enable the PHY and wait until completion
         * This includes BaseBand and Synthesizer
         * activation.
         */
        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);

        /*
         * On 5211+ read activation -> rx delay
         * and use it.
         *
         * TODO: Half/quarter rate support
         */
        if (ah->ah_version != AR5K_AR5210) {
                u32 delay;
                delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
                        AR5K_PHY_RX_DELAY_M;
                delay = (channel->hw_value & CHANNEL_CCK) ?
                        ((delay << 2) / 22) : (delay / 10);

                udelay(100 + (2 * delay));
        } else {
                mdelay(1);
        }

        /*
         * Perform ADC test to see if baseband is ready
         * Set tx hold and check adc test register
         */
        phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
        ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
        for (i = 0; i <= 20; i++) {
                if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
                        break;
                udelay(200);
        }
        ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);

        /*
         * Start automatic gain control calibration
         *
         * During AGC calibration RX path is re-routed to
         * a power detector so we don't receive anything.
         *
         * This method is used to calibrate some static offsets
         * used together with on-the fly I/Q calibration (the
         * one performed via ath5k_hw_phy_calibrate), that doesn't
         * interrupt rx path.
         *
         * While rx path is re-routed to the power detector we also
         * start a noise floor calibration, to measure the
         * card's noise floor (the noise we measure when we are not
         * transmiting or receiving anything).
         *
         * If we are in a noisy environment AGC calibration may time
         * out and/or noise floor calibration might timeout.
         */
        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
                                AR5K_PHY_AGCCTL_CAL);

        /* At the same time start I/Q calibration for QAM constellation
         * -no need for CCK- */
        ah->ah_calibration = 0;
        if (!(mode == AR5K_MODE_11B)) {
                ah->ah_calibration = 1;
                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
                                AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
                                AR5K_PHY_IQ_RUN);
        }

        /* Wait for gain calibration to finish (we check for I/Q calibration
         * during ath5k_phy_calibrate) */
        if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
                        AR5K_PHY_AGCCTL_CAL, 0, 0)) {
                DBG("ath5k: gain calibration timeout (%d MHz)\n",
                    channel->center_freq);
        }

        /*
         * If we run NF calibration before AGC, it always times out.
         * Binary HAL starts NF and AGC calibration at the same time
         * and only waits for AGC to finish. Also if AGC or NF cal.
         * times out, reset doesn't fail on binary HAL. I believe
         * that's wrong because since rx path is routed to a detector,
         * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211
         * enables noise floor calibration after offset calibration and if noise
         * floor calibration fails, reset fails. I believe that's
         * a better approach, we just need to find a polling interval
         * that suits best, even if reset continues we need to make
         * sure that rx path is ready.
         */
        ath5k_hw_noise_floor_calibration(ah, channel->center_freq);


        /*
         * Configure QCUs/DCUs
         */

        /* TODO: HW Compression support for data queues */
        /* TODO: Burst prefetch for data queues */

        /*
         * Reset queues and start beacon timers at the end of the reset routine
         * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
         * Note: If we want we can assign multiple qcus on one dcu.
         */
        ret = ath5k_hw_reset_tx_queue(ah);
        if (ret) {
                DBG("ath5k: failed to reset TX queue\n");
                return ret;
        }

        /*
         * Configure DMA/Interrupts
         */

        /*
         * Set Rx/Tx DMA Configuration
         *
         * Set standard DMA size (128). Note that
         * a DMA size of 512 causes rx overruns and tx errors
         * on pci-e cards (tested on 5424 but since rx overruns
         * also occur on 5416/5418 with madwifi we set 128
         * for all PCI-E cards to be safe).
         *
         * XXX: need to check 5210 for this
         * TODO: Check out tx triger level, it's always 64 on dumps but I
         * guess we can tweak it and see how it goes ;-)
         */
        if (ah->ah_version != AR5K_AR5210) {
                AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
                        AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
                AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
                        AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
        }

        /* Pre-enable interrupts on 5211/5212*/
        if (ah->ah_version != AR5K_AR5210)
                ath5k_hw_set_imr(ah, ah->ah_imr);

        /*
         * Setup RFKill interrupt if rfkill flag is set on eeprom.
         * TODO: Use gpio pin and polarity infos from eeprom
         * TODO: Handle this in ath5k_intr because it'll result
         *       a nasty interrupt storm.
         */
#if 0
        if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
                ath5k_hw_set_gpio_input(ah, 0);
                ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
                if (ah->ah_gpio[0] == 0)
                        ath5k_hw_set_gpio_intr(ah, 0, 1);
                else
                        ath5k_hw_set_gpio_intr(ah, 0, 0);
        }
#endif

        /*
         * Disable beacons and reset the register
         */
        AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
                        AR5K_BEACON_RESET_TSF);

        return 0;
}
int ath5k_hw_set_power ( struct ath5k_hw ah,
enum ath5k_power_mode  mode,
int  set_chip,
u16  sleep_duration 
)
void ath5k_hw_start_rx_dma ( struct ath5k_hw ah)

ath5k_hw_start_rx_dma - Start DMA receive

: The &struct ath5k_hw

Definition at line 54 of file ath5k_dma.c.

References AR5K_CR, AR5K_CR_RXE, ath5k_hw_reg_read(), and ath5k_hw_reg_write().

Referenced by ath5k_rx_start().

int ath5k_hw_stop_rx_dma ( struct ath5k_hw ah)

ath5k_hw_stop_rx_dma - Stop DMA receive

: The &struct ath5k_hw

Definition at line 65 of file ath5k_dma.c.

References AR5K_CR, AR5K_CR_RXD, AR5K_CR_RXE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, and udelay().

Referenced by ath5k_rx_stop().

{
        unsigned int i;

        ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);

        /*
         * It may take some time to disable the DMA receive unit
         */
        for (i = 1000; i > 0 &&
                        (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
                        i--)
                udelay(10);

        return i ? 0 : -EBUSY;
}
u32 ath5k_hw_get_rxdp ( struct ath5k_hw ah)

ath5k_hw_get_rxdp - Get RX Descriptor's address

: The &struct ath5k_hw

XXX: Is RXDP read and clear ?

Definition at line 89 of file ath5k_dma.c.

References AR5K_RXDP, and ath5k_hw_reg_read().

{
        return ath5k_hw_reg_read(ah, AR5K_RXDP);
}
void ath5k_hw_set_rxdp ( struct ath5k_hw ah,
u32  phys_addr 
)

ath5k_hw_set_rxdp - Set RX Descriptor's address

: The &struct ath5k_hw : RX descriptor address

XXX: Should we check if rx is enabled before setting rxdp ?

Definition at line 102 of file ath5k_dma.c.

References AR5K_RXDP, and ath5k_hw_reg_write().

Referenced by ath5k_rx_start().

{
        ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
}
int ath5k_hw_start_tx_dma ( struct ath5k_hw ah,
unsigned int  queue 
)

ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue

: The &struct ath5k_hw : The hw queue number

Start DMA transmit for a specific queue and since 5210 doesn't have QCU/DCU, set up queue parameters for 5210 here based on queue type (one queue for normal data and one queue for beacons). For queue setup on newer chips check out qcu.c. Returns -EINVAL if queue number is out of range or if queue is already disabled.

NOTE: Must be called after setting up tx control descriptor for that queue (see below).

Definition at line 127 of file ath5k_dma.c.

References ath5k_hw::ah_txq, ath5k_hw::ah_version, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_QCU_TXD, AR5K_QCU_TXE, AR5K_REG_READ_Q, AR5K_REG_WRITE_Q, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EIO, and ath5k_txq_info::tqi_type.

Referenced by ath5k_txbuf_setup().

{
        u32 tx_queue;

        /* Return if queue is declared inactive */
        if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE)
                return -EIO;

        if (ah->ah_version == AR5K_AR5210) {
                tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);

                /* Assume always a data queue */
                tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;

                /* Start queue */
                ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
                ath5k_hw_reg_read(ah, AR5K_CR);
        } else {
                /* Return if queue is disabled */
                if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
                        return -EIO;

                /* Start queue */
                AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
        }

        return 0;
}
int ath5k_hw_stop_tx_dma ( struct ath5k_hw ah,
unsigned int  queue 
)

ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue

: The &struct ath5k_hw : The hw queue number

Stop DMA transmit on a specific hw queue and drain queue so we don't have any pending frames. Returns -EBUSY if we still have pending frames, -EINVAL if queue number is out of range.

Definition at line 167 of file ath5k_dma.c.

References ath5k_hw::ah_mac_version, ath5k_hw::ah_txq, ath5k_hw::ah_version, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_DIAG_SW_5211, AR5K_DIAG_SW_CHANEL_IDLE_HIGH, AR5K_QCU_STS_FRMPENDCNT, AR5K_QCU_TXD, AR5K_QUEUE_STATUS, AR5K_QUIET_CTL1, AR5K_QUIET_CTL1_NEXT_QT_TSF, AR5K_QUIET_CTL1_QT_EN, AR5K_QUIET_CTL2, AR5K_QUIET_CTL2_QT_DUR, AR5K_QUIET_CTL2_QT_PER, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SREV_AR2414, AR5K_TSF_L32_5211, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, EIO, pending, ath5k_txq_info::tqi_type, and udelay().

Referenced by ath5k_txq_cleanup().

{
        unsigned int i = 40;
        u32 tx_queue, pending;

        /* Return if queue is declared inactive */
        if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE)
                return -EIO;

        if (ah->ah_version == AR5K_AR5210) {
                tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);

                /* Assume a data queue */
                tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;

                /* Stop queue */
                ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
                ath5k_hw_reg_read(ah, AR5K_CR);
        } else {
                /*
                 * Schedule TX disable and wait until queue is empty
                 */
                AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);

                /*Check for pending frames*/
                do {
                        pending = ath5k_hw_reg_read(ah,
                                AR5K_QUEUE_STATUS(queue)) &
                                AR5K_QCU_STS_FRMPENDCNT;
                        udelay(100);
                } while (--i && pending);

                /* For 2413+ order PCU to drop packets using
                 * QUIET mechanism */
                if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && pending) {
                        /* Set periodicity and duration */
                        ath5k_hw_reg_write(ah,
                                AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
                                AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR),
                                AR5K_QUIET_CTL2);

                        /* Enable quiet period for current TSF */
                        ath5k_hw_reg_write(ah,
                                AR5K_QUIET_CTL1_QT_EN |
                                AR5K_REG_SM(ath5k_hw_reg_read(ah,
                                                AR5K_TSF_L32_5211) >> 10,
                                                AR5K_QUIET_CTL1_NEXT_QT_TSF),
                                AR5K_QUIET_CTL1);

                        /* Force channel idle high */
                        AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
                                        AR5K_DIAG_SW_CHANEL_IDLE_HIGH);

                        /* Wait a while and disable mechanism */
                        udelay(200);
                        AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
                                                AR5K_QUIET_CTL1_QT_EN);

                        /* Re-check for pending frames */
                        i = 40;
                        do {
                                pending = ath5k_hw_reg_read(ah,
                                        AR5K_QUEUE_STATUS(queue)) &
                                        AR5K_QCU_STS_FRMPENDCNT;
                                udelay(100);
                        } while (--i && pending);

                        AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
                                        AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
                }

                /* Clear register */
                ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
                if (pending)
                        return -EBUSY;
        }

        /* TODO: Check for success on 5210 else return error */
        return 0;
}
u32 ath5k_hw_get_txdp ( struct ath5k_hw ah,
unsigned int  queue 
)

ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue

: The &struct ath5k_hw : The hw queue number

Get TX descriptor's address for a specific queue. For 5210 we ignore the queue number and use tx queue type since we only have 2 queues. We use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just read the corresponding TXDP register.

XXX: Is TXDP read and clear ?

Definition at line 261 of file ath5k_dma.c.

References ath5k_hw::ah_version, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QUEUE_TXDP, and ath5k_hw_reg_read().

Referenced by ath5k_txq_cleanup().

{
        u16 tx_reg;

        /*
         * Get the transmit queue descriptor pointer from the selected queue
         */
        /*5210 doesn't have QCU*/
        if (ah->ah_version == AR5K_AR5210) {
                /* Assume a data queue */
                tx_reg = AR5K_NOQCU_TXDP0;
        } else {
                tx_reg = AR5K_QUEUE_TXDP(queue);
        }

        return ath5k_hw_reg_read(ah, tx_reg);
}
int ath5k_hw_set_txdp ( struct ath5k_hw ah,
unsigned int  queue,
u32  phys_addr 
)

ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue

: The &struct ath5k_hw : The hw queue number

Set TX descriptor's address for a specific queue. For 5210 we ignore the queue number and we use tx queue type since we only have 2 queues so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just set the corresponding TXDP register. Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still active.

Definition at line 292 of file ath5k_dma.c.

References ath5k_hw::ah_version, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QCU_TXE, AR5K_QUEUE_TXDP, AR5K_REG_READ_Q, ath5k_hw_reg_write(), and EIO.

Referenced by ath5k_txbuf_setup().

{
        u16 tx_reg;

        /*
         * Set the transmit queue descriptor pointer register by type
         * on 5210
         */
        if (ah->ah_version == AR5K_AR5210) {
                /* Assume a data queue */
                tx_reg = AR5K_NOQCU_TXDP0;
        } else {
                /*
                 * Set the transmit queue descriptor pointer for
                 * the selected queue on QCU for 5211+
                 * (this won't work if the queue is still active)
                 */
                if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
                        return -EIO;

                tx_reg = AR5K_QUEUE_TXDP(queue);
        }

        /* Set descriptor pointer */
        ath5k_hw_reg_write(ah, phys_addr, tx_reg);

        return 0;
}
int ath5k_hw_update_tx_triglevel ( struct ath5k_hw ah,
int  increase 
)

ath5k_hw_update_tx_triglevel - Update tx trigger level

: The &struct ath5k_hw : Flag to force increase of trigger level

This function increases/decreases the tx trigger level for the tx fifo buffer (aka FIFO threshold) that is used to indicate when PCU flushes the buffer and transmits it's data. Lowering this results sending small frames more quickly but can lead to tx underruns, raising it a lot can result other problems (i think bmiss is related). Right now we start with the lowest possible (64Bytes) and if we get tx underrun we increase it using the increase flag. Returns -EIO if we have have reached maximum/minimum.

XXX: Link this with tx DMA size ? XXX: Use it to save interrupts ? TODO: Needs testing, i think it's related to bmiss...

Definition at line 339 of file ath5k_dma.c.

References ath5k_hw::ah_imr, ath5k_hw::ah_version, AR5K_AR5210, AR5K_INT_GLOBAL, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TRIG_LVL, AR5K_TUNE_MAX_TX_FIFO_THRES, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_TXCFG, AR5K_TXCFG_TXFULL, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_set_imr(), done, EIO, imr, and ret.

Referenced by ath5k_poll().

{
        u32 trigger_level, imr;
        int ret = -EIO;

        /*
         * Disable interrupts by setting the mask
         */
        imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);

        trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
                        AR5K_TXCFG_TXFULL);

        if (!increase) {
                if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
                        goto done;
        } else
                trigger_level +=
                        ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);

        /*
         * Update trigger level on success
         */
        if (ah->ah_version == AR5K_AR5210)
                ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
        else
                AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
                                AR5K_TXCFG_TXFULL, trigger_level);

        ret = 0;

done:
        /*
         * Restore interrupt mask
         */
        ath5k_hw_set_imr(ah, imr);

        return ret;
}
int ath5k_hw_is_intr_pending ( struct ath5k_hw ah)

ath5k_hw_is_intr_pending - Check if we have pending interrupts

: The &struct ath5k_hw

Check if we have pending interrupts to process. Returns 1 if we have pending interrupts and 0 if we haven't.

Definition at line 391 of file ath5k_dma.c.

References AR5K_INTPEND, and ath5k_hw_reg_read().

Referenced by ath5k_poll().

{
        return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
}
int ath5k_hw_get_isr ( struct ath5k_hw ah,
enum ath5k_int interrupt_mask 
)

Definition at line 412 of file ath5k_dma.c.

References ath5k_hw::ah_imr, ath5k_hw::ah_txq_isr, ath5k_hw::ah_version, AR5K_AR5210, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_NOCARD, AR5K_INT_QCBRORN, AR5K_INT_QCBRURN, AR5K_INT_QTRIG, AR5K_INT_RX_DOPPLER, AR5K_INT_TIM, AR5K_ISR, AR5K_ISR_BCNMISC, AR5K_ISR_BNR, AR5K_ISR_DPERR, AR5K_ISR_HIUERR, AR5K_ISR_MCABT, AR5K_ISR_QCBRORN, AR5K_ISR_QCBRURN, AR5K_ISR_QTRIG, AR5K_ISR_RXDOPPLER, AR5K_ISR_SSERR, AR5K_ISR_TIM, AR5K_ISR_TXDESC, AR5K_ISR_TXEOL, AR5K_ISR_TXERR, AR5K_ISR_TXOK, AR5K_ISR_TXURN, AR5K_RAC_PISR, AR5K_RAC_SISR0, AR5K_RAC_SISR1, AR5K_RAC_SISR2, AR5K_RAC_SISR3, AR5K_RAC_SISR4, AR5K_REG_MS, AR5K_SISR0_QCU_TXDESC, AR5K_SISR0_QCU_TXOK, AR5K_SISR1_QCU_TXEOL, AR5K_SISR1_QCU_TXERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DPERR, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_MCABT, AR5K_SISR2_QCU_TXURN, AR5K_SISR2_SSERR, AR5K_SISR2_TIM, AR5K_SISR3_QCBRORN, AR5K_SISR3_QCBRURN, AR5K_SISR4_QTRIG, ath5k_hw_reg_read(), data, and ENODEV.

Referenced by ath5k_poll().

{
        u32 data;

        /*
         * Read interrupt status from the Interrupt Status register
         * on 5210
         */
        if (ah->ah_version == AR5K_AR5210) {
                data = ath5k_hw_reg_read(ah, AR5K_ISR);
                if (data == AR5K_INT_NOCARD) {
                        *interrupt_mask = data;
                        return -ENODEV;
                }
        } else {
                /*
                 * Read interrupt status from Interrupt
                 * Status Register shadow copy (Read And Clear)
                 *
                 * Note: PISR/SISR Not available on 5210
                 */
                data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
                if (data == AR5K_INT_NOCARD) {
                        *interrupt_mask = data;
                        return -ENODEV;
                }
        }

        /*
         * Get abstract interrupt mask (driver-compatible)
         */
        *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;

        if (ah->ah_version != AR5K_AR5210) {
                u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2);

                /*HIU = Host Interface Unit (PCI etc)*/
                if (data & (AR5K_ISR_HIUERR))
                        *interrupt_mask |= AR5K_INT_FATAL;

                /*Beacon Not Ready*/
                if (data & (AR5K_ISR_BNR))
                        *interrupt_mask |= AR5K_INT_BNR;

                if (sisr2 & (AR5K_SISR2_SSERR | AR5K_SISR2_DPERR |
                             AR5K_SISR2_MCABT))
                        *interrupt_mask |= AR5K_INT_FATAL;

                if (data & AR5K_ISR_TIM)
                        *interrupt_mask |= AR5K_INT_TIM;

                if (data & AR5K_ISR_BCNMISC) {
                        if (sisr2 & AR5K_SISR2_TIM)
                                *interrupt_mask |= AR5K_INT_TIM;
                        if (sisr2 & AR5K_SISR2_DTIM)
                                *interrupt_mask |= AR5K_INT_DTIM;
                        if (sisr2 & AR5K_SISR2_DTIM_SYNC)
                                *interrupt_mask |= AR5K_INT_DTIM_SYNC;
                        if (sisr2 & AR5K_SISR2_BCN_TIMEOUT)
                                *interrupt_mask |= AR5K_INT_BCN_TIMEOUT;
                        if (sisr2 & AR5K_SISR2_CAB_TIMEOUT)
                                *interrupt_mask |= AR5K_INT_CAB_TIMEOUT;
                }

                if (data & AR5K_ISR_RXDOPPLER)
                        *interrupt_mask |= AR5K_INT_RX_DOPPLER;
                if (data & AR5K_ISR_QCBRORN) {
                        *interrupt_mask |= AR5K_INT_QCBRORN;
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
                                        AR5K_SISR3_QCBRORN);
                }
                if (data & AR5K_ISR_QCBRURN) {
                        *interrupt_mask |= AR5K_INT_QCBRURN;
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
                                        AR5K_SISR3_QCBRURN);
                }
                if (data & AR5K_ISR_QTRIG) {
                        *interrupt_mask |= AR5K_INT_QTRIG;
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR4),
                                        AR5K_SISR4_QTRIG);
                }

                if (data & AR5K_ISR_TXOK)
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
                                        AR5K_SISR0_QCU_TXOK);

                if (data & AR5K_ISR_TXDESC)
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
                                        AR5K_SISR0_QCU_TXDESC);

                if (data & AR5K_ISR_TXERR)
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
                                        AR5K_SISR1_QCU_TXERR);

                if (data & AR5K_ISR_TXEOL)
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
                                        AR5K_SISR1_QCU_TXEOL);

                if (data & AR5K_ISR_TXURN)
                        ah->ah_txq_isr |= AR5K_REG_MS(
                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR2),
                                        AR5K_SISR2_QCU_TXURN);
        } else {
                if (data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT |
                            AR5K_ISR_HIUERR | AR5K_ISR_DPERR))
                        *interrupt_mask |= AR5K_INT_FATAL;

                /*
                 * XXX: BMISS interrupts may occur after association.
                 * I found this on 5210 code but it needs testing. If this is
                 * true we should disable them before assoc and re-enable them
                 * after a successful assoc + some jiffies.
                        interrupt_mask &= ~AR5K_INT_BMISS;
                 */
        }

        return 0;
}
enum ath5k_int ath5k_hw_set_imr ( struct ath5k_hw ah,
enum ath5k_int  new_mask 
)

ath5k_hw_set_imr - Set interrupt mask

: The &struct ath5k_hw : The new interrupt mask to be set

Set the interrupt mask in hw to save interrupts. We do that by mapping ath5k_int bits to hw-specific bits to remove abstraction and writing Interrupt Mask Register.

Definition at line 548 of file ath5k_dma.c.

References ath5k_hw::ah_ier, ath5k_hw::ah_imr, ath5k_hw::ah_version, AR5K_AR5210, AR5K_IER, AR5K_IER_DISABLE, AR5K_IMR, AR5K_IMR_DPERR, AR5K_IMR_HIUERR, AR5K_IMR_MCABT, AR5K_IMR_RXDOPPLER, AR5K_IMR_SSERR, AR5K_IMR_TIM, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_GLOBAL, AR5K_INT_RX_DOPPLER, AR5K_INT_RXNOFRM, AR5K_INT_TIM, AR5K_PIMR, AR5K_RXNOFRM, AR5K_SIMR2, AR5K_SIMR2_DPERR, AR5K_SIMR2_MCABT, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR2_SSERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_TIM, ath5k_hw_reg_read(), and ath5k_hw_reg_write().

Referenced by ath5k_hw_reset(), ath5k_hw_update_tx_triglevel(), ath5k_irq(), ath5k_reset(), and ath5k_stop_hw().

{
        enum ath5k_int old_mask, int_mask;

        old_mask = ah->ah_imr;

        /*
         * Disable card interrupts to prevent any race conditions
         * (they will be re-enabled afterwards if AR5K_INT GLOBAL
         * is set again on the new mask).
         */
        if (old_mask & AR5K_INT_GLOBAL) {
                ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
                ath5k_hw_reg_read(ah, AR5K_IER);
        }

        /*
         * Add additional, chipset-dependent interrupt mask flags
         * and write them to the IMR (interrupt mask register).
         */
        int_mask = new_mask & AR5K_INT_COMMON;

        if (ah->ah_version != AR5K_AR5210) {
                /* Preserve per queue TXURN interrupt mask */
                u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
                                & AR5K_SIMR2_QCU_TXURN;

                if (new_mask & AR5K_INT_FATAL) {
                        int_mask |= AR5K_IMR_HIUERR;
                        simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR
                                | AR5K_SIMR2_DPERR);
                }

                /*Beacon Not Ready*/
                if (new_mask & AR5K_INT_BNR)
                        int_mask |= AR5K_INT_BNR;

                if (new_mask & AR5K_INT_TIM)
                        int_mask |= AR5K_IMR_TIM;

                if (new_mask & AR5K_INT_TIM)
                        simr2 |= AR5K_SISR2_TIM;
                if (new_mask & AR5K_INT_DTIM)
                        simr2 |= AR5K_SISR2_DTIM;
                if (new_mask & AR5K_INT_DTIM_SYNC)
                        simr2 |= AR5K_SISR2_DTIM_SYNC;
                if (new_mask & AR5K_INT_BCN_TIMEOUT)
                        simr2 |= AR5K_SISR2_BCN_TIMEOUT;
                if (new_mask & AR5K_INT_CAB_TIMEOUT)
                        simr2 |= AR5K_SISR2_CAB_TIMEOUT;

                if (new_mask & AR5K_INT_RX_DOPPLER)
                        int_mask |= AR5K_IMR_RXDOPPLER;

                /* Note: Per queue interrupt masks
                 * are set via reset_tx_queue (qcu.c) */
                ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
                ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);

        } else {
                if (new_mask & AR5K_INT_FATAL)
                        int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT
                                | AR5K_IMR_HIUERR | AR5K_IMR_DPERR);

                ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
        }

        /* If RXNOFRM interrupt is masked disable it
         * by setting AR5K_RXNOFRM to zero */
        if (!(new_mask & AR5K_INT_RXNOFRM))
                ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM);

        /* Store new interrupt mask */
        ah->ah_imr = new_mask;

        /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */
        if (new_mask & AR5K_INT_GLOBAL) {
                ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER);
                ath5k_hw_reg_read(ah, AR5K_IER);
        }

        return old_mask;
}
int ath5k_eeprom_init ( struct ath5k_hw ah)

Definition at line 1693 of file ath5k_eeprom.c.

References ath5k_eeprom_init_header(), ath5k_eeprom_init_modes(), ath5k_eeprom_read_ctl_info(), and ath5k_eeprom_read_pcal_info().

Referenced by ath5k_hw_attach().

{
        int err;

        err = ath5k_eeprom_init_header(ah);
        if (err < 0)
                return err;

        err = ath5k_eeprom_init_modes(ah);
        if (err < 0)
                return err;

        err = ath5k_eeprom_read_pcal_info(ah);
        if (err < 0)
                return err;

        err = ath5k_eeprom_read_ctl_info(ah);
        if (err < 0)
                return err;

        return 0;
}
void ath5k_eeprom_detach ( struct ath5k_hw ah)

Definition at line 1572 of file ath5k_eeprom.c.

References AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11G, and ath5k_eeprom_free_pcal_info().

Referenced by ath5k_hw_detach().

{
        u8 mode;

        for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
                ath5k_eeprom_free_pcal_info(ah, mode);
}
int ath5k_eeprom_read_mac ( struct ath5k_hw ah,
u8 mac 
)

Definition at line 1719 of file ath5k_eeprom.c.

References ath5k_hw_eeprom_read(), data, EINVAL, ETH_ALEN, memcpy(), offset, ret, and total.

Referenced by ath5k_attach().

{
        u8 mac_d[ETH_ALEN] = {};
        u32 total, offset;
        u16 data;
        int octet, ret;

        ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
        if (ret)
                return ret;

        for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
                ret = ath5k_hw_eeprom_read(ah, offset, &data);
                if (ret)
                        return ret;

                total += data;
                mac_d[octet + 1] = data & 0xff;
                mac_d[octet] = data >> 8;
                octet += 2;
        }

        if (!total || total == 3 * 0xffff)
                return -EINVAL;

        memcpy(mac, mac_d, ETH_ALEN);

        return 0;
}
int ath5k_eeprom_is_hb63 ( struct ath5k_hw ah)

Definition at line 1749 of file ath5k_eeprom.c.

References ath5k_hw::ah_mac_version, AR5K_EEPROM_IS_HB63, AR5K_SREV_AR2425, ath5k_hw_eeprom_read(), and data.

Referenced by ath5k_hw_tweak_initval_settings().

{
        u16 data;

        ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data);

        if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
                return 1;
        else
                return 0;
}
int ath5k_hw_set_opmode ( struct ath5k_hw ah)

ath5k_hw_set_opmode - Set PCU operating mode

: The &struct ath5k_hw

Initialize PCU for the various operating modes (AP/STA etc)

For iPXE we always assume STA mode.

Definition at line 48 of file ath5k_pcu.c.

References ath5k_hw::ah_sta_id, ath5k_hw::ah_version, AR5K_AR5210, AR5K_BCR, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ADHOC, AR5K_STA_ID1_AP, AR5K_STA_ID1_KEYSRCH_MODE, AR5K_STA_ID1_NO_PSPOLL, AR5K_STA_ID1_PWR_SV, ath5k_hw_reg_read(), and ath5k_hw_reg_write().

Referenced by ath5k_hw_attach(), ath5k_hw_reset(), and ath5k_mode_setup().

{
        u32 pcu_reg, beacon_reg, low_id, high_id;


        /* Preserve rest settings */
        pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
        pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
                        | AR5K_STA_ID1_KEYSRCH_MODE
                        | (ah->ah_version == AR5K_AR5210 ?
                        (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));

        beacon_reg = 0;

        pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
                | (ah->ah_version == AR5K_AR5210 ?
                   AR5K_STA_ID1_PWR_SV : 0);

        /*
         * Set PCU registers
         */
        low_id = AR5K_LOW_ID(ah->ah_sta_id);
        high_id = AR5K_HIGH_ID(ah->ah_sta_id);
        ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
        ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);

        /*
         * Set Beacon Control Register on 5210
         */
        if (ah->ah_version == AR5K_AR5210)
                ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);

        return 0;
}
void ath5k_hw_get_lladdr ( struct ath5k_hw ah,
u8 mac 
)

ath5k_hw_get_lladdr - Get station id

: The &struct ath5k_hw : The card's mac address

Initialize ah->ah_sta_id using the mac address provided (just a memcpy).

TODO: Remove it once we merge ath5k_softc and ath5k_hw

Definition at line 187 of file ath5k_pcu.c.

References ath5k_hw::ah_sta_id, ETH_ALEN, and memcpy().

int ath5k_hw_set_lladdr ( struct ath5k_hw ah,
const u8 mac 
)

ath5k_hw_set_lladdr - Set station id

: The &struct ath5k_hw : The card's mac address

Set station id on hw using the provided mac address

Definition at line 200 of file ath5k_pcu.c.

References ath5k_hw::ah_sta_id, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ETH_ALEN, and memcpy().

Referenced by ath5k_start(), and ath5k_stop().

{
        u32 low_id, high_id;
        u32 pcu_reg;

        /* Set new station ID */
        memcpy(ah->ah_sta_id, mac, ETH_ALEN);

        pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;

        low_id = AR5K_LOW_ID(mac);
        high_id = AR5K_HIGH_ID(mac);

        ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
        ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);

        return 0;
}
void ath5k_hw_set_associd ( struct ath5k_hw ah,
const u8 bssid,
u16  assoc_id 
)

ath5k_hw_set_associd - Set BSSID for association

: The &struct ath5k_hw : BSSID : Assoc id

Sets the BSSID which trigers the "SME Join" operation

Definition at line 228 of file ath5k_pcu.c.

References ath5k_hw::ah_bssid_mask, ath5k_hw::ah_version, AR5K_AR5212, AR5K_BSS_ID0, AR5K_BSS_ID1, AR5K_BSS_ID1_AID_S, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, and ath5k_hw_reg_write().

Referenced by ath5k_config(), ath5k_hw_attach(), and ath5k_hw_reset().

{
        u32 low_id, high_id;

        /*
         * Set simple BSSID mask on 5212
         */
        if (ah->ah_version == AR5K_AR5212) {
                ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_bssid_mask),
                                                        AR5K_BSS_IDM0);
                ath5k_hw_reg_write(ah, AR5K_HIGH_ID(ah->ah_bssid_mask),
                                                        AR5K_BSS_IDM1);
        }

        /*
         * Set BSSID which triggers the "SME Join" operation
         */
        low_id = AR5K_LOW_ID(bssid);
        high_id = AR5K_HIGH_ID(bssid);
        ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
        ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
                                AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
}
int ath5k_hw_set_bssid_mask ( struct ath5k_hw ah,
const u8 mask 
)

ath5k_hw_set_bssid_mask - filter out bssids we listen

: the &struct ath5k_hw : the bssid_mask, a u8 array of size ETH_ALEN

BSSID masking is a method used by AR5212 and newer hardware to inform PCU which bits of the interface's MAC address should be looked at when trying to decide which packets to ACK. In station mode and AP mode with a single BSS every bit matters since we lock to only one BSS. In AP mode with multiple BSSes (virtual interfaces) not every bit matters because hw must accept frames for all BSSes and so we tweak some bits of our mac address in order to have multiple BSSes.

NOTE: This is a simple filter and does *not* filter out all relevant frames. Some frames that are not for us might get ACKed from us by PCU because they just match the mask.

When handling multiple BSSes you can get the BSSID mask by computing the set of ~ ( MAC XOR BSSID ) for all bssids we handle.

When you do this you are essentially computing the common bits of all your BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with the MAC address to obtain the relevant bits and compare the result with (frame's BSSID & mask) to see if they match.

Definition at line 348 of file ath5k_pcu.c.

References ath5k_hw::ah_bssid_mask, ath5k_hw::ah_version, AR5K_AR5212, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, ath5k_hw_reg_write(), EIO, ETH_ALEN, and memcpy().

Referenced by ath5k_attach(), and ath5k_mode_setup().

{
        u32 low_id, high_id;

        /* Cache bssid mask so that we can restore it
         * on reset */
        memcpy(ah->ah_bssid_mask, mask, ETH_ALEN);
        if (ah->ah_version == AR5K_AR5212) {
                low_id = AR5K_LOW_ID(mask);
                high_id = AR5K_HIGH_ID(mask);

                ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
                ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);

                return 0;
        }

        return -EIO;
}
void ath5k_hw_start_rx_pcu ( struct ath5k_hw ah)

ath5k_hw_start_rx_pcu - Start RX engine

: The &struct ath5k_hw

Starts RX engine on PCU so that hw can process RXed frames (ACK etc).

NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma TODO: Init ANI here

Definition at line 384 of file ath5k_pcu.c.

References AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_DISABLE_BITS.

Referenced by ath5k_rx_start().

void ath5k_hw_stop_rx_pcu ( struct ath5k_hw ah)

at5k_hw_stop_rx_pcu - Stop RX engine

: The &struct ath5k_hw

Stops RX engine on PCU

TODO: Detach ANI here

Definition at line 398 of file ath5k_pcu.c.

References AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_ENABLE_BITS.

Referenced by ath5k_rx_stop().

void ath5k_hw_set_mcast_filter ( struct ath5k_hw ah,
u32  filter0,
u32  filter1 
)

Definition at line 406 of file ath5k_pcu.c.

References AR5K_MCAST_FILTER0, AR5K_MCAST_FILTER1, and ath5k_hw_reg_write().

Referenced by ath5k_configure_filter(), and ath5k_mode_setup().

{
        /* Set the multicat filter */
        ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
        ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
}

ath5k_hw_get_rx_filter - Get current rx filter

: The &struct ath5k_hw

Returns the RX filter by reading rx filter and phy error filter registers. RX filter is used to set the allowed frame types that PCU will accept and pass to the driver. For a list of frame types check out reg.h.

Definition at line 424 of file ath5k_pcu.c.

References ath5k_hw::ah_version, AR5K_AR5212, AR5K_PHY_ERR_FIL, AR5K_PHY_ERR_FIL_CCK, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHY_ERR_FIL_RADAR, AR5K_RX_FILTER, AR5K_RX_FILTER_PHYERR, AR5K_RX_FILTER_RADARERR, ath5k_hw_reg_read(), data, and filter.

{
        u32 data, filter = 0;

        filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);

        /*Radar detection for 5212*/
        if (ah->ah_version == AR5K_AR5212) {
                data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);

                if (data & AR5K_PHY_ERR_FIL_RADAR)
                        filter |= AR5K_RX_FILTER_RADARERR;
                if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
                        filter |= AR5K_RX_FILTER_PHYERR;
        }

        return filter;
}
void ath5k_hw_set_rx_filter ( struct ath5k_hw ah,
u32  filter 
)

ath5k_hw_set_rx_filter - Set rx filter

: The &struct ath5k_hw : RX filter mask (see reg.h)

Sets RX filter register and also handles PHY error filter register on 5212 and newer chips so that we have proper PHY error reporting.

Definition at line 453 of file ath5k_pcu.c.

References ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5212, AR5K_PHY_ERR_FIL, AR5K_PHY_ERR_FIL_CCK, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHY_ERR_FIL_RADAR, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_RX_FILTER, AR5K_RX_FILTER_PHYERR, AR5K_RX_FILTER_PROM, AR5K_RX_FILTER_RADARERR, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA, ath5k_hw_reg_write(), and data.

Referenced by ath5k_configure_filter(), ath5k_mode_setup(), and ath5k_rx_stop().

{
        u32 data = 0;

        /* Set PHY error filter register on 5212*/
        if (ah->ah_version == AR5K_AR5212) {
                if (filter & AR5K_RX_FILTER_RADARERR)
                        data |= AR5K_PHY_ERR_FIL_RADAR;
                if (filter & AR5K_RX_FILTER_PHYERR)
                        data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
        }

        /*
         * The AR5210 uses promiscous mode to detect radar activity
         */
        if (ah->ah_version == AR5K_AR5210 &&
                        (filter & AR5K_RX_FILTER_RADARERR)) {
                filter &= ~AR5K_RX_FILTER_RADARERR;
                filter |= AR5K_RX_FILTER_PROM;
        }

        /*Zero length DMA (phy error reporting) */
        if (data)
                AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
        else
                AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);

        /*Write RX Filter register*/
        ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);

        /*Write PHY error filter register on 5212*/
        if (ah->ah_version == AR5K_AR5212)
                ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);

}
void ath5k_hw_set_ack_bitrate_high ( struct ath5k_hw ah,
int  high 
)

ath5k_hw_set_ack_bitrate - set bitrate for ACKs

: The &struct ath5k_hw : Flag to determine if we want to use high transmition rate for ACKs or not

If high flag is set, we tell hw to use a set of control rates based on the current transmition rate (check out control_rates array inside reset.c). If not hw just uses the lowest rate available for the current modulation scheme being used (1Mbit for CCK and 6Mbits for OFDM).

Definition at line 95 of file ath5k_pcu.c.

References ath5k_hw::ah_version, AR5K_AR5212, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, and val.

Referenced by ath5k_init().

int ath5k_hw_set_ack_timeout ( struct ath5k_hw ah,
unsigned int  timeout 
)

ath5k_hw_set_ack_timeout - Set ACK timeout on PCU

: The &struct ath5k_hw : Timeout in usec

Definition at line 130 of file ath5k_pcu.c.

References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_clocktoh(), ath5k_hw_htoclock(), and EINVAL.

unsigned int ath5k_hw_get_ack_timeout ( struct ath5k_hw ah)

ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec

: The &struct ath5k_hw

Definition at line 118 of file ath5k_pcu.c.

References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_clocktoh(), and ath5k_hw_reg_read().

int ath5k_hw_set_cts_timeout ( struct ath5k_hw ah,
unsigned int  timeout 
)

ath5k_hw_set_cts_timeout - Set CTS timeout on PCU

: The &struct ath5k_hw : Timeout in usec

Definition at line 159 of file ath5k_pcu.c.

References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_clocktoh(), ath5k_hw_htoclock(), and EINVAL.

unsigned int ath5k_hw_get_cts_timeout ( struct ath5k_hw ah)

ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec

: The &struct ath5k_hw

Definition at line 147 of file ath5k_pcu.c.

References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_clocktoh(), and ath5k_hw_reg_read().

int ath5k_hw_reset_key ( struct ath5k_hw ah,
u16  entry 
)

Definition at line 496 of file ath5k_pcu.c.

References ath5k_hw::ah_version, AR5K_AR5211, AR5K_KEYCACHE_SIZE, AR5K_KEYTABLE_MIC_OFFSET, AR5K_KEYTABLE_OFF, AR5K_KEYTABLE_TYPE, AR5K_KEYTABLE_TYPE_NULL, AR5K_KEYTABLE_TYPE_TKIP, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and type.

Referenced by ath5k_init().

{
        unsigned int i, type;
        u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;

        type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));

        for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
                ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));

        /* Reset associated MIC entry if TKIP
         * is enabled located at offset (entry + 64) */
        if (type == AR5K_KEYTABLE_TYPE_TKIP) {
                for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
                        ath5k_hw_reg_write(ah, 0,
                                AR5K_KEYTABLE_OFF(micentry, i));
        }

        /*
         * Set NULL encryption on AR5212+
         *
         * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
         *       AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
         *
         * Note2: Windows driver (ndiswrapper) sets this to
         *        0x00000714 instead of 0x00000007
         */
        if (ah->ah_version >= AR5K_AR5211) {
                ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
                                AR5K_KEYTABLE_TYPE(entry));

                if (type == AR5K_KEYTABLE_TYPE_TKIP) {
                        ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
                                AR5K_KEYTABLE_TYPE(micentry));
                }
        }

        return 0;
}
int ath5k_hw_set_tx_queueprops ( struct ath5k_hw ah,
const struct ath5k_txq_info queue_info 
)
int ath5k_hw_setup_tx_queue ( struct ath5k_hw ah,
enum ath5k_tx_queue  queue_type,
struct ath5k_txq_info queue_info 
)

Definition at line 55 of file ath5k_qcu.c.

References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_ENABLE_BITS, ath5k_hw_set_tx_queueprops(), memset(), NULL, ret, and ath5k_txq_info::tqi_type.

Referenced by ath5k_txq_setup().

{
        int ret;

        /*
         * Setup internal queue structure
         */
        memset(&ah->ah_txq, 0, sizeof(struct ath5k_txq_info));
        ah->ah_txq.tqi_type = queue_type;

        if (queue_info != NULL) {
                queue_info->tqi_type = queue_type;
                ret = ath5k_hw_set_tx_queueprops(ah, queue_info);
                if (ret)
                        return ret;
        }

        /*
         * We use ah_txq_status to hold a temp value for
         * the Secondary interrupt mask registers on 5211+
         * check out ath5k_hw_reset_tx_queue
         */
        AR5K_Q_ENABLE_BITS(ah->ah_txq_status, 0);

        return 0;
}
void ath5k_hw_release_tx_queue ( struct ath5k_hw ah)

Definition at line 86 of file ath5k_qcu.c.

References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_DISABLE_BITS, AR5K_TX_QUEUE_INACTIVE, and ath5k_txq_info::tqi_type.

Referenced by ath5k_txq_release().

{
        /* This queue will be skipped in further operations */
        ah->ah_txq.tqi_type = AR5K_TX_QUEUE_INACTIVE;
        /*For SIMR setup*/
        AR5K_Q_DISABLE_BITS(ah->ah_txq_status, 0);
}
int ath5k_hw_reset_tx_queue ( struct ath5k_hw ah)

Definition at line 97 of file ath5k_qcu.c.

References ath5k_hw::ah_aifs, ath5k_hw::ah_current_channel, ath5k_hw::ah_cw_max, ath5k_hw::ah_cw_min, ath5k_hw::ah_limit_tx_retries, ath5k_hw::ah_mac_version, ath5k_hw::ah_software_retry, ath5k_hw::ah_turbo, ath5k_hw::ah_txq, ath5k_hw::ah_txq_imr_cbrorn, ath5k_hw::ah_txq_imr_cbrurn, ath5k_hw::ah_txq_imr_nofrm, ath5k_hw::ah_txq_imr_qtrig, ath5k_hw::ah_txq_imr_txdesc, ath5k_hw::ah_txq_imr_txeol, ath5k_hw::ah_txq_imr_txerr, ath5k_hw::ah_txq_imr_txok, ath5k_hw::ah_txq_imr_txurn, ath5k_hw::ah_txq_status, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5212, AR5K_DCU_CHAN_TIME_DUR, AR5K_DCU_CHAN_TIME_ENABLE, AR5K_DCU_LCL_IFS_AIFS, AR5K_DCU_LCL_IFS_CW_MAX, AR5K_DCU_LCL_IFS_CW_MIN, AR5K_DCU_MISC_BACKOFF_FRAG, AR5K_DCU_MISC_FRAG_WAIT, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, AR5K_DCU_MISC_SEQNUM_CTL, AR5K_DCU_RETRY_LMT_LG_RETRY, AR5K_DCU_RETRY_LMT_SH_RETRY, AR5K_DCU_RETRY_LMT_SLG_RETRY, AR5K_DCU_RETRY_LMT_SSH_RETRY, AR5K_IFS0, AR5K_IFS0_DIFS_S, AR5K_IFS1, AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_INIT_ACK_CTS_TIMEOUT_TURBO, AR5K_INIT_LG_RETRY, AR5K_INIT_PROTO_TIME_CNTRL, AR5K_INIT_PROTO_TIME_CNTRL_TURBO, AR5K_INIT_SH_RETRY, AR5K_INIT_SIFS, AR5K_INIT_SIFS_TURBO, AR5K_INIT_SLG_RETRY, AR5K_INIT_SLOT_TIME, AR5K_INIT_SLOT_TIME_TURBO, AR5K_INIT_SSH_RETRY, AR5K_INIT_TRANSMIT_LATENCY, AR5K_INIT_TRANSMIT_LATENCY_TURBO, AR5K_NODCU_RETRY_LMT, AR5K_NODCU_RETRY_LMT_CW_MIN_S, AR5K_NODCU_RETRY_LMT_LG_RETRY, AR5K_NODCU_RETRY_LMT_SH_RETRY, AR5K_NODCU_RETRY_LMT_SLG_RETRY, AR5K_NODCU_RETRY_LMT_SSH_RETRY, AR5K_PHY_FRAME_CTL_5210, AR5K_PHY_FRAME_CTL_INI, AR5K_PHY_SETTLING, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_Q_ENABLE_BITS, AR5K_QCU_CBRCFG_INTVAL, AR5K_QCU_CBRCFG_ORN_THRES, AR5K_QCU_MISC_CBR_THRES_ENABLE, AR5K_QCU_MISC_DCU_EARLY, AR5K_QCU_MISC_FRSHED_CBR, AR5K_QCU_MISC_RDY_VEOL_POLICY, AR5K_QCU_RDYTIMECFG_ENABLE, AR5K_QCU_RDYTIMECFG_INTVAL, AR5K_QUEUE_CBRCFG, AR5K_QUEUE_DFS_CHANNEL_TIME, AR5K_QUEUE_DFS_LOCAL_IFS, AR5K_QUEUE_DFS_MISC, AR5K_QUEUE_DFS_RETRY_LIMIT, AR5K_QUEUE_MISC, AR5K_QUEUE_QCUMASK, AR5K_QUEUE_RDYTIMECFG, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SIMR0, AR5K_SIMR0_QCU_TXDESC, AR5K_SIMR0_QCU_TXOK, AR5K_SIMR1, AR5K_SIMR1_QCU_TXEOL, AR5K_SIMR1_QCU_TXERR, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR3, AR5K_SIMR3_QCBRORN, AR5K_SIMR3_QCBRURN, AR5K_SIMR4, AR5K_SIMR4_QTRIG, AR5K_SLOT_TIME, AR5K_SREV_AR5211, AR5K_TUNE_AIFS, AR5K_TUNE_AIFS_11B, AR5K_TUNE_AIFS_XR, AR5K_TUNE_CWMAX, AR5K_TUNE_CWMAX_11B, AR5K_TUNE_CWMAX_XR, AR5K_TUNE_CWMIN, AR5K_TUNE_CWMIN_11B, AR5K_TUNE_CWMIN_XR, AR5K_TX_QUEUE_CAB, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_INACTIVE, AR5K_TXNOFRM, AR5K_TXNOFRM_QCU, AR5K_TXQ_FLAG_BACKOFF_DISABLE, AR5K_TXQ_FLAG_CBRORNINT_ENABLE, AR5K_TXQ_FLAG_CBRURNINT_ENABLE, AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, AR5K_TXQ_FLAG_QTRIGINT_ENABLE, AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, AR5K_TXQ_FLAG_TXDESCINT_ENABLE, AR5K_TXQ_FLAG_TXEOLINT_ENABLE, AR5K_TXQ_FLAG_TXERRINT_ENABLE, AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE, AR5K_TXQ_FLAG_TXOKINT_ENABLE, AR5K_TXQ_FLAG_TXURNINT_ENABLE, AR5K_USEC_5210, ath5k_hw_reg_read(), ath5k_hw_reg_write(), IS_CHAN_B, IS_CHAN_XR, queue, ath5k_txq_info::tqi_aifs, ath5k_txq_info::tqi_burst_time, ath5k_txq_info::tqi_cbr_overflow_limit, ath5k_txq_info::tqi_cbr_period, ath5k_txq_info::tqi_cw_max, ath5k_txq_info::tqi_cw_min, ath5k_txq_info::tqi_flags, ath5k_txq_info::tqi_ready_time, and ath5k_txq_info::tqi_type.

Referenced by ath5k_hw_reset().

{
        u32 cw_min, cw_max, retry_lg, retry_sh;
        struct ath5k_txq_info *tq = &ah->ah_txq;
        const int queue = 0;

        tq = &ah->ah_txq;

        if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
                return 0;

        if (ah->ah_version == AR5K_AR5210) {
                /* Only handle data queues, others will be ignored */
                if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
                        return 0;

                /* Set Slot time */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
                        AR5K_SLOT_TIME);
                /* Set ACK_CTS timeout */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
                        AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
                /* Set Transmit Latency */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_TRANSMIT_LATENCY_TURBO :
                        AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);

                /* Set IFS0 */
                if (ah->ah_turbo) {
                         ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
                                (ah->ah_aifs + tq->tqi_aifs) *
                                AR5K_INIT_SLOT_TIME_TURBO) <<
                                AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
                                AR5K_IFS0);
                } else {
                        ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
                                (ah->ah_aifs + tq->tqi_aifs) *
                                AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
                                AR5K_INIT_SIFS, AR5K_IFS0);
                }

                /* Set IFS1 */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
                        AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
                /* Set AR5K_PHY_SETTLING */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
                        | 0x38 :
                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
                        | 0x1C,
                        AR5K_PHY_SETTLING);
                /* Set Frame Control Register */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
                        AR5K_PHY_TURBO_SHORT | 0x2020) :
                        (AR5K_PHY_FRAME_CTL_INI | 0x1020),
                        AR5K_PHY_FRAME_CTL_5210);
        }

        /*
         * Calculate cwmin/max by channel mode
         */
        cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
        cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
        ah->ah_aifs = AR5K_TUNE_AIFS;
        /*XR is only supported on 5212*/
        if (IS_CHAN_XR(ah->ah_current_channel) &&
                        ah->ah_version == AR5K_AR5212) {
                cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
                cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
                ah->ah_aifs = AR5K_TUNE_AIFS_XR;
        /*B mode is not supported on 5210*/
        } else if (IS_CHAN_B(ah->ah_current_channel) &&
                        ah->ah_version != AR5K_AR5210) {
                cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
                cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
                ah->ah_aifs = AR5K_TUNE_AIFS_11B;
        }

        cw_min = 1;
        while (cw_min < ah->ah_cw_min)
                cw_min = (cw_min << 1) | 1;

        cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
                ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
        cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
                ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);

        /*
         * Calculate and set retry limits
         */
        if (ah->ah_software_retry) {
                /* XXX Need to test this */
                retry_lg = ah->ah_limit_tx_retries;
                retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
                        AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
        } else {
                retry_lg = AR5K_INIT_LG_RETRY;
                retry_sh = AR5K_INIT_SH_RETRY;
        }

        /*No QCU/DCU [5210]*/
        if (ah->ah_version == AR5K_AR5210) {
                ath5k_hw_reg_write(ah,
                        (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
                        | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
                                AR5K_NODCU_RETRY_LMT_SLG_RETRY)
                        | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
                                AR5K_NODCU_RETRY_LMT_SSH_RETRY)
                        | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
                        | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
                        AR5K_NODCU_RETRY_LMT);
        } else {
                /*QCU/DCU [5211+]*/
                ath5k_hw_reg_write(ah,
                        AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
                                AR5K_DCU_RETRY_LMT_SLG_RETRY) |
                        AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
                                AR5K_DCU_RETRY_LMT_SSH_RETRY) |
                        AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
                        AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
                        AR5K_QUEUE_DFS_RETRY_LIMIT(queue));

        /*===Rest is also for QCU/DCU only [5211+]===*/

                /*
                 * Set initial content window (cw_min/cw_max)
                 * and arbitrated interframe space (aifs)...
                 */
                ath5k_hw_reg_write(ah,
                        AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
                        AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
                        AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
                                AR5K_DCU_LCL_IFS_AIFS),
                        AR5K_QUEUE_DFS_LOCAL_IFS(queue));

                /*
                 * Set misc registers
                 */
                /* Enable DCU early termination for this queue */
                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                        AR5K_QCU_MISC_DCU_EARLY);

                /* Enable DCU to wait for next fragment from QCU */
                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
                                        AR5K_DCU_MISC_FRAG_WAIT);

                /* On Maui and Spirit use the global seqnum on DCU */
                if (ah->ah_mac_version < AR5K_SREV_AR5211)
                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
                                                AR5K_DCU_MISC_SEQNUM_CTL);

                if (tq->tqi_cbr_period) {
                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
                                AR5K_QCU_CBRCFG_INTVAL) |
                                AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
                                AR5K_QCU_CBRCFG_ORN_THRES),
                                AR5K_QUEUE_CBRCFG(queue));
                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                AR5K_QCU_MISC_FRSHED_CBR);
                        if (tq->tqi_cbr_overflow_limit)
                                AR5K_REG_ENABLE_BITS(ah,
                                        AR5K_QUEUE_MISC(queue),
                                        AR5K_QCU_MISC_CBR_THRES_ENABLE);
                }

                if (tq->tqi_ready_time &&
                (tq->tqi_type != AR5K_TX_QUEUE_CAB))
                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
                                AR5K_QCU_RDYTIMECFG_INTVAL) |
                                AR5K_QCU_RDYTIMECFG_ENABLE,
                                AR5K_QUEUE_RDYTIMECFG(queue));

                if (tq->tqi_burst_time) {
                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
                                AR5K_DCU_CHAN_TIME_DUR) |
                                AR5K_DCU_CHAN_TIME_ENABLE,
                                AR5K_QUEUE_DFS_CHANNEL_TIME(queue));

                        if (tq->tqi_flags
                        & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
                                AR5K_REG_ENABLE_BITS(ah,
                                        AR5K_QUEUE_MISC(queue),
                                        AR5K_QCU_MISC_RDY_VEOL_POLICY);
                }

                if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
                                AR5K_QUEUE_DFS_MISC(queue));

                if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
                                AR5K_QUEUE_DFS_MISC(queue));

                /* TODO: Handle frame compression */

                /*
                 * Enable interrupts for this tx queue
                 * in the secondary interrupt mask registers
                 */
                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);

                /* Update secondary interrupt mask registers */

                /* Filter out inactive queues */
                ah->ah_txq_imr_txok &= ah->ah_txq_status;
                ah->ah_txq_imr_txerr &= ah->ah_txq_status;
                ah->ah_txq_imr_txurn &= ah->ah_txq_status;
                ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
                ah->ah_txq_imr_txeol &= ah->ah_txq_status;
                ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
                ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
                ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
                ah->ah_txq_imr_nofrm &= ah->ah_txq_status;

                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
                        AR5K_SIMR0_QCU_TXOK) |
                        AR5K_REG_SM(ah->ah_txq_imr_txdesc,
                        AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
                        AR5K_SIMR1_QCU_TXERR) |
                        AR5K_REG_SM(ah->ah_txq_imr_txeol,
                        AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
                /* Update simr2 but don't overwrite rest simr2 settings */
                AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
                AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
                        AR5K_REG_SM(ah->ah_txq_imr_txurn,
                        AR5K_SIMR2_QCU_TXURN));
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
                        AR5K_SIMR3_QCBRORN) |
                        AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
                        AR5K_SIMR3_QCBRURN), AR5K_SIMR3);
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
                        AR5K_SIMR4_QTRIG), AR5K_SIMR4);
                /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
                        AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
                /* No queue has TXNOFRM enabled, disable the interrupt
                 * by setting AR5K_TXNOFRM to zero */
                if (ah->ah_txq_imr_nofrm == 0)
                        ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);

                /* Set QCU mask for this DCU to save power */
                AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
        }

        return 0;
}
int ath5k_hw_set_slot_time ( struct ath5k_hw ah,
unsigned int  slot_time 
)

Definition at line 377 of file ath5k_qcu.c.

References ath5k_hw::ah_turbo, ath5k_hw::ah_version, AR5K_AR5210, AR5K_DCU_GBL_IFS_SLOT, AR5K_SLOT_TIME, AR5K_SLOT_TIME_MAX, ath5k_hw_htoclock(), ath5k_hw_reg_write(), and EINVAL.

{
        if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
                return -EINVAL;

        if (ah->ah_version == AR5K_AR5210)
                ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
                                ah->ah_turbo), AR5K_SLOT_TIME);
        else
                ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);

        return 0;
}
int ath5k_hw_init_desc_functions ( struct ath5k_hw ah)
int ath5k_hw_set_gpio_input ( struct ath5k_hw ah,
u32  gpio 
)
int ath5k_hw_set_gpio_output ( struct ath5k_hw ah,
u32  gpio 
)
u32 ath5k_hw_get_gpio ( struct ath5k_hw ah,
u32  gpio 
)

Definition at line 64 of file ath5k_gpio.c.

References AR5K_GPIODI, AR5K_GPIODI_M, AR5K_NUM_GPIO, and ath5k_hw_reg_read().

Referenced by ath5k_hw_reset(), ath5k_is_rfkill_set(), and ath5k_rfkill_set_intr().

{
        if (gpio >= AR5K_NUM_GPIO)
                return 0xffffffff;

        /* GPIO input magic */
        return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
                0x1;
}
int ath5k_hw_set_gpio ( struct ath5k_hw ah,
u32  gpio,
u32  val 
)

Definition at line 77 of file ath5k_gpio.c.

References AR5K_GPIODO, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), data, EINVAL, and gpio.

Referenced by ath5k_rfkill_disable(), and ath5k_rfkill_enable().

{
        u32 data;

        if (gpio >= AR5K_NUM_GPIO)
                return -EINVAL;

        /* GPIO output magic */
        data = ath5k_hw_reg_read(ah, AR5K_GPIODO);

        data &= ~(1 << gpio);
        data |= (val & 1) << gpio;

        ath5k_hw_reg_write(ah, data, AR5K_GPIODO);

        return 0;
}
void ath5k_hw_set_gpio_intr ( struct ath5k_hw ah,
unsigned int  gpio,
u32  interrupt_level 
)
void ath5k_rfkill_hw_start ( struct ath5k_hw ah)
void ath5k_rfkill_hw_stop ( struct ath5k_hw ah)

Definition at line 97 of file ath5k_rfkill.c.

References ath5k_hw::ah_capabilities, ath5k_hw::ah_sc, AR5K_EEPROM_HDR_RFKILL, ath5k_rfkill_enable(), ath5k_rfkill_set_intr(), ath5k_capabilities::cap_eeprom, and ath5k_eeprom_info::ee_header.

Referenced by ath5k_stop_hw().

{
        struct ath5k_softc *sc = ah->ah_sc;

        /* disable interrupt for rfkill switch */
        if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header))
                ath5k_rfkill_set_intr(sc, 0);

        /* enable RFKILL when stopping HW so Wifi LED is turned off */
        ath5k_rfkill_enable(sc);
}
int ath5k_hw_set_capabilities ( struct ath5k_hw ah)

Definition at line 36 of file ath5k_caps.c.

References ath5k_hw::ah_capabilities, ath5k_hw::ah_gpio_npins, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_EEPROM_HDR_11A, AR5K_EEPROM_HDR_11B, AR5K_EEPROM_HDR_11G, AR5K_MODE_BIT_11A, AR5K_MODE_BIT_11A_TURBO, AR5K_MODE_BIT_11B, AR5K_MODE_BIT_11G, AR5K_MODE_BIT_11G_TURBO, AR5K_NUM_GPIO, ath5k_capabilities::cap_eeprom, ath5k_capabilities::cap_mode, ath5k_capabilities::cap_queues, ath5k_capabilities::cap_range, ath5k_eeprom_info::ee_header, ath5k_capabilities::q_tx_num, ath5k_capabilities::range_2ghz_max, ath5k_capabilities::range_2ghz_min, ath5k_capabilities::range_5ghz_max, and ath5k_capabilities::range_5ghz_min.

Referenced by ath5k_hw_attach().

{
        u16 ee_header;

        /* Capabilities stored in the EEPROM */
        ee_header = ah->ah_capabilities.cap_eeprom.ee_header;

        if (ah->ah_version == AR5K_AR5210) {
                /*
                 * Set radio capabilities
                 * (The AR5110 only supports the middle 5GHz band)
                 */
                ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
                ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
                ah->ah_capabilities.cap_range.range_2ghz_min = 0;
                ah->ah_capabilities.cap_range.range_2ghz_max = 0;

                /* Set supported modes */
                ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A;
                ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO;
        } else {
                /*
                 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
                 * XXX and from 2312 to 2732GHz. There are problems with the
                 * XXX current ieee80211 implementation because the IEEE
                 * XXX channel mapping does not support negative channel
                 * XXX numbers (2312MHz is channel -19). Of course, this
                 * XXX doesn't matter because these channels are out of range
                 * XXX but some regulation domains like MKK (Japan) will
                 * XXX support frequencies somewhere around 4.8GHz.
                 */

                /*
                 * Set radio capabilities
                 */

                if (AR5K_EEPROM_HDR_11A(ee_header)) {
                        /* 4920 */
                        ah->ah_capabilities.cap_range.range_5ghz_min = 5005;
                        ah->ah_capabilities.cap_range.range_5ghz_max = 6100;

                        /* Set supported modes */
                        ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A;
                        ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO;
                        if (ah->ah_version == AR5K_AR5212)
                                ah->ah_capabilities.cap_mode |=
                                        AR5K_MODE_BIT_11G_TURBO;
                }

                /* Enable  802.11b if a 2GHz capable radio (2111/5112) is
                 * connected */
                if (AR5K_EEPROM_HDR_11B(ee_header) ||
                    (AR5K_EEPROM_HDR_11G(ee_header) &&
                     ah->ah_version != AR5K_AR5211)) {
                        /* 2312 */
                        ah->ah_capabilities.cap_range.range_2ghz_min = 2412;
                        ah->ah_capabilities.cap_range.range_2ghz_max = 2732;

                        if (AR5K_EEPROM_HDR_11B(ee_header))
                                ah->ah_capabilities.cap_mode |=
                                        AR5K_MODE_BIT_11B;

                        if (AR5K_EEPROM_HDR_11G(ee_header) &&
                            ah->ah_version != AR5K_AR5211)
                                ah->ah_capabilities.cap_mode |=
                                        AR5K_MODE_BIT_11G;
                }
        }

        /* GPIO */
        ah->ah_gpio_npins = AR5K_NUM_GPIO;

        /* Set number of supported TX queues */
        ah->ah_capabilities.cap_queues.q_tx_num = 1;

        return 0;
}
int ath5k_hw_get_capability ( struct ath5k_hw ah,
enum ath5k_capability_type  cap_type,
u32  capability,
u32 result 
)

Definition at line 115 of file ath5k_caps.c.

References ath5k_hw::ah_version, AR5K_AR5212, AR5K_CAP_BSSIDMASK, AR5K_CAP_BURST, AR5K_CAP_COMPRESSION, AR5K_CAP_NUM_TXQUEUES, AR5K_CAP_TPC, AR5K_CAP_VEOL, AR5K_CAP_XR, and EINVAL.

{
        switch (cap_type) {
        case AR5K_CAP_NUM_TXQUEUES:
                if (result) {
                        *result = 1;
                        goto yes;
                }
        case AR5K_CAP_VEOL:
                goto yes;
        case AR5K_CAP_COMPRESSION:
                if (ah->ah_version == AR5K_AR5212)
                        goto yes;
                else
                        goto no;
        case AR5K_CAP_BURST:
                goto yes;
        case AR5K_CAP_TPC:
                goto yes;
        case AR5K_CAP_BSSIDMASK:
                if (ah->ah_version == AR5K_AR5212)
                        goto yes;
                else
                        goto no;
        case AR5K_CAP_XR:
                if (ah->ah_version == AR5K_AR5212)
                        goto yes;
                else
                        goto no;
        default:
                goto no;
        }

no:
        return -EINVAL;
yes:
        return 0;
}
int ath5k_hw_enable_pspoll ( struct ath5k_hw ah,
u8 bssid,
u16  assoc_id 
)
int ath5k_hw_disable_pspoll ( struct ath5k_hw ah)
int ath5k_hw_write_initvals ( struct ath5k_hw ah,
u8  mode,
int  change_channel 
)

Definition at line 1418 of file ath5k_initvals.c.

References ath5k_hw::ah_radio, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_PHY_AGC, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, ARRAY_SIZE, ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_reg_write(), DBG, and EINVAL.

Referenced by ath5k_hw_reset().

{
        /*
         * Write initial register settings
         */

        /* For AR5212 and combatible */
        if (ah->ah_version == AR5K_AR5212) {

                /* First set of mode-specific settings */
                ath5k_hw_ini_mode_registers(ah,
                        ARRAY_SIZE(ar5212_ini_mode_start),
                        ar5212_ini_mode_start, mode);

                /*
                 * Write initial settings common for all modes
                 */
                ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
                                ar5212_ini_common_start, change_channel);

                /* Second set of mode-specific settings */
                switch (ah->ah_radio) {
                case AR5K_RF5111:

                        ath5k_hw_ini_mode_registers(ah,
                                        ARRAY_SIZE(rf5111_ini_mode_end),
                                        rf5111_ini_mode_end, mode);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5111_ini_common_end),
                                        rf5111_ini_common_end, change_channel);

                        /* Baseband gain table */
                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5111_ini_bbgain),
                                        rf5111_ini_bbgain, change_channel);

                        break;
                case AR5K_RF5112:

                        ath5k_hw_ini_mode_registers(ah,
                                        ARRAY_SIZE(rf5112_ini_mode_end),
                                        rf5112_ini_mode_end, mode);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5112_ini_common_end),
                                        rf5112_ini_common_end, change_channel);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5112_ini_bbgain),
                                        rf5112_ini_bbgain, change_channel);

                        break;
                case AR5K_RF5413:

                        ath5k_hw_ini_mode_registers(ah,
                                        ARRAY_SIZE(rf5413_ini_mode_end),
                                        rf5413_ini_mode_end, mode);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5413_ini_common_end),
                                        rf5413_ini_common_end, change_channel);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5112_ini_bbgain),
                                        rf5112_ini_bbgain, change_channel);

                        break;
                case AR5K_RF2316:
                case AR5K_RF2413:

                        ath5k_hw_ini_mode_registers(ah,
                                        ARRAY_SIZE(rf2413_ini_mode_end),
                                        rf2413_ini_mode_end, mode);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf2413_ini_common_end),
                                        rf2413_ini_common_end, change_channel);

                        /* Override settings from rf2413_ini_common_end */
                        if (ah->ah_radio == AR5K_RF2316) {
                                ath5k_hw_reg_write(ah, 0x00004000,
                                                        AR5K_PHY_AGC);
                                ath5k_hw_reg_write(ah, 0x081b7caa,
                                                        0xa274);
                        }

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5112_ini_bbgain),
                                        rf5112_ini_bbgain, change_channel);
                        break;
                case AR5K_RF2317:
                case AR5K_RF2425:

                        ath5k_hw_ini_mode_registers(ah,
                                        ARRAY_SIZE(rf2425_ini_mode_end),
                                        rf2425_ini_mode_end, mode);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf2425_ini_common_end),
                                        rf2425_ini_common_end, change_channel);

                        ath5k_hw_ini_registers(ah,
                                        ARRAY_SIZE(rf5112_ini_bbgain),
                                        rf5112_ini_bbgain, change_channel);
                        break;
                default:
                        return -EINVAL;

                }

        /* For AR5211 */
        } else if (ah->ah_version == AR5K_AR5211) {

                /* AR5K_MODE_11B */
                if (mode > 2) {
                        DBG("ath5k: unsupported channel mode %d\n", mode);
                        return -EINVAL;
                }

                /* Mode-specific settings */
                ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
                                ar5211_ini_mode, mode);

                /*
                 * Write initial settings common for all modes
                 */
                ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
                                ar5211_ini, change_channel);

                /* AR5211 only comes with 5111 */

                /* Baseband gain table */
                ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
                                rf5111_ini_bbgain, change_channel);
        /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
        } else if (ah->ah_version == AR5K_AR5210) {
                ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
                                ar5210_ini, change_channel);
        }

        return 0;
}
int ath5k_hw_rfregs_init ( struct ath5k_hw ah,
struct net80211_channel channel,
unsigned int  mode 
)

Definition at line 514 of file ath5k_phy.c.

References ath5k_hw::ah_capabilities, ath5k_hw::ah_gain, ath5k_hw::ah_mac_srev, ath5k_hw::ah_offset, ath5k_hw::ah_phy_revision, ath5k_hw::ah_radio, ath5k_hw::ah_radio_5ghz_revision, ath5k_hw::ah_rf_banks, ath5k_hw::ah_rf_banks_size, ath5k_hw::ah_rf_regs_count, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_MAX_RF_BANKS, AR5K_PHY_FRAME_CTL, AR5K_PHY_FRAME_CTL_TX_CLIP, AR5K_REG_WAIT, AR5K_REG_WRITE_BITS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_RF_DB_2GHZ, AR5K_RF_DB_5GHZ, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF_GAIN_I, AR5K_RF_HIGH_VC_CP, AR5K_RF_LOW_VC_CP, AR5K_RF_MID_VC_CP, AR5K_RF_MIXGAIN_OVR, AR5K_RF_OB_2GHZ, AR5K_RF_OB_5GHZ, AR5K_RF_PAD2GND, AR5K_RF_PD_GAIN_HI, AR5K_RF_PD_GAIN_LO, AR5K_RF_PLO_SEL, AR5K_RF_PUSH_UP, AR5K_RF_PWD_130, AR5K_RF_PWD_131, AR5K_RF_PWD_132, AR5K_RF_PWD_136, AR5K_RF_PWD_137, AR5K_RF_PWD_138, AR5K_RF_PWD_166, AR5K_RF_PWD_167, AR5K_RF_PWD_84, AR5K_RF_PWD_90, AR5K_RF_PWD_ICLOBUF_2G, AR5K_RF_PWD_XPD, AR5K_RF_RFGAIN_SEL, AR5K_RF_XB2_LVL, AR5K_RF_XB5_LVL, AR5K_RF_XPD_GAIN, AR5K_RF_XPD_SEL, AR5K_RFGAIN_ACTIVE, AR5K_SREV_AR2417, AR5K_SREV_AR5413, AR5K_SREV_AR5424, AR5K_SREV_PHY_5212A, AR5K_SREV_RAD_5112A, ARRAY_SIZE, ath5k_hw_bitswap(), ath5k_hw_reg_write(), ath5k_hw_rfb_op(), ath5k_capabilities::cap_eeprom, net80211_channel::center_freq, CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, DBG, ath5k_eeprom_info::ee_db, ath5k_eeprom_info::ee_i_gain, ath5k_eeprom_info::ee_ob, ath5k_eeprom_info::ee_x_gain, ath5k_eeprom_info::ee_xpd, EINVAL, ENOMEM, ath5k_gain::g_state, ath5k_gain::g_step_idx, ath5k_gain_opt::go_step, ath5k_gain_opt_step::gos_param, net80211_channel::hw_value, malloc(), NULL, rf_regs_2316, rf_regs_2413, rf_regs_2425, rf_regs_5111, rf_regs_5112, rf_regs_5112a, rf_regs_5413, rfb_2316, rfb_2317, rfb_2413, rfb_2417, rfb_2425, rfb_5111, rfb_5112, rfb_5112a, rfb_5413, ath5k_ini_rfbuffer::rfb_bank, ath5k_ini_rfbuffer::rfb_mode_data, rfgain_opt_5111, and rfgain_opt_5112.

Referenced by ath5k_hw_reset().

{
        const struct ath5k_rf_reg *rf_regs;
        const struct ath5k_ini_rfbuffer *ini_rfb;
        const struct ath5k_gain_opt *go = NULL;
        const struct ath5k_gain_opt_step *g_step;
        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
        u8 ee_mode = 0;
        u32 *rfb;
        int obdb = -1, bank = -1;
        unsigned i;

        switch (ah->ah_radio) {
        case AR5K_RF5111:
                rf_regs = rf_regs_5111;
                ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
                ini_rfb = rfb_5111;
                ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
                go = &rfgain_opt_5111;
                break;
        case AR5K_RF5112:
                if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
                        rf_regs = rf_regs_5112a;
                        ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
                        ini_rfb = rfb_5112a;
                        ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
                } else {
                        rf_regs = rf_regs_5112;
                        ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
                        ini_rfb = rfb_5112;
                        ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
                }
                go = &rfgain_opt_5112;
                break;
        case AR5K_RF2413:
                rf_regs = rf_regs_2413;
                ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
                ini_rfb = rfb_2413;
                ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
                break;
        case AR5K_RF2316:
                rf_regs = rf_regs_2316;
                ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
                ini_rfb = rfb_2316;
                ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
                break;
        case AR5K_RF5413:
                rf_regs = rf_regs_5413;
                ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
                ini_rfb = rfb_5413;
                ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
                break;
        case AR5K_RF2317:
                rf_regs = rf_regs_2425;
                ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
                ini_rfb = rfb_2317;
                ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
                break;
        case AR5K_RF2425:
                rf_regs = rf_regs_2425;
                ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
                if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
                        ini_rfb = rfb_2425;
                        ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
                } else {
                        ini_rfb = rfb_2417;
                        ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
                }
                break;
        default:
                return -EINVAL;
        }

        /* If it's the first time we set rf buffer, allocate
         * ah->ah_rf_banks based on ah->ah_rf_banks_size
         * we set above */
        if (ah->ah_rf_banks == NULL) {
                ah->ah_rf_banks = malloc(sizeof(u32) * ah->ah_rf_banks_size);
                if (ah->ah_rf_banks == NULL) {
                        return -ENOMEM;
                }
        }

        /* Copy values to modify them */
        rfb = ah->ah_rf_banks;

        for (i = 0; i < ah->ah_rf_banks_size; i++) {
                if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
                        DBG("ath5k: invalid RF register bank\n");
                        return -EINVAL;
                }

                /* Bank changed, write down the offset */
                if (bank != ini_rfb[i].rfb_bank) {
                        bank = ini_rfb[i].rfb_bank;
                        ah->ah_offset[bank] = i;
                }

                rfb[i] = ini_rfb[i].rfb_mode_data[mode];
        }

        /* Set Output and Driver bias current (OB/DB) */
        if (channel->hw_value & CHANNEL_2GHZ) {

                if (channel->hw_value & CHANNEL_CCK)
                        ee_mode = AR5K_EEPROM_MODE_11B;
                else
                        ee_mode = AR5K_EEPROM_MODE_11G;

                /* For RF511X/RF211X combination we
                 * use b_OB and b_DB parameters stored
                 * in eeprom on ee->ee_ob[ee_mode][0]
                 *
                 * For all other chips we use OB/DB for 2Ghz
                 * stored in the b/g modal section just like
                 * 802.11a on ee->ee_ob[ee_mode][1] */
                if ((ah->ah_radio == AR5K_RF5111) ||
                (ah->ah_radio == AR5K_RF5112))
                        obdb = 0;
                else
                        obdb = 1;

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
                                                AR5K_RF_OB_2GHZ, 1);

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
                                                AR5K_RF_DB_2GHZ, 1);

        /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
        } else if ((channel->hw_value & CHANNEL_5GHZ) ||
                        (ah->ah_radio == AR5K_RF5111)) {

                /* For 11a, Turbo and XR we need to choose
                 * OB/DB based on frequency range */
                ee_mode = AR5K_EEPROM_MODE_11A;
                obdb =   channel->center_freq >= 5725 ? 3 :
                        (channel->center_freq >= 5500 ? 2 :
                        (channel->center_freq >= 5260 ? 1 :
                         (channel->center_freq > 4000 ? 0 : -1)));

                if (obdb < 0)
                        return -EINVAL;

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
                                                AR5K_RF_OB_5GHZ, 1);

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
                                                AR5K_RF_DB_5GHZ, 1);
        }

        g_step = &go->go_step[ah->ah_gain.g_step_idx];

        /* Bank Modifications (chip-specific) */
        if (ah->ah_radio == AR5K_RF5111) {

                /* Set gain_F settings according to current step */
                if (channel->hw_value & CHANNEL_OFDM) {

                        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
                                        AR5K_PHY_FRAME_CTL_TX_CLIP,
                                        g_step->gos_param[0]);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
                                                        AR5K_RF_PWD_90, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
                                                        AR5K_RF_PWD_84, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
                                                AR5K_RF_RFGAIN_SEL, 1);

                        /* We programmed gain_F parameters, switch back
                         * to active state */
                        ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;

                }

                /* Bank 6/7 setup */

                ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
                                                AR5K_RF_PWD_XPD, 1);

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
                                                AR5K_RF_XPD_GAIN, 1);

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
                                                AR5K_RF_GAIN_I, 1);

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
                                                AR5K_RF_PLO_SEL, 1);

                /* TODO: Half/quarter channel support */
        }

        if (ah->ah_radio == AR5K_RF5112) {

                /* Set gain_F settings according to current step */
                if (channel->hw_value & CHANNEL_OFDM) {

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
                                                AR5K_RF_MIXGAIN_OVR, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
                                                AR5K_RF_PWD_138, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
                                                AR5K_RF_PWD_137, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
                                                AR5K_RF_PWD_136, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
                                                AR5K_RF_PWD_132, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
                                                AR5K_RF_PWD_131, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
                                                AR5K_RF_PWD_130, 1);

                        /* We programmed gain_F parameters, switch back
                         * to active state */
                        ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
                }

                /* Bank 6/7 setup */

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
                                                AR5K_RF_XPD_SEL, 1);

                if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
                        /* Rev. 1 supports only one xpd */
                        ath5k_hw_rfb_op(ah, rf_regs,
                                                ee->ee_x_gain[ee_mode],
                                                AR5K_RF_XPD_GAIN, 1);

                } else {
                        /* TODO: Set high and low gain bits */
                        ath5k_hw_rfb_op(ah, rf_regs,
                                                ee->ee_x_gain[ee_mode],
                                                AR5K_RF_PD_GAIN_LO, 1);
                        ath5k_hw_rfb_op(ah, rf_regs,
                                                ee->ee_x_gain[ee_mode],
                                                AR5K_RF_PD_GAIN_HI, 1);

                        /* Lower synth voltage on Rev 2 */
                        ath5k_hw_rfb_op(ah, rf_regs, 2,
                                        AR5K_RF_HIGH_VC_CP, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, 2,
                                        AR5K_RF_MID_VC_CP, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, 2,
                                        AR5K_RF_LOW_VC_CP, 1);

                        ath5k_hw_rfb_op(ah, rf_regs, 2,
                                        AR5K_RF_PUSH_UP, 1);

                        /* Decrease power consumption on 5213+ BaseBand */
                        if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
                                ath5k_hw_rfb_op(ah, rf_regs, 1,
                                                AR5K_RF_PAD2GND, 1);

                                ath5k_hw_rfb_op(ah, rf_regs, 1,
                                                AR5K_RF_XB2_LVL, 1);

                                ath5k_hw_rfb_op(ah, rf_regs, 1,
                                                AR5K_RF_XB5_LVL, 1);

                                ath5k_hw_rfb_op(ah, rf_regs, 1,
                                                AR5K_RF_PWD_167, 1);

                                ath5k_hw_rfb_op(ah, rf_regs, 1,
                                                AR5K_RF_PWD_166, 1);
                        }
                }

                ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
                                                AR5K_RF_GAIN_I, 1);

                /* TODO: Half/quarter channel support */

        }

        if (ah->ah_radio == AR5K_RF5413 &&
        channel->hw_value & CHANNEL_2GHZ) {

                ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
                                                                        1);

                /* Set optimum value for early revisions (on pci-e chips) */
                if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
                ah->ah_mac_srev < AR5K_SREV_AR5413)
                        ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
                                                AR5K_RF_PWD_ICLOBUF_2G, 1);

        }

        /* Write RF banks on hw */
        for (i = 0; i < ah->ah_rf_banks_size; i++) {
                AR5K_REG_WAIT(i);
                ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
        }

        return 0;
}
int ath5k_hw_rfgain_init ( struct ath5k_hw ah,
unsigned int  freq 
)

Definition at line 452 of file ath5k_phy.c.

References ath5k_hw::ah_radio, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_REG_WAIT, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, ARRAY_SIZE, ath5k_hw_reg_write(), EINVAL, ath5k_ini_rfgain::rfg_register, ath5k_ini_rfgain::rfg_value, rfgain_2316, rfgain_2413, rfgain_2425, rfgain_5111, rfgain_5112, rfgain_5413, and size.

Referenced by ath5k_hw_reset().

{
        const struct ath5k_ini_rfgain *ath5k_rfg;
        unsigned int i, size;

        switch (ah->ah_radio) {
        case AR5K_RF5111:
                ath5k_rfg = rfgain_5111;
                size = ARRAY_SIZE(rfgain_5111);
                break;
        case AR5K_RF5112:
                ath5k_rfg = rfgain_5112;
                size = ARRAY_SIZE(rfgain_5112);
                break;
        case AR5K_RF2413:
                ath5k_rfg = rfgain_2413;
                size = ARRAY_SIZE(rfgain_2413);
                break;
        case AR5K_RF2316:
                ath5k_rfg = rfgain_2316;
                size = ARRAY_SIZE(rfgain_2316);
                break;
        case AR5K_RF5413:
                ath5k_rfg = rfgain_5413;
                size = ARRAY_SIZE(rfgain_5413);
                break;
        case AR5K_RF2317:
        case AR5K_RF2425:
                ath5k_rfg = rfgain_2425;
                size = ARRAY_SIZE(rfgain_2425);
                break;
        default:
                return -EINVAL;
        }

        switch (freq) {
        case AR5K_INI_RFGAIN_2GHZ:
        case AR5K_INI_RFGAIN_5GHZ:
                break;
        default:
                return -EINVAL;
        }

        for (i = 0; i < size; i++) {
                AR5K_REG_WAIT(i);
                ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
                        (u32)ath5k_rfg[i].rfg_register);
        }

        return 0;
}

Definition at line 389 of file ath5k_phy.c.

References ath5k_hw::ah_capabilities, ath5k_hw::ah_gain, ath5k_hw::ah_radio_5ghz_revision, ath5k_hw::ah_rf_banks, AR5K_GAIN_CCK_PROBE_CORR, AR5K_GAIN_CHECK_ADJUST, AR5K_PHY_PAPD_PROBE, AR5K_PHY_PAPD_PROBE_GAINF_S, AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE_TYPE, AR5K_PHY_PAPD_PROBE_TYPE_CCK, AR5K_REG_MS, AR5K_RFGAIN_ACTIVE, AR5K_RFGAIN_INACTIVE, AR5K_RFGAIN_NEED_CHANGE, AR5K_RFGAIN_READ_REQUESTED, AR5K_SREV_RAD_5112A, ath5k_hw_reg_read(), ath5k_hw_rf_check_gainf_readback(), ath5k_hw_rf_gainf_adjust(), ath5k_hw_rf_gainf_corr(), ath5k_capabilities::cap_eeprom, data, done, ath5k_eeprom_info::ee_cck_ofdm_gain_delta, ath5k_gain::g_current, ath5k_gain::g_f_corr, ath5k_gain::g_state, NULL, and type.

Referenced by ath5k_calibrate(), and ath5k_hw_reset().

{
        u32 data, type;
        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;

        if (ah->ah_rf_banks == NULL ||
        ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
                return AR5K_RFGAIN_INACTIVE;

        /* No check requested, either engine is inactive
         * or an adjustment is already requested */
        if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
                goto done;

        /* Read the PAPD (Peak to Average Power Detector)
         * register */
        data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);

        /* No probe is scheduled, read gain_F measurement */
        if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
                ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
                type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);

                /* If tx packet is CCK correct the gain_F measurement
                 * by cck ofdm gain delta */
                if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
                        if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
                                ah->ah_gain.g_current +=
                                        ee->ee_cck_ofdm_gain_delta;
                        else
                                ah->ah_gain.g_current +=
                                        AR5K_GAIN_CCK_PROBE_CORR;
                }

                /* Further correct gain_F measurement for
                 * RF5112A radios */
                if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
                        ath5k_hw_rf_gainf_corr(ah);
                        ah->ah_gain.g_current =
                                ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
                                (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
                                0;
                }

                /* Check if measurement is ok and if we need
                 * to adjust gain, schedule a gain adjustment,
                 * else switch back to the acive state */
                if (ath5k_hw_rf_check_gainf_readback(ah) &&
                AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
                ath5k_hw_rf_gainf_adjust(ah)) {
                        ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
                } else {
                        ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
                }
        }

done:
        return ah->ah_gain.g_state;
}
int ath5k_hw_rfgain_opt_init ( struct ath5k_hw ah)
int ath5k_channel_ok ( struct ath5k_hw ah,
u16  freq,
unsigned int  flags 
)

Definition at line 830 of file ath5k_phy.c.

References ath5k_hw::ah_capabilities, ath5k_capabilities::cap_range, CHANNEL_2GHZ, CHANNEL_5GHZ, ath5k_capabilities::range_2ghz_min, and ath5k_capabilities::range_5ghz_min.

Referenced by ath5k_copy_channels(), and ath5k_hw_channel().

{
        /* Check if the channel is in our supported range */
        if (flags & CHANNEL_2GHZ) {
                if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
                    (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
                        return 1;
        } else if (flags & CHANNEL_5GHZ)
                if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
                    (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
                        return 1;

        return 0;
}
int ath5k_hw_channel ( struct ath5k_hw ah,
struct net80211_channel channel 
)

Definition at line 1048 of file ath5k_phy.c.

References ath5k_hw::ah_current_channel, ath5k_hw::ah_radio, ath5k_hw::ah_turbo, AR5K_PHY_CCKTXCTL, AR5K_PHY_CCKTXCTL_JAPAN, AR5K_PHY_CCKTXCTL_WORLD, AR5K_REG_ENABLE_BITS, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, ath5k_channel_ok(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_channel(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), net80211_channel::center_freq, channel, CHANNEL_T, DBG, EINVAL, net80211_channel::hw_value, ret, and strerror().

Referenced by ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().

{
        int ret;
        /*
         * Check bounds supported by the PHY (we don't care about regultory
         * restrictions at this point). Note: hw_value already has the band
         * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
         * of the band by that */
        if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
                DBG("ath5k: channel frequency (%d MHz) out of supported "
                    "range\n", channel->center_freq);
                return -EINVAL;
        }

        /*
         * Set the channel and wait
         */
        switch (ah->ah_radio) {
        case AR5K_RF5110:
                ret = ath5k_hw_rf5110_channel(ah, channel);
                break;
        case AR5K_RF5111:
                ret = ath5k_hw_rf5111_channel(ah, channel);
                break;
        case AR5K_RF2425:
                ret = ath5k_hw_rf2425_channel(ah, channel);
                break;
        default:
                ret = ath5k_hw_rf5112_channel(ah, channel);
                break;
        }

        if (ret) {
                DBG("ath5k: setting channel failed: %s\n", strerror(ret));
                return ret;
        }

        /* Set JAPAN setting for channel 14 */
        if (channel->center_freq == 2484) {
                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
                                AR5K_PHY_CCKTXCTL_JAPAN);
        } else {
                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
                                AR5K_PHY_CCKTXCTL_WORLD);
        }

        ah->ah_current_channel = channel;
        ah->ah_turbo = (channel->hw_value == CHANNEL_T ? 1 : 0);

        return 0;
}
int ath5k_hw_phy_calibrate ( struct ath5k_hw ah,
struct net80211_channel channel 
)

Definition at line 1345 of file ath5k_phy.c.

References ath5k_hw::ah_radio, AR5K_RF5110, ath5k_hw_rf5110_calibrate(), ath5k_hw_rf511x_calibrate(), and ret.

Referenced by ath5k_calibrate().

{
        int ret;

        if (ah->ah_radio == AR5K_RF5110)
                ret = ath5k_hw_rf5110_calibrate(ah, channel);
        else
                ret = ath5k_hw_rf511x_calibrate(ah, channel);

        return ret;
}
int ath5k_hw_noise_floor_calibration ( struct ath5k_hw ah,
short  freq 
)

ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration

: struct ath5k_hw pointer we are operating on : the channel frequency, just used for error logging

This function performs a noise floor calibration of the PHY and waits for it to complete. Then the noise floor value is compared to some maximum noise floor we consider valid.

Note that this is different from what the madwifi HAL does: it reads the noise floor and afterwards initiates the calibration. Since the noise floor calibration can take some time to finish, depending on the current channel use, that avoids the occasional timeout warnings we are seeing now.

See the following link for an Atheros patent on noise floor calibration: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7

XXX: Since during noise floor calibration antennas are detached according to the patent, we should stop tx queues here.

Definition at line 1127 of file ath5k_phy.c.

References ath5k_hw::ah_noise_floor, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, AR5K_PHY_NF, AR5K_PHY_NF_ACTIVE, AR5K_PHY_NF_AVAL, AR5K_PHY_NF_RVAL, AR5K_REG_ENABLE_BITS, AR5K_TUNE_NOISE_FLOOR, ath5k_hw_reg_read(), DBG, DBG2, EAGAIN, mdelay(), and ret.

Referenced by ath5k_hw_reset(), ath5k_hw_rf5110_calibrate(), and ath5k_hw_rf511x_calibrate().

{
        int ret;
        unsigned int i;
        s32 noise_floor;

        /*
         * Enable noise floor calibration
         */
        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
                                AR5K_PHY_AGCCTL_NF);

        ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
                        AR5K_PHY_AGCCTL_NF, 0, 0);

        if (ret) {
                DBG("ath5k: noise floor calibration timeout (%d MHz)\n", freq);
                return -EAGAIN;
        }

        /* Wait until the noise floor is calibrated and read the value */
        for (i = 20; i > 0; i--) {
                mdelay(1);
                noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
                noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
                if (noise_floor & AR5K_PHY_NF_ACTIVE) {
                        noise_floor = AR5K_PHY_NF_AVAL(noise_floor);

                        if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
                                break;
                }
        }

        DBG2("ath5k: noise floor %d\n", noise_floor);

        if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
                DBG("ath5k: noise floor calibration failed (%d MHz)\n", freq);
                return -EAGAIN;
        }

        ah->ah_noise_floor = noise_floor;

        return 0;
}
u16 ath5k_hw_radio_revision ( struct ath5k_hw ah,
unsigned int  chan 
)

Definition at line 1372 of file ath5k_phy.c.

References ath5k_hw::ah_version, AR5K_AR5210, AR5K_PHY, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY_SHIFT_5GHZ, ath5k_hw_bitswap(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), CHANNEL_2GHZ, CHANNEL_5GHZ, mdelay(), ret, and u16.

Referenced by ath5k_hw_attach().

{
        unsigned int i;
        u32 srev;
        u16 ret;

        /*
         * Set the radio chip access register
         */
        switch (chan) {
        case CHANNEL_2GHZ:
                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
                break;
        case CHANNEL_5GHZ:
                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
                break;
        default:
                return 0;
        }

        mdelay(2);

        /* ...wait until PHY is ready and read the selected radio revision */
        ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));

        for (i = 0; i < 8; i++)
                ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));

        if (ah->ah_version == AR5K_AR5210) {
                srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
                ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
        } else {
                srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
                ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
                                ((srev & 0x0f) << 4), 8);
        }

        /* Reset to the 5GHz mode */
        ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));

        return ret;
}
void ath5k_hw_set_def_antenna ( struct ath5k_hw ah,
unsigned int  ant 
)
unsigned int ath5k_hw_get_def_antenna ( struct ath5k_hw ah)

Definition at line 1422 of file ath5k_phy.c.

References ath5k_hw::ah_version, AR5K_AR5210, AR5K_DEFAULT_ANTENNA, and ath5k_hw_reg_read().

{
        if (ah->ah_version != AR5K_AR5210)
                return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);

        return 0; /*XXX: What do we return for 5210 ?*/
}
int ath5k_hw_phy_disable ( struct ath5k_hw ah)

Definition at line 1358 of file ath5k_phy.c.

References AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, and ath5k_hw_reg_write().

Referenced by ath5k_stop_hw().

int ath5k_hw_txpower ( struct ath5k_hw ah,
struct net80211_channel channel,
u8  ee_mode,
u8  txpower 
)

Definition at line 2474 of file ath5k_phy.c.

References ath5k_hw::ah_radio, ath5k_hw::ah_txpower, AR5K_PHY_TXPOWER_RATE1, AR5K_PHY_TXPOWER_RATE2, AR5K_PHY_TXPOWER_RATE3, AR5K_PHY_TXPOWER_RATE4, AR5K_PHY_TXPOWER_RATE_MAX, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE, AR5K_PWRTABLE_LINEAR_PCDAC, AR5K_PWRTABLE_PWR_TO_PCDAC, AR5K_PWRTABLE_PWR_TO_PDADC, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_TPC, AR5K_TPC_ACK, AR5K_TPC_CHIRP, AR5K_TPC_CTS, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_MAX_TXPOWER, AR5K_TUNE_TPC_TXPOWER, AR5K_TXPOWER_CCK, AR5K_TXPOWER_OFDM, ath5k_get_max_ctl_power(), ath5k_get_rate_pcal_data(), ath5k_hw_reg_write(), ath5k_setup_channel_powertable(), ath5k_setup_rate_powertable(), DBG, EINVAL, memset(), ret, ath5k_hw::txp_max_pwr, ath5k_hw::txp_min_pwr, ath5k_hw::txp_tpc, and type.

Referenced by ath5k_hw_reset(), and ath5k_hw_set_txpower_limit().

{
        struct ath5k_rate_pcal_info rate_info;
        u8 type;
        int ret;

        if (txpower > AR5K_TUNE_MAX_TXPOWER) {
                DBG("ath5k: invalid tx power %d\n", txpower);
                return -EINVAL;
        }
        if (txpower == 0)
                txpower = AR5K_TUNE_DEFAULT_TXPOWER;

        /* Reset TX power values */
        memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
        ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
        ah->ah_txpower.txp_min_pwr = 0;
        ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;

        /* Initialize TX power table */
        switch (ah->ah_radio) {
        case AR5K_RF5111:
                type = AR5K_PWRTABLE_PWR_TO_PCDAC;
                break;
        case AR5K_RF5112:
                type = AR5K_PWRTABLE_LINEAR_PCDAC;
                break;
        case AR5K_RF2413:
        case AR5K_RF5413:
        case AR5K_RF2316:
        case AR5K_RF2317:
        case AR5K_RF2425:
                type = AR5K_PWRTABLE_PWR_TO_PDADC;
                break;
        default:
                return -EINVAL;
        }

        /* FIXME: Only on channel/mode change */
        ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
        if (ret)
                return ret;

        /* Limit max power if we have a CTL available */
        ath5k_get_max_ctl_power(ah, channel);

        /* FIXME: Tx power limit for this regdomain
         * XXX: Mac80211/CRDA will do that anyway ? */

        /* FIXME: Antenna reduction stuff */

        /* FIXME: Limit power on turbo modes */

        /* FIXME: TPC scale reduction */

        /* Get surounding channels for per-rate power table
         * calibration */
        ath5k_get_rate_pcal_data(ah, channel, &rate_info);

        /* Setup rate power table */
        ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);

        /* Write rate power table on hw */
        ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
                AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
                AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);

        ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
                AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
                AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);

        ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
                AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
                AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);

        ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
                AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
                AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);

        /* FIXME: TPC support */
        if (ah->ah_txpower.txp_tpc) {
                ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
                        AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);

                ath5k_hw_reg_write(ah,
                        AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
                        AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
                        AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
                        AR5K_TPC);
        } else {
                ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
                        AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
        }

        return 0;
}
int ath5k_hw_set_txpower_limit ( struct ath5k_hw ah,
u8  ee_mode,
u8  txpower 
)

Definition at line 2572 of file ath5k_phy.c.

References ath5k_hw::ah_current_channel, ath5k_hw_txpower(), channel, and DBG2.

{
        struct net80211_channel *channel = ah->ah_current_channel;

        DBG2("ath5k: changing txpower to %d\n", txpower);

        return ath5k_hw_txpower(ah, channel, mode, txpower);
}
static unsigned int ath5k_hw_htoclock ( unsigned int  usec,
int  turbo 
) [inline, static]

Definition at line 1197 of file ath5k.h.

Referenced by ath5k_hw_set_ack_timeout(), ath5k_hw_set_cts_timeout(), ath5k_hw_set_slot_time(), and ath5k_hw_write_ofdm_timings().

{
        return turbo ? (usec * 80) : (usec * 40);
}
static unsigned int ath5k_hw_clocktoh ( unsigned int  clock,
int  turbo 
) [inline, static]

Definition at line 1206 of file ath5k.h.

Referenced by ath5k_hw_get_ack_timeout(), ath5k_hw_get_cts_timeout(), ath5k_hw_set_ack_timeout(), and ath5k_hw_set_cts_timeout().

{
        return turbo ? (clock / 80) : (clock / 40);
}
static u32 ath5k_hw_reg_read ( struct ath5k_hw ah,
u16  reg 
) [inline, static]
static void ath5k_hw_reg_write ( struct ath5k_hw ah,
u32  val,
u16  reg 
) [inline, static]
static u32 ath5k_hw_bitswap ( u32  val,
unsigned int  bits 
) [inline, static]

Definition at line 1265 of file ath5k.h.

Referenced by ath5k_hw_radio_revision(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_chan2athchan(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), ath5k_hw_rfb_op(), and ath5k_hw_rfregs_init().

{
        u32 retval = 0, bit, i;

        for (i = 0; i < bits; i++) {
                bit = (val >> i) & 1;
                retval = (retval << 1) | bit;
        }

        return retval;
}