iPXE
ath5k.h
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00001 /*
00002  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
00003  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
00004  *
00005  * Modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
00006  * Original from Linux kernel 2.6.30.
00007  *
00008  * Permission to use, copy, modify, and distribute this software for any
00009  * purpose with or without fee is hereby granted, provided that the above
00010  * copyright notice and this permission notice appear in all copies.
00011  *
00012  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00013  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00014  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00015  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00016  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00017  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00018  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00019  */
00020 
00021 #ifndef _ATH5K_H
00022 #define _ATH5K_H
00023 
00024 FILE_LICENCE ( MIT );
00025 
00026 #include <stddef.h>
00027 #include <byteswap.h>
00028 #include <ipxe/io.h>
00029 #include <ipxe/netdevice.h>
00030 #include <ipxe/net80211.h>
00031 #include <errno.h>
00032 
00033 /* Keep all ath5k files under one errfile ID */
00034 #undef ERRFILE
00035 #define ERRFILE ERRFILE_ath5k
00036 
00037 /* RX/TX descriptor hw structs */
00038 #include "desc.h"
00039 
00040 /* EEPROM structs/offsets */
00041 #include "eeprom.h"
00042 
00043 /* PCI IDs */
00044 #define PCI_DEVICE_ID_ATHEROS_AR5210            0x0007 /* AR5210 */
00045 #define PCI_DEVICE_ID_ATHEROS_AR5311            0x0011 /* AR5311 */
00046 #define PCI_DEVICE_ID_ATHEROS_AR5211            0x0012 /* AR5211 */
00047 #define PCI_DEVICE_ID_ATHEROS_AR5212            0x0013 /* AR5212 */
00048 #define PCI_DEVICE_ID_3COM_3CRDAG675            0x0013 /* 3CRDAG675 (Atheros AR5212) */
00049 #define PCI_DEVICE_ID_3COM_2_3CRPAG175          0x0013 /* 3CRPAG175 (Atheros AR5212) */
00050 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP         0x0207 /* AR5210 (Early) */
00051 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM        0x1014 /* AR5212 (IBM MiniPCI) */
00052 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT    0x1107 /* AR5210 (no eeprom) */
00053 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT    0x1113 /* AR5212 (no eeprom) */
00054 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT    0x1112 /* AR5211 (no eeprom) */
00055 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA       0xf013 /* AR5212 (emulation board) */
00056 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY     0xff12 /* AR5211 (emulation board) */
00057 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B    0xf11b /* AR5211 (emulation board) */
00058 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2       0x0052 /* AR5312 WMAC (AP31) */
00059 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7       0x0057 /* AR5312 WMAC (AP30-040) */
00060 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8       0x0058 /* AR5312 WMAC (AP43-030) */
00061 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014       0x0014 /* AR5212 compatible */
00062 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015       0x0015 /* AR5212 compatible */
00063 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016       0x0016 /* AR5212 compatible */
00064 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017       0x0017 /* AR5212 compatible */
00065 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018       0x0018 /* AR5212 compatible */
00066 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019       0x0019 /* AR5212 compatible */
00067 #define PCI_DEVICE_ID_ATHEROS_AR2413            0x001a /* AR2413 (Griffin-lite) */
00068 #define PCI_DEVICE_ID_ATHEROS_AR5413            0x001b /* AR5413 (Eagle) */
00069 #define PCI_DEVICE_ID_ATHEROS_AR5424            0x001c /* AR5424 (Condor PCI-E) */
00070 #define PCI_DEVICE_ID_ATHEROS_AR5416            0x0023 /* AR5416 */
00071 #define PCI_DEVICE_ID_ATHEROS_AR5418            0x0024 /* AR5418 */
00072 
00073 /****************************\
00074   GENERIC DRIVER DEFINITIONS
00075 \****************************/
00076 
00077 /*
00078  * AR5K REGISTER ACCESS
00079  */
00080 
00081 /* Some macros to read/write fields */
00082 
00083 /* First shift, then mask */
00084 #define AR5K_REG_SM(_val, _flags)                                       \
00085         (((_val) << _flags##_S) & (_flags))
00086 
00087 /* First mask, then shift */
00088 #define AR5K_REG_MS(_val, _flags)                                       \
00089         (((_val) & (_flags)) >> _flags##_S)
00090 
00091 /* Some registers can hold multiple values of interest. For this
00092  * reason when we want to write to these registers we must first
00093  * retrieve the values which we do not want to clear (lets call this
00094  * old_data) and then set the register with this and our new_value:
00095  * ( old_data | new_value) */
00096 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)                     \
00097         ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
00098             (((_val) << _flags##_S) & (_flags)), _reg)
00099 
00100 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)                   \
00101         ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) &           \
00102                         (_mask)) | (_flags), _reg)
00103 
00104 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)                          \
00105         ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
00106 
00107 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)                 \
00108         ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
00109 
00110 /* Access to PHY registers */
00111 #define AR5K_PHY_READ(ah, _reg)                                 \
00112         ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
00113 
00114 #define AR5K_PHY_WRITE(ah, _reg, _val)                                  \
00115         ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
00116 
00117 /* Access QCU registers per queue */
00118 #define AR5K_REG_READ_Q(ah, _reg, _queue)                               \
00119         (ath5k_hw_reg_read(ah, _reg) & (1 << _queue))                   \
00120 
00121 #define AR5K_REG_WRITE_Q(ah, _reg, _queue)                              \
00122         ath5k_hw_reg_write(ah, (1 << _queue), _reg)
00123 
00124 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do {                           \
00125         _reg |= 1 << _queue;                                            \
00126 } while (0)
00127 
00128 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do {                          \
00129         _reg &= ~(1 << _queue);                                         \
00130 } while (0)
00131 
00132 /* Used while writing initvals */
00133 #define AR5K_REG_WAIT(_i) do {                                          \
00134         if (_i % 64)                                                    \
00135                 udelay(1);                                              \
00136 } while (0)
00137 
00138 /* Register dumps are done per operation mode */
00139 #define AR5K_INI_RFGAIN_5GHZ            0
00140 #define AR5K_INI_RFGAIN_2GHZ            1
00141 
00142 /* TODO: Clean this up */
00143 #define AR5K_INI_VAL_11A                0
00144 #define AR5K_INI_VAL_11A_TURBO          1
00145 #define AR5K_INI_VAL_11B                2
00146 #define AR5K_INI_VAL_11G                3
00147 #define AR5K_INI_VAL_11G_TURBO          4
00148 #define AR5K_INI_VAL_XR                 0
00149 #define AR5K_INI_VAL_MAX                5
00150 
00151 /* Used for BSSID etc manipulation */
00152 #define AR5K_LOW_ID(_a)(                                \
00153 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24  \
00154 )
00155 
00156 #define AR5K_HIGH_ID(_a)        ((_a)[4] | (_a)[5] << 8)
00157 
00158 #define IEEE80211_MAX_LEN       2352
00159 
00160 /*
00161  * Some tuneable values (these should be changeable by the user)
00162  */
00163 #define AR5K_TUNE_DMA_BEACON_RESP               2
00164 #define AR5K_TUNE_SW_BEACON_RESP                10
00165 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF       0
00166 #define AR5K_TUNE_RADAR_ALERT                   0
00167 #define AR5K_TUNE_MIN_TX_FIFO_THRES             1
00168 #define AR5K_TUNE_MAX_TX_FIFO_THRES             ((IEEE80211_MAX_LEN / 64) + 1)
00169 #define AR5K_TUNE_REGISTER_TIMEOUT              20000
00170 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
00171  * be the max value. */
00172 #define AR5K_TUNE_RSSI_THRES                    129
00173 /* This must be set when setting the RSSI threshold otherwise it can
00174  * prevent a reset. If AR5K_RSSI_THR is read after writing to it
00175  * the BMISS_THRES will be seen as 0, seems harware doesn't keep
00176  * track of it. Max value depends on harware. For AR5210 this is just 7.
00177  * For AR5211+ this seems to be up to 255. */
00178 #define AR5K_TUNE_BMISS_THRES                   7
00179 #define AR5K_TUNE_REGISTER_DWELL_TIME           20000
00180 #define AR5K_TUNE_BEACON_INTERVAL               100
00181 #define AR5K_TUNE_AIFS                          2
00182 #define AR5K_TUNE_AIFS_11B                      2
00183 #define AR5K_TUNE_AIFS_XR                       0
00184 #define AR5K_TUNE_CWMIN                         15
00185 #define AR5K_TUNE_CWMIN_11B                     31
00186 #define AR5K_TUNE_CWMIN_XR                      3
00187 #define AR5K_TUNE_CWMAX                         1023
00188 #define AR5K_TUNE_CWMAX_11B                     1023
00189 #define AR5K_TUNE_CWMAX_XR                      7
00190 #define AR5K_TUNE_NOISE_FLOOR                   -72
00191 #define AR5K_TUNE_MAX_TXPOWER                   63
00192 #define AR5K_TUNE_DEFAULT_TXPOWER               25
00193 #define AR5K_TUNE_TPC_TXPOWER                   0
00194 #define AR5K_TUNE_ANT_DIVERSITY                 1
00195 #define AR5K_TUNE_HWTXTRIES                     4
00196 
00197 #define AR5K_INIT_CARR_SENSE_EN                 1
00198 
00199 /*Swap RX/TX Descriptor for big endian archs*/
00200 #if __BYTE_ORDER == __BIG_ENDIAN
00201 #define AR5K_INIT_CFG   (               \
00202         AR5K_CFG_SWTD | AR5K_CFG_SWRD   \
00203 )
00204 #else
00205 #define AR5K_INIT_CFG   0x00000000
00206 #endif
00207 
00208 /* Initial values */
00209 #define AR5K_INIT_CYCRSSI_THR1                  2
00210 #define AR5K_INIT_TX_LATENCY                    502
00211 #define AR5K_INIT_USEC                          39
00212 #define AR5K_INIT_USEC_TURBO                    79
00213 #define AR5K_INIT_USEC_32                       31
00214 #define AR5K_INIT_SLOT_TIME                     396
00215 #define AR5K_INIT_SLOT_TIME_TURBO               480
00216 #define AR5K_INIT_ACK_CTS_TIMEOUT               1024
00217 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO         0x08000800
00218 #define AR5K_INIT_PROG_IFS                      920
00219 #define AR5K_INIT_PROG_IFS_TURBO                960
00220 #define AR5K_INIT_EIFS                          3440
00221 #define AR5K_INIT_EIFS_TURBO                    6880
00222 #define AR5K_INIT_SIFS                          560
00223 #define AR5K_INIT_SIFS_TURBO                    480
00224 #define AR5K_INIT_SH_RETRY                      10
00225 #define AR5K_INIT_LG_RETRY                      AR5K_INIT_SH_RETRY
00226 #define AR5K_INIT_SSH_RETRY                     32
00227 #define AR5K_INIT_SLG_RETRY                     AR5K_INIT_SSH_RETRY
00228 #define AR5K_INIT_TX_RETRY                      10
00229 
00230 #define AR5K_INIT_TRANSMIT_LATENCY              (                       \
00231         (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
00232         (AR5K_INIT_USEC)                                                \
00233 )
00234 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO        (                       \
00235         (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
00236         (AR5K_INIT_USEC_TURBO)                                          \
00237 )
00238 #define AR5K_INIT_PROTO_TIME_CNTRL              (                       \
00239         (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) |      \
00240         (AR5K_INIT_PROG_IFS)                                            \
00241 )
00242 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO        (                       \
00243         (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
00244         (AR5K_INIT_PROG_IFS_TURBO)                                      \
00245 )
00246 
00247 /* token to use for aifs, cwmin, cwmax in MadWiFi */
00248 #define AR5K_TXQ_USEDEFAULT     ((u32) -1)
00249 
00250 /* GENERIC CHIPSET DEFINITIONS */
00251 
00252 /* MAC Chips */
00253 enum ath5k_version {
00254         AR5K_AR5210     = 0,
00255         AR5K_AR5211     = 1,
00256         AR5K_AR5212     = 2,
00257 };
00258 
00259 /* PHY Chips */
00260 enum ath5k_radio {
00261         AR5K_RF5110     = 0,
00262         AR5K_RF5111     = 1,
00263         AR5K_RF5112     = 2,
00264         AR5K_RF2413     = 3,
00265         AR5K_RF5413     = 4,
00266         AR5K_RF2316     = 5,
00267         AR5K_RF2317     = 6,
00268         AR5K_RF2425     = 7,
00269 };
00270 
00271 /*
00272  * Common silicon revision/version values
00273  */
00274 
00275 enum ath5k_srev_type {
00276         AR5K_VERSION_MAC,
00277         AR5K_VERSION_RAD,
00278 };
00279 
00280 struct ath5k_srev_name {
00281         const char              *sr_name;
00282         enum ath5k_srev_type    sr_type;
00283         unsigned                sr_val;
00284 };
00285 
00286 #define AR5K_SREV_UNKNOWN       0xffff
00287 
00288 #define AR5K_SREV_AR5210        0x00 /* Crete */
00289 #define AR5K_SREV_AR5311        0x10 /* Maui 1 */
00290 #define AR5K_SREV_AR5311A       0x20 /* Maui 2 */
00291 #define AR5K_SREV_AR5311B       0x30 /* Spirit */
00292 #define AR5K_SREV_AR5211        0x40 /* Oahu */
00293 #define AR5K_SREV_AR5212        0x50 /* Venice */
00294 #define AR5K_SREV_AR5213        0x55 /* ??? */
00295 #define AR5K_SREV_AR5213A       0x59 /* Hainan */
00296 #define AR5K_SREV_AR2413        0x78 /* Griffin lite */
00297 #define AR5K_SREV_AR2414        0x70 /* Griffin */
00298 #define AR5K_SREV_AR5424        0x90 /* Condor */
00299 #define AR5K_SREV_AR5413        0xa4 /* Eagle lite */
00300 #define AR5K_SREV_AR5414        0xa0 /* Eagle */
00301 #define AR5K_SREV_AR2415        0xb0 /* Talon */
00302 #define AR5K_SREV_AR5416        0xc0 /* PCI-E */
00303 #define AR5K_SREV_AR5418        0xca /* PCI-E */
00304 #define AR5K_SREV_AR2425        0xe0 /* Swan */
00305 #define AR5K_SREV_AR2417        0xf0 /* Nala */
00306 
00307 #define AR5K_SREV_RAD_5110      0x00
00308 #define AR5K_SREV_RAD_5111      0x10
00309 #define AR5K_SREV_RAD_5111A     0x15
00310 #define AR5K_SREV_RAD_2111      0x20
00311 #define AR5K_SREV_RAD_5112      0x30
00312 #define AR5K_SREV_RAD_5112A     0x35
00313 #define AR5K_SREV_RAD_5112B     0x36
00314 #define AR5K_SREV_RAD_2112      0x40
00315 #define AR5K_SREV_RAD_2112A     0x45
00316 #define AR5K_SREV_RAD_2112B     0x46
00317 #define AR5K_SREV_RAD_2413      0x50
00318 #define AR5K_SREV_RAD_5413      0x60
00319 #define AR5K_SREV_RAD_2316      0x70 /* Cobra SoC */
00320 #define AR5K_SREV_RAD_2317      0x80
00321 #define AR5K_SREV_RAD_5424      0xa0 /* Mostly same as 5413 */
00322 #define AR5K_SREV_RAD_2425      0xa2
00323 #define AR5K_SREV_RAD_5133      0xc0
00324 
00325 #define AR5K_SREV_PHY_5211      0x30
00326 #define AR5K_SREV_PHY_5212      0x41
00327 #define AR5K_SREV_PHY_5212A     0x42
00328 #define AR5K_SREV_PHY_5212B     0x43
00329 #define AR5K_SREV_PHY_2413      0x45
00330 #define AR5K_SREV_PHY_5413      0x61
00331 #define AR5K_SREV_PHY_2425      0x70
00332 
00333 /*
00334  * Some of this information is based on Documentation from:
00335  *
00336  * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
00337  *
00338  * Modulation for Atheros' eXtended Range - range enhancing extension that is
00339  * supposed to double the distance an Atheros client device can keep a
00340  * connection with an Atheros access point. This is achieved by increasing
00341  * the receiver sensitivity up to, -105dBm, which is about 20dB above what
00342  * the 802.11 specifications demand. In addition, new (proprietary) data rates
00343  * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
00344  *
00345  * Please note that can you either use XR or TURBO but you cannot use both,
00346  * they are exclusive.
00347  *
00348  */
00349 #define MODULATION_XR           0x00000200
00350 
00351 /*
00352  * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
00353  * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
00354  * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
00355  * channels. To use this feature your Access Point must also suport it.
00356  * There is also a distinction between "static" and "dynamic" turbo modes:
00357  *
00358  * - Static: is the dumb version: devices set to this mode stick to it until
00359  *     the mode is turned off.
00360  * - Dynamic: is the intelligent version, the network decides itself if it
00361  *     is ok to use turbo. As soon as traffic is detected on adjacent channels
00362  *     (which would get used in turbo mode), or when a non-turbo station joins
00363  *     the network, turbo mode won't be used until the situation changes again.
00364  *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
00365  *     monitors the used radio band in order to decide whether turbo mode may
00366  *     be used or not.
00367  *
00368  * This article claims Super G sticks to bonding of channels 5 and 6 for
00369  * USA:
00370  *
00371  * http://www.pcworld.com/article/id,113428-page,1/article.html
00372  *
00373  * The channel bonding seems to be driver specific though. In addition to
00374  * deciding what channels will be used, these "Turbo" modes are accomplished
00375  * by also enabling the following features:
00376  *
00377  * - Bursting: allows multiple frames to be sent at once, rather than pausing
00378  *     after each frame. Bursting is a standards-compliant feature that can be
00379  *     used with any Access Point.
00380  * - Fast frames: increases the amount of information that can be sent per
00381  *     frame, also resulting in a reduction of transmission overhead. It is a
00382  *     proprietary feature that needs to be supported by the Access Point.
00383  * - Compression: data frames are compressed in real time using a Lempel Ziv
00384  *     algorithm. This is done transparently. Once this feature is enabled,
00385  *     compression and decompression takes place inside the chipset, without
00386  *     putting additional load on the host CPU.
00387  *
00388  */
00389 #define MODULATION_TURBO        0x00000080
00390 
00391 enum ath5k_driver_mode {
00392         AR5K_MODE_11A           = 0,
00393         AR5K_MODE_11A_TURBO     = 1,
00394         AR5K_MODE_11B           = 2,
00395         AR5K_MODE_11G           = 3,
00396         AR5K_MODE_11G_TURBO     = 4,
00397         AR5K_MODE_XR            = 5,
00398 };
00399 
00400 enum {
00401         AR5K_MODE_BIT_11A       = (1 << AR5K_MODE_11A),
00402         AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO),
00403         AR5K_MODE_BIT_11B       = (1 << AR5K_MODE_11B),
00404         AR5K_MODE_BIT_11G       = (1 << AR5K_MODE_11G),
00405         AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO),
00406         AR5K_MODE_BIT_XR        = (1 << AR5K_MODE_XR),
00407 };
00408 
00409 /****************\
00410   TX DEFINITIONS
00411 \****************/
00412 
00413 /*
00414  * TX Status descriptor
00415  */
00416 struct ath5k_tx_status {
00417         u16     ts_seqnum;
00418         u16     ts_tstamp;
00419         u8      ts_status;
00420         u8      ts_rate[4];
00421         u8      ts_retry[4];
00422         u8      ts_final_idx;
00423         s8      ts_rssi;
00424         u8      ts_shortretry;
00425         u8      ts_longretry;
00426         u8      ts_virtcol;
00427         u8      ts_antenna;
00428 } __attribute__ ((packed));
00429 
00430 #define AR5K_TXSTAT_ALTRATE     0x80
00431 #define AR5K_TXERR_XRETRY       0x01
00432 #define AR5K_TXERR_FILT         0x02
00433 #define AR5K_TXERR_FIFO         0x04
00434 
00435 /**
00436  * enum ath5k_tx_queue - Queue types used to classify tx queues.
00437  * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
00438  * @AR5K_TX_QUEUE_DATA: A normal data queue
00439  * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
00440  * @AR5K_TX_QUEUE_BEACON: The beacon queue
00441  * @AR5K_TX_QUEUE_CAB: The after-beacon queue
00442  * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
00443  */
00444 enum ath5k_tx_queue {
00445         AR5K_TX_QUEUE_INACTIVE = 0,
00446         AR5K_TX_QUEUE_DATA,
00447         AR5K_TX_QUEUE_XR_DATA,
00448         AR5K_TX_QUEUE_BEACON,
00449         AR5K_TX_QUEUE_CAB,
00450         AR5K_TX_QUEUE_UAPSD,
00451 };
00452 
00453 /*
00454  * Queue syb-types to classify normal data queues.
00455  * These are the 4 Access Categories as defined in
00456  * WME spec. 0 is the lowest priority and 4 is the
00457  * highest. Normal data that hasn't been classified
00458  * goes to the Best Effort AC.
00459  */
00460 enum ath5k_tx_queue_subtype {
00461         AR5K_WME_AC_BK = 0,     /*Background traffic*/
00462         AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
00463         AR5K_WME_AC_VI,         /*Video traffic*/
00464         AR5K_WME_AC_VO,         /*Voice traffic*/
00465 };
00466 
00467 /*
00468  * Queue ID numbers as returned by the hw functions, each number
00469  * represents a hw queue. If hw does not support hw queues
00470  * (eg 5210) all data goes in one queue. These match
00471  * d80211 definitions (net80211/MadWiFi don't use them).
00472  */
00473 enum ath5k_tx_queue_id {
00474         AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
00475         AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
00476         AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
00477         AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
00478         AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
00479         AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
00480         AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
00481         AR5K_TX_QUEUE_ID_UAPSD          = 8,
00482         AR5K_TX_QUEUE_ID_XR_DATA        = 9,
00483 };
00484 
00485 /*
00486  * Flags to set hw queue's parameters...
00487  */
00488 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE            0x0001  /* Enable TXOK interrupt */
00489 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE           0x0002  /* Enable TXERR interrupt */
00490 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE           0x0004  /* Enable TXEOL interrupt -not used- */
00491 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE          0x0008  /* Enable TXDESC interrupt -not used- */
00492 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE           0x0010  /* Enable TXURN interrupt */
00493 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE          0x0020  /* Enable CBRORN interrupt */
00494 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE          0x0040  /* Enable CBRURN interrupt */
00495 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE           0x0080  /* Enable QTRIG interrupt */
00496 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE         0x0100  /* Enable TXNOFRM interrupt */
00497 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0200  /* Disable random post-backoff */
00498 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300  /* Enable ready time expiry policy (?)*/
00499 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800  /* Enable backoff while bursting */
00500 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x1000  /* Disable backoff while bursting */
00501 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x2000  /* Enable hw compression -not implemented-*/
00502 
00503 /*
00504  * A struct to hold tx queue's parameters
00505  */
00506 struct ath5k_txq_info {
00507         enum ath5k_tx_queue tqi_type;
00508         enum ath5k_tx_queue_subtype tqi_subtype;
00509         u16     tqi_flags;      /* Tx queue flags (see above) */
00510         u32     tqi_aifs;       /* Arbitrated Interframe Space */
00511         s32     tqi_cw_min;     /* Minimum Contention Window */
00512         s32     tqi_cw_max;     /* Maximum Contention Window */
00513         u32     tqi_cbr_period; /* Constant bit rate period */
00514         u32     tqi_cbr_overflow_limit;
00515         u32     tqi_burst_time;
00516         u32     tqi_ready_time; /* Not used */
00517 };
00518 
00519 /*
00520  * Transmit packet types.
00521  * used on tx control descriptor
00522  * TODO: Use them inside base.c corectly
00523  */
00524 enum ath5k_pkt_type {
00525         AR5K_PKT_TYPE_NORMAL            = 0,
00526         AR5K_PKT_TYPE_ATIM              = 1,
00527         AR5K_PKT_TYPE_PSPOLL            = 2,
00528         AR5K_PKT_TYPE_BEACON            = 3,
00529         AR5K_PKT_TYPE_PROBE_RESP        = 4,
00530         AR5K_PKT_TYPE_PIFS              = 5,
00531 };
00532 
00533 /*
00534  * TX power and TPC settings
00535  */
00536 #define AR5K_TXPOWER_OFDM(_r, _v)       (                       \
00537         ((0 & 1) << ((_v) + 6)) |                               \
00538         (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
00539 )
00540 
00541 #define AR5K_TXPOWER_CCK(_r, _v)        (                       \
00542         (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v)     \
00543 )
00544 
00545 /*
00546  * DMA size definitions (2^n+2)
00547  */
00548 enum ath5k_dmasize {
00549         AR5K_DMASIZE_4B = 0,
00550         AR5K_DMASIZE_8B,
00551         AR5K_DMASIZE_16B,
00552         AR5K_DMASIZE_32B,
00553         AR5K_DMASIZE_64B,
00554         AR5K_DMASIZE_128B,
00555         AR5K_DMASIZE_256B,
00556         AR5K_DMASIZE_512B
00557 };
00558 
00559 
00560 /****************\
00561   RX DEFINITIONS
00562 \****************/
00563 
00564 /*
00565  * RX Status descriptor
00566  */
00567 struct ath5k_rx_status {
00568         u16     rs_datalen;
00569         u16     rs_tstamp;
00570         u8      rs_status;
00571         u8      rs_phyerr;
00572         s8      rs_rssi;
00573         u8      rs_keyix;
00574         u8      rs_rate;
00575         u8      rs_antenna;
00576         u8      rs_more;
00577 };
00578 
00579 #define AR5K_RXERR_CRC          0x01
00580 #define AR5K_RXERR_PHY          0x02
00581 #define AR5K_RXERR_FIFO         0x04
00582 #define AR5K_RXERR_DECRYPT      0x08
00583 #define AR5K_RXERR_MIC          0x10
00584 #define AR5K_RXKEYIX_INVALID    ((u8) - 1)
00585 #define AR5K_TXKEYIX_INVALID    ((u32) - 1)
00586 
00587 
00588 /*
00589  * TSF to TU conversion:
00590  *
00591  * TSF is a 64bit value in usec (microseconds).
00592  * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
00593  * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
00594  */
00595 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
00596 
00597 
00598 /*******************************\
00599   GAIN OPTIMIZATION DEFINITIONS
00600 \*******************************/
00601 
00602 enum ath5k_rfgain {
00603         AR5K_RFGAIN_INACTIVE = 0,
00604         AR5K_RFGAIN_ACTIVE,
00605         AR5K_RFGAIN_READ_REQUESTED,
00606         AR5K_RFGAIN_NEED_CHANGE,
00607 };
00608 
00609 struct ath5k_gain {
00610         u8                      g_step_idx;
00611         u8                      g_current;
00612         u8                      g_target;
00613         u8                      g_low;
00614         u8                      g_high;
00615         u8                      g_f_corr;
00616         u8                      g_state;
00617 };
00618 
00619 /********************\
00620   COMMON DEFINITIONS
00621 \********************/
00622 
00623 #define AR5K_SLOT_TIME_9        396
00624 #define AR5K_SLOT_TIME_20       880
00625 #define AR5K_SLOT_TIME_MAX      0xffff
00626 
00627 /* channel_flags */
00628 #define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
00629 #define CHANNEL_TURBO   0x0010  /* Turbo Channel */
00630 #define CHANNEL_CCK     0x0020  /* CCK channel */
00631 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
00632 #define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
00633 #define CHANNEL_5GHZ    0x0100  /* 5GHz channel */
00634 #define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed */
00635 #define CHANNEL_DYN     0x0400  /* Dynamic CCK-OFDM channel (for g operation) */
00636 #define CHANNEL_XR      0x0800  /* XR channel */
00637 
00638 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
00639 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
00640 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
00641 #define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
00642 #define CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
00643 #define CHANNEL_108A    CHANNEL_T
00644 #define CHANNEL_108G    CHANNEL_TG
00645 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
00646 
00647 #define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
00648                 CHANNEL_TURBO)
00649 
00650 #define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
00651 #define CHANNEL_MODES           CHANNEL_ALL
00652 
00653 /*
00654  * Used internaly for reset_tx_queue).
00655  * Also see struct struct net80211_channel.
00656  */
00657 #define IS_CHAN_XR(_c)  ((_c->hw_value & CHANNEL_XR) != 0)
00658 #define IS_CHAN_B(_c)   ((_c->hw_value & CHANNEL_B) != 0)
00659 
00660 /*
00661  * The following structure is used to map 2GHz channels to
00662  * 5GHz Atheros channels.
00663  * TODO: Clean up
00664  */
00665 struct ath5k_athchan_2ghz {
00666         u32     a2_flags;
00667         u16     a2_athchan;
00668 };
00669 
00670 
00671 /******************\
00672   RATE DEFINITIONS
00673 \******************/
00674 
00675 /**
00676  * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
00677  *
00678  * The rate code is used to get the RX rate or set the TX rate on the
00679  * hardware descriptors. It is also used for internal modulation control
00680  * and settings.
00681  *
00682  * This is the hardware rate map we are aware of:
00683  *
00684  * rate_code   0x01    0x02    0x03    0x04    0x05    0x06    0x07    0x08
00685  * rate_kbps   3000    1000    ?       ?       ?       2000    500     48000
00686  *
00687  * rate_code   0x09    0x0A    0x0B    0x0C    0x0D    0x0E    0x0F    0x10
00688  * rate_kbps   24000   12000   6000    54000   36000   18000   9000    ?
00689  *
00690  * rate_code   17      18      19      20      21      22      23      24
00691  * rate_kbps   ?       ?       ?       ?       ?       ?       ?       11000
00692  *
00693  * rate_code   25      26      27      28      29      30      31      32
00694  * rate_kbps   5500    2000    1000    11000S  5500S   2000S   ?       ?
00695  *
00696  * "S" indicates CCK rates with short preamble.
00697  *
00698  * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
00699  * lowest 4 bits, so they are the same as below with a 0xF mask.
00700  * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
00701  * We handle this in ath5k_setup_bands().
00702  */
00703 #define AR5K_MAX_RATES 32
00704 
00705 /* B */
00706 #define ATH5K_RATE_CODE_1M      0x1B
00707 #define ATH5K_RATE_CODE_2M      0x1A
00708 #define ATH5K_RATE_CODE_5_5M    0x19
00709 #define ATH5K_RATE_CODE_11M     0x18
00710 /* A and G */
00711 #define ATH5K_RATE_CODE_6M      0x0B
00712 #define ATH5K_RATE_CODE_9M      0x0F
00713 #define ATH5K_RATE_CODE_12M     0x0A
00714 #define ATH5K_RATE_CODE_18M     0x0E
00715 #define ATH5K_RATE_CODE_24M     0x09
00716 #define ATH5K_RATE_CODE_36M     0x0D
00717 #define ATH5K_RATE_CODE_48M     0x08
00718 #define ATH5K_RATE_CODE_54M     0x0C
00719 /* XR */
00720 #define ATH5K_RATE_CODE_XR_500K 0x07
00721 #define ATH5K_RATE_CODE_XR_1M   0x02
00722 #define ATH5K_RATE_CODE_XR_2M   0x06
00723 #define ATH5K_RATE_CODE_XR_3M   0x01
00724 
00725 /* adding this flag to rate_code enables short preamble */
00726 #define AR5K_SET_SHORT_PREAMBLE 0x04
00727 
00728 /*
00729  * Crypto definitions
00730  */
00731 
00732 #define AR5K_KEYCACHE_SIZE      8
00733 
00734 /***********************\
00735  HW RELATED DEFINITIONS
00736 \***********************/
00737 
00738 /*
00739  * Misc definitions
00740  */
00741 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
00742 
00743 #define AR5K_ASSERT_ENTRY(_e, _s) do {          \
00744         if (_e >= _s)                           \
00745                 return 0;                       \
00746 } while (0)
00747 
00748 /*
00749  * Hardware interrupt abstraction
00750  */
00751 
00752 /**
00753  * enum ath5k_int - Hardware interrupt masks helpers
00754  *
00755  * @AR5K_INT_RX: mask to identify received frame interrupts, of type
00756  *      AR5K_ISR_RXOK or AR5K_ISR_RXERR
00757  * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
00758  * @AR5K_INT_RXNOFRM: No frame received (?)
00759  * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
00760  *      Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
00761  *      LinkPtr is NULL. For more details, refer to:
00762  *      http://www.freepatentsonline.com/20030225739.html
00763  * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
00764  *      Note that Rx overrun is not always fatal, on some chips we can continue
00765  *      operation without reseting the card, that's why int_fatal is not
00766  *      common for all chips.
00767  * @AR5K_INT_TX: mask to identify received frame interrupts, of type
00768  *      AR5K_ISR_TXOK or AR5K_ISR_TXERR
00769  * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
00770  * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
00771  *      We currently do increments on interrupt by
00772  *      (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
00773  * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
00774  *      checked. We should do this with ath5k_hw_update_mib_counters() but
00775  *      it seems we should also then do some noise immunity work.
00776  * @AR5K_INT_RXPHY: RX PHY Error
00777  * @AR5K_INT_RXKCM: RX Key cache miss
00778  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
00779  *      beacon that must be handled in software. The alternative is if you
00780  *      have VEOL support, in that case you let the hardware deal with things.
00781  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
00782  *      beacons from the AP have associated with, we should probably try to
00783  *      reassociate. When in IBSS mode this might mean we have not received
00784  *      any beacons from any local stations. Note that every station in an
00785  *      IBSS schedules to send beacons at the Target Beacon Transmission Time
00786  *      (TBTT) with a random backoff.
00787  * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
00788  * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
00789  *      until properly handled
00790  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
00791  *      errors. These types of errors we can enable seem to be of type
00792  *      AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
00793  * @AR5K_INT_GLOBAL: Used to clear and set the IER
00794  * @AR5K_INT_NOCARD: signals the card has been removed
00795  * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
00796  *      bit value
00797  *
00798  * These are mapped to take advantage of some common bits
00799  * between the MACs, to be able to set intr properties
00800  * easier. Some of them are not used yet inside hw.c. Most map
00801  * to the respective hw interrupt value as they are common amogst different
00802  * MACs.
00803  */
00804 enum ath5k_int {
00805         AR5K_INT_RXOK   = 0x00000001,
00806         AR5K_INT_RXDESC = 0x00000002,
00807         AR5K_INT_RXERR  = 0x00000004,
00808         AR5K_INT_RXNOFRM = 0x00000008,
00809         AR5K_INT_RXEOL  = 0x00000010,
00810         AR5K_INT_RXORN  = 0x00000020,
00811         AR5K_INT_TXOK   = 0x00000040,
00812         AR5K_INT_TXDESC = 0x00000080,
00813         AR5K_INT_TXERR  = 0x00000100,
00814         AR5K_INT_TXNOFRM = 0x00000200,
00815         AR5K_INT_TXEOL  = 0x00000400,
00816         AR5K_INT_TXURN  = 0x00000800,
00817         AR5K_INT_MIB    = 0x00001000,
00818         AR5K_INT_SWI    = 0x00002000,
00819         AR5K_INT_RXPHY  = 0x00004000,
00820         AR5K_INT_RXKCM  = 0x00008000,
00821         AR5K_INT_SWBA   = 0x00010000,
00822         AR5K_INT_BRSSI  = 0x00020000,
00823         AR5K_INT_BMISS  = 0x00040000,
00824         AR5K_INT_FATAL  = 0x00080000, /* Non common */
00825         AR5K_INT_BNR    = 0x00100000, /* Non common */
00826         AR5K_INT_TIM    = 0x00200000, /* Non common */
00827         AR5K_INT_DTIM   = 0x00400000, /* Non common */
00828         AR5K_INT_DTIM_SYNC =    0x00800000, /* Non common */
00829         AR5K_INT_GPIO   =       0x01000000,
00830         AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
00831         AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
00832         AR5K_INT_RX_DOPPLER =   0x08000000, /* Non common */
00833         AR5K_INT_QCBRORN =      0x10000000, /* Non common */
00834         AR5K_INT_QCBRURN =      0x20000000, /* Non common */
00835         AR5K_INT_QTRIG  =       0x40000000, /* Non common */
00836         AR5K_INT_GLOBAL =       0x80000000,
00837 
00838         AR5K_INT_COMMON  = AR5K_INT_RXOK
00839                 | AR5K_INT_RXDESC
00840                 | AR5K_INT_RXERR
00841                 | AR5K_INT_RXNOFRM
00842                 | AR5K_INT_RXEOL
00843                 | AR5K_INT_RXORN
00844                 | AR5K_INT_TXOK
00845                 | AR5K_INT_TXDESC
00846                 | AR5K_INT_TXERR
00847                 | AR5K_INT_TXNOFRM
00848                 | AR5K_INT_TXEOL
00849                 | AR5K_INT_TXURN
00850                 | AR5K_INT_MIB
00851                 | AR5K_INT_SWI
00852                 | AR5K_INT_RXPHY
00853                 | AR5K_INT_RXKCM
00854                 | AR5K_INT_SWBA
00855                 | AR5K_INT_BRSSI
00856                 | AR5K_INT_BMISS
00857                 | AR5K_INT_GPIO
00858                 | AR5K_INT_GLOBAL,
00859 
00860         AR5K_INT_NOCARD = 0xffffffff
00861 };
00862 
00863 /*
00864  * Power management
00865  */
00866 enum ath5k_power_mode {
00867         AR5K_PM_UNDEFINED = 0,
00868         AR5K_PM_AUTO,
00869         AR5K_PM_AWAKE,
00870         AR5K_PM_FULL_SLEEP,
00871         AR5K_PM_NETWORK_SLEEP,
00872 };
00873 
00874 /* GPIO-controlled software LED */
00875 #define AR5K_SOFTLED_PIN        0
00876 #define AR5K_SOFTLED_ON         0
00877 #define AR5K_SOFTLED_OFF        1
00878 
00879 /*
00880  * Chipset capabilities -see ath5k_hw_get_capability-
00881  * get_capability function is not yet fully implemented
00882  * in ath5k so most of these don't work yet...
00883  * TODO: Implement these & merge with _TUNE_ stuff above
00884  */
00885 enum ath5k_capability_type {
00886         AR5K_CAP_REG_DMN                = 0,    /* Used to get current reg. domain id */
00887         AR5K_CAP_TKIP_MIC               = 2,    /* Can handle TKIP MIC in hardware */
00888         AR5K_CAP_TKIP_SPLIT             = 3,    /* TKIP uses split keys */
00889         AR5K_CAP_PHYCOUNTERS            = 4,    /* PHY error counters */
00890         AR5K_CAP_DIVERSITY              = 5,    /* Supports fast diversity */
00891         AR5K_CAP_NUM_TXQUEUES           = 6,    /* Used to get max number of hw txqueues */
00892         AR5K_CAP_VEOL                   = 7,    /* Supports virtual EOL */
00893         AR5K_CAP_COMPRESSION            = 8,    /* Supports compression */
00894         AR5K_CAP_BURST                  = 9,    /* Supports packet bursting */
00895         AR5K_CAP_FASTFRAME              = 10,   /* Supports fast frames */
00896         AR5K_CAP_TXPOW                  = 11,   /* Used to get global tx power limit */
00897         AR5K_CAP_TPC                    = 12,   /* Can do per-packet tx power control (needed for 802.11a) */
00898         AR5K_CAP_BSSIDMASK              = 13,   /* Supports bssid mask */
00899         AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
00900         AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
00901         AR5K_CAP_XR                     = 16,   /* Supports XR mode */
00902         AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
00903         AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
00904         AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
00905         AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
00906 };
00907 
00908 
00909 /* XXX: we *may* move cap_range stuff to struct wiphy */
00910 struct ath5k_capabilities {
00911         /*
00912          * Supported PHY modes
00913          * (ie. CHANNEL_A, CHANNEL_B, ...)
00914          */
00915         u16 cap_mode;
00916 
00917         /*
00918          * Frequency range (without regulation restrictions)
00919          */
00920         struct {
00921                 u16     range_2ghz_min;
00922                 u16     range_2ghz_max;
00923                 u16     range_5ghz_min;
00924                 u16     range_5ghz_max;
00925         } cap_range;
00926 
00927         /*
00928          * Values stored in the EEPROM (some of them...)
00929          */
00930         struct ath5k_eeprom_info        cap_eeprom;
00931 
00932         /*
00933          * Queue information
00934          */
00935         struct {
00936                 u8      q_tx_num;
00937         } cap_queues;
00938 };
00939 
00940 
00941 /***************************************\
00942   HARDWARE ABSTRACTION LAYER STRUCTURE
00943 \***************************************/
00944 
00945 /*
00946  * Misc defines
00947  */
00948 
00949 #define AR5K_MAX_GPIO           10
00950 #define AR5K_MAX_RF_BANKS       8
00951 
00952 /* TODO: Clean up and merge with ath5k_softc */
00953 struct ath5k_hw {
00954         struct ath5k_softc      *ah_sc;
00955         void                    *ah_iobase;
00956 
00957         enum ath5k_int          ah_imr;
00958         int                     ah_ier;
00959 
00960         struct net80211_channel *ah_current_channel;
00961         int                     ah_turbo;
00962         int                     ah_calibration;
00963         int                     ah_running;
00964         int                     ah_single_chip;
00965         int                     ah_combined_mic;
00966 
00967         u32                     ah_mac_srev;
00968         u16                     ah_mac_version;
00969         u16                     ah_mac_revision;
00970         u16                     ah_phy_revision;
00971         u16                     ah_radio_5ghz_revision;
00972         u16                     ah_radio_2ghz_revision;
00973 
00974         enum ath5k_version      ah_version;
00975         enum ath5k_radio        ah_radio;
00976         u32                     ah_phy;
00977 
00978         int                     ah_5ghz;
00979         int                     ah_2ghz;
00980 
00981 #define ah_regdomain            ah_capabilities.cap_regdomain.reg_current
00982 #define ah_regdomain_hw         ah_capabilities.cap_regdomain.reg_hw
00983 #define ah_modes                ah_capabilities.cap_mode
00984 #define ah_ee_version           ah_capabilities.cap_eeprom.ee_version
00985 
00986         u32                     ah_atim_window;
00987         u32                     ah_aifs;
00988         u32                     ah_cw_min;
00989         u32                     ah_cw_max;
00990         int                     ah_software_retry;
00991         u32                     ah_limit_tx_retries;
00992 
00993         u32                     ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
00994         int                     ah_ant_diversity;
00995 
00996         u8                      ah_sta_id[ETH_ALEN];
00997 
00998         /* Current BSSID we are trying to assoc to / create.
00999          * This is passed by mac80211 on config_interface() and cached here for
01000          * use in resets */
01001         u8                      ah_bssid[ETH_ALEN];
01002         u8                      ah_bssid_mask[ETH_ALEN];
01003 
01004         u32                     ah_gpio[AR5K_MAX_GPIO];
01005         int                     ah_gpio_npins;
01006 
01007         struct ath5k_capabilities ah_capabilities;
01008 
01009         struct ath5k_txq_info   ah_txq;
01010         u32                     ah_txq_status;
01011         u32                     ah_txq_imr_txok;
01012         u32                     ah_txq_imr_txerr;
01013         u32                     ah_txq_imr_txurn;
01014         u32                     ah_txq_imr_txdesc;
01015         u32                     ah_txq_imr_txeol;
01016         u32                     ah_txq_imr_cbrorn;
01017         u32                     ah_txq_imr_cbrurn;
01018         u32                     ah_txq_imr_qtrig;
01019         u32                     ah_txq_imr_nofrm;
01020         u32                     ah_txq_isr;
01021         u32                     *ah_rf_banks;
01022         size_t                  ah_rf_banks_size;
01023         size_t                  ah_rf_regs_count;
01024         struct ath5k_gain       ah_gain;
01025         u8                      ah_offset[AR5K_MAX_RF_BANKS];
01026 
01027 
01028         struct {
01029                 /* Temporary tables used for interpolation */
01030                 u8              tmpL[AR5K_EEPROM_N_PD_GAINS]
01031                                         [AR5K_EEPROM_POWER_TABLE_SIZE];
01032                 u8              tmpR[AR5K_EEPROM_N_PD_GAINS]
01033                                         [AR5K_EEPROM_POWER_TABLE_SIZE];
01034                 u8              txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
01035                 u16             txp_rates_power_table[AR5K_MAX_RATES];
01036                 u8              txp_min_idx;
01037                 int             txp_tpc;
01038                 /* Values in 0.25dB units */
01039                 s16             txp_min_pwr;
01040                 s16             txp_max_pwr;
01041                 s16             txp_offset;
01042                 s16             txp_ofdm;
01043                 /* Values in dB units */
01044                 s16             txp_cck_ofdm_pwr_delta;
01045                 s16             txp_cck_ofdm_gainf_delta;
01046         } ah_txpower;
01047 
01048         /* noise floor from last periodic calibration */
01049         s32                     ah_noise_floor;
01050 
01051         /*
01052          * Function pointers
01053          */
01054         int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
01055                                 u32 size, unsigned int flags);
01056         int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01057                 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
01058                 unsigned int, unsigned int, unsigned int, unsigned int,
01059                 unsigned int, unsigned int, unsigned int);
01060         int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01061                 struct ath5k_tx_status *);
01062         int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01063                 struct ath5k_rx_status *);
01064 };
01065 
01066 /*
01067  * Prototypes
01068  */
01069 
01070 extern int ath5k_bitrate_to_hw_rix(int bitrate);
01071 
01072 /* Attach/Detach Functions */
01073 extern int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah);
01074 extern void ath5k_hw_detach(struct ath5k_hw *ah);
01075 
01076 /* LED functions */
01077 extern int ath5k_init_leds(struct ath5k_softc *sc);
01078 extern void ath5k_led_enable(struct ath5k_softc *sc);
01079 extern void ath5k_led_off(struct ath5k_softc *sc);
01080 extern void ath5k_unregister_leds(struct ath5k_softc *sc);
01081 
01082 /* Reset Functions */
01083 extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial);
01084 extern int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel);
01085 /* Power management functions */
01086 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration);
01087 
01088 /* DMA Related Functions */
01089 extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
01090 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
01091 extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
01092 extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
01093 extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
01094 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
01095 extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
01096 extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
01097                                 u32 phys_addr);
01098 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase);
01099 /* Interrupt handling */
01100 extern int ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
01101 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
01102 extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
01103 
01104 /* EEPROM access functions */
01105 extern int ath5k_eeprom_init(struct ath5k_hw *ah);
01106 extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
01107 extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
01108 extern int ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
01109 
01110 /* Protocol Control Unit Functions */
01111 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
01112 /* BSSID Functions */
01113 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
01114 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
01115 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
01116 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
01117 /* Receive start/stop functions */
01118 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
01119 extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
01120 /* RX Filter functions */
01121 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
01122 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
01123 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
01124 /* ACK bit rate */
01125 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high);
01126 /* ACK/CTS Timeouts */
01127 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
01128 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
01129 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
01130 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
01131 /* Key table (WEP) functions */
01132 extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
01133 
01134 /* Queue Control Unit, DFS Control Unit Functions */
01135 extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info);
01136 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
01137                                 enum ath5k_tx_queue queue_type,
01138                                 struct ath5k_txq_info *queue_info);
01139 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah);
01140 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah);
01141 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah);
01142 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
01143 
01144 /* Hardware Descriptor Functions */
01145 extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
01146 
01147 /* GPIO Functions */
01148 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
01149 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
01150 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
01151 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
01152 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
01153 
01154 /* rfkill Functions */
01155 extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
01156 extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
01157 
01158 /* Misc functions */
01159 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
01160 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
01161 extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
01162 extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
01163 
01164 /* Initial register settings functions */
01165 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel);
01166 
01167 /* Initialize RF */
01168 extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
01169                                 struct net80211_channel *channel,
01170                                 unsigned int mode);
01171 extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
01172 extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
01173 extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
01174 /* PHY/RF channel functions */
01175 extern int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
01176 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel);
01177 /* PHY calibration */
01178 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel);
01179 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
01180 /* Misc PHY functions */
01181 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
01182 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
01183 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
01184 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
01185 /* TX power setup */
01186 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower);
01187 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower);
01188 
01189 /*
01190  * Functions used internaly
01191  */
01192 
01193 /*
01194  * Translate usec to hw clock units
01195  * TODO: Half/quarter rate
01196  */
01197 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo)
01198 {
01199         return turbo ? (usec * 80) : (usec * 40);
01200 }
01201 
01202 /*
01203  * Translate hw clock units to usec
01204  * TODO: Half/quarter rate
01205  */
01206 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, int turbo)
01207 {
01208         return turbo ? (clock / 80) : (clock / 40);
01209 }
01210 
01211 /*
01212  * Read from a register
01213  */
01214 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
01215 {
01216         return readl(ah->ah_iobase + reg);
01217 }
01218 
01219 /*
01220  * Write to a register
01221  */
01222 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
01223 {
01224         writel(val, ah->ah_iobase + reg);
01225 }
01226 
01227 #if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
01228 /*
01229  * Check if a register write has been completed
01230  */
01231 static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
01232                 u32 val, int is_set)
01233 {
01234         int i;
01235         u32 data;
01236 
01237         for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
01238                 data = ath5k_hw_reg_read(ah, reg);
01239                 if (is_set && (data & flag))
01240                         break;
01241                 else if ((data & flag) == val)
01242                         break;
01243                 udelay(15);
01244         }
01245 
01246         return (i <= 0) ? -EAGAIN : 0;
01247 }
01248 
01249 /*
01250  * Convert channel frequency to channel number
01251  */
01252 static inline int ath5k_freq_to_channel(int freq)
01253 {
01254         if (freq == 2484)
01255                 return 14;
01256 
01257         if (freq < 2484)
01258                 return (freq - 2407) / 5;
01259 
01260         return freq/5 - 1000;
01261 }
01262 
01263 #endif
01264 
01265 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
01266 {
01267         u32 retval = 0, bit, i;
01268 
01269         for (i = 0; i < bits; i++) {
01270                 bit = (val >> i) & 1;
01271                 retval = (retval << 1) | bit;
01272         }
01273 
01274         return retval;
01275 }
01276 
01277 #endif