iPXE
ath5k_desc.c
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00001 /*
00002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
00003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
00004  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
00005  *
00006  * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
00007  *
00008  * Permission to use, copy, modify, and distribute this software for any
00009  * purpose with or without fee is hereby granted, provided that the above
00010  * copyright notice and this permission notice appear in all copies.
00011  *
00012  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00013  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00014  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00015  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00016  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00017  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00018  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00019  *
00020  */
00021 
00022 FILE_LICENCE ( MIT );
00023 
00024 /******************************\
00025  Hardware Descriptor Functions
00026 \******************************/
00027 
00028 #include "ath5k.h"
00029 #include "reg.h"
00030 #include "base.h"
00031 
00032 /*
00033  * TX Descriptors
00034  */
00035 
00036 #define FCS_LEN 4
00037 
00038 /*
00039  * Initialize the 2-word tx control descriptor on 5210/5211
00040  */
00041 static int
00042 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
00043         unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
00044         unsigned int tx_power __unused, unsigned int tx_rate0, unsigned int tx_tries0,
00045         unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags,
00046         unsigned int rtscts_rate __unused, unsigned int rtscts_duration)
00047 {
00048         u32 frame_type;
00049         struct ath5k_hw_2w_tx_ctl *tx_ctl;
00050         unsigned int frame_len;
00051 
00052         tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
00053 
00054         /*
00055          * Validate input
00056          * - Zero retries don't make sense.
00057          * - A zero rate will put the HW into a mode where it continously sends
00058          *   noise on the channel, so it is important to avoid this.
00059          */
00060         if (tx_tries0 == 0) {
00061                 DBG("ath5k: zero retries\n");
00062                 return -EINVAL;
00063         }
00064         if (tx_rate0 == 0) {
00065                 DBG("ath5k: zero rate\n");
00066                 return -EINVAL;
00067         }
00068 
00069         /* Clear descriptor */
00070         memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
00071 
00072         /* Setup control descriptor */
00073 
00074         /* Verify and set frame length */
00075 
00076         frame_len = pkt_len + FCS_LEN;
00077 
00078         if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
00079                 return -EINVAL;
00080 
00081         tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
00082 
00083         /* Verify and set buffer length */
00084 
00085         if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
00086                 return -EINVAL;
00087 
00088         tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
00089 
00090         /*
00091          * Verify and set header length
00092          * XXX: I only found that on 5210 code, does it work on 5211 ?
00093          */
00094         if (ah->ah_version == AR5K_AR5210) {
00095                 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
00096                         return -EINVAL;
00097                 tx_ctl->tx_control_0 |=
00098                         AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
00099         }
00100 
00101         /*Diferences between 5210-5211*/
00102         if (ah->ah_version == AR5K_AR5210) {
00103                 switch (type) {
00104                 case AR5K_PKT_TYPE_BEACON:
00105                 case AR5K_PKT_TYPE_PROBE_RESP:
00106                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
00107                         break;
00108                 case AR5K_PKT_TYPE_PIFS:
00109                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
00110                         break;
00111                 default:
00112                         frame_type = type /*<< 2 ?*/;
00113                         break;
00114                 }
00115 
00116                 tx_ctl->tx_control_0 |=
00117                 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
00118                 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
00119 
00120         } else {
00121                 tx_ctl->tx_control_0 |=
00122                         AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
00123                         AR5K_REG_SM(antenna_mode,
00124                                 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
00125                 tx_ctl->tx_control_1 |=
00126                         AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
00127         }
00128 #define _TX_FLAGS(_c, _flag)                                    \
00129         if (flags & AR5K_TXDESC_##_flag) {                      \
00130                 tx_ctl->tx_control_##_c |=                      \
00131                         AR5K_2W_TX_DESC_CTL##_c##_##_flag;      \
00132         }
00133 
00134         _TX_FLAGS(0, CLRDMASK);
00135         _TX_FLAGS(0, VEOL);
00136         _TX_FLAGS(0, INTREQ);
00137         _TX_FLAGS(0, RTSENA);
00138         _TX_FLAGS(1, NOACK);
00139 
00140 #undef _TX_FLAGS
00141 
00142         /*
00143          * RTS/CTS Duration [5210 ?]
00144          */
00145         if ((ah->ah_version == AR5K_AR5210) &&
00146                         (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
00147                 tx_ctl->tx_control_1 |= rtscts_duration &
00148                                 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
00149 
00150         return 0;
00151 }
00152 
00153 /*
00154  * Initialize the 4-word tx control descriptor on 5212
00155  */
00156 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
00157         struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len __unused,
00158         enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
00159         unsigned int tx_tries0, unsigned int key_index __unused,
00160         unsigned int antenna_mode, unsigned int flags,
00161         unsigned int rtscts_rate,
00162         unsigned int rtscts_duration)
00163 {
00164         struct ath5k_hw_4w_tx_ctl *tx_ctl;
00165         unsigned int frame_len;
00166 
00167         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
00168 
00169         /*
00170          * Validate input
00171          * - Zero retries don't make sense.
00172          * - A zero rate will put the HW into a mode where it continously sends
00173          *   noise on the channel, so it is important to avoid this.
00174          */
00175         if (tx_tries0 == 0) {
00176                 DBG("ath5k: zero retries\n");
00177                 return -EINVAL;
00178         }
00179         if (tx_rate0 == 0) {
00180                 DBG("ath5k: zero rate\n");
00181                 return -EINVAL;
00182         }
00183 
00184         tx_power += ah->ah_txpower.txp_offset;
00185         if (tx_power > AR5K_TUNE_MAX_TXPOWER)
00186                 tx_power = AR5K_TUNE_MAX_TXPOWER;
00187 
00188         /* Clear descriptor */
00189         memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
00190 
00191         /* Setup control descriptor */
00192 
00193         /* Verify and set frame length */
00194 
00195         frame_len = pkt_len + FCS_LEN;
00196 
00197         if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
00198                 return -EINVAL;
00199 
00200         tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
00201 
00202         /* Verify and set buffer length */
00203 
00204         if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
00205                 return -EINVAL;
00206 
00207         tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
00208 
00209         tx_ctl->tx_control_0 |=
00210                 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
00211                 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
00212         tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
00213                                         AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
00214         tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
00215                                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
00216         tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
00217 
00218 #define _TX_FLAGS(_c, _flag)                                    \
00219         if (flags & AR5K_TXDESC_##_flag) {                      \
00220                 tx_ctl->tx_control_##_c |=                      \
00221                         AR5K_4W_TX_DESC_CTL##_c##_##_flag;      \
00222         }
00223 
00224         _TX_FLAGS(0, CLRDMASK);
00225         _TX_FLAGS(0, VEOL);
00226         _TX_FLAGS(0, INTREQ);
00227         _TX_FLAGS(0, RTSENA);
00228         _TX_FLAGS(0, CTSENA);
00229         _TX_FLAGS(1, NOACK);
00230 
00231 #undef _TX_FLAGS
00232 
00233         /*
00234          * RTS/CTS
00235          */
00236         if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
00237                 if ((flags & AR5K_TXDESC_RTSENA) &&
00238                                 (flags & AR5K_TXDESC_CTSENA))
00239                         return -EINVAL;
00240                 tx_ctl->tx_control_2 |= rtscts_duration &
00241                                 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
00242                 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
00243                                 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
00244         }
00245 
00246         return 0;
00247 }
00248 
00249 /*
00250  * Proccess the tx status descriptor on 5210/5211
00251  */
00252 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah __unused,
00253                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
00254 {
00255         struct ath5k_hw_2w_tx_ctl *tx_ctl;
00256         struct ath5k_hw_tx_status *tx_status;
00257 
00258         tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
00259         tx_status = &desc->ud.ds_tx5210.tx_stat;
00260 
00261         /* No frame has been send or error */
00262         if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
00263                 return -EINPROGRESS;
00264 
00265         /*
00266          * Get descriptor status
00267          */
00268         ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
00269                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
00270         ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
00271                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
00272         ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
00273                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
00274         /*TODO: ts->ts_virtcol + test*/
00275         ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
00276                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
00277         ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
00278                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
00279         ts->ts_antenna = 1;
00280         ts->ts_status = 0;
00281         ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
00282                 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
00283         ts->ts_retry[0] = ts->ts_longretry;
00284         ts->ts_final_idx = 0;
00285 
00286         if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
00287                 if (tx_status->tx_status_0 &
00288                                 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
00289                         ts->ts_status |= AR5K_TXERR_XRETRY;
00290 
00291                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
00292                         ts->ts_status |= AR5K_TXERR_FIFO;
00293 
00294                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
00295                         ts->ts_status |= AR5K_TXERR_FILT;
00296         }
00297 
00298         return 0;
00299 }
00300 
00301 /*
00302  * Proccess a tx status descriptor on 5212
00303  */
00304 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah __unused,
00305                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
00306 {
00307         struct ath5k_hw_4w_tx_ctl *tx_ctl;
00308         struct ath5k_hw_tx_status *tx_status;
00309 
00310         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
00311         tx_status = &desc->ud.ds_tx5212.tx_stat;
00312 
00313         /* No frame has been send or error */
00314         if (!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE))
00315                 return -EINPROGRESS;
00316 
00317         /*
00318          * Get descriptor status
00319          */
00320         ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
00321                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
00322         ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
00323                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
00324         ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
00325                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
00326         ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
00327                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
00328         ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
00329                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
00330         ts->ts_antenna = (tx_status->tx_status_1 &
00331                 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
00332         ts->ts_status = 0;
00333 
00334         ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
00335                         AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
00336 
00337         ts->ts_retry[0] = ts->ts_longretry;
00338         ts->ts_rate[0] = tx_ctl->tx_control_3 &
00339                 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
00340 
00341         /* TX error */
00342         if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
00343                 if (tx_status->tx_status_0 &
00344                                 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
00345                         ts->ts_status |= AR5K_TXERR_XRETRY;
00346 
00347                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
00348                         ts->ts_status |= AR5K_TXERR_FIFO;
00349 
00350                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
00351                         ts->ts_status |= AR5K_TXERR_FILT;
00352         }
00353 
00354         return 0;
00355 }
00356 
00357 /*
00358  * RX Descriptors
00359  */
00360 
00361 /*
00362  * Initialize an rx control descriptor
00363  */
00364 static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah __unused,
00365                                   struct ath5k_desc *desc,
00366                                   u32 size, unsigned int flags)
00367 {
00368         struct ath5k_hw_rx_ctl *rx_ctl;
00369 
00370         rx_ctl = &desc->ud.ds_rx.rx_ctl;
00371 
00372         /*
00373          * Clear the descriptor
00374          * If we don't clean the status descriptor,
00375          * while scanning we get too many results,
00376          * most of them virtual, after some secs
00377          * of scanning system hangs. M.F.
00378         */
00379         memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
00380 
00381         /* Setup descriptor */
00382         rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
00383         if (rx_ctl->rx_control_1 != size)
00384                 return -EINVAL;
00385 
00386         if (flags & AR5K_RXDESC_INTREQ)
00387                 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
00388 
00389         return 0;
00390 }
00391 
00392 /*
00393  * Proccess the rx status descriptor on 5210/5211
00394  */
00395 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah __unused,
00396                 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
00397 {
00398         struct ath5k_hw_rx_status *rx_status;
00399 
00400         rx_status = &desc->ud.ds_rx.u.rx_stat;
00401 
00402         /* No frame received / not ready */
00403         if (!(rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE))
00404                 return -EINPROGRESS;
00405 
00406         /*
00407          * Frame receive status
00408          */
00409         rs->rs_datalen = rx_status->rx_status_0 &
00410                 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
00411         rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
00412                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
00413         rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
00414                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
00415         rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
00416                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
00417         rs->rs_more = !!(rx_status->rx_status_0 &
00418                 AR5K_5210_RX_DESC_STATUS0_MORE);
00419         /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
00420         rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
00421                 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
00422         rs->rs_status = 0;
00423         rs->rs_phyerr = 0;
00424         rs->rs_keyix = AR5K_RXKEYIX_INVALID;
00425 
00426         /*
00427          * Receive/descriptor errors
00428          */
00429         if (!(rx_status->rx_status_1 &
00430               AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
00431                 if (rx_status->rx_status_1 &
00432                                 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
00433                         rs->rs_status |= AR5K_RXERR_CRC;
00434 
00435                 if (rx_status->rx_status_1 &
00436                                 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
00437                         rs->rs_status |= AR5K_RXERR_FIFO;
00438 
00439                 if (rx_status->rx_status_1 &
00440                                 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
00441                         rs->rs_status |= AR5K_RXERR_PHY;
00442                         rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
00443                                 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
00444                 }
00445 
00446                 if (rx_status->rx_status_1 &
00447                                 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
00448                         rs->rs_status |= AR5K_RXERR_DECRYPT;
00449         }
00450 
00451         return 0;
00452 }
00453 
00454 /*
00455  * Proccess the rx status descriptor on 5212
00456  */
00457 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah __unused,
00458                 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
00459 {
00460         struct ath5k_hw_rx_status *rx_status;
00461         struct ath5k_hw_rx_error *rx_err;
00462 
00463         rx_status = &desc->ud.ds_rx.u.rx_stat;
00464 
00465         /* Overlay on error */
00466         rx_err = &desc->ud.ds_rx.u.rx_err;
00467 
00468         /* No frame received / not ready */
00469         if (!(rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE))
00470                 return -EINPROGRESS;
00471 
00472         /*
00473          * Frame receive status
00474          */
00475         rs->rs_datalen = rx_status->rx_status_0 &
00476                 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
00477         rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
00478                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
00479         rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
00480                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
00481         rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
00482                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
00483         rs->rs_more = !!(rx_status->rx_status_0 &
00484                 AR5K_5212_RX_DESC_STATUS0_MORE);
00485         rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
00486                 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
00487         rs->rs_status = 0;
00488         rs->rs_phyerr = 0;
00489         rs->rs_keyix = AR5K_RXKEYIX_INVALID;
00490 
00491         /*
00492          * Receive/descriptor errors
00493          */
00494         if (!(rx_status->rx_status_1 &
00495               AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
00496                 if (rx_status->rx_status_1 &
00497                                 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
00498                         rs->rs_status |= AR5K_RXERR_CRC;
00499 
00500                 if (rx_status->rx_status_1 &
00501                                 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
00502                         rs->rs_status |= AR5K_RXERR_PHY;
00503                         rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
00504                                            AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
00505                 }
00506 
00507                 if (rx_status->rx_status_1 &
00508                                 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
00509                         rs->rs_status |= AR5K_RXERR_DECRYPT;
00510 
00511                 if (rx_status->rx_status_1 &
00512                                 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
00513                         rs->rs_status |= AR5K_RXERR_MIC;
00514         }
00515 
00516         return 0;
00517 }
00518 
00519 /*
00520  * Init function pointers inside ath5k_hw struct
00521  */
00522 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
00523 {
00524 
00525         if (ah->ah_version != AR5K_AR5210 &&
00526             ah->ah_version != AR5K_AR5211 &&
00527             ah->ah_version != AR5K_AR5212)
00528                 return -ENOTSUP;
00529 
00530         if (ah->ah_version == AR5K_AR5212) {
00531                 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
00532                 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
00533                 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
00534         } else {
00535                 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
00536                 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
00537                 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
00538         }
00539 
00540         if (ah->ah_version == AR5K_AR5212)
00541                 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
00542         else if (ah->ah_version <= AR5K_AR5211)
00543                 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
00544 
00545         return 0;
00546 }
00547