iPXE
ath5k_pcu.c
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00001 /*
00002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
00003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
00004  * Copyright (c) 2007-2008 Matthew W. S. Bell  <mentor@madwifi.org>
00005  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
00006  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
00007  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
00008  *
00009  * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
00010  *
00011  * Permission to use, copy, modify, and distribute this software for any
00012  * purpose with or without fee is hereby granted, provided that the above
00013  * copyright notice and this permission notice appear in all copies.
00014  *
00015  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00016  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00017  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00018  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00019  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00020  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00021  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00022  *
00023  */
00024 
00025 FILE_LICENCE ( MIT );
00026 
00027 /*********************************\
00028 * Protocol Control Unit Functions *
00029 \*********************************/
00030 
00031 #include "ath5k.h"
00032 #include "reg.h"
00033 #include "base.h"
00034 
00035 /*******************\
00036 * Generic functions *
00037 \*******************/
00038 
00039 /**
00040  * ath5k_hw_set_opmode - Set PCU operating mode
00041  *
00042  * @ah: The &struct ath5k_hw
00043  *
00044  * Initialize PCU for the various operating modes (AP/STA etc)
00045  *
00046  * For iPXE we always assume STA mode.
00047  */
00048 int ath5k_hw_set_opmode(struct ath5k_hw *ah)
00049 {
00050         u32 pcu_reg, beacon_reg, low_id, high_id;
00051 
00052 
00053         /* Preserve rest settings */
00054         pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
00055         pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
00056                         | AR5K_STA_ID1_KEYSRCH_MODE
00057                         | (ah->ah_version == AR5K_AR5210 ?
00058                         (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
00059 
00060         beacon_reg = 0;
00061 
00062         pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
00063                 | (ah->ah_version == AR5K_AR5210 ?
00064                    AR5K_STA_ID1_PWR_SV : 0);
00065 
00066         /*
00067          * Set PCU registers
00068          */
00069         low_id = AR5K_LOW_ID(ah->ah_sta_id);
00070         high_id = AR5K_HIGH_ID(ah->ah_sta_id);
00071         ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
00072         ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
00073 
00074         /*
00075          * Set Beacon Control Register on 5210
00076          */
00077         if (ah->ah_version == AR5K_AR5210)
00078                 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
00079 
00080         return 0;
00081 }
00082 
00083 /**
00084  * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
00085  *
00086  * @ah: The &struct ath5k_hw
00087  * @high: Flag to determine if we want to use high transmition rate
00088  * for ACKs or not
00089  *
00090  * If high flag is set, we tell hw to use a set of control rates based on
00091  * the current transmition rate (check out control_rates array inside reset.c).
00092  * If not hw just uses the lowest rate available for the current modulation
00093  * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
00094  */
00095 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high)
00096 {
00097         if (ah->ah_version != AR5K_AR5212)
00098                 return;
00099         else {
00100                 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
00101                 if (high)
00102                         AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
00103                 else
00104                         AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
00105         }
00106 }
00107 
00108 
00109 /******************\
00110 * ACK/CTS Timeouts *
00111 \******************/
00112 
00113 /**
00114  * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
00115  *
00116  * @ah: The &struct ath5k_hw
00117  */
00118 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
00119 {
00120         return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
00121                         AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
00122 }
00123 
00124 /**
00125  * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
00126  *
00127  * @ah: The &struct ath5k_hw
00128  * @timeout: Timeout in usec
00129  */
00130 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
00131 {
00132         if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
00133                         ah->ah_turbo) <= timeout)
00134                 return -EINVAL;
00135 
00136         AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
00137                 ath5k_hw_htoclock(timeout, ah->ah_turbo));
00138 
00139         return 0;
00140 }
00141 
00142 /**
00143  * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
00144  *
00145  * @ah: The &struct ath5k_hw
00146  */
00147 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
00148 {
00149         return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
00150                         AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
00151 }
00152 
00153 /**
00154  * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
00155  *
00156  * @ah: The &struct ath5k_hw
00157  * @timeout: Timeout in usec
00158  */
00159 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
00160 {
00161         if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
00162                         ah->ah_turbo) <= timeout)
00163                 return -EINVAL;
00164 
00165         AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
00166                         ath5k_hw_htoclock(timeout, ah->ah_turbo));
00167 
00168         return 0;
00169 }
00170 
00171 
00172 /****************\
00173 * BSSID handling *
00174 \****************/
00175 
00176 /**
00177  * ath5k_hw_get_lladdr - Get station id
00178  *
00179  * @ah: The &struct ath5k_hw
00180  * @mac: The card's mac address
00181  *
00182  * Initialize ah->ah_sta_id using the mac address provided
00183  * (just a memcpy).
00184  *
00185  * TODO: Remove it once we merge ath5k_softc and ath5k_hw
00186  */
00187 void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
00188 {
00189         memcpy(mac, ah->ah_sta_id, ETH_ALEN);
00190 }
00191 
00192 /**
00193  * ath5k_hw_set_lladdr - Set station id
00194  *
00195  * @ah: The &struct ath5k_hw
00196  * @mac: The card's mac address
00197  *
00198  * Set station id on hw using the provided mac address
00199  */
00200 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
00201 {
00202         u32 low_id, high_id;
00203         u32 pcu_reg;
00204 
00205         /* Set new station ID */
00206         memcpy(ah->ah_sta_id, mac, ETH_ALEN);
00207 
00208         pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
00209 
00210         low_id = AR5K_LOW_ID(mac);
00211         high_id = AR5K_HIGH_ID(mac);
00212 
00213         ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
00214         ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
00215 
00216         return 0;
00217 }
00218 
00219 /**
00220  * ath5k_hw_set_associd - Set BSSID for association
00221  *
00222  * @ah: The &struct ath5k_hw
00223  * @bssid: BSSID
00224  * @assoc_id: Assoc id
00225  *
00226  * Sets the BSSID which trigers the "SME Join" operation
00227  */
00228 void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
00229 {
00230         u32 low_id, high_id;
00231 
00232         /*
00233          * Set simple BSSID mask on 5212
00234          */
00235         if (ah->ah_version == AR5K_AR5212) {
00236                 ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_bssid_mask),
00237                                                         AR5K_BSS_IDM0);
00238                 ath5k_hw_reg_write(ah, AR5K_HIGH_ID(ah->ah_bssid_mask),
00239                                                         AR5K_BSS_IDM1);
00240         }
00241 
00242         /*
00243          * Set BSSID which triggers the "SME Join" operation
00244          */
00245         low_id = AR5K_LOW_ID(bssid);
00246         high_id = AR5K_HIGH_ID(bssid);
00247         ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
00248         ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
00249                                 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
00250 }
00251 
00252 /**
00253  * ath5k_hw_set_bssid_mask - filter out bssids we listen
00254  *
00255  * @ah: the &struct ath5k_hw
00256  * @mask: the bssid_mask, a u8 array of size ETH_ALEN
00257  *
00258  * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
00259  * which bits of the interface's MAC address should be looked at when trying
00260  * to decide which packets to ACK. In station mode and AP mode with a single
00261  * BSS every bit matters since we lock to only one BSS. In AP mode with
00262  * multiple BSSes (virtual interfaces) not every bit matters because hw must
00263  * accept frames for all BSSes and so we tweak some bits of our mac address
00264  * in order to have multiple BSSes.
00265  *
00266  * NOTE: This is a simple filter and does *not* filter out all
00267  * relevant frames. Some frames that are not for us might get ACKed from us
00268  * by PCU because they just match the mask.
00269  *
00270  * When handling multiple BSSes you can get the BSSID mask by computing the
00271  * set of  ~ ( MAC XOR BSSID ) for all bssids we handle.
00272  *
00273  * When you do this you are essentially computing the common bits of all your
00274  * BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with
00275  * the MAC address to obtain the relevant bits and compare the result with
00276  * (frame's BSSID & mask) to see if they match.
00277  */
00278 /*
00279  * Simple example: on your card you have have two BSSes you have created with
00280  * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
00281  * There is another BSSID-03 but you are not part of it. For simplicity's sake,
00282  * assuming only 4 bits for a mac address and for BSSIDs you can then have:
00283  *
00284  *                  \
00285  * MAC:                0001 |
00286  * BSSID-01:   0100 | --> Belongs to us
00287  * BSSID-02:   1001 |
00288  *                  /
00289  * -------------------
00290  * BSSID-03:   0110  | --> External
00291  * -------------------
00292  *
00293  * Our bssid_mask would then be:
00294  *
00295  *             On loop iteration for BSSID-01:
00296  *             ~(0001 ^ 0100)  -> ~(0101)
00297  *                             ->   1010
00298  *             bssid_mask      =    1010
00299  *
00300  *             On loop iteration for BSSID-02:
00301  *             bssid_mask &= ~(0001   ^   1001)
00302  *             bssid_mask =   (1010)  & ~(0001 ^ 1001)
00303  *             bssid_mask =   (1010)  & ~(1001)
00304  *             bssid_mask =   (1010)  &  (0110)
00305  *             bssid_mask =   0010
00306  *
00307  * A bssid_mask of 0010 means "only pay attention to the second least
00308  * significant bit". This is because its the only bit common
00309  * amongst the MAC and all BSSIDs we support. To findout what the real
00310  * common bit is we can simply "&" the bssid_mask now with any BSSID we have
00311  * or our MAC address (we assume the hardware uses the MAC address).
00312  *
00313  * Now, suppose there's an incoming frame for BSSID-03:
00314  *
00315  * IFRAME-01:  0110
00316  *
00317  * An easy eye-inspeciton of this already should tell you that this frame
00318  * will not pass our check. This is beacuse the bssid_mask tells the
00319  * hardware to only look at the second least significant bit and the
00320  * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
00321  * as 1, which does not match 0.
00322  *
00323  * So with IFRAME-01 we *assume* the hardware will do:
00324  *
00325  *     allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
00326  *  --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
00327  *  --> allow = (0010) == 0000 ? 1 : 0;
00328  *  --> allow = 0
00329  *
00330  *  Lets now test a frame that should work:
00331  *
00332  * IFRAME-02:  0001 (we should allow)
00333  *
00334  *     allow = (0001 & 1010) == 1010
00335  *
00336  *     allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
00337  *  --> allow = (0001 & 0010) ==  (0010 & 0001) ? 1 :0;
00338  *  --> allow = (0010) == (0010)
00339  *  --> allow = 1
00340  *
00341  * Other examples:
00342  *
00343  * IFRAME-03:  0100 --> allowed
00344  * IFRAME-04:  1001 --> allowed
00345  * IFRAME-05:  1101 --> allowed but its not for us!!!
00346  *
00347  */
00348 int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
00349 {
00350         u32 low_id, high_id;
00351 
00352         /* Cache bssid mask so that we can restore it
00353          * on reset */
00354         memcpy(ah->ah_bssid_mask, mask, ETH_ALEN);
00355         if (ah->ah_version == AR5K_AR5212) {
00356                 low_id = AR5K_LOW_ID(mask);
00357                 high_id = AR5K_HIGH_ID(mask);
00358 
00359                 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
00360                 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
00361 
00362                 return 0;
00363         }
00364 
00365         return -EIO;
00366 }
00367 
00368 
00369 /************\
00370 * RX Control *
00371 \************/
00372 
00373 /**
00374  * ath5k_hw_start_rx_pcu - Start RX engine
00375  *
00376  * @ah: The &struct ath5k_hw
00377  *
00378  * Starts RX engine on PCU so that hw can process RXed frames
00379  * (ACK etc).
00380  *
00381  * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
00382  * TODO: Init ANI here
00383  */
00384 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
00385 {
00386         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
00387 }
00388 
00389 /**
00390  * at5k_hw_stop_rx_pcu - Stop RX engine
00391  *
00392  * @ah: The &struct ath5k_hw
00393  *
00394  * Stops RX engine on PCU
00395  *
00396  * TODO: Detach ANI here
00397  */
00398 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
00399 {
00400         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
00401 }
00402 
00403 /*
00404  * Set multicast filter
00405  */
00406 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
00407 {
00408         /* Set the multicat filter */
00409         ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
00410         ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
00411 }
00412 
00413 /**
00414  * ath5k_hw_get_rx_filter - Get current rx filter
00415  *
00416  * @ah: The &struct ath5k_hw
00417  *
00418  * Returns the RX filter by reading rx filter and
00419  * phy error filter registers. RX filter is used
00420  * to set the allowed frame types that PCU will accept
00421  * and pass to the driver. For a list of frame types
00422  * check out reg.h.
00423  */
00424 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
00425 {
00426         u32 data, filter = 0;
00427 
00428         filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
00429 
00430         /*Radar detection for 5212*/
00431         if (ah->ah_version == AR5K_AR5212) {
00432                 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
00433 
00434                 if (data & AR5K_PHY_ERR_FIL_RADAR)
00435                         filter |= AR5K_RX_FILTER_RADARERR;
00436                 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
00437                         filter |= AR5K_RX_FILTER_PHYERR;
00438         }
00439 
00440         return filter;
00441 }
00442 
00443 /**
00444  * ath5k_hw_set_rx_filter - Set rx filter
00445  *
00446  * @ah: The &struct ath5k_hw
00447  * @filter: RX filter mask (see reg.h)
00448  *
00449  * Sets RX filter register and also handles PHY error filter
00450  * register on 5212 and newer chips so that we have proper PHY
00451  * error reporting.
00452  */
00453 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
00454 {
00455         u32 data = 0;
00456 
00457         /* Set PHY error filter register on 5212*/
00458         if (ah->ah_version == AR5K_AR5212) {
00459                 if (filter & AR5K_RX_FILTER_RADARERR)
00460                         data |= AR5K_PHY_ERR_FIL_RADAR;
00461                 if (filter & AR5K_RX_FILTER_PHYERR)
00462                         data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
00463         }
00464 
00465         /*
00466          * The AR5210 uses promiscous mode to detect radar activity
00467          */
00468         if (ah->ah_version == AR5K_AR5210 &&
00469                         (filter & AR5K_RX_FILTER_RADARERR)) {
00470                 filter &= ~AR5K_RX_FILTER_RADARERR;
00471                 filter |= AR5K_RX_FILTER_PROM;
00472         }
00473 
00474         /*Zero length DMA (phy error reporting) */
00475         if (data)
00476                 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
00477         else
00478                 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
00479 
00480         /*Write RX Filter register*/
00481         ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
00482 
00483         /*Write PHY error filter register on 5212*/
00484         if (ah->ah_version == AR5K_AR5212)
00485                 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
00486 
00487 }
00488 
00489 /*********************\
00490 * Key table functions *
00491 \*********************/
00492 
00493 /*
00494  * Reset a key entry on the table
00495  */
00496 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
00497 {
00498         unsigned int i, type;
00499         u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
00500 
00501         type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
00502 
00503         for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
00504                 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
00505 
00506         /* Reset associated MIC entry if TKIP
00507          * is enabled located at offset (entry + 64) */
00508         if (type == AR5K_KEYTABLE_TYPE_TKIP) {
00509                 for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
00510                         ath5k_hw_reg_write(ah, 0,
00511                                 AR5K_KEYTABLE_OFF(micentry, i));
00512         }
00513 
00514         /*
00515          * Set NULL encryption on AR5212+
00516          *
00517          * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
00518          *       AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
00519          *
00520          * Note2: Windows driver (ndiswrapper) sets this to
00521          *        0x00000714 instead of 0x00000007
00522          */
00523         if (ah->ah_version >= AR5K_AR5211) {
00524                 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
00525                                 AR5K_KEYTABLE_TYPE(entry));
00526 
00527                 if (type == AR5K_KEYTABLE_TYPE_TKIP) {
00528                         ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
00529                                 AR5K_KEYTABLE_TYPE(micentry));
00530                 }
00531         }
00532 
00533         return 0;
00534 }