iPXE
Functions
ath5k_qcu.c File Reference
#include "ath5k.h"
#include "reg.h"
#include "base.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (MIT)
int ath5k_hw_set_tx_queueprops (struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info)
int ath5k_hw_setup_tx_queue (struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info)
void ath5k_hw_release_tx_queue (struct ath5k_hw *ah)
int ath5k_hw_reset_tx_queue (struct ath5k_hw *ah)
int ath5k_hw_set_slot_time (struct ath5k_hw *ah, unsigned int slot_time)

Function Documentation

FILE_LICENCE ( MIT  )
int ath5k_hw_set_tx_queueprops ( struct ath5k_hw ah,
const struct ath5k_txq_info queue_info 
)
int ath5k_hw_setup_tx_queue ( struct ath5k_hw ah,
enum ath5k_tx_queue  queue_type,
struct ath5k_txq_info queue_info 
)

Definition at line 55 of file ath5k_qcu.c.

References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_ENABLE_BITS, ath5k_hw_set_tx_queueprops(), memset(), NULL, ret, and ath5k_txq_info::tqi_type.

Referenced by ath5k_txq_setup().

{
        int ret;

        /*
         * Setup internal queue structure
         */
        memset(&ah->ah_txq, 0, sizeof(struct ath5k_txq_info));
        ah->ah_txq.tqi_type = queue_type;

        if (queue_info != NULL) {
                queue_info->tqi_type = queue_type;
                ret = ath5k_hw_set_tx_queueprops(ah, queue_info);
                if (ret)
                        return ret;
        }

        /*
         * We use ah_txq_status to hold a temp value for
         * the Secondary interrupt mask registers on 5211+
         * check out ath5k_hw_reset_tx_queue
         */
        AR5K_Q_ENABLE_BITS(ah->ah_txq_status, 0);

        return 0;
}
void ath5k_hw_release_tx_queue ( struct ath5k_hw ah)

Definition at line 86 of file ath5k_qcu.c.

References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_DISABLE_BITS, AR5K_TX_QUEUE_INACTIVE, and ath5k_txq_info::tqi_type.

Referenced by ath5k_txq_release().

{
        /* This queue will be skipped in further operations */
        ah->ah_txq.tqi_type = AR5K_TX_QUEUE_INACTIVE;
        /*For SIMR setup*/
        AR5K_Q_DISABLE_BITS(ah->ah_txq_status, 0);
}
int ath5k_hw_reset_tx_queue ( struct ath5k_hw ah)

Definition at line 97 of file ath5k_qcu.c.

References ath5k_hw::ah_aifs, ath5k_hw::ah_current_channel, ath5k_hw::ah_cw_max, ath5k_hw::ah_cw_min, ath5k_hw::ah_limit_tx_retries, ath5k_hw::ah_mac_version, ath5k_hw::ah_software_retry, ath5k_hw::ah_turbo, ath5k_hw::ah_txq, ath5k_hw::ah_txq_imr_cbrorn, ath5k_hw::ah_txq_imr_cbrurn, ath5k_hw::ah_txq_imr_nofrm, ath5k_hw::ah_txq_imr_qtrig, ath5k_hw::ah_txq_imr_txdesc, ath5k_hw::ah_txq_imr_txeol, ath5k_hw::ah_txq_imr_txerr, ath5k_hw::ah_txq_imr_txok, ath5k_hw::ah_txq_imr_txurn, ath5k_hw::ah_txq_status, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5212, AR5K_DCU_CHAN_TIME_DUR, AR5K_DCU_CHAN_TIME_ENABLE, AR5K_DCU_LCL_IFS_AIFS, AR5K_DCU_LCL_IFS_CW_MAX, AR5K_DCU_LCL_IFS_CW_MIN, AR5K_DCU_MISC_BACKOFF_FRAG, AR5K_DCU_MISC_FRAG_WAIT, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, AR5K_DCU_MISC_SEQNUM_CTL, AR5K_DCU_RETRY_LMT_LG_RETRY, AR5K_DCU_RETRY_LMT_SH_RETRY, AR5K_DCU_RETRY_LMT_SLG_RETRY, AR5K_DCU_RETRY_LMT_SSH_RETRY, AR5K_IFS0, AR5K_IFS0_DIFS_S, AR5K_IFS1, AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_INIT_ACK_CTS_TIMEOUT_TURBO, AR5K_INIT_LG_RETRY, AR5K_INIT_PROTO_TIME_CNTRL, AR5K_INIT_PROTO_TIME_CNTRL_TURBO, AR5K_INIT_SH_RETRY, AR5K_INIT_SIFS, AR5K_INIT_SIFS_TURBO, AR5K_INIT_SLG_RETRY, AR5K_INIT_SLOT_TIME, AR5K_INIT_SLOT_TIME_TURBO, AR5K_INIT_SSH_RETRY, AR5K_INIT_TRANSMIT_LATENCY, AR5K_INIT_TRANSMIT_LATENCY_TURBO, AR5K_NODCU_RETRY_LMT, AR5K_NODCU_RETRY_LMT_CW_MIN_S, AR5K_NODCU_RETRY_LMT_LG_RETRY, AR5K_NODCU_RETRY_LMT_SH_RETRY, AR5K_NODCU_RETRY_LMT_SLG_RETRY, AR5K_NODCU_RETRY_LMT_SSH_RETRY, AR5K_PHY_FRAME_CTL_5210, AR5K_PHY_FRAME_CTL_INI, AR5K_PHY_SETTLING, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_Q_ENABLE_BITS, AR5K_QCU_CBRCFG_INTVAL, AR5K_QCU_CBRCFG_ORN_THRES, AR5K_QCU_MISC_CBR_THRES_ENABLE, AR5K_QCU_MISC_DCU_EARLY, AR5K_QCU_MISC_FRSHED_CBR, AR5K_QCU_MISC_RDY_VEOL_POLICY, AR5K_QCU_RDYTIMECFG_ENABLE, AR5K_QCU_RDYTIMECFG_INTVAL, AR5K_QUEUE_CBRCFG, AR5K_QUEUE_DFS_CHANNEL_TIME, AR5K_QUEUE_DFS_LOCAL_IFS, AR5K_QUEUE_DFS_MISC, AR5K_QUEUE_DFS_RETRY_LIMIT, AR5K_QUEUE_MISC, AR5K_QUEUE_QCUMASK, AR5K_QUEUE_RDYTIMECFG, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SIMR0, AR5K_SIMR0_QCU_TXDESC, AR5K_SIMR0_QCU_TXOK, AR5K_SIMR1, AR5K_SIMR1_QCU_TXEOL, AR5K_SIMR1_QCU_TXERR, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR3, AR5K_SIMR3_QCBRORN, AR5K_SIMR3_QCBRURN, AR5K_SIMR4, AR5K_SIMR4_QTRIG, AR5K_SLOT_TIME, AR5K_SREV_AR5211, AR5K_TUNE_AIFS, AR5K_TUNE_AIFS_11B, AR5K_TUNE_AIFS_XR, AR5K_TUNE_CWMAX, AR5K_TUNE_CWMAX_11B, AR5K_TUNE_CWMAX_XR, AR5K_TUNE_CWMIN, AR5K_TUNE_CWMIN_11B, AR5K_TUNE_CWMIN_XR, AR5K_TX_QUEUE_CAB, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_INACTIVE, AR5K_TXNOFRM, AR5K_TXNOFRM_QCU, AR5K_TXQ_FLAG_BACKOFF_DISABLE, AR5K_TXQ_FLAG_CBRORNINT_ENABLE, AR5K_TXQ_FLAG_CBRURNINT_ENABLE, AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, AR5K_TXQ_FLAG_QTRIGINT_ENABLE, AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, AR5K_TXQ_FLAG_TXDESCINT_ENABLE, AR5K_TXQ_FLAG_TXEOLINT_ENABLE, AR5K_TXQ_FLAG_TXERRINT_ENABLE, AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE, AR5K_TXQ_FLAG_TXOKINT_ENABLE, AR5K_TXQ_FLAG_TXURNINT_ENABLE, AR5K_USEC_5210, ath5k_hw_reg_read(), ath5k_hw_reg_write(), IS_CHAN_B, IS_CHAN_XR, queue, ath5k_txq_info::tqi_aifs, ath5k_txq_info::tqi_burst_time, ath5k_txq_info::tqi_cbr_overflow_limit, ath5k_txq_info::tqi_cbr_period, ath5k_txq_info::tqi_cw_max, ath5k_txq_info::tqi_cw_min, ath5k_txq_info::tqi_flags, ath5k_txq_info::tqi_ready_time, and ath5k_txq_info::tqi_type.

Referenced by ath5k_hw_reset().

{
        u32 cw_min, cw_max, retry_lg, retry_sh;
        struct ath5k_txq_info *tq = &ah->ah_txq;
        const int queue = 0;

        tq = &ah->ah_txq;

        if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
                return 0;

        if (ah->ah_version == AR5K_AR5210) {
                /* Only handle data queues, others will be ignored */
                if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
                        return 0;

                /* Set Slot time */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
                        AR5K_SLOT_TIME);
                /* Set ACK_CTS timeout */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
                        AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
                /* Set Transmit Latency */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_TRANSMIT_LATENCY_TURBO :
                        AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);

                /* Set IFS0 */
                if (ah->ah_turbo) {
                         ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
                                (ah->ah_aifs + tq->tqi_aifs) *
                                AR5K_INIT_SLOT_TIME_TURBO) <<
                                AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
                                AR5K_IFS0);
                } else {
                        ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
                                (ah->ah_aifs + tq->tqi_aifs) *
                                AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
                                AR5K_INIT_SIFS, AR5K_IFS0);
                }

                /* Set IFS1 */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
                        AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
                /* Set AR5K_PHY_SETTLING */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
                        | 0x38 :
                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
                        | 0x1C,
                        AR5K_PHY_SETTLING);
                /* Set Frame Control Register */
                ath5k_hw_reg_write(ah, ah->ah_turbo ?
                        (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
                        AR5K_PHY_TURBO_SHORT | 0x2020) :
                        (AR5K_PHY_FRAME_CTL_INI | 0x1020),
                        AR5K_PHY_FRAME_CTL_5210);
        }

        /*
         * Calculate cwmin/max by channel mode
         */
        cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
        cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
        ah->ah_aifs = AR5K_TUNE_AIFS;
        /*XR is only supported on 5212*/
        if (IS_CHAN_XR(ah->ah_current_channel) &&
                        ah->ah_version == AR5K_AR5212) {
                cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
                cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
                ah->ah_aifs = AR5K_TUNE_AIFS_XR;
        /*B mode is not supported on 5210*/
        } else if (IS_CHAN_B(ah->ah_current_channel) &&
                        ah->ah_version != AR5K_AR5210) {
                cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
                cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
                ah->ah_aifs = AR5K_TUNE_AIFS_11B;
        }

        cw_min = 1;
        while (cw_min < ah->ah_cw_min)
                cw_min = (cw_min << 1) | 1;

        cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
                ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
        cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
                ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);

        /*
         * Calculate and set retry limits
         */
        if (ah->ah_software_retry) {
                /* XXX Need to test this */
                retry_lg = ah->ah_limit_tx_retries;
                retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
                        AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
        } else {
                retry_lg = AR5K_INIT_LG_RETRY;
                retry_sh = AR5K_INIT_SH_RETRY;
        }

        /*No QCU/DCU [5210]*/
        if (ah->ah_version == AR5K_AR5210) {
                ath5k_hw_reg_write(ah,
                        (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
                        | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
                                AR5K_NODCU_RETRY_LMT_SLG_RETRY)
                        | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
                                AR5K_NODCU_RETRY_LMT_SSH_RETRY)
                        | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
                        | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
                        AR5K_NODCU_RETRY_LMT);
        } else {
                /*QCU/DCU [5211+]*/
                ath5k_hw_reg_write(ah,
                        AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
                                AR5K_DCU_RETRY_LMT_SLG_RETRY) |
                        AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
                                AR5K_DCU_RETRY_LMT_SSH_RETRY) |
                        AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
                        AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
                        AR5K_QUEUE_DFS_RETRY_LIMIT(queue));

        /*===Rest is also for QCU/DCU only [5211+]===*/

                /*
                 * Set initial content window (cw_min/cw_max)
                 * and arbitrated interframe space (aifs)...
                 */
                ath5k_hw_reg_write(ah,
                        AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
                        AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
                        AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
                                AR5K_DCU_LCL_IFS_AIFS),
                        AR5K_QUEUE_DFS_LOCAL_IFS(queue));

                /*
                 * Set misc registers
                 */
                /* Enable DCU early termination for this queue */
                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                        AR5K_QCU_MISC_DCU_EARLY);

                /* Enable DCU to wait for next fragment from QCU */
                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
                                        AR5K_DCU_MISC_FRAG_WAIT);

                /* On Maui and Spirit use the global seqnum on DCU */
                if (ah->ah_mac_version < AR5K_SREV_AR5211)
                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
                                                AR5K_DCU_MISC_SEQNUM_CTL);

                if (tq->tqi_cbr_period) {
                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
                                AR5K_QCU_CBRCFG_INTVAL) |
                                AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
                                AR5K_QCU_CBRCFG_ORN_THRES),
                                AR5K_QUEUE_CBRCFG(queue));
                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                AR5K_QCU_MISC_FRSHED_CBR);
                        if (tq->tqi_cbr_overflow_limit)
                                AR5K_REG_ENABLE_BITS(ah,
                                        AR5K_QUEUE_MISC(queue),
                                        AR5K_QCU_MISC_CBR_THRES_ENABLE);
                }

                if (tq->tqi_ready_time &&
                (tq->tqi_type != AR5K_TX_QUEUE_CAB))
                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
                                AR5K_QCU_RDYTIMECFG_INTVAL) |
                                AR5K_QCU_RDYTIMECFG_ENABLE,
                                AR5K_QUEUE_RDYTIMECFG(queue));

                if (tq->tqi_burst_time) {
                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
                                AR5K_DCU_CHAN_TIME_DUR) |
                                AR5K_DCU_CHAN_TIME_ENABLE,
                                AR5K_QUEUE_DFS_CHANNEL_TIME(queue));

                        if (tq->tqi_flags
                        & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
                                AR5K_REG_ENABLE_BITS(ah,
                                        AR5K_QUEUE_MISC(queue),
                                        AR5K_QCU_MISC_RDY_VEOL_POLICY);
                }

                if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
                                AR5K_QUEUE_DFS_MISC(queue));

                if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
                                AR5K_QUEUE_DFS_MISC(queue));

                /* TODO: Handle frame compression */

                /*
                 * Enable interrupts for this tx queue
                 * in the secondary interrupt mask registers
                 */
                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);

                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);

                /* Update secondary interrupt mask registers */

                /* Filter out inactive queues */
                ah->ah_txq_imr_txok &= ah->ah_txq_status;
                ah->ah_txq_imr_txerr &= ah->ah_txq_status;
                ah->ah_txq_imr_txurn &= ah->ah_txq_status;
                ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
                ah->ah_txq_imr_txeol &= ah->ah_txq_status;
                ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
                ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
                ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
                ah->ah_txq_imr_nofrm &= ah->ah_txq_status;

                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
                        AR5K_SIMR0_QCU_TXOK) |
                        AR5K_REG_SM(ah->ah_txq_imr_txdesc,
                        AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
                        AR5K_SIMR1_QCU_TXERR) |
                        AR5K_REG_SM(ah->ah_txq_imr_txeol,
                        AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
                /* Update simr2 but don't overwrite rest simr2 settings */
                AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
                AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
                        AR5K_REG_SM(ah->ah_txq_imr_txurn,
                        AR5K_SIMR2_QCU_TXURN));
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
                        AR5K_SIMR3_QCBRORN) |
                        AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
                        AR5K_SIMR3_QCBRURN), AR5K_SIMR3);
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
                        AR5K_SIMR4_QTRIG), AR5K_SIMR4);
                /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
                        AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
                /* No queue has TXNOFRM enabled, disable the interrupt
                 * by setting AR5K_TXNOFRM to zero */
                if (ah->ah_txq_imr_nofrm == 0)
                        ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);

                /* Set QCU mask for this DCU to save power */
                AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
        }

        return 0;
}
int ath5k_hw_set_slot_time ( struct ath5k_hw ah,
unsigned int  slot_time 
)

Definition at line 377 of file ath5k_qcu.c.

References ath5k_hw::ah_turbo, ath5k_hw::ah_version, AR5K_AR5210, AR5K_DCU_GBL_IFS_SLOT, AR5K_SLOT_TIME, AR5K_SLOT_TIME_MAX, ath5k_hw_htoclock(), ath5k_hw_reg_write(), and EINVAL.

{
        if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
                return -EINVAL;

        if (ah->ah_version == AR5K_AR5210)
                ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
                                ah->ah_turbo), AR5K_SLOT_TIME);
        else
                ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);

        return 0;
}