iPXE
ath9k.c
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #include <ipxe/pci.h>
00021 
00022 #include "ath9k.h"
00023 
00024 static struct pci_device_id ath_pci_id_table[] = {
00025         PCI_ROM(0x168c, 0x0023, "ar5416", "Atheros 5416 PCI", 0),       /* PCI   */
00026         PCI_ROM(0x168c, 0x0024, "ar5416", "Atheros 5416 PCI-E", 0),     /* PCI-E */
00027         PCI_ROM(0x168c, 0x0027, "ar9160", "Atheros 9160 PCI", 0),       /* PCI   */
00028         PCI_ROM(0x168c, 0x0029, "ar9280", "Atheros 9280 PCI", 0),       /* PCI   */
00029         PCI_ROM(0x168c, 0x002A, "ar9280", "Atheros 9280 PCI-E", 0),     /* PCI-E */
00030         PCI_ROM(0x168c, 0x002B, "ar9285", "Atheros 9285 PCI-E", 0),     /* PCI-E */
00031         PCI_ROM(0x168c, 0x002C, "ar2427", "Atheros 2427 PCI-E", 0),     /* PCI-E 802.11n bonded out */
00032         PCI_ROM(0x168c, 0x002D, "ar9287", "Atheros 9287 PCI", 0),       /* PCI   */
00033         PCI_ROM(0x168c, 0x002E, "ar9287", "Atheros 9287 PCI-E", 0),     /* PCI-E */
00034         PCI_ROM(0x168c, 0x0030, "ar9300", "Atheros 9300 PCI-E", 0),     /* PCI-E  AR9300 */
00035         PCI_ROM(0x168c, 0x0032, "ar9485", "Atheros 9485 PCI-E", 0),     /* PCI-E  AR9485 */
00036 };
00037 
00038 
00039 /* return bus cachesize in 4B word units */
00040 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
00041 {
00042         struct ath_softc *sc = (struct ath_softc *) common->priv;
00043         u8 u8tmp;
00044 
00045         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
00046         *csz = (int)u8tmp;
00047 
00048         /*
00049          * This check was put in to avoid "unpleasant" consequences if
00050          * the bootrom has not fully initialized all PCI devices.
00051          * Sometimes the cache line size register is not set
00052          */
00053 
00054         if (*csz == 0)
00055                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
00056 }
00057 
00058 static int ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
00059 {
00060         struct ath_hw *ah = (struct ath_hw *) common->ah;
00061 
00062         common->ops->read(ah, AR5416_EEPROM_OFFSET +
00063                               (off << AR5416_EEPROM_S));
00064 
00065         if (!ath9k_hw_wait(ah,
00066                            AR_EEPROM_STATUS_DATA,
00067                            AR_EEPROM_STATUS_DATA_BUSY |
00068                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
00069                            AH_WAIT_TIMEOUT)) {
00070                 return 0;
00071         }
00072 
00073         *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
00074                    AR_EEPROM_STATUS_DATA_VAL);
00075 
00076         return 1;
00077 }
00078 
00079 static void ath_pci_extn_synch_enable(struct ath_common *common)
00080 {
00081         struct ath_softc *sc = (struct ath_softc *) common->priv;
00082         struct pci_device *pdev = sc->pdev;
00083         u8 lnkctl;
00084 
00085         pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
00086         lnkctl |= 0x0080;
00087         pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
00088 }
00089 
00090 static const struct ath_bus_ops ath_pci_bus_ops = {
00091         .ath_bus_type = ATH_PCI,
00092         .read_cachesize = ath_pci_read_cachesize,
00093         .eeprom_read = ath_pci_eeprom_read,
00094         .extn_synch_en = ath_pci_extn_synch_enable,
00095 };
00096 
00097 static int ath_pci_probe(struct pci_device *pdev)
00098 {
00099         void *mem;
00100         struct ath_softc *sc;
00101         struct net80211_device *dev;
00102         u8 csz;
00103         u16 subsysid;
00104         u32 val;
00105         int ret = 0;
00106         char hw_name[64];
00107 
00108         adjust_pci_device(pdev);
00109 
00110         /*
00111          * Cache line size is used to size and align various
00112          * structures used to communicate with the hardware.
00113          */
00114         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
00115         if (csz == 0) {
00116                 /*
00117                  * Linux 2.4.18 (at least) writes the cache line size
00118                  * register as a 16-bit wide register which is wrong.
00119                  * We must have this setup properly for rx buffer
00120                  * DMA to work so force a reasonable value here if it
00121                  * comes up zero.
00122                  */
00123                 csz =16;
00124                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
00125         }
00126         /*
00127          * The default setting of latency timer yields poor results,
00128          * set it to the value used by other systems. It may be worth
00129          * tweaking this setting more.
00130          */
00131         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
00132 
00133         /*
00134          * Disable the RETRY_TIMEOUT register (0x41) to keep
00135          * PCI Tx retries from interfering with C3 CPU state.
00136          */
00137         pci_read_config_dword(pdev, 0x40, &val);
00138         if ((val & 0x0000ff00) != 0)
00139                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
00140 
00141         mem = ioremap(pdev->membase, 0x10000);
00142         if (!mem) {
00143                 DBG("ath9K: PCI memory map error\n") ;
00144                 ret = -EIO;
00145                 goto err_iomap;
00146         }
00147 
00148         dev = net80211_alloc(sizeof(struct ath_softc));
00149         if (!dev) {
00150                 DBG("ath9k: No memory for net80211_device\n");
00151                 ret = -ENOMEM;
00152                 goto err_alloc_hw;
00153         }
00154 
00155         pci_set_drvdata(pdev, dev);
00156         dev->netdev->dev = (struct device *)pdev;
00157 
00158         sc = dev->priv;
00159         sc->dev = dev;
00160         sc->pdev = pdev;
00161         sc->mem = mem;
00162 
00163         /* Will be cleared in ath9k_start() */
00164         sc->sc_flags |= SC_OP_INVALID;
00165 
00166         sc->irq = pdev->irq;
00167 
00168         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
00169         ret = ath9k_init_device(pdev->device, sc, subsysid, &ath_pci_bus_ops);
00170         if (ret) {
00171                 DBG("ath9k: Failed to initialize device\n");
00172                 goto err_init;
00173         }
00174 
00175         ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
00176         DBG("ath9k: %s mem=0x%lx, irq=%d\n",
00177                    hw_name, (unsigned long)mem, pdev->irq);
00178 
00179         return 0;
00180 
00181 err_init:
00182         net80211_free(dev);
00183 err_alloc_hw:
00184         iounmap(mem);
00185 err_iomap:
00186         return ret;
00187 }
00188 
00189 static void ath_pci_remove(struct pci_device *pdev)
00190 {
00191         struct net80211_device *dev = pci_get_drvdata(pdev);
00192         struct ath_softc *sc = dev->priv;
00193         void *mem = sc->mem;
00194 
00195         if (!is_ath9k_unloaded)
00196                 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
00197         ath9k_deinit_device(sc);
00198         net80211_free(sc->dev);
00199 
00200         iounmap(mem);
00201 }
00202 
00203 struct pci_driver ath_pci_driver __pci_driver = {
00204         .id_count   = ARRAY_SIZE(ath_pci_id_table),
00205         .ids        = ath_pci_id_table,
00206         .probe      = ath_pci_probe,
00207         .remove     = ath_pci_remove,
00208 };