iPXE
ath9k.h
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #ifndef ATH9K_H
00021 #define ATH9K_H
00022 
00023 FILE_LICENCE ( BSD2 );
00024 
00025 #include "common.h"
00026 
00027 /*
00028  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
00029  * should rely on this file or its contents.
00030  */
00031 
00032 struct ath_node;
00033 struct ath_softc;
00034 
00035 /* Macro to expand scalars to 64-bit objects */
00036 
00037 #define ito64(x) (sizeof(x) == 1) ?                     \
00038         (((unsigned long long int)(x)) & (0xff)) :      \
00039         (sizeof(x) == 2) ?                              \
00040         (((unsigned long long int)(x)) & 0xffff) :      \
00041         ((sizeof(x) == 4) ?                             \
00042          (((unsigned long long int)(x)) & 0xffffffff) : \
00043          (unsigned long long int)(x))
00044 
00045 /* increment with wrap-around */
00046 #define INCR(_l, _sz)   do {                    \
00047                 (_l)++;                         \
00048                 (_l) &= ((_sz) - 1);            \
00049         } while (0)
00050 
00051 /* decrement with wrap-around */
00052 #define DECR(_l,  _sz)  do {                    \
00053                 (_l)--;                         \
00054                 (_l) &= ((_sz) - 1);            \
00055         } while (0)
00056 
00057 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
00058 
00059 #define TSF_TO_TU(_h,_l) \
00060         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
00061 
00062 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
00063 
00064 struct ath_config {
00065         u16 txpowlimit;
00066         u8 cabqReadytime;
00067 };
00068 
00069 /*************************/
00070 /* Descriptor Management */
00071 /*************************/
00072 
00073 #define ATH_TXBUF_RESET(_bf) do {                               \
00074                 (_bf)->bf_stale = 0;                    \
00075                 (_bf)->bf_lastbf = NULL;                        \
00076                 (_bf)->bf_next = NULL;                          \
00077                 memset(&((_bf)->bf_state), 0,                   \
00078                        sizeof(struct ath_buf_state));           \
00079         } while (0)
00080 
00081 #define ATH_RXBUF_RESET(_bf) do {               \
00082                 (_bf)->bf_stale = 0;    \
00083         } while (0)
00084 
00085 /**
00086  * enum buffer_type - Buffer type flags
00087  *
00088  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
00089  * @BUF_AGGR: Indicates whether the buffer can be aggregated
00090  *      (used in aggregation scheduling)
00091  * @BUF_XRETRY: To denote excessive retries of the buffer
00092  */
00093 enum buffer_type {
00094         BUF_AMPDU               = BIT(0),
00095         BUF_AGGR                = BIT(1),
00096         BUF_XRETRY              = BIT(2),
00097 };
00098 
00099 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
00100 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
00101 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
00102 
00103 #define ATH_TXSTATUS_RING_SIZE 64
00104 
00105 struct ath_descdma {
00106         void *dd_desc;
00107         u32 dd_desc_paddr;
00108         u32 dd_desc_len;
00109         struct ath_buf *dd_bufptr;
00110 };
00111 
00112 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
00113                       struct list_head *head, const char *name,
00114                       int nbuf, int ndesc, int is_tx);
00115 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
00116                          struct list_head *head);
00117 
00118 /***********/
00119 /* RX / TX */
00120 /***********/
00121 
00122 #define ATH_RXBUF               16
00123 #define ATH_TXBUF               16
00124 #define ATH_TXBUF_RESERVE       5
00125 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
00126 #define ATH_TXMAXTRY            13
00127 
00128 #define TID_TO_WME_AC(_tid)                             \
00129         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
00130          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
00131          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
00132          WME_AC_VO)
00133 
00134 #define ATH_AGGR_DELIM_SZ          4
00135 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
00136 /* number of delimiters for encryption padding */
00137 #define ATH_AGGR_ENCRYPTDELIM      10
00138 /* minimum h/w qdepth to be sustained to maximize aggregation */
00139 #define ATH_AGGR_MIN_QDEPTH        2
00140 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
00141 
00142 #define FCS_LEN                    4
00143 #define IEEE80211_SEQ_SEQ_SHIFT    4
00144 #define IEEE80211_SEQ_MAX          4096
00145 #define IEEE80211_WEP_IVLEN        3
00146 #define IEEE80211_WEP_KIDLEN       1
00147 #define IEEE80211_WEP_CRCLEN       4
00148 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
00149                                     (IEEE80211_WEP_IVLEN +      \
00150                                      IEEE80211_WEP_KIDLEN +     \
00151                                      IEEE80211_WEP_CRCLEN))
00152 
00153 /* return whether a bit at index _n in bitmap _bm is set
00154  * _sz is the size of the bitmap  */
00155 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
00156                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
00157 
00158 /* return block-ack bitmap index given sequence and starting sequence */
00159 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
00160 
00161 /* returns delimiter padding required given the packet length */
00162 #define ATH_AGGR_GET_NDELIM(_len)                                       \
00163        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
00164         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
00165 
00166 #define BAW_WITHIN(_start, _bawsz, _seqno) \
00167         ((((_seqno) - (_start)) & 4095) < (_bawsz))
00168 
00169 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
00170 
00171 #define ATH_TX_COMPLETE_POLL_INT        1000
00172 
00173 enum ATH_AGGR_STATUS {
00174         ATH_AGGR_DONE,
00175         ATH_AGGR_BAW_CLOSED,
00176         ATH_AGGR_LIMITED,
00177 };
00178 
00179 #define ATH_TXFIFO_DEPTH 8
00180 struct ath_txq {
00181         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
00182         u32 axq_qnum; /* ath9k hardware queue number */
00183         u32 *axq_link;
00184         struct list_head axq_q;
00185         u32 axq_depth;
00186         u32 axq_ampdu_depth;
00187         int stopped;
00188         int axq_tx_inprogress;
00189         struct list_head axq_acq;
00190         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
00191         struct list_head txq_fifo_pending;
00192         u8 txq_headidx;
00193         u8 txq_tailidx;
00194         int pending_frames;
00195 };
00196 
00197 struct ath_atx_ac {
00198         struct ath_txq *txq;
00199         int sched;
00200         struct list_head list;
00201         struct list_head tid_q;
00202         int clear_ps_filter;
00203 };
00204 
00205 struct ath_frame_info {
00206         int framelen;
00207         u32 keyix;
00208         enum ath9k_key_type keytype;
00209         u8 retries;
00210         u16 seqno;
00211 };
00212 
00213 struct ath_buf_state {
00214         u8 bf_type;
00215         u8 bfs_paprd;
00216         unsigned long bfs_paprd_timestamp;
00217 };
00218 
00219 struct ath_buf {
00220         struct list_head list;
00221         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
00222                                            an aggregate) */
00223         struct ath_buf *bf_next;        /* next subframe in the aggregate */
00224         struct io_buffer *bf_mpdu;      /* enclosing frame structure */
00225         void *bf_desc;                  /* virtual addr of desc */
00226         u32 bf_daddr;                   /* physical addr of desc */
00227         u32 bf_buf_addr;                /* physical addr of data buffer, for DMA */
00228         int bf_stale;
00229         u16 bf_flags;
00230         struct ath_buf_state bf_state;
00231 };
00232 
00233 struct ath_atx_tid {
00234         struct list_head list;
00235         struct list_head buf_q;
00236         struct ath_node *an;
00237         struct ath_atx_ac *ac;
00238         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
00239         u16 seq_start;
00240         u16 seq_next;
00241         u16 baw_size;
00242         int tidno;
00243         int baw_head;   /* first un-acked tx buffer */
00244         int baw_tail;   /* next unused tx buffer slot */
00245         int sched;
00246         int paused;
00247         u8 state;
00248 };
00249 
00250 struct ath_node {
00251         struct ath_atx_tid tid[WME_NUM_TID];
00252         struct ath_atx_ac ac[WME_NUM_AC];
00253         int ps_key;
00254 
00255         u16 maxampdu;
00256         u8 mpdudensity;
00257 
00258         int sleeping;
00259 };
00260 
00261 #define AGGR_CLEANUP         BIT(1)
00262 #define AGGR_ADDBA_COMPLETE  BIT(2)
00263 #define AGGR_ADDBA_PROGRESS  BIT(3)
00264 
00265 struct ath_tx_control {
00266         struct ath_txq *txq;
00267         struct ath_node *an;
00268         int if_id;
00269         u8 paprd;
00270 };
00271 
00272 #define ATH_TX_ERROR        0x01
00273 #define ATH_TX_XRETRY       0x02
00274 #define ATH_TX_BAR          0x04
00275 
00276 /**
00277  * @txq_map:  Index is mac80211 queue number.  This is
00278  *  not necessarily the same as the hardware queue number
00279  *  (axq_qnum).
00280  */
00281 struct ath_tx {
00282         u16 seq_no;
00283         u32 txqsetup;
00284         struct list_head txbuf;
00285         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
00286         struct ath_descdma txdma;
00287         struct ath_txq *txq_map[WME_NUM_AC];
00288 };
00289 
00290 struct ath_rx_edma {
00291         struct list_head rx_fifo;
00292         struct list_head rx_buffers;
00293         u32 rx_fifo_hwsize;
00294 };
00295 
00296 struct ath_rx {
00297         u8 defant;
00298         u8 rxotherant;
00299         u32 *rxlink;
00300         unsigned int rxfilter;
00301         struct list_head rxbuf;
00302         struct ath_descdma rxdma;
00303         struct ath_buf *rx_bufptr;
00304         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
00305 
00306         struct io_buffer *frag;
00307 };
00308 
00309 int ath_startrecv(struct ath_softc *sc);
00310 int ath_stoprecv(struct ath_softc *sc);
00311 void ath_flushrecv(struct ath_softc *sc);
00312 u32 ath_calcrxfilter(struct ath_softc *sc);
00313 int ath_rx_init(struct ath_softc *sc, int nbufs);
00314 void ath_rx_cleanup(struct ath_softc *sc);
00315 int ath_rx_tasklet(struct ath_softc *sc, int flush, int hp);
00316 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
00317 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
00318 int ath_drain_all_txq(struct ath_softc *sc, int retry_tx);
00319 void ath_draintxq(struct ath_softc *sc,
00320                      struct ath_txq *txq, int retry_tx);
00321 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
00322 int ath_tx_init(struct ath_softc *sc, int nbufs);
00323 void ath_tx_cleanup(struct ath_softc *sc);
00324 int ath_txq_update(struct ath_softc *sc, int qnum,
00325                    struct ath9k_tx_queue_info *q);
00326 int ath_tx_start(struct net80211_device *dev, struct io_buffer *iob,
00327                  struct ath_tx_control *txctl);
00328 void ath_tx_tasklet(struct ath_softc *sc);
00329 
00330 /*******/
00331 /* ANI */
00332 /*******/
00333 
00334 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
00335 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
00336 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
00337 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
00338 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
00339 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
00340 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
00341 
00342 void ath_hw_pll_work(struct ath_softc *sc);
00343 void ath_ani_calibrate(struct ath_softc *sc);
00344 
00345 /********************/
00346 /* Main driver core */
00347 /********************/
00348 
00349 /*
00350  * Default cache line size, in bytes.
00351  * Used when PCI device not fully initialized by bootrom/BIOS
00352 */
00353 #define DEFAULT_CACHELINE       32
00354 #define ATH_REGCLASSIDS_MAX     10
00355 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
00356 #define ATH_MAX_SW_RETRIES      10
00357 #define ATH_CHAN_MAX            255
00358 
00359 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
00360 #define ATH_RATE_DUMMY_MARKER   0
00361 
00362 #define SC_OP_INVALID                BIT(0)
00363 #define SC_OP_BEACONS                BIT(1)
00364 #define SC_OP_RXAGGR                 BIT(2)
00365 #define SC_OP_TXAGGR                 BIT(3)
00366 #define SC_OP_OFFCHANNEL             BIT(4)
00367 #define SC_OP_PREAMBLE_SHORT         BIT(5)
00368 #define SC_OP_PROTECT_ENABLE         BIT(6)
00369 #define SC_OP_RXFLUSH                BIT(7)
00370 #define SC_OP_LED_ASSOCIATED         BIT(8)
00371 #define SC_OP_LED_ON                 BIT(9)
00372 #define SC_OP_TSF_RESET              BIT(11)
00373 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
00374 #define SC_OP_BT_SCAN                BIT(13)
00375 #define SC_OP_ANI_RUN                BIT(14)
00376 #define SC_OP_ENABLE_APM             BIT(15)
00377 #define SC_OP_PRIM_STA_VIF           BIT(16)
00378 
00379 /* Powersave flags */
00380 #define PS_WAIT_FOR_BEACON        BIT(0)
00381 #define PS_WAIT_FOR_CAB           BIT(1)
00382 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
00383 #define PS_WAIT_FOR_TX_ACK        BIT(3)
00384 #define PS_BEACON_SYNC            BIT(4)
00385 #define PS_TSFOOR_SYNC            BIT(5)
00386 
00387 struct ath_rate_table;
00388 
00389 struct ath9k_legacy_rate {
00390         u16 bitrate;
00391         u32 flags;
00392         u16 hw_value;
00393         u16 hw_value_short;
00394 };
00395 
00396 enum ath9k_rate_control_flags {
00397         IEEE80211_TX_RC_USE_RTS_CTS             = BIT(0),
00398         IEEE80211_TX_RC_USE_CTS_PROTECT         = BIT(1),
00399         IEEE80211_TX_RC_USE_SHORT_PREAMBLE      = BIT(2),
00400 
00401         /* rate index is an MCS rate number instead of an index */
00402         IEEE80211_TX_RC_MCS                     = BIT(3),
00403         IEEE80211_TX_RC_GREEN_FIELD             = BIT(4),
00404         IEEE80211_TX_RC_40_MHZ_WIDTH            = BIT(5),
00405         IEEE80211_TX_RC_DUP_DATA                = BIT(6),
00406         IEEE80211_TX_RC_SHORT_GI                = BIT(7),
00407 };
00408 
00409 struct survey_info {
00410         struct net80211_channel *channel;
00411         u64 channel_time;
00412         u64 channel_time_busy;
00413         u64 channel_time_ext_busy;
00414         u64 channel_time_rx;
00415         u64 channel_time_tx;
00416         u32 filled;
00417         s8 noise;
00418 };
00419 
00420 enum survey_info_flags {
00421         SURVEY_INFO_NOISE_DBM = 1<<0,
00422         SURVEY_INFO_IN_USE = 1<<1,
00423         SURVEY_INFO_CHANNEL_TIME = 1<<2,
00424         SURVEY_INFO_CHANNEL_TIME_BUSY = 1<<3,
00425         SURVEY_INFO_CHANNEL_TIME_EXT_BUSY = 1<<4,
00426         SURVEY_INFO_CHANNEL_TIME_RX = 1<<5,
00427         SURVEY_INFO_CHANNEL_TIME_TX = 1<<6,
00428 };
00429 
00430 struct ath9k_vif_iter_data {
00431         const u8 *hw_macaddr; /* phy's hardware address, set
00432                                * before starting iteration for
00433                                * valid bssid mask.
00434                                */
00435         u8 mask[ETH_ALEN]; /* bssid mask */
00436         int naps;      /* number of AP vifs */
00437         int nmeshes;   /* number of mesh vifs */
00438         int nstations; /* number of station vifs */
00439         int nwds;      /* number of nwd vifs */
00440         int nadhocs;   /* number of adhoc vifs */
00441         int nothers;   /* number of vifs not specified above. */
00442 };
00443 
00444 struct ath_softc {
00445         struct net80211_device *dev;
00446         struct pci_device *pdev;
00447 
00448         int chan_idx;
00449         int chan_is_ht;
00450         struct survey_info *cur_survey;
00451         struct survey_info survey[ATH9K_NUM_CHANNELS];
00452 
00453         void (*intr_tq)(struct ath_softc *sc);
00454         struct ath_hw *sc_ah;
00455         void *mem;
00456         int irq;
00457 
00458         void (*paprd_work)(struct ath_softc *sc);
00459         void (*hw_check_work)(struct ath_softc *sc);
00460         void (*paprd_complete)(struct ath_softc *sc);
00461 
00462         unsigned int hw_busy_count;
00463 
00464         u32 intrstatus;
00465         u32 sc_flags; /* SC_OP_* */
00466         u16 ps_flags; /* PS_* */
00467         u16 curtxpow;
00468         int ps_enabled;
00469         int ps_idle;
00470         short nbcnvifs;
00471         short nvifs;
00472         unsigned long ps_usecount;
00473 
00474         struct ath_config config;
00475         struct ath_rx rx;
00476         struct ath_tx tx;
00477         struct net80211_hw_info *hwinfo;
00478         struct ath9k_legacy_rate rates[NET80211_MAX_RATES];
00479         int hw_rix;
00480 
00481         struct ath9k_hw_cal_data caldata;
00482         int last_rssi;
00483 
00484         void (*tx_complete_work)(struct ath_softc *sc);
00485         unsigned long tx_complete_work_timer;
00486         void (*hw_pll_work)(struct ath_softc *sc);
00487         unsigned long hw_pll_work_timer;
00488 
00489         struct ath_descdma txsdma;
00490 };
00491 
00492 void ath9k_tasklet(struct ath_softc *sc);
00493 int ath_reset(struct ath_softc *sc, int retry_tx);
00494 
00495 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
00496 {
00497         common->bus_ops->read_cachesize(common, csz);
00498 }
00499 
00500 extern struct net80211_device_operations ath9k_ops;
00501 extern int ath9k_modparam_nohwcrypt;
00502 extern int is_ath9k_unloaded;
00503 
00504 void ath_isr(struct net80211_device *dev);
00505 void ath9k_init_crypto(struct ath_softc *sc);
00506 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
00507                     const struct ath_bus_ops *bus_ops);
00508 void ath9k_deinit_device(struct ath_softc *sc);
00509 void ath9k_set_hw_capab(struct ath_softc *sc, struct net80211_device *dev);
00510 int ath_set_channel(struct ath_softc *sc, struct net80211_device *dev,
00511                     struct ath9k_channel *hchan);
00512 
00513 void ath_radio_enable(struct ath_softc *sc, struct net80211_device *dev);
00514 void ath_radio_disable(struct ath_softc *sc, struct net80211_device *dev);
00515 int ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
00516 int ath9k_uses_beacons(int type);
00517 
00518 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
00519 
00520 void ath_start_rfkill_poll(struct ath_softc *sc);
00521 extern void ath9k_rfkill_poll_state(struct net80211_device *dev);
00522 
00523 #endif /* ATH9K_H */