iPXE
ath9k_ar5008_phy.c
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #include <ipxe/malloc.h>
00021 #include <ipxe/io.h>
00022 
00023 #include "hw.h"
00024 #include "hw-ops.h"
00025 #include "../regd.h"
00026 #include "ar9002_phy.h"
00027 
00028 /* All code below is for AR5008, AR9001, AR9002 */
00029 
00030 static const int firstep_table[] =
00031 /* level:  0   1   2   3   4   5   6   7   8  */
00032         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
00033 
00034 static const int cycpwrThr1_table[] =
00035 /* level:  0   1   2   3   4   5   6   7   8  */
00036         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
00037 
00038 /*
00039  * register values to turn OFDM weak signal detection OFF
00040  */
00041 static const int m1ThreshLow_off = 127;
00042 static const int m2ThreshLow_off = 127;
00043 static const int m1Thresh_off = 127;
00044 static const int m2Thresh_off = 127;
00045 static const int m2CountThr_off =  31;
00046 static const int m2CountThrLow_off =  63;
00047 static const int m1ThreshLowExt_off = 127;
00048 static const int m2ThreshLowExt_off = 127;
00049 static const int m1ThreshExt_off = 127;
00050 static const int m2ThreshExt_off = 127;
00051 
00052 
00053 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
00054                                  int col)
00055 {
00056         unsigned int i;
00057 
00058         for (i = 0; i < array->ia_rows; i++)
00059                 bank[i] = INI_RA(array, i, col);
00060 }
00061 
00062 
00063 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
00064         ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
00065 
00066 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
00067                                   u32 *data, unsigned int *writecnt)
00068 {
00069         unsigned int r;
00070 
00071         ENABLE_REGWRITE_BUFFER(ah);
00072 
00073         for (r = 0; r < array->ia_rows; r++) {
00074                 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
00075                 DO_DELAY(*writecnt);
00076         }
00077 
00078         REGWRITE_BUFFER_FLUSH(ah);
00079 }
00080 
00081 /**
00082  * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
00083  * @rfbuf:
00084  * @reg32:
00085  * @numBits:
00086  * @firstBit:
00087  * @column:
00088  *
00089  * Performs analog "swizzling" of parameters into their location.
00090  * Used on external AR2133/AR5133 radios.
00091  */
00092 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
00093                                            u32 numBits, u32 firstBit,
00094                                            u32 column)
00095 {
00096         u32 tmp32, mask, arrayEntry, lastBit;
00097         int32_t bitPosition, bitsLeft;
00098 
00099         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
00100         arrayEntry = (firstBit - 1) / 8;
00101         bitPosition = (firstBit - 1) % 8;
00102         bitsLeft = numBits;
00103         while (bitsLeft > 0) {
00104                 lastBit = (bitPosition + bitsLeft > 8) ?
00105                     8 : bitPosition + bitsLeft;
00106                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
00107                     (column * 8);
00108                 rfBuf[arrayEntry] &= ~mask;
00109                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
00110                                       (column * 8)) & mask;
00111                 bitsLeft -= 8 - bitPosition;
00112                 tmp32 = tmp32 >> (8 - bitPosition);
00113                 bitPosition = 0;
00114                 arrayEntry++;
00115         }
00116 }
00117 
00118 /*
00119  * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
00120  * rf_pwd_icsyndiv.
00121  *
00122  * Theoretical Rules:
00123  *   if 2 GHz band
00124  *      if forceBiasAuto
00125  *         if synth_freq < 2412
00126  *            bias = 0
00127  *         else if 2412 <= synth_freq <= 2422
00128  *            bias = 1
00129  *         else // synth_freq > 2422
00130  *            bias = 2
00131  *      else if forceBias > 0
00132  *         bias = forceBias & 7
00133  *      else
00134  *         no change, use value from ini file
00135  *   else
00136  *      no change, invalid band
00137  *
00138  *  1st Mod:
00139  *    2422 also uses value of 2
00140  *    <approved>
00141  *
00142  *  2nd Mod:
00143  *    Less than 2412 uses value of 0, 2412 and above uses value of 2
00144  */
00145 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
00146 {
00147         u32 tmp_reg;
00148         unsigned int reg_writes = 0;
00149         u32 new_bias = 0;
00150 
00151         if (!AR_SREV_5416(ah) || synth_freq >= 3000)
00152                 return;
00153 
00154         if (synth_freq < 2412)
00155                 new_bias = 0;
00156         else if (synth_freq < 2422)
00157                 new_bias = 1;
00158         else
00159                 new_bias = 2;
00160 
00161         /* pre-reverse this field */
00162         tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
00163 
00164         DBG("ath9k: Force rf_pwd_icsyndiv to %1d on %4d\n",
00165                 new_bias, synth_freq);
00166 
00167         /* swizzle rf_pwd_icsyndiv */
00168         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
00169 
00170         /* write Bank 6 with new params */
00171         REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
00172 }
00173 
00174 /**
00175  * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
00176  * @ah: atheros hardware structure
00177  * @chan:
00178  *
00179  * For the external AR2133/AR5133 radios, takes the MHz channel value and set
00180  * the channel value. Assumes writes enabled to analog bus and bank6 register
00181  * cache in ah->analogBank6Data.
00182  */
00183 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
00184 {
00185         u32 channelSel = 0;
00186         u32 bModeSynth = 0;
00187         u32 aModeRefSel = 0;
00188         u32 reg32 = 0;
00189         u16 freq;
00190         struct chan_centers centers;
00191 
00192         ath9k_hw_get_channel_centers(ah, chan, &centers);
00193         freq = centers.synth_center;
00194 
00195         if (freq < 4800) {
00196                 u32 txctl;
00197 
00198                 if (((freq - 2192) % 5) == 0) {
00199                         channelSel = ((freq - 672) * 2 - 3040) / 10;
00200                         bModeSynth = 0;
00201                 } else if (((freq - 2224) % 5) == 0) {
00202                         channelSel = ((freq - 704) * 2 - 3040) / 10;
00203                         bModeSynth = 1;
00204                 } else {
00205                         DBG("ath9k: Invalid channel %d MHz\n", freq);
00206                         return -EINVAL;
00207                 }
00208 
00209                 channelSel = (channelSel << 2) & 0xff;
00210                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
00211 
00212                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
00213                 if (freq == 2484) {
00214 
00215                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
00216                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
00217                 } else {
00218                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
00219                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
00220                 }
00221 
00222         } else if ((freq % 20) == 0 && freq >= 5120) {
00223                 channelSel =
00224                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
00225                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
00226         } else if ((freq % 10) == 0) {
00227                 channelSel =
00228                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
00229                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
00230                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
00231                 else
00232                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
00233         } else if ((freq % 5) == 0) {
00234                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
00235                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
00236         } else {
00237                 DBG("ath9k: Invalid channel %d MHz\n", freq);
00238                 return -EINVAL;
00239         }
00240 
00241         ar5008_hw_force_bias(ah, freq);
00242 
00243         reg32 =
00244             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
00245             (1 << 5) | 0x1;
00246 
00247         REG_WRITE(ah, AR_PHY(0x37), reg32);
00248 
00249         ah->curchan = chan;
00250         ah->curchan_rad_index = -1;
00251 
00252         return 0;
00253 }
00254 
00255 /**
00256  * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
00257  * @ah: atheros hardware structure
00258  * @chan:
00259  *
00260  * For non single-chip solutions. Converts to baseband spur frequency given the
00261  * input channel frequency and compute register settings below.
00262  */
00263 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
00264                                     struct ath9k_channel *chan)
00265 {
00266         int bb_spur = AR_NO_SPUR;
00267         int bin, cur_bin;
00268         int spur_freq_sd;
00269         int spur_delta_phase;
00270         int denominator;
00271         int upper, lower, cur_vit_mask;
00272         int tmp, new;
00273         int i;
00274         static int pilot_mask_reg[4] = {
00275                 AR_PHY_TIMING7, AR_PHY_TIMING8,
00276                 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
00277         };
00278         static int chan_mask_reg[4] = {
00279                 AR_PHY_TIMING9, AR_PHY_TIMING10,
00280                 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
00281         };
00282         static int inc[4] = { 0, 100, 0, 0 };
00283 
00284         int8_t mask_m[123];
00285         int8_t mask_p[123];
00286         int8_t mask_amt;
00287         int tmp_mask;
00288         int cur_bb_spur;
00289         int is2GHz = IS_CHAN_2GHZ(chan);
00290 
00291         memset(&mask_m, 0, sizeof(int8_t) * 123);
00292         memset(&mask_p, 0, sizeof(int8_t) * 123);
00293 
00294         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
00295                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
00296                 if (AR_NO_SPUR == cur_bb_spur)
00297                         break;
00298                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
00299                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
00300                         bb_spur = cur_bb_spur;
00301                         break;
00302                 }
00303         }
00304 
00305         if (AR_NO_SPUR == bb_spur)
00306                 return;
00307 
00308         bin = bb_spur * 32;
00309 
00310         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
00311         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
00312                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
00313                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
00314                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
00315 
00316         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
00317 
00318         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
00319                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
00320                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
00321                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
00322                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
00323         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
00324 
00325         spur_delta_phase = ((bb_spur * 524288) / 100) &
00326                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
00327 
00328         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
00329         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
00330 
00331         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
00332                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
00333                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
00334         REG_WRITE(ah, AR_PHY_TIMING11, new);
00335 
00336         cur_bin = -6000;
00337         upper = bin + 100;
00338         lower = bin - 100;
00339 
00340         for (i = 0; i < 4; i++) {
00341                 int pilot_mask = 0;
00342                 int chan_mask = 0;
00343                 int bp = 0;
00344                 for (bp = 0; bp < 30; bp++) {
00345                         if ((cur_bin > lower) && (cur_bin < upper)) {
00346                                 pilot_mask = pilot_mask | 0x1 << bp;
00347                                 chan_mask = chan_mask | 0x1 << bp;
00348                         }
00349                         cur_bin += 100;
00350                 }
00351                 cur_bin += inc[i];
00352                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
00353                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
00354         }
00355 
00356         cur_vit_mask = 6100;
00357         upper = bin + 120;
00358         lower = bin - 120;
00359 
00360         for (i = 0; i < 123; i++) {
00361                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
00362 
00363                         /* workaround for gcc bug #37014 */
00364                         volatile int tmp_v = abs(cur_vit_mask - bin);
00365 
00366                         if (tmp_v < 75)
00367                                 mask_amt = 1;
00368                         else
00369                                 mask_amt = 0;
00370                         if (cur_vit_mask < 0)
00371                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
00372                         else
00373                                 mask_p[cur_vit_mask / 100] = mask_amt;
00374                 }
00375                 cur_vit_mask -= 100;
00376         }
00377 
00378         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
00379                 | (mask_m[48] << 26) | (mask_m[49] << 24)
00380                 | (mask_m[50] << 22) | (mask_m[51] << 20)
00381                 | (mask_m[52] << 18) | (mask_m[53] << 16)
00382                 | (mask_m[54] << 14) | (mask_m[55] << 12)
00383                 | (mask_m[56] << 10) | (mask_m[57] << 8)
00384                 | (mask_m[58] << 6) | (mask_m[59] << 4)
00385                 | (mask_m[60] << 2) | (mask_m[61] << 0);
00386         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
00387         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
00388 
00389         tmp_mask = (mask_m[31] << 28)
00390                 | (mask_m[32] << 26) | (mask_m[33] << 24)
00391                 | (mask_m[34] << 22) | (mask_m[35] << 20)
00392                 | (mask_m[36] << 18) | (mask_m[37] << 16)
00393                 | (mask_m[48] << 14) | (mask_m[39] << 12)
00394                 | (mask_m[40] << 10) | (mask_m[41] << 8)
00395                 | (mask_m[42] << 6) | (mask_m[43] << 4)
00396                 | (mask_m[44] << 2) | (mask_m[45] << 0);
00397         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
00398         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
00399 
00400         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
00401                 | (mask_m[18] << 26) | (mask_m[18] << 24)
00402                 | (mask_m[20] << 22) | (mask_m[20] << 20)
00403                 | (mask_m[22] << 18) | (mask_m[22] << 16)
00404                 | (mask_m[24] << 14) | (mask_m[24] << 12)
00405                 | (mask_m[25] << 10) | (mask_m[26] << 8)
00406                 | (mask_m[27] << 6) | (mask_m[28] << 4)
00407                 | (mask_m[29] << 2) | (mask_m[30] << 0);
00408         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
00409         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
00410 
00411         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
00412                 | (mask_m[2] << 26) | (mask_m[3] << 24)
00413                 | (mask_m[4] << 22) | (mask_m[5] << 20)
00414                 | (mask_m[6] << 18) | (mask_m[7] << 16)
00415                 | (mask_m[8] << 14) | (mask_m[9] << 12)
00416                 | (mask_m[10] << 10) | (mask_m[11] << 8)
00417                 | (mask_m[12] << 6) | (mask_m[13] << 4)
00418                 | (mask_m[14] << 2) | (mask_m[15] << 0);
00419         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
00420         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
00421 
00422         tmp_mask = (mask_p[15] << 28)
00423                 | (mask_p[14] << 26) | (mask_p[13] << 24)
00424                 | (mask_p[12] << 22) | (mask_p[11] << 20)
00425                 | (mask_p[10] << 18) | (mask_p[9] << 16)
00426                 | (mask_p[8] << 14) | (mask_p[7] << 12)
00427                 | (mask_p[6] << 10) | (mask_p[5] << 8)
00428                 | (mask_p[4] << 6) | (mask_p[3] << 4)
00429                 | (mask_p[2] << 2) | (mask_p[1] << 0);
00430         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
00431         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
00432 
00433         tmp_mask = (mask_p[30] << 28)
00434                 | (mask_p[29] << 26) | (mask_p[28] << 24)
00435                 | (mask_p[27] << 22) | (mask_p[26] << 20)
00436                 | (mask_p[25] << 18) | (mask_p[24] << 16)
00437                 | (mask_p[23] << 14) | (mask_p[22] << 12)
00438                 | (mask_p[21] << 10) | (mask_p[20] << 8)
00439                 | (mask_p[19] << 6) | (mask_p[18] << 4)
00440                 | (mask_p[17] << 2) | (mask_p[16] << 0);
00441         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
00442         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
00443 
00444         tmp_mask = (mask_p[45] << 28)
00445                 | (mask_p[44] << 26) | (mask_p[43] << 24)
00446                 | (mask_p[42] << 22) | (mask_p[41] << 20)
00447                 | (mask_p[40] << 18) | (mask_p[39] << 16)
00448                 | (mask_p[38] << 14) | (mask_p[37] << 12)
00449                 | (mask_p[36] << 10) | (mask_p[35] << 8)
00450                 | (mask_p[34] << 6) | (mask_p[33] << 4)
00451                 | (mask_p[32] << 2) | (mask_p[31] << 0);
00452         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
00453         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
00454 
00455         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
00456                 | (mask_p[59] << 26) | (mask_p[58] << 24)
00457                 | (mask_p[57] << 22) | (mask_p[56] << 20)
00458                 | (mask_p[55] << 18) | (mask_p[54] << 16)
00459                 | (mask_p[53] << 14) | (mask_p[52] << 12)
00460                 | (mask_p[51] << 10) | (mask_p[50] << 8)
00461                 | (mask_p[49] << 6) | (mask_p[48] << 4)
00462                 | (mask_p[47] << 2) | (mask_p[46] << 0);
00463         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
00464         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
00465 }
00466 
00467 /**
00468  * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
00469  * @ah: atheros hardware structure
00470  *
00471  * Only required for older devices with external AR2133/AR5133 radios.
00472  */
00473 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
00474 {
00475 #define ATH_ALLOC_BANK(bank, size) do { \
00476                 bank = zalloc((sizeof(u32) * size)); \
00477                 if (!bank) { \
00478                         DBG("ath9k: Cannot allocate RF banks\n"); \
00479                         return -ENOMEM; \
00480                 } \
00481         } while (0);
00482 
00483         ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
00484         ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
00485         ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
00486         ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
00487         ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
00488         ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
00489         ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
00490         ATH_ALLOC_BANK(ah->addac5416_21,
00491                        ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
00492         ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
00493 
00494         return 0;
00495 #undef ATH_ALLOC_BANK
00496 }
00497 
00498 
00499 /**
00500  * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
00501  * @ah: atheros hardware struture
00502  * For the external AR2133/AR5133 radios banks.
00503  */
00504 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
00505 {
00506 #define ATH_FREE_BANK(bank) do { \
00507                 free(bank); \
00508                 bank = NULL; \
00509         } while (0);
00510 
00511         ATH_FREE_BANK(ah->analogBank0Data);
00512         ATH_FREE_BANK(ah->analogBank1Data);
00513         ATH_FREE_BANK(ah->analogBank2Data);
00514         ATH_FREE_BANK(ah->analogBank3Data);
00515         ATH_FREE_BANK(ah->analogBank6Data);
00516         ATH_FREE_BANK(ah->analogBank6TPCData);
00517         ATH_FREE_BANK(ah->analogBank7Data);
00518         ATH_FREE_BANK(ah->addac5416_21);
00519         ATH_FREE_BANK(ah->bank6Temp);
00520 
00521 #undef ATH_FREE_BANK
00522 }
00523 
00524 /* *
00525  * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
00526  * @ah: atheros hardware structure
00527  * @chan:
00528  * @modesIndex:
00529  *
00530  * Used for the external AR2133/AR5133 radios.
00531  *
00532  * Reads the EEPROM header info from the device structure and programs
00533  * all rf registers. This routine requires access to the analog
00534  * rf device. This is not required for single-chip devices.
00535  */
00536 static int ar5008_hw_set_rf_regs(struct ath_hw *ah,
00537                                   struct ath9k_channel *chan,
00538                                   u16 modesIndex)
00539 {
00540         u32 eepMinorRev;
00541         u32 ob5GHz = 0, db5GHz = 0;
00542         u32 ob2GHz = 0, db2GHz = 0;
00543         unsigned int regWrites = 0;
00544 
00545         /*
00546          * Software does not need to program bank data
00547          * for single chip devices, that is AR9280 or anything
00548          * after that.
00549          */
00550         if (AR_SREV_9280_20_OR_LATER(ah))
00551                 return 1;
00552 
00553         /* Setup rf parameters */
00554         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
00555 
00556         /* Setup Bank 0 Write */
00557         ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
00558 
00559         /* Setup Bank 1 Write */
00560         ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
00561 
00562         /* Setup Bank 2 Write */
00563         ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
00564 
00565         /* Setup Bank 6 Write */
00566         ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
00567                       modesIndex);
00568         {
00569                 unsigned int i;
00570                 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
00571                         ah->analogBank6Data[i] =
00572                             INI_RA(&ah->iniBank6TPC, i, modesIndex);
00573                 }
00574         }
00575 
00576         /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
00577         if (eepMinorRev >= 2) {
00578                 if (IS_CHAN_2GHZ(chan)) {
00579                         ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
00580                         db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
00581                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
00582                                                        ob2GHz, 3, 197, 0);
00583                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
00584                                                        db2GHz, 3, 194, 0);
00585                 } else {
00586                         ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
00587                         db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
00588                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
00589                                                        ob5GHz, 3, 203, 0);
00590                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
00591                                                        db5GHz, 3, 200, 0);
00592                 }
00593         }
00594 
00595         /* Setup Bank 7 Setup */
00596         ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
00597 
00598         /* Write Analog registers */
00599         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
00600                            regWrites);
00601         REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
00602                            regWrites);
00603         REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
00604                            regWrites);
00605         REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
00606                            regWrites);
00607         REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
00608                            regWrites);
00609         REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
00610                            regWrites);
00611 
00612         return 1;
00613 }
00614 
00615 static void ar5008_hw_init_bb(struct ath_hw *ah,
00616                               struct ath9k_channel *chan)
00617 {
00618         u32 synthDelay;
00619 
00620         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
00621         if (IS_CHAN_B(chan))
00622                 synthDelay = (4 * synthDelay) / 22;
00623         else
00624                 synthDelay /= 10;
00625 
00626         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
00627 
00628         udelay(synthDelay + BASE_ACTIVATE_DELAY);
00629 }
00630 
00631 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
00632 {
00633         int rx_chainmask, tx_chainmask;
00634 
00635         rx_chainmask = ah->rxchainmask;
00636         tx_chainmask = ah->txchainmask;
00637 
00638 
00639         switch (rx_chainmask) {
00640         case 0x5:
00641                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
00642                             AR_PHY_SWAP_ALT_CHAIN);
00643                 /* Fall through */
00644         case 0x3:
00645                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
00646                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
00647                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
00648                         break;
00649                 }
00650                 /* Fall through */
00651         case 0x1:
00652         case 0x2:
00653         case 0x7:
00654                 ENABLE_REGWRITE_BUFFER(ah);
00655                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
00656                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
00657                 break;
00658         default:
00659                 ENABLE_REGWRITE_BUFFER(ah);
00660                 break;
00661         }
00662 
00663         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
00664 
00665         REGWRITE_BUFFER_FLUSH(ah);
00666 
00667         if (tx_chainmask == 0x5) {
00668                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
00669                             AR_PHY_SWAP_ALT_CHAIN);
00670         }
00671         if (AR_SREV_9100(ah))
00672                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
00673                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
00674 }
00675 
00676 static void ar5008_hw_override_ini(struct ath_hw *ah,
00677                                    struct ath9k_channel *chan __unused)
00678 {
00679         u32 val;
00680 
00681         /*
00682          * Set the RX_ABORT and RX_DIS and clear if off only after
00683          * RXE is set for MAC. This prevents frames with corrupted
00684          * descriptor status.
00685          */
00686         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
00687 
00688         if (AR_SREV_9280_20_OR_LATER(ah)) {
00689                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
00690 
00691                 if (!AR_SREV_9271(ah))
00692                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
00693 
00694                 if (AR_SREV_9287_11_OR_LATER(ah))
00695                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
00696 
00697                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
00698         }
00699 
00700         if (!AR_SREV_5416_20_OR_LATER(ah) ||
00701             AR_SREV_9280_20_OR_LATER(ah))
00702                 return;
00703         /*
00704          * Disable BB clock gating
00705          * Necessary to avoid issues on AR5416 2.0
00706          */
00707         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
00708 
00709         /*
00710          * Disable RIFS search on some chips to avoid baseband
00711          * hang issues.
00712          */
00713         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
00714                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
00715                 val &= ~AR_PHY_RIFS_INIT_DELAY;
00716                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
00717         }
00718 }
00719 
00720 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
00721                                        struct ath9k_channel *chan)
00722 {
00723         u32 phymode;
00724         u32 enableDacFifo = 0;
00725 
00726         if (AR_SREV_9285_12_OR_LATER(ah))
00727                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
00728                                          AR_PHY_FC_ENABLE_DAC_FIFO);
00729 
00730         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
00731                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
00732 
00733         if (IS_CHAN_HT40(chan)) {
00734                 phymode |= AR_PHY_FC_DYN2040_EN;
00735 
00736                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
00737                     (chan->chanmode == CHANNEL_G_HT40PLUS))
00738                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
00739 
00740         }
00741         REG_WRITE(ah, AR_PHY_TURBO, phymode);
00742 
00743         ath9k_hw_set11nmac2040(ah);
00744 
00745         ENABLE_REGWRITE_BUFFER(ah);
00746 
00747         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
00748         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
00749 
00750         REGWRITE_BUFFER_FLUSH(ah);
00751 }
00752 
00753 
00754 static int ar5008_hw_process_ini(struct ath_hw *ah,
00755                                  struct ath9k_channel *chan)
00756 {
00757         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
00758         struct ath_common *common = ath9k_hw_common(ah);
00759         unsigned int i, regWrites = 0;
00760         struct net80211_channel *channel = chan->chan;
00761         u32 modesIndex, freqIndex;
00762 
00763         switch (chan->chanmode) {
00764         case CHANNEL_A:
00765         case CHANNEL_A_HT20:
00766                 modesIndex = 1;
00767                 freqIndex = 1;
00768                 break;
00769         case CHANNEL_A_HT40PLUS:
00770         case CHANNEL_A_HT40MINUS:
00771                 modesIndex = 2;
00772                 freqIndex = 1;
00773                 break;
00774         case CHANNEL_G:
00775         case CHANNEL_G_HT20:
00776         case CHANNEL_B:
00777                 modesIndex = 4;
00778                 freqIndex = 2;
00779                 break;
00780         case CHANNEL_G_HT40PLUS:
00781         case CHANNEL_G_HT40MINUS:
00782                 modesIndex = 3;
00783                 freqIndex = 2;
00784                 break;
00785 
00786         default:
00787                 return -EINVAL;
00788         }
00789 
00790         /*
00791          * Set correct baseband to analog shift setting to
00792          * access analog chips.
00793          */
00794         REG_WRITE(ah, AR_PHY(0), 0x00000007);
00795 
00796         /* Write ADDAC shifts */
00797         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
00798         ah->eep_ops->set_addac(ah, chan);
00799 
00800         if (AR_SREV_5416_22_OR_LATER(ah)) {
00801                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
00802         } else {
00803                 struct ar5416IniArray temp;
00804                 u32 addacSize =
00805                         sizeof(u32) * ah->iniAddac.ia_rows *
00806                         ah->iniAddac.ia_columns;
00807 
00808                 /* For AR5416 2.0/2.1 */
00809                 memcpy(ah->addac5416_21,
00810                        ah->iniAddac.ia_array, addacSize);
00811 
00812                 /* override CLKDRV value at [row, column] = [31, 1] */
00813                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
00814 
00815                 temp.ia_array = ah->addac5416_21;
00816                 temp.ia_columns = ah->iniAddac.ia_columns;
00817                 temp.ia_rows = ah->iniAddac.ia_rows;
00818                 REG_WRITE_ARRAY(&temp, 1, regWrites);
00819         }
00820 
00821         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
00822 
00823         ENABLE_REGWRITE_BUFFER(ah);
00824 
00825         for (i = 0; i < ah->iniModes.ia_rows; i++) {
00826                 u32 reg = INI_RA(&ah->iniModes, i, 0);
00827                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
00828 
00829                 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
00830                         val &= ~AR_AN_TOP2_PWDCLKIND;
00831 
00832                 REG_WRITE(ah, reg, val);
00833 
00834                 if (reg >= 0x7800 && reg < 0x78a0
00835                     && ah->config.analog_shiftreg
00836                     && (common->bus_ops->ath_bus_type != ATH_USB)) {
00837                         udelay(100);
00838                 }
00839 
00840                 DO_DELAY(regWrites);
00841         }
00842 
00843         REGWRITE_BUFFER_FLUSH(ah);
00844 
00845         if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
00846                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
00847 
00848         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
00849             AR_SREV_9287_11_OR_LATER(ah))
00850                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
00851 
00852         if (AR_SREV_9271_10(ah))
00853                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
00854                                 modesIndex, regWrites);
00855 
00856         ENABLE_REGWRITE_BUFFER(ah);
00857 
00858         /* Write common array parameters */
00859         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
00860                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
00861                 u32 val = INI_RA(&ah->iniCommon, i, 1);
00862 
00863                 REG_WRITE(ah, reg, val);
00864 
00865                 if (reg >= 0x7800 && reg < 0x78a0
00866                     && ah->config.analog_shiftreg
00867                     && (common->bus_ops->ath_bus_type != ATH_USB)) {
00868                         udelay(100);
00869                 }
00870 
00871                 DO_DELAY(regWrites);
00872         }
00873 
00874         REGWRITE_BUFFER_FLUSH(ah);
00875 
00876         if (AR_SREV_9271(ah)) {
00877                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
00878                         REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
00879                                         modesIndex, regWrites);
00880                 else
00881                         REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
00882                                         modesIndex, regWrites);
00883         }
00884 
00885         REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
00886 
00887         if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
00888                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
00889                                 regWrites);
00890         }
00891 
00892         ar5008_hw_override_ini(ah, chan);
00893         ar5008_hw_set_channel_regs(ah, chan);
00894         ar5008_hw_init_chain_masks(ah);
00895         ath9k_olc_init(ah);
00896 
00897         /* Set TX power */
00898         ah->eep_ops->set_txpower(ah, chan,
00899                                  ath9k_regd_get_ctl(regulatory, chan),
00900                                  0,
00901                                  channel->maxpower * 2,
00902                                  min((u32) MAX_RATE_POWER,
00903                                  (u32) regulatory->power_limit), 0);
00904 
00905         /* Write analog registers */
00906         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
00907                 DBG("ath9k: ar5416SetRfRegs failed\n");
00908                 return -EIO;
00909         }
00910 
00911         return 0;
00912 }
00913 
00914 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
00915 {
00916         u32 rfMode = 0;
00917 
00918         if (chan == NULL)
00919                 return;
00920 
00921         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
00922                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
00923 
00924         if (!AR_SREV_9280_20_OR_LATER(ah))
00925                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
00926                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
00927 
00928         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
00929                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
00930 
00931         REG_WRITE(ah, AR_PHY_MODE, rfMode);
00932 }
00933 
00934 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
00935 {
00936         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
00937 }
00938 
00939 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
00940                                       struct ath9k_channel *chan)
00941 {
00942         u32 coef_scaled, ds_coef_exp, ds_coef_man;
00943         u32 clockMhzScaled = 0x64000000;
00944         struct chan_centers centers;
00945 
00946         if (IS_CHAN_HALF_RATE(chan))
00947                 clockMhzScaled = clockMhzScaled >> 1;
00948         else if (IS_CHAN_QUARTER_RATE(chan))
00949                 clockMhzScaled = clockMhzScaled >> 2;
00950 
00951         ath9k_hw_get_channel_centers(ah, chan, &centers);
00952         coef_scaled = clockMhzScaled / centers.synth_center;
00953 
00954         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
00955                                       &ds_coef_exp);
00956 
00957         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
00958                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
00959         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
00960                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
00961 
00962         coef_scaled = (9 * coef_scaled) / 10;
00963 
00964         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
00965                                       &ds_coef_exp);
00966 
00967         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
00968                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
00969         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
00970                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
00971 }
00972 
00973 static int ar5008_hw_rfbus_req(struct ath_hw *ah)
00974 {
00975         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
00976         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
00977                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
00978 }
00979 
00980 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
00981 {
00982         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
00983         if (IS_CHAN_B(ah->curchan))
00984                 synthDelay = (4 * synthDelay) / 22;
00985         else
00986                 synthDelay /= 10;
00987 
00988         udelay(synthDelay + BASE_ACTIVATE_DELAY);
00989 
00990         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
00991 }
00992 
00993 static void ar5008_restore_chainmask(struct ath_hw *ah)
00994 {
00995         int rx_chainmask = ah->rxchainmask;
00996 
00997         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
00998                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
00999                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
01000         }
01001 }
01002 
01003 static void ar5008_set_diversity(struct ath_hw *ah, int value)
01004 {
01005         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
01006         if (value)
01007                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
01008         else
01009                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
01010         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
01011 }
01012 
01013 static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah __unused,
01014                                          struct ath9k_channel *chan)
01015 {
01016         if (chan && IS_CHAN_5GHZ(chan))
01017                 return 0x1450;
01018         return 0x1458;
01019 }
01020 
01021 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah __unused,
01022                                          struct ath9k_channel *chan)
01023 {
01024         u32 pll;
01025 
01026         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
01027 
01028         if (chan && IS_CHAN_HALF_RATE(chan))
01029                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
01030         else if (chan && IS_CHAN_QUARTER_RATE(chan))
01031                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
01032 
01033         if (chan && IS_CHAN_5GHZ(chan))
01034                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
01035         else
01036                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
01037 
01038         return pll;
01039 }
01040 
01041 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah __unused,
01042                                          struct ath9k_channel *chan)
01043 {
01044         u32 pll;
01045 
01046         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
01047 
01048         if (chan && IS_CHAN_HALF_RATE(chan))
01049                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
01050         else if (chan && IS_CHAN_QUARTER_RATE(chan))
01051                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
01052 
01053         if (chan && IS_CHAN_5GHZ(chan))
01054                 pll |= SM(0xa, AR_RTC_PLL_DIV);
01055         else
01056                 pll |= SM(0xb, AR_RTC_PLL_DIV);
01057 
01058         return pll;
01059 }
01060 
01061 static int ar5008_hw_ani_control_old(struct ath_hw *ah,
01062                                       enum ath9k_ani_cmd cmd,
01063                                       int param)
01064 {
01065         struct ar5416AniState *aniState = &ah->curchan->ani;
01066 
01067         switch (cmd & ah->ani_function) {
01068         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
01069                 u32 level = param;
01070 
01071                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
01072                         DBG("ath9k: "
01073                                 "level out of range (%d > %zd)\n",
01074                                 level, ARRAY_SIZE(ah->totalSizeDesired));
01075                         return 0;
01076                 }
01077 
01078                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
01079                               AR_PHY_DESIRED_SZ_TOT_DES,
01080                               ah->totalSizeDesired[level]);
01081                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
01082                               AR_PHY_AGC_CTL1_COARSE_LOW,
01083                               ah->coarse_low[level]);
01084                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
01085                               AR_PHY_AGC_CTL1_COARSE_HIGH,
01086                               ah->coarse_high[level]);
01087                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
01088                               AR_PHY_FIND_SIG_FIRPWR,
01089                               ah->firpwr[level]);
01090 
01091                 if (level > aniState->noiseImmunityLevel)
01092                         ah->stats.ast_ani_niup++;
01093                 else if (level < aniState->noiseImmunityLevel)
01094                         ah->stats.ast_ani_nidown++;
01095                 aniState->noiseImmunityLevel = level;
01096                 break;
01097         }
01098         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
01099                 static const int m1ThreshLow[] = { 127, 50 };
01100                 static const int m2ThreshLow[] = { 127, 40 };
01101                 static const int m1Thresh[] = { 127, 0x4d };
01102                 static const int m2Thresh[] = { 127, 0x40 };
01103                 static const int m2CountThr[] = { 31, 16 };
01104                 static const int m2CountThrLow[] = { 63, 48 };
01105                 u32 on = param ? 1 : 0;
01106 
01107                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
01108                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
01109                               m1ThreshLow[on]);
01110                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
01111                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
01112                               m2ThreshLow[on]);
01113                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
01114                               AR_PHY_SFCORR_M1_THRESH,
01115                               m1Thresh[on]);
01116                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
01117                               AR_PHY_SFCORR_M2_THRESH,
01118                               m2Thresh[on]);
01119                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
01120                               AR_PHY_SFCORR_M2COUNT_THR,
01121                               m2CountThr[on]);
01122                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
01123                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
01124                               m2CountThrLow[on]);
01125 
01126                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01127                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
01128                               m1ThreshLow[on]);
01129                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01130                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
01131                               m2ThreshLow[on]);
01132                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01133                               AR_PHY_SFCORR_EXT_M1_THRESH,
01134                               m1Thresh[on]);
01135                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01136                               AR_PHY_SFCORR_EXT_M2_THRESH,
01137                               m2Thresh[on]);
01138 
01139                 if (on)
01140                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
01141                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
01142                 else
01143                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
01144                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
01145 
01146                 if (on != aniState->ofdmWeakSigDetect) {
01147                         if (on)
01148                                 ah->stats.ast_ani_ofdmon++;
01149                         else
01150                                 ah->stats.ast_ani_ofdmoff++;
01151                         aniState->ofdmWeakSigDetect = on;
01152                 }
01153                 break;
01154         }
01155         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
01156                 static const int weakSigThrCck[] = { 8, 6 };
01157                 u32 high = param ? 1 : 0;
01158 
01159                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
01160                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
01161                               weakSigThrCck[high]);
01162                 if (high != aniState->cckWeakSigThreshold) {
01163                         if (high)
01164                                 ah->stats.ast_ani_cckhigh++;
01165                         else
01166                                 ah->stats.ast_ani_ccklow++;
01167                         aniState->cckWeakSigThreshold = high;
01168                 }
01169                 break;
01170         }
01171         case ATH9K_ANI_FIRSTEP_LEVEL:{
01172                 static const int firstep[] = { 0, 4, 8 };
01173                 u32 level = param;
01174 
01175                 if (level >= ARRAY_SIZE(firstep)) {
01176                         DBG("ath9k: "
01177                                 "level out of range (%d > %zd)\n",
01178                                 level, ARRAY_SIZE(firstep));
01179                         return 0;
01180                 }
01181                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
01182                               AR_PHY_FIND_SIG_FIRSTEP,
01183                               firstep[level]);
01184                 if (level > aniState->firstepLevel)
01185                         ah->stats.ast_ani_stepup++;
01186                 else if (level < aniState->firstepLevel)
01187                         ah->stats.ast_ani_stepdown++;
01188                 aniState->firstepLevel = level;
01189                 break;
01190         }
01191         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
01192                 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
01193                 u32 level = param;
01194 
01195                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
01196                         DBG("ath9k: "
01197                                 "level out of range (%d > %zd)\n",
01198                                 level, ARRAY_SIZE(cycpwrThr1));
01199                         return 0;
01200                 }
01201                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
01202                               AR_PHY_TIMING5_CYCPWR_THR1,
01203                               cycpwrThr1[level]);
01204                 if (level > aniState->spurImmunityLevel)
01205                         ah->stats.ast_ani_spurup++;
01206                 else if (level < aniState->spurImmunityLevel)
01207                         ah->stats.ast_ani_spurdown++;
01208                 aniState->spurImmunityLevel = level;
01209                 break;
01210         }
01211         case ATH9K_ANI_PRESENT:
01212                 break;
01213         default:
01214                 DBG("ath9k: invalid cmd %d\n", cmd);
01215                 return 0;
01216         }
01217 
01218         DBG2("ath9k: ANI parameters:\n");
01219         DBG2(
01220                 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetect=%d\n",
01221                 aniState->noiseImmunityLevel,
01222                 aniState->spurImmunityLevel,
01223                 aniState->ofdmWeakSigDetect);
01224         DBG2(
01225                 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
01226                 aniState->cckWeakSigThreshold,
01227                 aniState->firstepLevel,
01228                 aniState->listenTime);
01229         DBG2(
01230                 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
01231                 aniState->ofdmPhyErrCount,
01232                 aniState->cckPhyErrCount);
01233 
01234         return 1;
01235 }
01236 
01237 static int ar5008_hw_ani_control_new(struct ath_hw *ah,
01238                                       enum ath9k_ani_cmd cmd,
01239                                       int param)
01240 {
01241         struct ath9k_channel *chan = ah->curchan;
01242         struct ar5416AniState *aniState = &chan->ani;
01243         s32 value, value2;
01244 
01245         switch (cmd & ah->ani_function) {
01246         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
01247                 /*
01248                  * on == 1 means ofdm weak signal detection is ON
01249                  * on == 1 is the default, for less noise immunity
01250                  *
01251                  * on == 0 means ofdm weak signal detection is OFF
01252                  * on == 0 means more noise imm
01253                  */
01254                 u32 on = param ? 1 : 0;
01255                 /*
01256                  * make register setting for default
01257                  * (weak sig detect ON) come from INI file
01258                  */
01259                 int m1ThreshLow = on ?
01260                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
01261                 int m2ThreshLow = on ?
01262                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
01263                 int m1Thresh = on ?
01264                         aniState->iniDef.m1Thresh : m1Thresh_off;
01265                 int m2Thresh = on ?
01266                         aniState->iniDef.m2Thresh : m2Thresh_off;
01267                 int m2CountThr = on ?
01268                         aniState->iniDef.m2CountThr : m2CountThr_off;
01269                 int m2CountThrLow = on ?
01270                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
01271                 int m1ThreshLowExt = on ?
01272                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
01273                 int m2ThreshLowExt = on ?
01274                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
01275                 int m1ThreshExt = on ?
01276                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
01277                 int m2ThreshExt = on ?
01278                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
01279 
01280                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
01281                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
01282                               m1ThreshLow);
01283                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
01284                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
01285                               m2ThreshLow);
01286                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
01287                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
01288                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
01289                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
01290                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
01291                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
01292                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
01293                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
01294                               m2CountThrLow);
01295 
01296                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01297                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
01298                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01299                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
01300                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01301                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
01302                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
01303                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
01304 
01305                 if (on)
01306                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
01307                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
01308                 else
01309                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
01310                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
01311 
01312                 if (on != aniState->ofdmWeakSigDetect) {
01313                         DBG2("ath9k: "
01314                                 "** ch %d: ofdm weak signal: %s=>%s\n",
01315                                 chan->channel,
01316                                 aniState->ofdmWeakSigDetect ?
01317                                 "on" : "off",
01318                                 on ? "on" : "off");
01319                         if (on)
01320                                 ah->stats.ast_ani_ofdmon++;
01321                         else
01322                                 ah->stats.ast_ani_ofdmoff++;
01323                         aniState->ofdmWeakSigDetect = on;
01324                 }
01325                 break;
01326         }
01327         case ATH9K_ANI_FIRSTEP_LEVEL:{
01328                 u32 level = param;
01329 
01330                 if (level >= ARRAY_SIZE(firstep_table)) {
01331                         DBG("ath9k: "
01332                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
01333                                 level, ARRAY_SIZE(firstep_table));
01334                         return 0;
01335                 }
01336 
01337                 /*
01338                  * make register setting relative to default
01339                  * from INI file & cap value
01340                  */
01341                 value = firstep_table[level] -
01342                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
01343                         aniState->iniDef.firstep;
01344                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
01345                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
01346                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
01347                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
01348                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
01349                               AR_PHY_FIND_SIG_FIRSTEP,
01350                               value);
01351                 /*
01352                  * we need to set first step low register too
01353                  * make register setting relative to default
01354                  * from INI file & cap value
01355                  */
01356                 value2 = firstep_table[level] -
01357                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
01358                          aniState->iniDef.firstepLow;
01359                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
01360                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
01361                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
01362                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
01363 
01364                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
01365                               AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
01366 
01367                 if (level != aniState->firstepLevel) {
01368                         DBG2("ath9k: "
01369                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
01370                                 chan->channel,
01371                                 aniState->firstepLevel,
01372                                 level,
01373                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
01374                                 value,
01375                                 aniState->iniDef.firstep);
01376                         DBG2("ath9k: "
01377                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
01378                                 chan->channel,
01379                                 aniState->firstepLevel,
01380                                 level,
01381                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
01382                                 value2,
01383                                 aniState->iniDef.firstepLow);
01384                         if (level > aniState->firstepLevel)
01385                                 ah->stats.ast_ani_stepup++;
01386                         else if (level < aniState->firstepLevel)
01387                                 ah->stats.ast_ani_stepdown++;
01388                         aniState->firstepLevel = level;
01389                 }
01390                 break;
01391         }
01392         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
01393                 u32 level = param;
01394 
01395                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
01396                         DBG("ath9k: "
01397                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
01398                                 level, ARRAY_SIZE(cycpwrThr1_table));
01399                         return 0;
01400                 }
01401                 /*
01402                  * make register setting relative to default
01403                  * from INI file & cap value
01404                  */
01405                 value = cycpwrThr1_table[level] -
01406                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
01407                         aniState->iniDef.cycpwrThr1;
01408                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
01409                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
01410                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
01411                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
01412                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
01413                               AR_PHY_TIMING5_CYCPWR_THR1,
01414                               value);
01415 
01416                 /*
01417                  * set AR_PHY_EXT_CCA for extension channel
01418                  * make register setting relative to default
01419                  * from INI file & cap value
01420                  */
01421                 value2 = cycpwrThr1_table[level] -
01422                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
01423                          aniState->iniDef.cycpwrThr1Ext;
01424                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
01425                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
01426                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
01427                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
01428                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
01429                               AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
01430 
01431                 if (level != aniState->spurImmunityLevel) {
01432                         DBG2("ath9k: "
01433                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
01434                                 chan->channel,
01435                                 aniState->spurImmunityLevel,
01436                                 level,
01437                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
01438                                 value,
01439                                 aniState->iniDef.cycpwrThr1);
01440                         DBG2("ath9k: "
01441                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
01442                                 chan->channel,
01443                                 aniState->spurImmunityLevel,
01444                                 level,
01445                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
01446                                 value2,
01447                                 aniState->iniDef.cycpwrThr1Ext);
01448                         if (level > aniState->spurImmunityLevel)
01449                                 ah->stats.ast_ani_spurup++;
01450                         else if (level < aniState->spurImmunityLevel)
01451                                 ah->stats.ast_ani_spurdown++;
01452                         aniState->spurImmunityLevel = level;
01453                 }
01454                 break;
01455         }
01456         case ATH9K_ANI_MRC_CCK:
01457                 /*
01458                  * You should not see this as AR5008, AR9001, AR9002
01459                  * does not have hardware support for MRC CCK.
01460                  */
01461                 break;
01462         case ATH9K_ANI_PRESENT:
01463                 break;
01464         default:
01465                 DBG("ath9k: invalid cmd %d\n", cmd);
01466                 return 0;
01467         }
01468 
01469         DBG2("ath9k: "
01470                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
01471                 aniState->spurImmunityLevel,
01472                 aniState->ofdmWeakSigDetect ? "on" : "off",
01473                 aniState->firstepLevel,
01474                 !aniState->mrcCCKOff ? "on" : "off",
01475                 aniState->listenTime,
01476                 aniState->ofdmPhyErrCount,
01477                 aniState->cckPhyErrCount);
01478         return 1;
01479 }
01480 
01481 static void ar5008_hw_do_getnf(struct ath_hw *ah,
01482                               int16_t nfarray[NUM_NF_READINGS])
01483 {
01484         int16_t nf;
01485 
01486         nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
01487         nfarray[0] = sign_extend32(nf, 8);
01488 
01489         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
01490         nfarray[1] = sign_extend32(nf, 8);
01491 
01492         nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
01493         nfarray[2] = sign_extend32(nf, 8);
01494 
01495         if (!IS_CHAN_HT40(ah->curchan))
01496                 return;
01497 
01498         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
01499         nfarray[3] = sign_extend32(nf, 8);
01500 
01501         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
01502         nfarray[4] = sign_extend32(nf, 8);
01503 
01504         nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
01505         nfarray[5] = sign_extend32(nf, 8);
01506 }
01507 
01508 /*
01509  * Initialize the ANI register values with default (ini) values.
01510  * This routine is called during a (full) hardware reset after
01511  * all the registers are initialised from the INI.
01512  */
01513 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
01514 {
01515         struct ath9k_channel *chan = ah->curchan;
01516         struct ar5416AniState *aniState = &chan->ani;
01517         struct ath9k_ani_default *iniDef;
01518         u32 val;
01519 
01520         iniDef = &aniState->iniDef;
01521 
01522         DBG2("ath9k: ver %d.%d chan %d Mhz/0x%x\n",
01523                 ah->hw_version.macVersion,
01524                 ah->hw_version.macRev,
01525                 chan->channel,
01526                 chan->channelFlags);
01527 
01528         val = REG_READ(ah, AR_PHY_SFCORR);
01529         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
01530         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
01531         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
01532 
01533         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
01534         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
01535         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
01536         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
01537 
01538         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
01539         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
01540         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
01541         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
01542         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
01543         iniDef->firstep = REG_READ_FIELD(ah,
01544                                          AR_PHY_FIND_SIG,
01545                                          AR_PHY_FIND_SIG_FIRSTEP);
01546         iniDef->firstepLow = REG_READ_FIELD(ah,
01547                                             AR_PHY_FIND_SIG_LOW,
01548                                             AR_PHY_FIND_SIG_FIRSTEP_LOW);
01549         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
01550                                             AR_PHY_TIMING5,
01551                                             AR_PHY_TIMING5_CYCPWR_THR1);
01552         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
01553                                                AR_PHY_EXT_CCA,
01554                                                AR_PHY_EXT_TIMING5_CYCPWR_THR1);
01555 
01556         /* these levels just got reset to defaults by the INI */
01557         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
01558         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
01559         aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
01560         aniState->mrcCCKOff = 1; /* not available on pre AR9003 */
01561 }
01562 
01563 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
01564 {
01565         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
01566         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
01567         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
01568         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
01569         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
01570         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
01571 }
01572 
01573 static void ar5008_hw_set_radar_params(struct ath_hw *ah,
01574                                        struct ath_hw_radar_conf *conf)
01575 {
01576         u32 radar_0 = 0, radar_1 = 0;
01577 
01578         if (!conf) {
01579                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
01580                 return;
01581         }
01582 
01583         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
01584         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
01585         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
01586         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
01587         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
01588         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
01589 
01590         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
01591         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
01592         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
01593         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
01594         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
01595 
01596         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
01597         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
01598         if (conf->ext_channel)
01599                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
01600         else
01601                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
01602 }
01603 
01604 static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
01605 {
01606         struct ath_hw_radar_conf *conf = &ah->radar_conf;
01607 
01608         conf->fir_power = -33;
01609         conf->radar_rssi = 20;
01610         conf->pulse_height = 10;
01611         conf->pulse_rssi = 24;
01612         conf->pulse_inband = 15;
01613         conf->pulse_maxlen = 255;
01614         conf->pulse_inband_step = 12;
01615         conf->radar_inband = 8;
01616 }
01617 
01618 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
01619 {
01620         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
01621         static const u32 ar5416_cca_regs[6] = {
01622                 AR_PHY_CCA,
01623                 AR_PHY_CH1_CCA,
01624                 AR_PHY_CH2_CCA,
01625                 AR_PHY_EXT_CCA,
01626                 AR_PHY_CH1_EXT_CCA,
01627                 AR_PHY_CH2_EXT_CCA
01628         };
01629 
01630         priv_ops->rf_set_freq = ar5008_hw_set_channel;
01631         priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
01632 
01633         priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
01634         priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
01635         priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
01636         priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
01637         priv_ops->init_bb = ar5008_hw_init_bb;
01638         priv_ops->process_ini = ar5008_hw_process_ini;
01639         priv_ops->set_rfmode = ar5008_hw_set_rfmode;
01640         priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
01641         priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
01642         priv_ops->rfbus_req = ar5008_hw_rfbus_req;
01643         priv_ops->rfbus_done = ar5008_hw_rfbus_done;
01644         priv_ops->restore_chainmask = ar5008_restore_chainmask;
01645         priv_ops->set_diversity = ar5008_set_diversity;
01646         priv_ops->do_getnf = ar5008_hw_do_getnf;
01647         priv_ops->set_radar_params = ar5008_hw_set_radar_params;
01648 
01649         if (modparam_force_new_ani) {
01650                 priv_ops->ani_control = ar5008_hw_ani_control_new;
01651                 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
01652         } else
01653                 priv_ops->ani_control = ar5008_hw_ani_control_old;
01654 
01655         if (AR_SREV_9100(ah))
01656                 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
01657         else if (AR_SREV_9160_10_OR_LATER(ah))
01658                 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
01659         else
01660                 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
01661 
01662         ar5008_hw_set_nf_limits(ah);
01663         ar5008_hw_set_radar_conf(ah);
01664         memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
01665 }