iPXE
Functions | Variables
ath9k_ar9002_hw.c File Reference
#include "hw.h"
#include "ar5008_initvals.h"
#include "ar9001_initvals.h"
#include "ar9002_initvals.h"
#include "ar9002_phy.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (BSD2)
static void ar9002_hw_init_mode_regs (struct ath_hw *ah)
void ar9002_hw_cck_chan14_spread (struct ath_hw *ah)
static void ar9280_20_hw_init_rxgain_ini (struct ath_hw *ah)
static void ar9280_20_hw_init_txgain_ini (struct ath_hw *ah)
static void ar9002_hw_init_mode_gain_regs (struct ath_hw *ah)
static void ar9002_hw_configpcipowersave (struct ath_hw *ah, int restore, int power_off)
static int ar9002_hw_get_radiorev (struct ath_hw *ah)
int ar9002_hw_rf_claim (struct ath_hw *ah)
void ar9002_hw_enable_async_fifo (struct ath_hw *ah)
void ar9002_hw_update_async_fifo (struct ath_hw *ah)
void ar9002_hw_enable_wep_aggregation (struct ath_hw *ah)
void ar9002_hw_attach_ops (struct ath_hw *ah)
void ar9002_hw_load_ani_reg (struct ath_hw *ah, struct ath9k_channel *chan)

Variables

int modparam_force_new_ani

Function Documentation

FILE_LICENCE ( BSD2  )
static void ar9002_hw_init_mode_regs ( struct ath_hw ah) [static]

Definition at line 32 of file ath9k_ar9002_hw.c.

References ar5416Addac, ar5416Addac_9100, ar5416Addac_9160, ar5416Addac_9160_1_1, ar5416Bank0, ar5416Bank0_9100, ar5416Bank0_9160, ar5416Bank1, ar5416Bank1_9100, ar5416Bank1_9160, ar5416Bank2, ar5416Bank2_9100, ar5416Bank2_9160, ar5416Bank3, ar5416Bank3_9100, ar5416Bank3_9160, ar5416Bank6, ar5416Bank6_9100, ar5416Bank6_9160, ar5416Bank6TPC, ar5416Bank6TPC_9100, ar5416Bank6TPC_9160, ar5416Bank7, ar5416Bank7_9100, ar5416Bank7_9160, ar5416BB_RfGain, ar5416BB_RfGain_9100, ar5416BB_RfGain_9160, ar5416Common, ar5416Common_9100, ar5416Common_9160, ar5416Modes, ar5416Modes_9100, ar5416Modes_9160, ar9271Common_9271, ar9271Common_japan_2484_cck_fir_coeff_9271, ar9271Common_normal_cck_fir_coeff_9271, ar9271Modes_9271, ar9271Modes_9271_1_0_only, ar9271Modes_9271_ANI_reg, ar9271Modes_high_power_tx_gain_9271, ar9271Modes_normal_power_tx_gain_9271, ar9280Common_9280_2, ar9280Modes_9280_2, ar9280Modes_fast_clock_9280_2, ar9280PciePhy_clkreq_always_on_L1_9280, ar9280PciePhy_clkreq_off_L1_9280, ar9285Common_9285_1_2, ar9285Modes_9285_1_2, ar9285PciePhy_clkreq_always_on_L1_9285_1_2, ar9285PciePhy_clkreq_off_L1_9285_1_2, ar9287Common_9287_1_1, ar9287Modes_9287_1_1, ar9287PciePhy_clkreq_always_on_L1_9287_1_1, ar9287PciePhy_clkreq_off_L1_9287_1_1, AR_SREV_9100_OR_LATER, AR_SREV_9160_10_OR_LATER, AR_SREV_9160_11, AR_SREV_9271, AR_SREV_9280_20_OR_LATER, AR_SREV_9285_12_OR_LATER, AR_SREV_9287_11_OR_LATER, ARRAY_SIZE, ath_hw::config, ath_hw::iniAddac, ath_hw::iniBank0, ath_hw::iniBank1, ath_hw::iniBank2, ath_hw::iniBank3, ath_hw::iniBank6, ath_hw::iniBank6TPC, ath_hw::iniBank7, ath_hw::iniBB_RfGain, ath_hw::iniCommon, ath_hw::iniCommon_japan_2484_cck_fir_coeff_9271, ath_hw::iniCommon_normal_cck_fir_coeff_9271, ath_hw::iniModes, ath_hw::iniModes_9271_1_0_only, ath_hw::iniModes_9271_ANI_reg, ath_hw::iniModes_high_power_tx_gain_9271, ath_hw::iniModes_normal_power_tx_gain_9271, ath_hw::iniModesAdditional, ath_hw::iniPcieSerdes, INIT_INI_ARRAY, and ath9k_ops_config::pcie_clock_req.

Referenced by ar9002_hw_attach_ops().

{
        if (AR_SREV_9271(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
                               ARRAY_SIZE(ar9271Modes_9271), 6);
                INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
                               ARRAY_SIZE(ar9271Common_9271), 2);
                INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
                               ar9271Common_normal_cck_fir_coeff_9271,
                               ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
                INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
                               ar9271Common_japan_2484_cck_fir_coeff_9271,
                               ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
                INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
                               ar9271Modes_9271_1_0_only,
                               ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
                INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
                               ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
                INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
                               ar9271Modes_high_power_tx_gain_9271,
                               ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
                INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
                               ar9271Modes_normal_power_tx_gain_9271,
                               ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
                return;
        }

        if (AR_SREV_9287_11_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
                                ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
                INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
                                ARRAY_SIZE(ar9287Common_9287_1_1), 2);
                if (ah->config.pcie_clock_req)
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
                        ar9287PciePhy_clkreq_off_L1_9287_1_1,
                        ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
                else
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
                        ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
                        ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
                                        2);
        } else if (AR_SREV_9285_12_OR_LATER(ah)) {


                INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
                               ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
                INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
                               ARRAY_SIZE(ar9285Common_9285_1_2), 2);

                if (ah->config.pcie_clock_req) {
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
                        ar9285PciePhy_clkreq_off_L1_9285_1_2,
                        ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
                } else {
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
                        ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
                        ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
                                  2);
                }
        } else if (AR_SREV_9280_20_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
                               ARRAY_SIZE(ar9280Modes_9280_2), 6);
                INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
                               ARRAY_SIZE(ar9280Common_9280_2), 2);

                if (ah->config.pcie_clock_req) {
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
                               ar9280PciePhy_clkreq_off_L1_9280,
                               ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
                } else {
                        INIT_INI_ARRAY(&ah->iniPcieSerdes,
                               ar9280PciePhy_clkreq_always_on_L1_9280,
                               ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
                }
                INIT_INI_ARRAY(&ah->iniModesAdditional,
                               ar9280Modes_fast_clock_9280_2,
                               ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
        } else if (AR_SREV_9160_10_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
                               ARRAY_SIZE(ar5416Modes_9160), 6);
                INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
                               ARRAY_SIZE(ar5416Common_9160), 2);
                INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
                               ARRAY_SIZE(ar5416Bank0_9160), 2);
                INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
                               ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
                INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
                               ARRAY_SIZE(ar5416Bank1_9160), 2);
                INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
                               ARRAY_SIZE(ar5416Bank2_9160), 2);
                INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
                               ARRAY_SIZE(ar5416Bank3_9160), 3);
                INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
                               ARRAY_SIZE(ar5416Bank6_9160), 3);
                INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
                               ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
                INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
                               ARRAY_SIZE(ar5416Bank7_9160), 2);
                if (AR_SREV_9160_11(ah)) {
                        INIT_INI_ARRAY(&ah->iniAddac,
                                       ar5416Addac_9160_1_1,
                                       ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
                } else {
                        INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
                                       ARRAY_SIZE(ar5416Addac_9160), 2);
                }
        } else if (AR_SREV_9100_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
                               ARRAY_SIZE(ar5416Modes_9100), 6);
                INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
                               ARRAY_SIZE(ar5416Common_9100), 2);
                INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
                               ARRAY_SIZE(ar5416Bank0_9100), 2);
                INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
                               ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
                INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
                               ARRAY_SIZE(ar5416Bank1_9100), 2);
                INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
                               ARRAY_SIZE(ar5416Bank2_9100), 2);
                INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
                               ARRAY_SIZE(ar5416Bank3_9100), 3);
                INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
                               ARRAY_SIZE(ar5416Bank6_9100), 3);
                INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
                               ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
                INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
                               ARRAY_SIZE(ar5416Bank7_9100), 2);
                INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
                               ARRAY_SIZE(ar5416Addac_9100), 2);
        } else {
                INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
                               ARRAY_SIZE(ar5416Modes), 6);
                INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
                               ARRAY_SIZE(ar5416Common), 2);
                INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
                               ARRAY_SIZE(ar5416Bank0), 2);
                INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
                               ARRAY_SIZE(ar5416BB_RfGain), 3);
                INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
                               ARRAY_SIZE(ar5416Bank1), 2);
                INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
                               ARRAY_SIZE(ar5416Bank2), 2);
                INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
                               ARRAY_SIZE(ar5416Bank3), 3);
                INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
                               ARRAY_SIZE(ar5416Bank6), 3);
                INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
                               ARRAY_SIZE(ar5416Bank6TPC), 3);
                INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
                               ARRAY_SIZE(ar5416Bank7), 2);
                INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
                               ARRAY_SIZE(ar5416Addac), 2);
        }
}
void ar9002_hw_cck_chan14_spread ( struct ath_hw ah)
static void ar9280_20_hw_init_rxgain_ini ( struct ath_hw ah) [static]
static void ar9280_20_hw_init_txgain_ini ( struct ath_hw ah) [static]
static void ar9002_hw_init_mode_gain_regs ( struct ath_hw ah) [static]

Definition at line 252 of file ath9k_ar9002_hw.c.

References AR5416_EEP_TXGAIN_HIGH_POWER, ar9280_20_hw_init_rxgain_ini(), ar9280_20_hw_init_txgain_ini(), ar9285Modes_high_power_tx_gain_9285_1_2, ar9285Modes_original_tx_gain_9285_1_2, ar9285Modes_XE2_0_high_power, ar9285Modes_XE2_0_normal_power, ar9287Modes_rx_gain_9287_1_1, ar9287Modes_tx_gain_9287_1_1, AR_SREV_9280_20, AR_SREV_9285_12_OR_LATER, AR_SREV_9285E_20, AR_SREV_9287_11_OR_LATER, ARRAY_SIZE, ath_hw::eep_ops, EEP_TXGAIN_TYPE, eeprom_ops::get_eeprom, ath_hw::iniModesRxGain, ath_hw::iniModesTxGain, and INIT_INI_ARRAY.

Referenced by ar9002_hw_attach_ops().

static void ar9002_hw_configpcipowersave ( struct ath_hw ah,
int  restore,
int  power_off 
) [static]

Definition at line 308 of file ath9k_ar9002_hw.c.

References AR9280_WA_DEFAULT, AR9285_WA_DEFAULT, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA, AR_PCIE_SERDES, AR_PCIE_SERDES2, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20_OR_LATER, AR_SREV_9285, AR_SREV_9285E_20, AR_SREV_9287, AR_WA, AR_WA_BIT22, AR_WA_BIT23, AR_WA_BIT6, AR_WA_BIT7, AR_WA_D3_L1_DISABLE, AR_WA_DEFAULT, ath_hw::config, ENABLE_REGWRITE_BUFFER, ar5416IniArray::ia_rows, INI_RA, ath_hw::iniPcieSerdes, ath_hw::is_pciexpress, ath9k_ops_config::pcie_powersave_enable, ath9k_ops_config::pcie_waen, REG_CLR_BIT, REG_READ, REG_SET_BIT, REG_WRITE, REGWRITE_BUFFER_FLUSH, udelay(), and val.

Referenced by ar9002_hw_attach_ops().

{
        u8 i;
        u32 val;

        if (ah->is_pciexpress != 1)
                return;

        /* Do not touch SerDes registers */
        if (ah->config.pcie_powersave_enable == 2)
                return;

        /* Nothing to do on restore for 11N */
        if (!restore) {
                if (AR_SREV_9280_20_OR_LATER(ah)) {
                        /*
                         * AR9280 2.0 or later chips use SerDes values from the
                         * initvals.h initialized depending on chipset during
                         * __ath9k_hw_init()
                         */
                        for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
                                REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
                                          INI_RA(&ah->iniPcieSerdes, i, 1));
                        }
                } else {
                        ENABLE_REGWRITE_BUFFER(ah);

                        REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
                        REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);

                        /* RX shut off when elecidle is asserted */
                        REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
                        REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
                        REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);

                        /*
                         * Ignore ah->ah_config.pcie_clock_req setting for
                         * pre-AR9280 11n
                         */
                        REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);

                        REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
                        REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
                        REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);

                        /* Load the new settings */
                        REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);

                        REGWRITE_BUFFER_FLUSH(ah);
                }

                udelay(1000);
        }

        if (power_off) {
                /* clear bit 19 to disable L1 */
                REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

                val = REG_READ(ah, AR_WA);

                /*
                 * Set PCIe workaround bits
                 * In AR9280 and AR9285, bit 14 in WA register (disable L1)
                 * should only  be set when device enters D3 and be
                 * cleared when device comes back to D0.
                 */
                if (ah->config.pcie_waen) {
                        if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
                                val |= AR_WA_D3_L1_DISABLE;
                } else {
                        if (((AR_SREV_9285(ah) ||
                              AR_SREV_9271(ah) ||
                              AR_SREV_9287(ah)) &&
                             (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
                            (AR_SREV_9280(ah) &&
                             (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
                                val |= AR_WA_D3_L1_DISABLE;
                        }
                }

                if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
                        /*
                         * Disable bit 6 and 7 before entering D3 to
                         * prevent system hang.
                         */
                        val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
                }

                if (AR_SREV_9280(ah))
                        val |= AR_WA_BIT22;

                if (AR_SREV_9285E_20(ah))
                        val |= AR_WA_BIT23;

                REG_WRITE(ah, AR_WA, val);
        } else {
                if (ah->config.pcie_waen) {
                        val = ah->config.pcie_waen;
                        if (!power_off)
                                val &= (~AR_WA_D3_L1_DISABLE);
                } else {
                        if (AR_SREV_9285(ah) ||
                            AR_SREV_9271(ah) ||
                            AR_SREV_9287(ah)) {
                                val = AR9285_WA_DEFAULT;
                                if (!power_off)
                                        val &= (~AR_WA_D3_L1_DISABLE);
                        }
                        else if (AR_SREV_9280(ah)) {
                                /*
                                 * For AR9280 chips, bit 22 of 0x4004
                                 * needs to be set.
                                 */
                                val = AR9280_WA_DEFAULT;
                                if (!power_off)
                                        val &= (~AR_WA_D3_L1_DISABLE);
                        } else {
                                val = AR_WA_DEFAULT;
                        }
                }

                /* WAR for ASPM system hang */
                if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
                        val |= (AR_WA_BIT6 | AR_WA_BIT7);

                if (AR_SREV_9285E_20(ah))
                        val |= AR_WA_BIT23;

                REG_WRITE(ah, AR_WA, val);

                /* set bit 19 to allow forcing of pcie core into L1 state */
                REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
        }
}
static int ar9002_hw_get_radiorev ( struct ath_hw ah) [static]

Definition at line 445 of file ath9k_ar9002_hw.c.

References AR_PHY, ath9k_hw_reverse_bits(), ENABLE_REGWRITE_BUFFER, REG_READ, REG_WRITE, REGWRITE_BUFFER_FLUSH, and val.

Referenced by ar9002_hw_rf_claim().

{
        u32 val;
        int i;

        ENABLE_REGWRITE_BUFFER(ah);

        REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
        for (i = 0; i < 8; i++)
                REG_WRITE(ah, AR_PHY(0x20), 0x00010000);

        REGWRITE_BUFFER_FLUSH(ah);

        val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
        val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);

        return ath9k_hw_reverse_bits(val, 8);
}
int ar9002_hw_rf_claim ( struct ath_hw ah)

Definition at line 464 of file ath9k_ar9002_hw.c.

References ath9k_hw_version::analog5GhzRev, ar9002_hw_get_radiorev(), AR_PHY, AR_RAD2122_SREV_MAJOR, AR_RAD2133_SREV_MAJOR, AR_RAD5122_SREV_MAJOR, AR_RAD5133_SREV_MAJOR, AR_RADIO_SREV_MAJOR, DBG, EOPNOTSUPP, ath_hw::hw_version, REG_WRITE, and val.

Referenced by ath9k_hw_post_init().

{
        u32 val;

        REG_WRITE(ah, AR_PHY(0), 0x00000007);

        val = ar9002_hw_get_radiorev(ah);
        switch (val & AR_RADIO_SREV_MAJOR) {
        case 0:
                val = AR_RAD5133_SREV_MAJOR;
                break;
        case AR_RAD5133_SREV_MAJOR:
        case AR_RAD5122_SREV_MAJOR:
        case AR_RAD2133_SREV_MAJOR:
        case AR_RAD2122_SREV_MAJOR:
                break;
        default:
                DBG("ath9k: "
                        "Radio Chip Rev 0x%02X not supported\n",
                        val & AR_RADIO_SREV_MAJOR);
                return -EOPNOTSUPP;
        }

        ah->hw_version.analog5GhzRev = val;

        return 0;
}
void ar9002_hw_enable_async_fifo ( struct ath_hw ah)
void ar9002_hw_update_async_fifo ( struct ath_hw ah)
void ar9002_hw_attach_ops ( struct ath_hw ah)
void ar9002_hw_load_ani_reg ( struct ath_hw ah,
struct ath9k_channel chan 
)

Definition at line 563 of file ath9k_ar9002_hw.c.

References AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, ath9k_channel::chanmode, CHANNEL_A, CHANNEL_A_HT20, CHANNEL_A_HT40MINUS, CHANNEL_A_HT40PLUS, CHANNEL_B, CHANNEL_G, CHANNEL_G_HT20, CHANNEL_G_HT40MINUS, CHANNEL_G_HT40PLUS, ENABLE_REGWRITE_BUFFER, ar5416IniArray::ia_rows, INI_RA, ath_hw::iniModes_9271_ANI_reg, reg, REG_READ, REG_WRITE, REGWRITE_BUFFER_FLUSH, and val.

Referenced by ath9k_hw_reset().

{
        u32 modesIndex;
        unsigned int i;

        switch (chan->chanmode) {
        case CHANNEL_A:
        case CHANNEL_A_HT20:
                modesIndex = 1;
                break;
        case CHANNEL_A_HT40PLUS:
        case CHANNEL_A_HT40MINUS:
                modesIndex = 2;
                break;
        case CHANNEL_G:
        case CHANNEL_G_HT20:
        case CHANNEL_B:
                modesIndex = 4;
                break;
        case CHANNEL_G_HT40PLUS:
        case CHANNEL_G_HT40MINUS:
                modesIndex = 3;
                break;

        default:
                return;
        }

        ENABLE_REGWRITE_BUFFER(ah);

        for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
                u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
                u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
                u32 val_orig;

                if (reg == AR_PHY_CCK_DETECT) {
                        val_orig = REG_READ(ah, reg);
                        val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
                        val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;

                        REG_WRITE(ah, reg, val|val_orig);
                } else
                        REG_WRITE(ah, reg, val);
        }

        REGWRITE_BUFFER_FLUSH(ah);
}

Variable Documentation

Definition at line 28 of file ath9k_ar9002_hw.c.

Referenced by ar5008_hw_attach_phy_ops(), and use_new_ani().