iPXE
ath9k_ar9002_mac.c
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #include <ipxe/io.h>
00021 
00022 #include "hw.h"
00023 
00024 #define AR_BufLen           0x00000fff
00025 
00026 static void ar9002_hw_rx_enable(struct ath_hw *ah)
00027 {
00028         REG_WRITE(ah, AR_CR, AR_CR_RXE);
00029 }
00030 
00031 static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
00032 {
00033         ((struct ath_desc*) ds)->ds_link = ds_link;
00034 }
00035 
00036 static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
00037 {
00038         *ds_link = &((struct ath_desc *)ds)->ds_link;
00039 }
00040 
00041 static int ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
00042 {
00043         u32 isr = 0;
00044         u32 mask2 = 0;
00045         struct ath9k_hw_capabilities *pCap = &ah->caps;
00046         u32 sync_cause = 0;
00047         int fatal_int = 0;
00048 
00049         if (!AR_SREV_9100(ah) && (ah->ah_ier & AR_IER_ENABLE)) {
00050                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
00051                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
00052                             == AR_RTC_STATUS_ON) {
00053                                 isr = REG_READ(ah, AR_ISR);
00054                         }
00055                 }
00056 
00057                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
00058                         AR_INTR_SYNC_DEFAULT;
00059 
00060                 *masked = 0;
00061 
00062                 if (!isr && !sync_cause)
00063                         return 0;
00064         } else {
00065                 *masked = 0;
00066                 isr = REG_READ(ah, AR_ISR);
00067         }
00068 
00069         if (isr) {
00070                 if (isr & AR_ISR_BCNMISC) {
00071                         u32 isr2;
00072                         isr2 = REG_READ(ah, AR_ISR_S2);
00073                         if (isr2 & AR_ISR_S2_TIM)
00074                                 mask2 |= ATH9K_INT_TIM;
00075                         if (isr2 & AR_ISR_S2_DTIM)
00076                                 mask2 |= ATH9K_INT_DTIM;
00077                         if (isr2 & AR_ISR_S2_DTIMSYNC)
00078                                 mask2 |= ATH9K_INT_DTIMSYNC;
00079                         if (isr2 & (AR_ISR_S2_CABEND))
00080                                 mask2 |= ATH9K_INT_CABEND;
00081                         if (isr2 & AR_ISR_S2_GTT)
00082                                 mask2 |= ATH9K_INT_GTT;
00083                         if (isr2 & AR_ISR_S2_CST)
00084                                 mask2 |= ATH9K_INT_CST;
00085                         if (isr2 & AR_ISR_S2_TSFOOR)
00086                                 mask2 |= ATH9K_INT_TSFOOR;
00087                 }
00088 
00089                 isr = REG_READ(ah, AR_ISR_RAC);
00090                 if (isr == 0xffffffff) {
00091                         *masked = 0;
00092                         return 0;
00093                 }
00094 
00095                 *masked = isr & ATH9K_INT_COMMON;
00096 
00097                 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
00098                            AR_ISR_RXOK | AR_ISR_RXERR))
00099                         *masked |= ATH9K_INT_RX;
00100 
00101                 if (isr &
00102                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
00103                      AR_ISR_TXEOL)) {
00104                         u32 s0_s, s1_s;
00105 
00106                         *masked |= ATH9K_INT_TX;
00107 
00108                         s0_s = REG_READ(ah, AR_ISR_S0_S);
00109                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
00110                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
00111 
00112                         s1_s = REG_READ(ah, AR_ISR_S1_S);
00113                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
00114                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
00115                 }
00116 
00117                 if (isr & AR_ISR_RXORN) {
00118                         DBG("ath9k: "
00119                                 "receive FIFO overrun interrupt\n");
00120                 }
00121 
00122                 *masked |= mask2;
00123         }
00124 
00125         if (AR_SREV_9100(ah))
00126                 return 1;
00127 
00128         if (isr & AR_ISR_GENTMR) {
00129                 u32 s5_s;
00130 
00131                 s5_s = REG_READ(ah, AR_ISR_S5_S);
00132                 ah->intr_gen_timer_trigger =
00133                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
00134 
00135                 ah->intr_gen_timer_thresh =
00136                         MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
00137 
00138                 if (ah->intr_gen_timer_trigger)
00139                         *masked |= ATH9K_INT_GENTIMER;
00140 
00141                 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
00142                     !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
00143                         *masked |= ATH9K_INT_TIM_TIMER;
00144         }
00145 
00146         if (sync_cause) {
00147                 fatal_int =
00148                         (sync_cause &
00149                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
00150                         ? 1 : 0;
00151 
00152                 if (fatal_int) {
00153                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
00154                                 DBG("ath9k: "
00155                                         "received PCI FATAL interrupt\n");
00156                         }
00157                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
00158                                 DBG("ath9k: "
00159                                         "received PCI PERR interrupt\n");
00160                         }
00161                         *masked |= ATH9K_INT_FATAL;
00162                 }
00163                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
00164                         DBG("ath9k: "
00165                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
00166                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
00167                         REG_WRITE(ah, AR_RC, 0);
00168                         *masked |= ATH9K_INT_FATAL;
00169                 }
00170                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
00171                         DBG("ath9k: "
00172                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
00173                 }
00174 
00175                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
00176                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
00177         }
00178 
00179         return 1;
00180 }
00181 
00182 static void ar9002_hw_fill_txdesc(struct ath_hw *ah __unused, void *ds, u32 seglen,
00183                                   int is_firstseg, int is_lastseg,
00184                                   const void *ds0, u32 buf_addr,
00185                                   unsigned int qcu __unused)
00186 {
00187         struct ar5416_desc *ads = AR5416DESC(ds);
00188 
00189         ads->ds_data = buf_addr;
00190 
00191         if (is_firstseg) {
00192                 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
00193         } else if (is_lastseg) {
00194                 ads->ds_ctl0 = 0;
00195                 ads->ds_ctl1 = seglen;
00196                 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
00197                 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
00198         } else {
00199                 ads->ds_ctl0 = 0;
00200                 ads->ds_ctl1 = seglen | AR_TxMore;
00201                 ads->ds_ctl2 = 0;
00202                 ads->ds_ctl3 = 0;
00203         }
00204         ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
00205         ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
00206         ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
00207         ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
00208         ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
00209 }
00210 
00211 static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
00212                                  struct ath_tx_status *ts)
00213 {
00214         struct ar5416_desc *ads = AR5416DESC(ds);
00215         u32 status;
00216 
00217         status = *(volatile typeof(ads->ds_txstatus9) *)&(ads->ds_txstatus9);
00218         if ((status & AR_TxDone) == 0)
00219                 return -EINPROGRESS;
00220 
00221         ts->ts_tstamp = ads->AR_SendTimestamp;
00222         ts->ts_status = 0;
00223         ts->ts_flags = 0;
00224 
00225         if (status & AR_TxOpExceeded)
00226                 ts->ts_status |= ATH9K_TXERR_XTXOP;
00227         ts->tid = MS(status, AR_TxTid);
00228         ts->ts_rateindex = MS(status, AR_FinalTxIdx);
00229         ts->ts_seqnum = MS(status, AR_SeqNum);
00230 
00231         status = *(volatile typeof(ads->ds_txstatus0) *)&(ads->ds_txstatus0);
00232         ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
00233         ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
00234         ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
00235         if (status & AR_TxBaStatus) {
00236                 ts->ts_flags |= ATH9K_TX_BA;
00237                 ts->ba_low = ads->AR_BaBitmapLow;
00238                 ts->ba_high = ads->AR_BaBitmapHigh;
00239         }
00240 
00241         status = *(volatile typeof(ads->ds_txstatus1) *)&(ads->ds_txstatus1);
00242         if (status & AR_FrmXmitOK)
00243                 ts->ts_status |= ATH9K_TX_ACKED;
00244         else {
00245                 if (status & AR_ExcessiveRetries)
00246                         ts->ts_status |= ATH9K_TXERR_XRETRY;
00247                 if (status & AR_Filtered)
00248                         ts->ts_status |= ATH9K_TXERR_FILT;
00249                 if (status & AR_FIFOUnderrun) {
00250                         ts->ts_status |= ATH9K_TXERR_FIFO;
00251                         ath9k_hw_updatetxtriglevel(ah, 1);
00252                 }
00253         }
00254         if (status & AR_TxTimerExpired)
00255                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
00256         if (status & AR_DescCfgErr)
00257                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
00258         if (status & AR_TxDataUnderrun) {
00259                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
00260                 ath9k_hw_updatetxtriglevel(ah, 1);
00261         }
00262         if (status & AR_TxDelimUnderrun) {
00263                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
00264                 ath9k_hw_updatetxtriglevel(ah, 1);
00265         }
00266         ts->ts_shortretry = MS(status, AR_RTSFailCnt);
00267         ts->ts_longretry = MS(status, AR_DataFailCnt);
00268         ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
00269 
00270         status = *(volatile typeof(ads->ds_txstatus5) *)&(ads->ds_txstatus5);
00271         ts->ts_rssi = MS(status, AR_TxRSSICombined);
00272         ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
00273         ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
00274         ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
00275 
00276         ts->evm0 = ads->AR_TxEVM0;
00277         ts->evm1 = ads->AR_TxEVM1;
00278         ts->evm2 = ads->AR_TxEVM2;
00279 
00280         return 0;
00281 }
00282 
00283 static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
00284                                     u32 pktLen, enum ath9k_pkt_type type,
00285                                     u32 txPower, u32 keyIx,
00286                                     enum ath9k_key_type keyType, u32 flags)
00287 {
00288         struct ar5416_desc *ads = AR5416DESC(ds);
00289 
00290         if (txPower > 63)
00291                 txPower = 63;
00292 
00293         ads->ds_ctl0 = (pktLen & AR_FrameLen)
00294                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
00295                 | SM(txPower, AR_XmitPower)
00296                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
00297                 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
00298                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
00299 
00300         ads->ds_ctl1 =
00301                 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
00302                 | SM(type, AR_FrameType)
00303                 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
00304                 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
00305                 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
00306 
00307         ads->ds_ctl6 = SM(keyType, AR_EncrType);
00308 
00309         if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
00310                 ads->ds_ctl8 = 0;
00311                 ads->ds_ctl9 = 0;
00312                 ads->ds_ctl10 = 0;
00313                 ads->ds_ctl11 = 0;
00314         }
00315 }
00316 
00317 static void ar9002_hw_set_clrdmask(struct ath_hw *ah __unused, void *ds, int val)
00318 {
00319         struct ar5416_desc *ads = AR5416DESC(ds);
00320 
00321         if (val)
00322                 ads->ds_ctl0 |= AR_ClrDestMask;
00323         else
00324                 ads->ds_ctl0 &= ~AR_ClrDestMask;
00325 }
00326 
00327 static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah __unused, void *ds,
00328                                           void *lastds,
00329                                           u32 durUpdateEn, u32 rtsctsRate,
00330                                           u32 rtsctsDuration __unused,
00331                                           struct ath9k_11n_rate_series series[],
00332                                           u32 nseries __unused, u32 flags)
00333 {
00334         struct ar5416_desc *ads = AR5416DESC(ds);
00335         struct ar5416_desc *last_ads = AR5416DESC(lastds);
00336         u32 ds_ctl0;
00337 
00338         if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
00339                 ds_ctl0 = ads->ds_ctl0;
00340 
00341                 if (flags & ATH9K_TXDESC_RTSENA) {
00342                         ds_ctl0 &= ~AR_CTSEnable;
00343                         ds_ctl0 |= AR_RTSEnable;
00344                 } else {
00345                         ds_ctl0 &= ~AR_RTSEnable;
00346                         ds_ctl0 |= AR_CTSEnable;
00347                 }
00348 
00349                 ads->ds_ctl0 = ds_ctl0;
00350         } else {
00351                 ads->ds_ctl0 =
00352                         (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
00353         }
00354 
00355         ads->ds_ctl2 = set11nTries(series, 0)
00356                 | set11nTries(series, 1)
00357                 | set11nTries(series, 2)
00358                 | set11nTries(series, 3)
00359                 | (durUpdateEn ? AR_DurUpdateEna : 0)
00360                 | SM(0, AR_BurstDur);
00361 
00362         ads->ds_ctl3 = set11nRate(series, 0)
00363                 | set11nRate(series, 1)
00364                 | set11nRate(series, 2)
00365                 | set11nRate(series, 3);
00366 
00367         ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
00368                 | set11nPktDurRTSCTS(series, 1);
00369 
00370         ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
00371                 | set11nPktDurRTSCTS(series, 3);
00372 
00373         ads->ds_ctl7 = set11nRateFlags(series, 0)
00374                 | set11nRateFlags(series, 1)
00375                 | set11nRateFlags(series, 2)
00376                 | set11nRateFlags(series, 3)
00377                 | SM(rtsctsRate, AR_RTSCTSRate);
00378         last_ads->ds_ctl2 = ads->ds_ctl2;
00379         last_ads->ds_ctl3 = ads->ds_ctl3;
00380 }
00381 
00382 static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah __unused, void *ds,
00383                                         u32 aggrLen)
00384 {
00385         struct ar5416_desc *ads = AR5416DESC(ds);
00386 
00387         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
00388         ads->ds_ctl6 &= ~AR_AggrLen;
00389         ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
00390 }
00391 
00392 static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah __unused, void *ds,
00393                                          u32 numDelims)
00394 {
00395         struct ar5416_desc *ads = AR5416DESC(ds);
00396         unsigned int ctl6;
00397 
00398         ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
00399 
00400         ctl6 = ads->ds_ctl6;
00401         ctl6 &= ~AR_PadDelim;
00402         ctl6 |= SM(numDelims, AR_PadDelim);
00403         ads->ds_ctl6 = ctl6;
00404 }
00405 
00406 static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah __unused, void *ds)
00407 {
00408         struct ar5416_desc *ads = AR5416DESC(ds);
00409 
00410         ads->ds_ctl1 |= AR_IsAggr;
00411         ads->ds_ctl1 &= ~AR_MoreAggr;
00412         ads->ds_ctl6 &= ~AR_PadDelim;
00413 }
00414 
00415 static void ar9002_hw_clr11n_aggr(struct ath_hw *ah __unused, void *ds)
00416 {
00417         struct ar5416_desc *ads = AR5416DESC(ds);
00418 
00419         ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
00420 }
00421 
00422 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
00423                           u32 size, u32 flags)
00424 {
00425         struct ar5416_desc *ads = AR5416DESC(ds);
00426         struct ath9k_hw_capabilities *pCap = &ah->caps;
00427 
00428         ads->ds_ctl1 = size & AR_BufLen;
00429         if (flags & ATH9K_RXDESC_INTREQ)
00430                 ads->ds_ctl1 |= AR_RxIntrReq;
00431 
00432         ads->ds_rxstatus8 &= ~AR_RxDone;
00433         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
00434                 memset(&(ads->u), 0, sizeof(ads->u));
00435 }
00436 
00437 void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
00438 {
00439         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
00440 
00441         ops->rx_enable = ar9002_hw_rx_enable;
00442         ops->set_desc_link = ar9002_hw_set_desc_link;
00443         ops->get_desc_link = ar9002_hw_get_desc_link;
00444         ops->get_isr = ar9002_hw_get_isr;
00445         ops->fill_txdesc = ar9002_hw_fill_txdesc;
00446         ops->proc_txdesc = ar9002_hw_proc_txdesc;
00447         ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
00448         ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
00449         ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
00450         ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
00451         ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
00452         ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
00453         ops->set_clrdmask = ar9002_hw_set_clrdmask;
00454 }