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Functions | |
static int | ar9002_hw_set_channel (struct ath_hw *ah, struct ath9k_channel *chan) |
DOC: Programming Atheros 802.11n analog front end radios. More... | |
static void | ar9002_hw_spur_mitigate (struct ath_hw *ah, struct ath9k_channel *chan) |
ar9002_hw_spur_mitigate - convert baseband spur frequency @ah: atheros hardware structure @chan: More... | |
static void | ar9002_olc_init (struct ath_hw *ah) |
static u32 | ar9002_hw_compute_pll_control (struct ath_hw *ah, struct ath9k_channel *chan) |
static void | ar9002_hw_do_getnf (struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]) |
static void | ar9002_hw_set_nf_limits (struct ath_hw *ah) |
static void | ar9002_hw_antdiv_comb_conf_get (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf) |
static void | ar9002_hw_antdiv_comb_conf_set (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf) |
void | ar9002_hw_attach_phy_ops (struct ath_hw *ah) |
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DOC: Programming Atheros 802.11n analog front end radios.
AR5416 MAC based PCI devices and AR518 MAC based PCI-Express devices have either an external AR2133 analog front end radio for single band 2.4 GHz communication or an AR5133 analog front end radio for dual band 2.4 GHz / 5 GHz communication.
All devices after the AR5416 and AR5418 family starting with the AR9280 have their analog front radios, MAC/BB and host PCIe/USB interface embedded into a single-chip and require less programming.
The following single-chips exist with a respective embedded radio:
AR9280 - 11n dual-band 2x2 MIMO for PCIe AR9281 - 11n single-band 1x2 MIMO for PCIe AR9285 - 11n single-band 1x1 for PCIe AR9287 - 11n single-band 2x2 MIMO for PCIe
AR9220 - 11n dual-band 2x2 MIMO for PCI AR9223 - 11n single-band 2x2 MIMO for PCI
AR9287 - 11n single-band 1x1 MIMO for USBar9002_hw_set_channel - set channel on single-chip device @ah: atheros hardware structure @chan:
This is the function to change channel on single-chip devices, that is all devices after ar9280.
This function takes the channel value in MHz and sets hardware channel value. Assumes writes have been enabled to analog bus.
Actual Expression,
For 2GHz channel, Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) (freq_ref = 40MHz)
For 5GHz channel, Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) (freq_ref = 40MHz/(24>>amodeRefSel))
Definition at line 71 of file ath9k_ar9002_phy.c.
References ah, AR_AN_SYNTH9, AR_AN_SYNTH9_REFDIVA, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_JAPAN, AR_PHY_SYNTH_CONTROL, AR_SREV_9287_11_OR_LATER, ath9k_hw_get_channel_centers(), CHANSEL_2G, CHANSEL_5G, EEP_FRAC_N_5G, REG_READ, REG_RMW_FIELD, REG_WRITE, REG_WRITE_ARRAY, and chan_centers::synth_center.
Referenced by ar9002_hw_attach_phy_ops().
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ar9002_hw_spur_mitigate - convert baseband spur frequency @ah: atheros hardware structure @chan:
For single-chip solutions. Converts to baseband spur frequency given the input channel frequency and compute register settings below.
Definition at line 171 of file ath9k_ar9002_phy.c.
References abs, ah, AR_BASE_FREQ_2GHZ, AR_BASE_FREQ_5GHZ, AR_EEPROM_MODAL_SPURS, AR_NO_SPUR, AR_PHY_BIN_MASK2_1, AR_PHY_BIN_MASK2_2, AR_PHY_BIN_MASK2_3, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK_1, AR_PHY_BIN_MASK_2, AR_PHY_BIN_MASK_3, AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX, AR_PHY_MASK2_M_00_15, AR_PHY_MASK2_M_16_30, AR_PHY_MASK2_M_31_45, AR_PHY_MASK2_P_15_01, AR_PHY_MASK2_P_30_16, AR_PHY_MASK2_P_45_31, AR_PHY_MASK2_P_61_45, AR_PHY_MASK_CTL, AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI, AR_PHY_SPUR_REG_MASK_RATE_CNTL, AR_PHY_SPUR_REG_MASK_RATE_SELECT, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_PHY_TIMING10, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, AR_PHY_TIMING11_SPUR_FREQ_SD, AR_PHY_TIMING11_USE_SPUR_IN_AGC, AR_PHY_TIMING7, AR_PHY_TIMING8, AR_PHY_TIMING9, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK, AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK, AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER, AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI, AR_PHY_VIT_MASK2_M_46_61, AR_SPUR_FEEQ_BOUND_HT20, AR_SPUR_FEEQ_BOUND_HT40, ath9k_hw_get_channel_centers(), bp, ENABLE_REGWRITE_BUFFER, IS_CHAN_2GHZ, IS_CHAN_HT40, memset(), REG_CLR_BIT, REG_READ, REG_WRITE, REGWRITE_BUFFER_FLUSH, SM, SPUR_ENABLE_EEPROM, SPUR_RSSI_THRESH, chan_centers::synth_center, and tmp.
Referenced by ar9002_hw_attach_phy_ops().
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Definition at line 429 of file ath9k_ar9002_phy.c.
References ah, AR9280_TX_GAIN_TABLE_SIZE, AR9287_AN_TXPC0, AR9287_AN_TXPC0_TXPCMODE, AR9287_AN_TXPC0_TXPCMODE_S, AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE, AR_PHY_TX_GAIN, AR_PHY_TX_GAIN_TBL1, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL, ath9k_hw_analog_shift_rmw(), MS, OLC_FOR_AR9280_20_LATER, OLC_FOR_AR9287_10_LATER, REG_READ, REG_SET_BIT, and udelay().
Referenced by ar9002_hw_attach_phy_ops().
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Definition at line 453 of file ath9k_ar9002_phy.c.
References ah, AR_RTC_9160_PLL_CLKSEL, AR_RTC_9160_PLL_DIV, AR_RTC_9160_PLL_REFDIV, AR_SREV_9280_20, IS_CHAN_5GHZ, IS_CHAN_A_FAST_CLOCK, IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, and SM.
Referenced by ar9002_hw_attach_phy_ops().
Definition at line 479 of file ath9k_ar9002_phy.c.
References ah, AR9280_PHY_CH1_EXT_MINCCA_PWR, AR9280_PHY_CH1_MINCCA_PWR, AR9280_PHY_EXT_MINCCA_PWR, AR9280_PHY_MINCCA_PWR, AR_PHY_CCA, AR_PHY_CH1_CCA, AR_PHY_CH1_EXT_CCA, AR_PHY_EXT_CCA, AR_SREV_9271, AR_SREV_9285, IS_CHAN_HT40, MS, REG_READ, and sign_extend32().
Referenced by ar9002_hw_attach_phy_ops().
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Definition at line 502 of file ath9k_ar9002_phy.c.
References ah, AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ, AR_PHY_CCA_NOM_VAL_9271_2GHZ, AR_PHY_CCA_NOM_VAL_9280_2GHZ, AR_PHY_CCA_NOM_VAL_9280_5GHZ, AR_PHY_CCA_NOM_VAL_9285_2GHZ, AR_PHY_CCA_NOM_VAL_9287_2GHZ, AR_SREV_9271, AR_SREV_9285, and AR_SREV_9287.
Referenced by ar9002_hw_attach_phy_ops().
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Definition at line 526 of file ath9k_ar9002_phy.c.
References ah, ath_hw_antcomb_conf::alt_lna_conf, AR_PHY_9285_ANT_DIV_ALT_LNACONF, AR_PHY_9285_ANT_DIV_ALT_LNACONF_S, AR_PHY_9285_ANT_DIV_MAIN_LNACONF, AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S, AR_PHY_9285_FAST_DIV_BIAS, AR_PHY_9285_FAST_DIV_BIAS_S, AR_PHY_MULTICHAIN_GAIN_CTL, ath_hw_antcomb_conf::div_group, ath_hw_antcomb_conf::fast_div_bias, ath_hw_antcomb_conf::lna1_lna2_delta, ath_hw_antcomb_conf::main_lna_conf, and REG_READ.
Referenced by ar9002_hw_attach_phy_ops().
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Definition at line 542 of file ath9k_ar9002_phy.c.
References ah, ath_hw_antcomb_conf::alt_lna_conf, AR_PHY_9285_ANT_DIV_ALT_LNACONF, AR_PHY_9285_ANT_DIV_ALT_LNACONF_S, AR_PHY_9285_ANT_DIV_MAIN_LNACONF, AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S, AR_PHY_9285_FAST_DIV_BIAS, AR_PHY_9285_FAST_DIV_BIAS_S, AR_PHY_MULTICHAIN_GAIN_CTL, ath_hw_antcomb_conf::fast_div_bias, ath_hw_antcomb_conf::main_lna_conf, REG_READ, and REG_WRITE.
Referenced by ar9002_hw_attach_phy_ops().
void ar9002_hw_attach_phy_ops | ( | struct ath_hw * | ah | ) |
Definition at line 561 of file ath9k_ar9002_phy.c.
References ah, ath_hw_ops::antdiv_comb_conf_get, ath_hw_ops::antdiv_comb_conf_set, ar9002_hw_antdiv_comb_conf_get(), ar9002_hw_antdiv_comb_conf_set(), ar9002_hw_compute_pll_control(), ar9002_hw_do_getnf(), ar9002_hw_set_channel(), ar9002_hw_set_nf_limits(), ar9002_hw_spur_mitigate(), ar9002_olc_init(), ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, NULL, ath_hw_private_ops::olc_init, ath_hw_private_ops::rf_alloc_ext_banks, ath_hw_private_ops::rf_free_ext_banks, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::set_rf_regs, and ath_hw_private_ops::spur_mitigate_freq.
Referenced by ar9002_hw_attach_ops().