iPXE
Functions
ath9k_ar9003_hw.c File Reference
#include "hw.h"
#include "ar9003_mac.h"
#include "ar9003_2p2_initvals.h"
#include "ar9485_initvals.h"
#include "ar9340_initvals.h"

Go to the source code of this file.

Functions

static void ar9003_hw_init_mode_regs (struct ath_hw *ah)
static void ar9003_tx_gain_table_apply (struct ath_hw *ah)
static void ar9003_rx_gain_table_apply (struct ath_hw *ah)
static void ar9003_hw_init_mode_gain_regs (struct ath_hw *ah)
static void ar9003_hw_configpcipowersave (struct ath_hw *ah, int restore, int power_off)
void ar9003_hw_attach_ops (struct ath_hw *ah)

Function Documentation

static void ar9003_hw_init_mode_regs ( struct ath_hw ah) [static]

Definition at line 33 of file ath9k_ar9003_hw.c.

References ar9300_2p2_baseband_core, ar9300_2p2_baseband_postamble, ar9300_2p2_mac_core, ar9300_2p2_mac_postamble, ar9300_2p2_radio_core, ar9300_2p2_radio_postamble, ar9300_2p2_soc_postamble, ar9300_2p2_soc_preamble, ar9300Common_rx_gain_table_2p2, ar9300Modes_fast_clock_2p2, ar9300Modes_lowest_ob_db_tx_gain_table_2p2, ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, ar9340_1p0_baseband_core, ar9340_1p0_baseband_postamble, ar9340_1p0_mac_core, ar9340_1p0_mac_postamble, ar9340_1p0_radio_core, ar9340_1p0_radio_core_40M, ar9340_1p0_radio_postamble, ar9340_1p0_soc_postamble, ar9340_1p0_soc_preamble, ar9340Common_wo_xlna_rx_gain_table_1p0, ar9340Modes_fast_clock_1p0, ar9340Modes_high_ob_db_tx_gain_table_1p0, ar9485_1_1, ar9485_1_1_baseband_core, ar9485_1_1_baseband_postamble, ar9485_1_1_mac_core, ar9485_1_1_mac_postamble, ar9485_1_1_pcie_phy_clkreq_disable_L1, ar9485_1_1_radio_core, ar9485_1_1_radio_postamble, ar9485_1_1_soc_preamble, ar9485_modes_lowest_ob_db_tx_gain_1_1, ar9485Common_wo_xlna_rx_gain_1_1, AR_SREV_9340, AR_SREV_9485_11, ARRAY_SIZE, ATH_INI_CORE, ATH_INI_POST, ATH_INI_PRE, ath_hw::iniBB, ath_hw::iniMac, ath_hw::iniModesAdditional, ath_hw::iniModesAdditional_40M, ath_hw::iniModesRxGain, ath_hw::iniModesTxGain, ath_hw::iniPcieSerdes, ath_hw::iniPcieSerdesLowPower, ath_hw::iniRadio, ath_hw::iniSOC, INIT_INI_ARRAY, and NULL.

Referenced by ar9003_hw_attach_ops().

{
        if (AR_SREV_9340(ah)) {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
                                ar9340_1p0_mac_core,
                                ARRAY_SIZE(ar9340_1p0_mac_core), 2);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
                                ar9340_1p0_mac_postamble,
                                ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);

                /* bb */
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
                                ar9340_1p0_baseband_core,
                                ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
                                ar9340_1p0_baseband_postamble,
                                ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);

                /* radio */
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
                                ar9340_1p0_radio_core,
                                ARRAY_SIZE(ar9340_1p0_radio_core), 2);
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
                                ar9340_1p0_radio_postamble,
                                ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);

                /* soc */
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
                                ar9340_1p0_soc_preamble,
                                ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
                                ar9340_1p0_soc_postamble,
                                ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);

                /* rx/tx gain */
                INIT_INI_ARRAY(&ah->iniModesRxGain,
                                ar9340Common_wo_xlna_rx_gain_table_1p0,
                                ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
                                5);
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                                ar9340Modes_high_ob_db_tx_gain_table_1p0,
                                ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
                                5);

                INIT_INI_ARRAY(&ah->iniModesAdditional,
                                ar9340Modes_fast_clock_1p0,
                                ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
                                3);

                INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
                                ar9340_1p0_radio_core_40M,
                                ARRAY_SIZE(ar9340_1p0_radio_core_40M),
                                2);
        } else if (AR_SREV_9485_11(ah)) {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
                                ar9485_1_1_mac_core,
                                ARRAY_SIZE(ar9485_1_1_mac_core), 2);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
                                ar9485_1_1_mac_postamble,
                                ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);

                /* bb */
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
                                ARRAY_SIZE(ar9485_1_1), 2);
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
                                ar9485_1_1_baseband_core,
                                ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
                                ar9485_1_1_baseband_postamble,
                                ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);

                /* radio */
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
                                ar9485_1_1_radio_core,
                                ARRAY_SIZE(ar9485_1_1_radio_core), 2);
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
                                ar9485_1_1_radio_postamble,
                                ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);

                /* soc */
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
                                ar9485_1_1_soc_preamble,
                                ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);

                /* rx/tx gain */
                INIT_INI_ARRAY(&ah->iniModesRxGain,
                                ar9485Common_wo_xlna_rx_gain_1_1,
                                ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                                ar9485_modes_lowest_ob_db_tx_gain_1_1,
                                ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
                                5);

                /* Load PCIE SERDES settings from INI */

                /* Awake Setting */

                INIT_INI_ARRAY(&ah->iniPcieSerdes,
                                ar9485_1_1_pcie_phy_clkreq_disable_L1,
                                ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
                                2);

                /* Sleep Setting */

                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
                                ar9485_1_1_pcie_phy_clkreq_disable_L1,
                                ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
                                2);
        } else {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
                                ar9300_2p2_mac_core,
                                ARRAY_SIZE(ar9300_2p2_mac_core), 2);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
                                ar9300_2p2_mac_postamble,
                                ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);

                /* bb */
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
                                ar9300_2p2_baseband_core,
                                ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
                                ar9300_2p2_baseband_postamble,
                                ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);

                /* radio */
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
                                ar9300_2p2_radio_core,
                                ARRAY_SIZE(ar9300_2p2_radio_core), 2);
                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
                                ar9300_2p2_radio_postamble,
                                ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);

                /* soc */
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
                                ar9300_2p2_soc_preamble,
                                ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
                                ar9300_2p2_soc_postamble,
                                ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);

                /* rx/tx gain */
                INIT_INI_ARRAY(&ah->iniModesRxGain,
                                ar9300Common_rx_gain_table_2p2,
                                ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                                ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
                                ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
                                5);

                /* Load PCIE SERDES settings from INI */

                /* Awake Setting */

                INIT_INI_ARRAY(&ah->iniPcieSerdes,
                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
                                2);

                /* Sleep Setting */

                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
                                2);

                /* Fast clock modal settings */
                INIT_INI_ARRAY(&ah->iniModesAdditional,
                                ar9300Modes_fast_clock_2p2,
                                ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
                                3);
        }
}
static void ar9003_tx_gain_table_apply ( struct ath_hw ah) [static]

Definition at line 221 of file ath9k_ar9003_hw.c.

References ar9003_hw_get_tx_gain_idx(), ar9300Modes_high_ob_db_tx_gain_table_2p2, ar9300Modes_high_power_tx_gain_table_2p2, ar9300Modes_low_ob_db_tx_gain_table_2p2, ar9300Modes_lowest_ob_db_tx_gain_table_2p2, ar9340Modes_lowest_ob_db_tx_gain_table_1p0, ar9485_modes_lowest_ob_db_tx_gain_1_1, ar9485Modes_high_ob_db_tx_gain_1_1, ar9485Modes_high_power_tx_gain_1_1, ar9485Modes_low_ob_db_tx_gain_1_1, AR_SREV_9340, AR_SREV_9485_11, ARRAY_SIZE, ath_hw::iniModesTxGain, and INIT_INI_ARRAY.

Referenced by ar9003_hw_init_mode_gain_regs().

{
        switch (ar9003_hw_get_tx_gain_idx(ah)) {
        case 0:
        default:
                if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
                                       5);
                else if (AR_SREV_9485_11(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9485_modes_lowest_ob_db_tx_gain_1_1,
                                       ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
                                       5);
                else
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
                                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
                                       5);
                break;
        case 1:
                if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
                                       5);
                else if (AR_SREV_9485_11(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9485Modes_high_ob_db_tx_gain_1_1,
                                       ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
                                       5);
                else
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9300Modes_high_ob_db_tx_gain_table_2p2,
                                       ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
                                       5);
                break;
        case 2:
                if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
                                       5);
                else if (AR_SREV_9485_11(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9485Modes_low_ob_db_tx_gain_1_1,
                                       ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
                                       5);
                else
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9300Modes_low_ob_db_tx_gain_table_2p2,
                                       ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
                                       5);
                break;
        case 3:
                if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
                                       5);
                else if (AR_SREV_9485_11(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9485Modes_high_power_tx_gain_1_1,
                                       ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
                                       5);
                else
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                       ar9300Modes_high_power_tx_gain_table_2p2,
                                       ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
                                       5);
                break;
        }
}
static void ar9003_rx_gain_table_apply ( struct ath_hw ah) [static]
static void ar9003_hw_init_mode_gain_regs ( struct ath_hw ah) [static]
static void ar9003_hw_configpcipowersave ( struct ath_hw ah,
int  restore,
int  power_off 
) [static]

Definition at line 353 of file ath9k_ar9003_hw.c.

References AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA, AR_WA, array, ath_hw::config, ar5416IniArray::ia_rows, INI_RA, ath_hw::iniPcieSerdes, ath_hw::iniPcieSerdesLowPower, ath_hw::is_pciexpress, ath9k_ops_config::pcie_powersave_enable, ath9k_ops_config::pcie_waen, ath9k_ops_config::pcieSerDesWrite, REG_SET_BIT, REG_WRITE, and ath_hw::WARegVal.

Referenced by ar9003_hw_attach_ops().

{
        if (ah->is_pciexpress != 1)
                return;

        /* Do not touch SerDes registers */
        if (ah->config.pcie_powersave_enable == 2)
                return;

        /* Nothing to do on restore for 11N */
        if (!restore) {
                /* set bit 19 to allow forcing of pcie core into L1 state */
                REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);

                /* Several PCIe massages to ensure proper behaviour */
                if (ah->config.pcie_waen)
                        REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
                else
                        REG_WRITE(ah, AR_WA, ah->WARegVal);
        }

        /*
         * Configire PCIE after Ini init. SERDES values now come from ini file
         * This enables PCIe low power mode.
         */
        if (ah->config.pcieSerDesWrite) {
                unsigned int i;
                struct ar5416IniArray *array;

                array = power_off ? &ah->iniPcieSerdes :
                                    &ah->iniPcieSerdesLowPower;

                for (i = 0; i < array->ia_rows; i++) {
                        REG_WRITE(ah,
                                  INI_RA(array, i, 0),
                                  INI_RA(array, i, 1));
                }
        }
}
void ar9003_hw_attach_ops ( struct ath_hw ah)