iPXE
Defines | Functions
ath9k_ar9003_mac.c File Reference
#include <ipxe/io.h>
#include "hw.h"
#include "ar9003_mac.h"

Go to the source code of this file.

Defines

#define FIRST_DESC_NDELIMS   60

Functions

static void ar9003_hw_rx_enable (struct ath_hw *hw)
static u16 ar9003_calc_ptr_chksum (struct ar9003_txc *ads)
static void ar9003_hw_set_desc_link (void *ds, u32 ds_link)
static void ar9003_hw_get_desc_link (void *ds, u32 **ds_link)
static int ar9003_hw_get_isr (struct ath_hw *ah, enum ath9k_int *masked)
static void ar9003_hw_fill_txdesc (struct ath_hw *ah __unused, void *ds, u32 seglen, int is_firstseg, int is_lastseg, const void *ds0, u32 buf_addr, unsigned int qcu)
static int ar9003_hw_proc_txdesc (struct ath_hw *ah, void *ds __unused, struct ath_tx_status *ts)
static void ar9003_hw_set11n_txdesc (struct ath_hw *ah, void *ds, u32 pktlen, enum ath9k_pkt_type type, u32 txpower, u32 keyIx, enum ath9k_key_type keyType, u32 flags)
static void ar9003_hw_set_clrdmask (struct ath_hw *ah __unused, void *ds, int val)
static void ar9003_hw_set11n_ratescenario (struct ath_hw *ah __unused, void *ds, void *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration __unused, struct ath9k_11n_rate_series series[], u32 nseries __unused, u32 flags)
static void ar9003_hw_set11n_aggr_first (struct ath_hw *ah, void *ds, u32 aggrLen)
static void ar9003_hw_set11n_aggr_middle (struct ath_hw *ah __unused, void *ds, u32 numDelims)
static void ar9003_hw_set11n_aggr_last (struct ath_hw *ah __unused, void *ds)
static void ar9003_hw_clr11n_aggr (struct ath_hw *ah __unused, void *ds)
void ar9003_hw_set_paprd_txdesc (struct ath_hw *ah __unused, void *ds, u8 chains)
void ar9003_hw_attach_mac_ops (struct ath_hw *hw)
void ath9k_hw_set_rx_bufsize (struct ath_hw *ah, u16 buf_size)
void ath9k_hw_addrxbuf_edma (struct ath_hw *ah, u32 rxdp, enum ath9k_rx_qtype qtype)
int ath9k_hw_process_rxdesc_edma (struct ath_hw *ah __unused, struct ath_rx_status *rxs, void *buf_addr)
void ath9k_hw_reset_txstatus_ring (struct ath_hw *ah)
void ath9k_hw_setup_statusring (struct ath_hw *ah, void *ts_start, u32 ts_paddr_start, u8 size)

Define Documentation

#define FIRST_DESC_NDELIMS   60

Function Documentation

static void ar9003_hw_rx_enable ( struct ath_hw hw) [static]

Definition at line 24 of file ath9k_ar9003_mac.c.

References AR_CR, and REG_WRITE.

Referenced by ar9003_hw_attach_mac_ops().

{
        REG_WRITE(hw, AR_CR, 0);
}
static u16 ar9003_calc_ptr_chksum ( struct ar9003_txc ads) [static]

Definition at line 29 of file ath9k_ar9003_mac.c.

References AR_TxPtrChkSum, checksum, ar9003_txc::ctl3, ar9003_txc::ctl5, ar9003_txc::ctl7, ar9003_txc::ctl9, ar9003_txc::data0, ar9003_txc::data1, ar9003_txc::data2, ar9003_txc::data3, ar9003_txc::info, and ar9003_txc::link.

Referenced by ar9003_hw_fill_txdesc(), and ar9003_hw_set_desc_link().

{
        int checksum;

        checksum = ads->info + ads->link
                + ads->data0 + ads->ctl3
                + ads->data1 + ads->ctl5
                + ads->data2 + ads->ctl7
                + ads->data3 + ads->ctl9;

        return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
}
static void ar9003_hw_set_desc_link ( void *  ds,
u32  ds_link 
) [static]

Definition at line 42 of file ath9k_ar9003_mac.c.

References ar9003_calc_ptr_chksum(), AR_TxPtrChkSum, ar9003_txc::ctl10, ds, ds_link, and ar9003_txc::link.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = ds;

        ads->link = ds_link;
        ads->ctl10 &= ~AR_TxPtrChkSum;
        ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
}
static void ar9003_hw_get_desc_link ( void *  ds,
u32 **  ds_link 
) [static]

Definition at line 51 of file ath9k_ar9003_mac.c.

References ds, and ar9003_txc::link.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = ds;

        *ds_link = &ads->link;
}
static int ar9003_hw_get_isr ( struct ath_hw ah,
enum ath9k_int masked 
) [static]

Definition at line 58 of file ath9k_ar9003_mac.c.

References ath_hw::ah_ier, AR_IER_ENABLE, AR_INTR_ASYNC_CAUSE, AR_INTR_MAC_IRQ, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_CAUSE_CLR, AR_INTR_SYNC_DEFAULT, AR_INTR_SYNC_LOCAL_TIMEOUT, AR_INTR_SYNC_RADM_CPL_TIMEOUT, AR_ISR, AR_ISR_BCNMISC, AR_ISR_GENTMR, AR_ISR_HP_RXOK, AR_ISR_LP_RXOK, AR_ISR_RAC, AR_ISR_RXERR, AR_ISR_RXINTM, AR_ISR_RXMINTR, AR_ISR_S0, AR_ISR_S1, AR_ISR_S2, AR_ISR_S2_BB_WATCHDOG, AR_ISR_S2_CABEND, AR_ISR_S2_CST, AR_ISR_S2_DTIM, AR_ISR_S2_DTIMSYNC, AR_ISR_S2_GTT, AR_ISR_S2_TIM, AR_ISR_S2_TSFOOR, AR_ISR_S5, AR_ISR_S5_GENTIMER_THRESH, AR_ISR_S5_GENTIMER_TRIG, AR_ISR_S5_S, AR_ISR_TXEOL, AR_ISR_TXERR, AR_ISR_TXINTM, AR_ISR_TXMINTR, AR_ISR_TXOK, AR_RC, AR_RC_HOSTIF, AR_RTC_STATUS, AR_RTC_STATUS_M, AR_RTC_STATUS_ON, ATH9K_HW_CAP_RAC_SUPPORTED, ATH9K_INT_COMMON, ATH9K_INT_FATAL, ATH9K_INT_GENTIMER, ATH9K_INT_RXHP, ATH9K_INT_RXLP, ATH9K_INT_TX, ath_hw::caps, ath_hw::config, DBG, ath9k_hw_capabilities::hw_caps, ath_hw::intr_gen_timer_thresh, ath_hw::intr_gen_timer_trigger, isr, MAP_ISR_S2_BB_WATCHDOG, MAP_ISR_S2_CABEND, MAP_ISR_S2_CST, MAP_ISR_S2_DTIM, MAP_ISR_S2_DTIMSYNC, MAP_ISR_S2_GTT, MAP_ISR_S2_TIM, MAP_ISR_S2_TSFOOR, MS, REG_READ, REG_WRITE, ath9k_ops_config::rx_intr_mitigation, and ath9k_ops_config::tx_intr_mitigation.

Referenced by ar9003_hw_attach_mac_ops().

{
        u32 isr = 0;
        u32 mask2 = 0;
        struct ath9k_hw_capabilities *pCap = &ah->caps;
        u32 sync_cause = 0;

        if (ah->ah_ier & AR_IER_ENABLE) {
                if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
                        if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
                                        == AR_RTC_STATUS_ON)
                                isr = REG_READ(ah, AR_ISR);
                }

                sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;

                *masked = 0;

                if (!isr && !sync_cause)
                        return 0;
        } else {
                *masked = 0;
                isr = REG_READ(ah, AR_ISR);
        }

        if (isr) {
                if (isr & AR_ISR_BCNMISC) {
                        u32 isr2;
                        isr2 = REG_READ(ah, AR_ISR_S2);

                        mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
                                  MAP_ISR_S2_TIM);
                        mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
                                  MAP_ISR_S2_DTIM);
                        mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
                                  MAP_ISR_S2_DTIMSYNC);
                        mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
                                  MAP_ISR_S2_CABEND);
                        mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
                                  MAP_ISR_S2_GTT);
                        mask2 |= ((isr2 & AR_ISR_S2_CST) <<
                                  MAP_ISR_S2_CST);
                        mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
                                  MAP_ISR_S2_TSFOOR);
                        mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
                                  MAP_ISR_S2_BB_WATCHDOG);

                        if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
                                REG_WRITE(ah, AR_ISR_S2, isr2);
                                isr &= ~AR_ISR_BCNMISC;
                        }
                }

                if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
                        isr = REG_READ(ah, AR_ISR_RAC);

                if (isr == 0xffffffff) {
                        *masked = 0;
                        return 0;
                }

                *masked = isr & ATH9K_INT_COMMON;

                if (ah->config.rx_intr_mitigation)
                        if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
                                *masked |= ATH9K_INT_RXLP;

                if (ah->config.tx_intr_mitigation)
                        if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
                                *masked |= ATH9K_INT_TX;

                if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
                        *masked |= ATH9K_INT_RXLP;

                if (isr & AR_ISR_HP_RXOK)
                        *masked |= ATH9K_INT_RXHP;

                if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
                        *masked |= ATH9K_INT_TX;

                        if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
                                u32 s0, s1;
                                s0 = REG_READ(ah, AR_ISR_S0);
                                REG_WRITE(ah, AR_ISR_S0, s0);
                                s1 = REG_READ(ah, AR_ISR_S1);
                                REG_WRITE(ah, AR_ISR_S1, s1);

                                isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
                                         AR_ISR_TXEOL);
                        }
                }

                if (isr & AR_ISR_GENTMR) {
                        u32 s5;

                        if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
                                s5 = REG_READ(ah, AR_ISR_S5_S);
                        else
                                s5 = REG_READ(ah, AR_ISR_S5);

                        ah->intr_gen_timer_trigger =
                                MS(s5, AR_ISR_S5_GENTIMER_TRIG);

                        ah->intr_gen_timer_thresh =
                                MS(s5, AR_ISR_S5_GENTIMER_THRESH);

                        if (ah->intr_gen_timer_trigger)
                                *masked |= ATH9K_INT_GENTIMER;

                        if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
                                REG_WRITE(ah, AR_ISR_S5, s5);
                                isr &= ~AR_ISR_GENTMR;
                        }

                }

                *masked |= mask2;

                if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
                        REG_WRITE(ah, AR_ISR, isr);

                        (void) REG_READ(ah, AR_ISR);
                }
        }

        if (sync_cause) {
                if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
                        REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
                        REG_WRITE(ah, AR_RC, 0);
                        *masked |= ATH9K_INT_FATAL;
                }

                if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
                        DBG("ath9k: "
                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");

                REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
                (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);

        }
        return 1;
}
static void ar9003_hw_fill_txdesc ( struct ath_hw *ah  __unused,
void *  ds,
u32  seglen,
int  is_firstseg,
int  is_lastseg,
const void *  ds0,
u32  buf_addr,
unsigned int  qcu 
) [static]

Definition at line 201 of file ath9k_ar9003_mac.c.

References ar9003_calc_ptr_chksum(), AR9003TXC_CONST, AR_BufLen, AR_BufLen_S, AR_CtrlStat_S, AR_DescId_S, AR_TxDescId_S, AR_TxMore, AR_TxQcuNum_S, AR_TxRxDesc_S, ATHEROS_VENDOR_ID, ar9003_txc::ctl10, ar9003_txc::ctl11, ar9003_txc::ctl12, ar9003_txc::ctl13, ar9003_txc::ctl14, ar9003_txc::ctl3, ar9003_txc::data0, ar9003_txc::data1, ar9003_txc::data2, ar9003_txc::data3, and ar9003_txc::info.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
        unsigned int descid = 0;

        ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
                                     (1 << AR_TxRxDesc_S) |
                                     (1 << AR_CtrlStat_S) |
                                     (qcu << AR_TxQcuNum_S) | 0x17;

        ads->data0 = buf_addr;
        ads->data1 = 0;
        ads->data2 = 0;
        ads->data3 = 0;

        ads->ctl3 = (seglen << AR_BufLen_S);
        ads->ctl3 &= AR_BufLen;

        /* Fill in pointer checksum and descriptor id */
        ads->ctl10 = ar9003_calc_ptr_chksum(ads);
        ads->ctl10 |= (descid << AR_TxDescId_S);

        if (is_firstseg) {
                ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
        } else if (is_lastseg) {
                ads->ctl11 = 0;
                ads->ctl12 = 0;
                ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
                ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
        } else {
                /* XXX Intermediate descriptor in a multi-descriptor frame.*/
                ads->ctl11 = 0;
                ads->ctl12 = AR_TxMore;
                ads->ctl13 = 0;
                ads->ctl14 = 0;
        }
}
static int ar9003_hw_proc_txdesc ( struct ath_hw ah,
void *ds  __unused,
struct ath_tx_status ts 
) [static]

Definition at line 242 of file ath9k_ar9003_mac.c.

References AR_DataFailCnt, AR_DescCfgErr, AR_DescId, AR_ExcessiveRetries, AR_FIFOUnderrun, AR_Filtered, AR_FinalTxIdx, AR_RTSFailCnt, AR_SeqNum, AR_TxBaStatus, AR_TxDataUnderrun, AR_TxDelimUnderrun, AR_TxDescId, AR_TxDone, AR_TxOpExceeded, AR_TxQcuNum, AR_TxRSSIAnt00, AR_TxRSSIAnt01, AR_TxRSSIAnt02, AR_TxRSSIAnt10, AR_TxRSSIAnt11, AR_TxRSSIAnt12, AR_TxRSSICombined, AR_TxRxDesc, AR_TxTid, AR_TxTimerExpired, AR_VirtRetryCnt, ath9k_hw_updatetxtriglevel(), ATH9K_TX_BA, ATH9K_TX_DATA_UNDERRUN, ATH9K_TX_DELIM_UNDERRUN, ATH9K_TX_DESC_CFG_ERR, ATH9K_TXERR_FIFO, ATH9K_TXERR_FILT, ATH9K_TXERR_TIMER_EXPIRED, ATH9K_TXERR_XRETRY, ATH9K_TXERR_XTXOP, ATHEROS_VENDOR_ID, ath_tx_status::ba_high, ath_tx_status::ba_low, DBG, ath_tx_status::desc_id, ar9003_txs::ds_info, EINPROGRESS, EIO, memset(), MS, ath_tx_status::qid, status, ar9003_txs::status1, ar9003_txs::status2, ar9003_txs::status3, ar9003_txs::status4, ar9003_txs::status5, ar9003_txs::status6, ar9003_txs::status7, ar9003_txs::status8, ath_tx_status::tid, ath_tx_status::ts_flags, ath_tx_status::ts_longretry, ath_tx_status::ts_rateindex, ath_hw::ts_ring, ath_tx_status::ts_rssi, ath_tx_status::ts_rssi_ctl0, ath_tx_status::ts_rssi_ctl1, ath_tx_status::ts_rssi_ctl2, ath_tx_status::ts_rssi_ext0, ath_tx_status::ts_rssi_ext1, ath_tx_status::ts_rssi_ext2, ath_tx_status::ts_seqnum, ath_tx_status::ts_shortretry, ath_hw::ts_size, ath_tx_status::ts_status, ath_hw::ts_tail, ath_tx_status::ts_tstamp, and ath_tx_status::ts_virtcol.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txs *ads;
        u32 status;

        ads = &ah->ts_ring[ah->ts_tail];

        status = *(volatile typeof(ads->status8) *)&(ads->status8);
        if ((status & AR_TxDone) == 0)
                return -EINPROGRESS;

        ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;

        if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
            (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
                DBG("ath9k: "
                        "Tx Descriptor error %x\n", ads->ds_info);
                memset(ads, 0, sizeof(*ads));
                return -EIO;
        }

        if (status & AR_TxOpExceeded)
                ts->ts_status |= ATH9K_TXERR_XTXOP;
        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
        ts->ts_seqnum = MS(status, AR_SeqNum);
        ts->tid = MS(status, AR_TxTid);

        ts->qid = MS(ads->ds_info, AR_TxQcuNum);
        ts->desc_id = MS(ads->status1, AR_TxDescId);
        ts->ts_tstamp = ads->status4;
        ts->ts_status = 0;
        ts->ts_flags  = 0;

        status = *(volatile typeof(ads->status2) *)&(ads->status2);
        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
        if (status & AR_TxBaStatus) {
                ts->ts_flags |= ATH9K_TX_BA;
                ts->ba_low = ads->status5;
                ts->ba_high = ads->status6;
        }

        status = *(volatile typeof(ads->status3) *)&(ads->status3);
        if (status & AR_ExcessiveRetries)
                ts->ts_status |= ATH9K_TXERR_XRETRY;
        if (status & AR_Filtered)
                ts->ts_status |= ATH9K_TXERR_FILT;
        if (status & AR_FIFOUnderrun) {
                ts->ts_status |= ATH9K_TXERR_FIFO;
                ath9k_hw_updatetxtriglevel(ah, 1);
        }
        if (status & AR_TxTimerExpired)
                ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
        if (status & AR_DescCfgErr)
                ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
        if (status & AR_TxDataUnderrun) {
                ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                ath9k_hw_updatetxtriglevel(ah, 1);
        }
        if (status & AR_TxDelimUnderrun) {
                ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                ath9k_hw_updatetxtriglevel(ah, 1);
        }
        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
        ts->ts_longretry = MS(status, AR_DataFailCnt);
        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);

        status = *(volatile typeof(ads->status7) *)&(ads->status7);
        ts->ts_rssi = MS(status, AR_TxRSSICombined);
        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);

        memset(ads, 0, sizeof(*ads));

        return 0;
}
static void ar9003_hw_set11n_txdesc ( struct ath_hw ah,
void *  ds,
u32  pktlen,
enum ath9k_pkt_type  type,
u32  txpower,
u32  keyIx,
enum ath9k_key_type  keyType,
u32  flags 
) [static]
static void ar9003_hw_set_clrdmask ( struct ath_hw *ah  __unused,
void *  ds,
int  val 
) [static]

Definition at line 358 of file ath9k_ar9003_mac.c.

References AR_ClrDestMask, and ar9003_txc::ctl11.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;

        if (val)
                ads->ctl11 |= AR_ClrDestMask;
        else
                ads->ctl11 &= ~AR_ClrDestMask;
}
static void ar9003_hw_set11n_ratescenario ( struct ath_hw *ah  __unused,
void *  ds,
void *  lastds,
u32  durUpdateEn,
u32  rtsctsRate,
u32 rtsctsDuration  __unused,
struct ath9k_11n_rate_series  series[],
u32 nseries  __unused,
u32  flags 
) [static]

Definition at line 368 of file ath9k_ar9003_mac.c.

References AR_BurstDur, AR_CTSEnable, AR_DurUpdateEna, AR_Not_Sounding, AR_RTSCTSRate, AR_RTSEnable, ATH9K_TXDESC_CTSENA, ATH9K_TXDESC_RTSENA, ar9003_txc::ctl11, ctl11, ar9003_txc::ctl13, ar9003_txc::ctl14, ar9003_txc::ctl15, ar9003_txc::ctl16, ar9003_txc::ctl18, ar9003_txc::ctl19, set11nPktDurRTSCTS, set11nRate, set11nRateFlags, set11nTries, and SM.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
        struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
        uint32_t ctl11;

        if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
                ctl11 = ads->ctl11;

                if (flags & ATH9K_TXDESC_RTSENA) {
                        ctl11 &= ~AR_CTSEnable;
                        ctl11 |= AR_RTSEnable;
                } else {
                        ctl11 &= ~AR_RTSEnable;
                        ctl11 |= AR_CTSEnable;
                }

                ads->ctl11 = ctl11;
        } else {
                ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
        }

        ads->ctl13 = set11nTries(series, 0)
                |  set11nTries(series, 1)
                |  set11nTries(series, 2)
                |  set11nTries(series, 3)
                |  (durUpdateEn ? AR_DurUpdateEna : 0)
                |  SM(0, AR_BurstDur);

        ads->ctl14 = set11nRate(series, 0)
                |  set11nRate(series, 1)
                |  set11nRate(series, 2)
                |  set11nRate(series, 3);

        ads->ctl15 = set11nPktDurRTSCTS(series, 0)
                |  set11nPktDurRTSCTS(series, 1);

        ads->ctl16 = set11nPktDurRTSCTS(series, 2)
                |  set11nPktDurRTSCTS(series, 3);

        ads->ctl18 = set11nRateFlags(series, 0)
                |  set11nRateFlags(series, 1)
                |  set11nRateFlags(series, 2)
                |  set11nRateFlags(series, 3)
                | SM(rtsctsRate, AR_RTSCTSRate);
        ads->ctl19 = AR_Not_Sounding;

        last_ads->ctl13 = ads->ctl13;
        last_ads->ctl14 = ads->ctl14;
}
static void ar9003_hw_set11n_aggr_first ( struct ath_hw ah,
void *  ds,
u32  aggrLen 
) [static]

Definition at line 424 of file ath9k_ar9003_mac.c.

References AR_AggrLen, AR_ENT_OTP_MPSD, AR_IsAggr, AR_MoreAggr, AR_PadDelim, ar9003_txc::ctl12, ar9003_txc::ctl17, ctl17, ath_hw::ent_mode, FIRST_DESC_NDELIMS, MS, and SM.

Referenced by ar9003_hw_attach_mac_ops().

{
#define FIRST_DESC_NDELIMS 60
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;

        ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);

        if (ah->ent_mode & AR_ENT_OTP_MPSD) {
                u32 ctl17, ndelim;
                /*
                 * Add delimiter when using RTS/CTS with aggregation
                 * and non enterprise AR9003 card
                 */
                ctl17 = ads->ctl17;
                ndelim = MS(ctl17, AR_PadDelim);

                if (ndelim < FIRST_DESC_NDELIMS) {
                        aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
                        ndelim = FIRST_DESC_NDELIMS;
                }

                ctl17 &= ~AR_AggrLen;
                ctl17 |= SM(aggrLen, AR_AggrLen);

                ctl17 &= ~AR_PadDelim;
                ctl17 |= SM(ndelim, AR_PadDelim);

                ads->ctl17 = ctl17;
        } else {
                ads->ctl17 &= ~AR_AggrLen;
                ads->ctl17 |= SM(aggrLen, AR_AggrLen);
        }
}
static void ar9003_hw_set11n_aggr_middle ( struct ath_hw *ah  __unused,
void *  ds,
u32  numDelims 
) [static]

Definition at line 459 of file ath9k_ar9003_mac.c.

References AR_IsAggr, AR_MoreAggr, AR_PadDelim, ar9003_txc::ctl12, ar9003_txc::ctl17, ctl17, and SM.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
        unsigned int ctl17;

        ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);

        /*
         * We use a stack variable to manipulate ctl6 to reduce uncached
         * read modify, modfiy, write.
         */
        ctl17 = ads->ctl17;
        ctl17 &= ~AR_PadDelim;
        ctl17 |= SM(numDelims, AR_PadDelim);
        ads->ctl17 = ctl17;
}
static void ar9003_hw_set11n_aggr_last ( struct ath_hw *ah  __unused,
void *  ds 
) [static]

Definition at line 477 of file ath9k_ar9003_mac.c.

References AR_IsAggr, AR_MoreAggr, AR_PadDelim, ar9003_txc::ctl12, and ar9003_txc::ctl17.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;

        ads->ctl12 |= AR_IsAggr;
        ads->ctl12 &= ~AR_MoreAggr;
        ads->ctl17 &= ~AR_PadDelim;
}
static void ar9003_hw_clr11n_aggr ( struct ath_hw *ah  __unused,
void *  ds 
) [static]

Definition at line 486 of file ath9k_ar9003_mac.c.

References AR_IsAggr, AR_MoreAggr, and ar9003_txc::ctl12.

Referenced by ar9003_hw_attach_mac_ops().

{
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;

        ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
}
void ar9003_hw_set_paprd_txdesc ( struct ath_hw *ah  __unused,
void *  ds,
u8  chains 
)

Definition at line 493 of file ath9k_ar9003_mac.c.

References AR_PAPRDChainMask, ar9003_txc::ctl12, ds, and SM.

{
        struct ar9003_txc *ads = ds;

        ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
}
void ar9003_hw_attach_mac_ops ( struct ath_hw hw)
void ath9k_hw_set_rx_bufsize ( struct ath_hw ah,
u16  buf_size 
)

Definition at line 519 of file ath9k_ar9003_mac.c.

References AR_DATABUF_SIZE, AR_DATABUF_SIZE_MASK, and REG_WRITE.

Referenced by ath9k_hw_set_dma().

void ath9k_hw_addrxbuf_edma ( struct ath_hw ah,
u32  rxdp,
enum ath9k_rx_qtype  qtype 
)

Definition at line 524 of file ath9k_ar9003_mac.c.

References AR_HP_RXDP, AR_LP_RXDP, ATH9K_RX_QUEUE_HP, and REG_WRITE.

{
        if (qtype == ATH9K_RX_QUEUE_HP)
                REG_WRITE(ah, AR_HP_RXDP, rxdp);
        else
                REG_WRITE(ah, AR_LP_RXDP, rxdp);
}
int ath9k_hw_process_rxdesc_edma ( struct ath_hw *ah  __unused,
struct ath_rx_status rxs,
void *  buf_addr 
)

Definition at line 533 of file ath9k_ar9003_mac.c.

References AR_2040, AR_CRCErr, AR_CtrlStat, AR_DataLen, AR_DecryptBusyErr, AR_DecryptCRCErr, AR_DescId, AR_GI, AR_KeyIdx, AR_KeyMiss, AR_MichaelErr, AR_PHYErr, AR_PHYErrCode, AR_PostDelimCRCErr, AR_PreDelimCRCErr, AR_RxAggr, AR_RxAntenna, AR_RxDone, AR_RxFrameOK, AR_RxKeyIdxValid, AR_RxMore, AR_RxMoreAggr, AR_RxRate, AR_RxRSSIAnt00, AR_RxRSSIAnt01, AR_RxRSSIAnt02, AR_RxRSSIAnt10, AR_RxRSSIAnt11, AR_RxRSSIAnt12, AR_RxRSSICombined, AR_TxRxDesc, ATH9K_PHYERR_OFDM_RESTART, ATH9K_RX_2040, ATH9K_RX_DECRYPT_BUSY, ATH9K_RX_DELIM_CRC_POST, ATH9K_RX_DELIM_CRC_PRE, ATH9K_RX_GI, ATH9K_RXERR_CRC, ATH9K_RXERR_DECRYPT, ATH9K_RXERR_MIC, ATH9K_RXERR_PHY, ATH9K_RXKEYIX_INVALID, ar9003_rxs::ds_info, EINPROGRESS, EINVAL, ath_rx_status::evm0, ath_rx_status::evm1, ath_rx_status::evm2, ath_rx_status::evm3, ath_rx_status::evm4, MS, ath_rx_status::rs_antenna, ath_rx_status::rs_datalen, ath_rx_status::rs_flags, ath_rx_status::rs_isaggr, ath_rx_status::rs_keyix, ath_rx_status::rs_more, ath_rx_status::rs_moreaggr, ath_rx_status::rs_phyerr, ath_rx_status::rs_rate, ath_rx_status::rs_rssi, ath_rx_status::rs_rssi_ctl0, ath_rx_status::rs_rssi_ctl1, ath_rx_status::rs_rssi_ctl2, ath_rx_status::rs_rssi_ext0, ath_rx_status::rs_rssi_ext1, ath_rx_status::rs_rssi_ext2, ath_rx_status::rs_status, ath_rx_status::rs_tstamp, ar9003_rxs::status1, ar9003_rxs::status10, ar9003_rxs::status11, ar9003_rxs::status2, ar9003_rxs::status3, ar9003_rxs::status4, ar9003_rxs::status5, ar9003_rxs::status6, ar9003_rxs::status7, ar9003_rxs::status8, and ar9003_rxs::status9.

{
        struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
        unsigned int phyerr;

        /* TODO: byte swap on big endian for ar9300_10 */

        if ((rxsp->status11 & AR_RxDone) == 0)
                return -EINPROGRESS;

        if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
                return -EINVAL;

        if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
                return -EINPROGRESS;

        if (!rxs)
                return 0;

        rxs->rs_status = 0;
        rxs->rs_flags =  0;

        rxs->rs_datalen = rxsp->status2 & AR_DataLen;
        rxs->rs_tstamp =  rxsp->status3;

        /* XXX: Keycache */
        rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
        rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
        rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
        rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
        rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
        rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
        rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);

        if (rxsp->status11 & AR_RxKeyIdxValid)
                rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
        else
                rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;

        rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
        rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;

        rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
        rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
        rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
        rxs->rs_flags  = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
        rxs->rs_flags  |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;

        rxs->evm0 = rxsp->status6;
        rxs->evm1 = rxsp->status7;
        rxs->evm2 = rxsp->status8;
        rxs->evm3 = rxsp->status9;
        rxs->evm4 = (rxsp->status10 & 0xffff);

        if (rxsp->status11 & AR_PreDelimCRCErr)
                rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;

        if (rxsp->status11 & AR_PostDelimCRCErr)
                rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;

        if (rxsp->status11 & AR_DecryptBusyErr)
                rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;

        if ((rxsp->status11 & AR_RxFrameOK) == 0) {
                /*
                 * AR_CRCErr will bet set to true if we're on the last
                 * subframe and the AR_PostDelimCRCErr is caught.
                 * In a way this also gives us a guarantee that when
                 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
                 * possibly be reviewing the last subframe. AR_CRCErr
                 * is the CRC of the actual data.
                 */
                if (rxsp->status11 & AR_CRCErr)
                        rxs->rs_status |= ATH9K_RXERR_CRC;
                else if (rxsp->status11 & AR_PHYErr) {
                        phyerr = MS(rxsp->status11, AR_PHYErrCode);
                        /*
                         * If we reach a point here where AR_PostDelimCRCErr is
                         * true it implies we're *not* on the last subframe. In
                         * in that case that we know already that the CRC of
                         * the frame was OK, and MAC would send an ACK for that
                         * subframe, even if we did get a phy error of type
                         * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
                         * to frame that are prior to the last subframe.
                         * The AR_PostDelimCRCErr is the CRC for the MPDU
                         * delimiter, which contains the 4 reserved bits,
                         * the MPDU length (12 bits), and follows the MPDU
                         * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
                         */
                        if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
                            (rxsp->status11 & AR_PostDelimCRCErr)) {
                                rxs->rs_phyerr = 0;
                        } else {
                                rxs->rs_status |= ATH9K_RXERR_PHY;
                                rxs->rs_phyerr = phyerr;
                        }

                } else if (rxsp->status11 & AR_DecryptCRCErr)
                        rxs->rs_status |= ATH9K_RXERR_DECRYPT;
                else if (rxsp->status11 & AR_MichaelErr)
                        rxs->rs_status |= ATH9K_RXERR_MIC;
                else if (rxsp->status11 & AR_KeyMiss)
                        rxs->rs_status |= ATH9K_RXERR_DECRYPT;
        }

        return 0;
}
void ath9k_hw_reset_txstatus_ring ( struct ath_hw ah)
void ath9k_hw_setup_statusring ( struct ath_hw ah,
void *  ts_start,
u32  ts_paddr_start,
u8  size 
)

Definition at line 658 of file ath9k_ar9003_mac.c.

References ath9k_hw_reset_txstatus_ring(), size, ath_hw::ts_paddr_end, ath_hw::ts_paddr_start, ath_hw::ts_ring, and ath_hw::ts_size.

{

        ah->ts_paddr_start = ts_paddr_start;
        ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
        ah->ts_size = size;
        ah->ts_ring = (struct ar9003_txs *) ts_start;

        ath9k_hw_reset_txstatus_ring(ah);
}