iPXE
Defines | Functions | Variables
ath9k_ar9003_phy.c File Reference
#include <ipxe/io.h>
#include "hw.h"
#include "ar9003_phy.h"

Go to the source code of this file.

Defines

#define AR_PHY_CH_MINCCA_PWR   0x1FF00000
#define AR_PHY_CH_MINCCA_PWR_S   20
#define AR_PHY_CH_EXT_MINCCA_PWR   0x01FF0000
#define AR_PHY_CH_EXT_MINCCA_PWR_S   16

Functions

static int ar9003_hw_set_channel (struct ath_hw *ah, struct ath9k_channel *chan)
 ar9003_hw_set_channel - set channel on single-chip device : atheros hardware structure :
static void ar9003_hw_spur_mitigate_mrc_cck (struct ath_hw *ah, struct ath9k_channel *chan)
 ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency : atheros hardware structure :
static void ar9003_hw_spur_ofdm_clear (struct ath_hw *ah)
static void ar9003_hw_spur_ofdm (struct ath_hw *ah, int freq_offset, int spur_freq_sd, int spur_delta_phase, int spur_subchannel_sd)
static void ar9003_hw_spur_ofdm_work (struct ath_hw *ah, struct ath9k_channel *chan, int freq_offset)
static void ar9003_hw_spur_mitigate_ofdm (struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_spur_mitigate (struct ath_hw *ah, struct ath9k_channel *chan)
static u32 ar9003_hw_compute_pll_control (struct ath_hw *ah __unused, struct ath9k_channel *chan)
static void ar9003_hw_set_channel_regs (struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_init_bb (struct ath_hw *ah, struct ath9k_channel *chan)
void ar9003_hw_set_chain_masks (struct ath_hw *ah, u8 rx, u8 tx)
static void ar9003_hw_override_ini (struct ath_hw *ah)
static void ar9003_hw_prog_ini (struct ath_hw *ah, struct ar5416IniArray *iniArr, int column)
static int ar9003_hw_process_ini (struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_set_rfmode (struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_mark_phy_inactive (struct ath_hw *ah)
static void ar9003_hw_set_delta_slope (struct ath_hw *ah, struct ath9k_channel *chan)
static int ar9003_hw_rfbus_req (struct ath_hw *ah)
static void ar9003_hw_rfbus_done (struct ath_hw *ah)
static void ar9003_hw_set_diversity (struct ath_hw *ah, int value)
static int ar9003_hw_ani_control (struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
static void ar9003_hw_do_getnf (struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
static void ar9003_hw_set_nf_limits (struct ath_hw *ah)
static void ar9003_hw_ani_cache_ini_regs (struct ath_hw *ah)
static void ar9003_hw_set_radar_params (struct ath_hw *ah, struct ath_hw_radar_conf *conf)
static void ar9003_hw_set_radar_conf (struct ath_hw *ah)
static void ar9003_hw_antdiv_comb_conf_get (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
static void ar9003_hw_antdiv_comb_conf_set (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
void ar9003_hw_attach_phy_ops (struct ath_hw *ah)
void ar9003_hw_disable_phy_restart (struct ath_hw *ah)

Variables

static const int firstep_table []
static const int cycpwrThr1_table []
static const int m1ThreshLow_off = 127
static const int m2ThreshLow_off = 127
static const int m1Thresh_off = 127
static const int m2Thresh_off = 127
static const int m2CountThr_off = 31
static const int m2CountThrLow_off = 63
static const int m1ThreshLowExt_off = 127
static const int m2ThreshLowExt_off = 127
static const int m1ThreshExt_off = 127
static const int m2ThreshExt_off = 127

Define Documentation

#define AR_PHY_CH_MINCCA_PWR   0x1FF00000

Referenced by ar9003_hw_do_getnf().

#define AR_PHY_CH_MINCCA_PWR_S   20
#define AR_PHY_CH_EXT_MINCCA_PWR   0x01FF0000

Referenced by ar9003_hw_do_getnf().

#define AR_PHY_CH_EXT_MINCCA_PWR_S   16

Function Documentation

static int ar9003_hw_set_channel ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

ar9003_hw_set_channel - set channel on single-chip device : atheros hardware structure :

This is the function to change channel on single-chip devices, that is all devices after ar9280.

This function takes the channel value in MHz and sets hardware channel value. Assumes writes have been enabled to analog bus.

Actual Expression,

For 2GHz channel, Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) (freq_ref = 40MHz)

For 5GHz channel, Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) (freq_ref = 40MHz/(24>>amodeRefSel))

For 5GHz channels which are 5MHz spaced, Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) (freq_ref = 40MHz)

Definition at line 72 of file ath9k_ar9003_phy.c.

References AR_PHY_65NM_CH0_SYNTH4, AR_PHY_65NM_CH0_SYNTH7, AR_PHY_SYNTH4_LONG_SHIFT_SELECT, AR_PHY_SYNTH_CONTROL, AR_SREV_9340, AR_SREV_9485, ath9k_hw_get_channel_centers(), CHANSEL_2G, CHANSEL_5G, ath_hw::curchan, ath_hw::curchan_rad_index, ath_hw::is_clk_25mhz, REG_RMW_FIELD, REG_WRITE, and chan_centers::synth_center.

Referenced by ar9003_hw_attach_phy_ops().

{
        u16 bMode, fracMode = 0, aModeRefSel = 0;
        u32 freq, channelSel = 0, reg32 = 0;
        struct chan_centers centers;
        int loadSynthChannel;

        ath9k_hw_get_channel_centers(ah, chan, &centers);
        freq = centers.synth_center;

        if (freq < 4800) {     /* 2 GHz, fractional mode */
                if (AR_SREV_9485(ah)) {
                        u32 chan_frac;

                        /*
                         * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
                         * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
                         * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
                         */
                        channelSel = (freq * 4) / 120;
                        chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
                        channelSel = (channelSel << 17) | chan_frac;
                } else if (AR_SREV_9340(ah)) {
                        if (ah->is_clk_25mhz) {
                                u32 chan_frac;

                                channelSel = (freq * 2) / 75;
                                chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
                                channelSel = (channelSel << 17) | chan_frac;
                        } else
                                channelSel = CHANSEL_2G(freq) >> 1;
                } else
                        channelSel = CHANSEL_2G(freq);
                /* Set to 2G mode */
                bMode = 1;
        } else {
                if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
                        u32 chan_frac;

                        channelSel = (freq * 2) / 75;
                        chan_frac = ((freq % 75) * 0x20000) / 75;
                        channelSel = (channelSel << 17) | chan_frac;
                } else {
                        channelSel = CHANSEL_5G(freq);
                        /* Doubler is ON, so, divide channelSel by 2. */
                        channelSel >>= 1;
                }
                /* Set to 5G mode */
                bMode = 0;
        }

        /* Enable fractional mode for all channels */
        fracMode = 1;
        aModeRefSel = 0;
        loadSynthChannel = 0;

        reg32 = (bMode << 29);
        REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);

        /* Enable Long shift Select for Synthesizer */
        REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
                      AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);

        /* Program Synth. setting */
        reg32 = (channelSel << 2) | (fracMode << 30) |
                (aModeRefSel << 28) | (loadSynthChannel << 31);
        REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);

        /* Toggle Load Synth channel bit */
        loadSynthChannel = 1;
        reg32 = (channelSel << 2) | (fracMode << 30) |
                (aModeRefSel << 28) | (loadSynthChannel << 31);
        REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);

        ah->curchan = chan;
        ah->curchan_rad_index = -1;

        return 0;
}
static void ar9003_hw_spur_mitigate_mrc_cck ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency : atheros hardware structure :

For single-chip solutions. Converts to baseband spur frequency given the input channel frequency and compute register settings below.

Spur mitigation for MRC CCK

Definition at line 162 of file ath9k_ar9003_phy.c.

References ar9003_get_spur_chan_ptr(), AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_YCOK_MAX, AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GEN_CTRL, AR_SREV_9340, AR_SREV_9485, ath9k_channel::channel, FBIN2FREQ, IS_CHAN_2GHZ, IS_CHAN_HT40, NULL, REG_READ_FIELD, and REG_RMW_FIELD.

Referenced by ar9003_hw_spur_mitigate().

{
        static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
        int cur_bb_spur, negative = 0, cck_spur_freq;
        int i;
        int range, max_spur_cnts, synth_freq;
        u8 *spur_fbin_ptr = NULL;

        /*
         * Need to verify range +/- 10 MHz in control channel, otherwise spur
         * is out-of-band and can be ignored.
         */

        if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
                spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
                                                         IS_CHAN_2GHZ(chan));
                if (spur_fbin_ptr[0] == 0) /* No spur */
                        return;
                max_spur_cnts = 5;
                if (IS_CHAN_HT40(chan)) {
                        range = 19;
                        if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
                                           AR_PHY_GC_DYN2040_PRI_CH) == 0)
                                synth_freq = chan->channel + 10;
                        else
                                synth_freq = chan->channel - 10;
                } else {
                        range = 10;
                        synth_freq = chan->channel;
                }
        } else {
                range = 10;
                max_spur_cnts = 4;
                synth_freq = chan->channel;
        }

        for (i = 0; i < max_spur_cnts; i++) {
                negative = 0;
                if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
                        cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
                                        IS_CHAN_2GHZ(chan)) - synth_freq;
                else
                        cur_bb_spur = spur_freq[i] - synth_freq;

                if (cur_bb_spur < 0) {
                        negative = 1;
                        cur_bb_spur = -cur_bb_spur;
                }
                if (cur_bb_spur < range) {
                        cck_spur_freq = (int)((cur_bb_spur << 19) / 11);

                        if (negative == 1)
                                cck_spur_freq = -cck_spur_freq;

                        cck_spur_freq = cck_spur_freq & 0xfffff;

                        REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
                                      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
                        REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
                                      AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
                        REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
                                      AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
                                      0x2);
                        REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
                                      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
                                      0x1);
                        REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
                                      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
                                      cck_spur_freq);

                        return;
                }
        }

        REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
                      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
        REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
                      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
        REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
                      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
}
static void ar9003_hw_spur_ofdm_clear ( struct ath_hw ah) [static]

Definition at line 246 of file ath9k_ar9003_phy.c.

References AR_PHY_CHAN_SPUR_MASK, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, AR_PHY_PILOT_SPUR_MASK, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, AR_PHY_SPUR_REG_MASK_RATE_CNTL, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, AR_PHY_TIMING11_SPUR_FREQ_SD, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_CHAN_MASK, AR_PHY_TIMING4_ENABLE_PILOT_MASK, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, AR_PHY_TIMING4_ENABLE_SPUR_RSSI, and REG_RMW_FIELD.

Referenced by ar9003_hw_spur_mitigate_ofdm().

static void ar9003_hw_spur_ofdm ( struct ath_hw ah,
int  freq_offset,
int  spur_freq_sd,
int  spur_delta_phase,
int  spur_subchannel_sd 
) [static]

Definition at line 289 of file ath9k_ar9003_phy.c.

References AR_PHY_CHAN_SPUR_MASK, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, AR_PHY_MODE, AR_PHY_MODE_DYNAMIC, AR_PHY_PILOT_SPUR_MASK, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, AR_PHY_SPUR_REG_MASK_RATE_CNTL, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, AR_PHY_TIMING11_SPUR_FREQ_SD, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_CHAN_MASK, AR_PHY_TIMING4_ENABLE_PILOT_MASK, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, AR_PHY_TIMING4_ENABLE_SPUR_RSSI, REG_READ_FIELD, and REG_RMW_FIELD.

Referenced by ar9003_hw_spur_ofdm_work().

{
        int mask_index = 0;

        /* OFDM Spur mitigation */
        REG_RMW_FIELD(ah, AR_PHY_TIMING4,
                 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
        REG_RMW_FIELD(ah, AR_PHY_TIMING11,
                      AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
        REG_RMW_FIELD(ah, AR_PHY_TIMING11,
                      AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
        REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
                      AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
        REG_RMW_FIELD(ah, AR_PHY_TIMING11,
                      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
        REG_RMW_FIELD(ah, AR_PHY_TIMING11,
                      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
        REG_RMW_FIELD(ah, AR_PHY_TIMING4,
                      AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
        REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                      AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
        REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                      AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);

        if (REG_READ_FIELD(ah, AR_PHY_MODE,
                           AR_PHY_MODE_DYNAMIC) == 0x1)
                REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                              AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);

        mask_index = (freq_offset << 4) / 5;
        if (mask_index < 0)
                mask_index = mask_index - 1;

        mask_index = mask_index & 0x7f;

        REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                      AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
        REG_RMW_FIELD(ah, AR_PHY_TIMING4,
                      AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
        REG_RMW_FIELD(ah, AR_PHY_TIMING4,
                      AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
        REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
                      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
        REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
                      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
        REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
                      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
        REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
                      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
        REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
                      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
        REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
                      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
        REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                      AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
}
static void ar9003_hw_spur_ofdm_work ( struct ath_hw ah,
struct ath9k_channel chan,
int  freq_offset 
) [static]

Definition at line 350 of file ath9k_ar9003_phy.c.

References ar9003_hw_spur_ofdm(), AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GEN_CTRL, IS_CHAN_HT40, and REG_READ_FIELD.

Referenced by ar9003_hw_spur_mitigate_ofdm().

{
        int spur_freq_sd = 0;
        int spur_subchannel_sd = 0;
        int spur_delta_phase = 0;

        if (IS_CHAN_HT40(chan)) {
                if (freq_offset < 0) {
                        if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
                                           AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
                                spur_subchannel_sd = 1;
                        else
                                spur_subchannel_sd = 0;

                        spur_freq_sd = ((freq_offset + 10) << 9) / 11;

                } else {
                        if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
                                spur_subchannel_sd = 0;
                        else
                                spur_subchannel_sd = 1;

                        spur_freq_sd = ((freq_offset - 10) << 9) / 11;

                }

                spur_delta_phase = (freq_offset << 17) / 5;

        } else {
                spur_subchannel_sd = 0;
                spur_freq_sd = (freq_offset << 9) /11;
                spur_delta_phase = (freq_offset << 18) / 5;
        }

        spur_freq_sd = spur_freq_sd & 0x3ff;
        spur_delta_phase = spur_delta_phase & 0xfffff;

        ar9003_hw_spur_ofdm(ah,
                            freq_offset,
                            spur_freq_sd,
                            spur_delta_phase,
                            spur_subchannel_sd);
}
static void ar9003_hw_spur_mitigate_ofdm ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

Definition at line 398 of file ath9k_ar9003_phy.c.

References abs, ar9003_hw_spur_ofdm_clear(), ar9003_hw_spur_ofdm_work(), ath_hw::ar9300_eep, AR_EEPROM_MODAL_SPURS, AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GEN_CTRL, ath9k_channel::channel, ath_hw::eeprom, FBIN2FREQ, IS_CHAN_5GHZ, IS_CHAN_HT40, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, REG_READ_FIELD, and ar9300_modal_eep_header::spurChans.

Referenced by ar9003_hw_spur_mitigate().

{
        int synth_freq;
        int range = 10;
        int freq_offset = 0;
        int mode;
        u8* spurChansPtr;
        unsigned int i;
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

        if (IS_CHAN_5GHZ(chan)) {
                spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
                mode = 0;
        }
        else {
                spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
                mode = 1;
        }

        if (spurChansPtr[0] == 0)
                return; /* No spur in the mode */

        if (IS_CHAN_HT40(chan)) {
                range = 19;
                if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
                                   AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
                        synth_freq = chan->channel - 10;
                else
                        synth_freq = chan->channel + 10;
        } else {
                range = 10;
                synth_freq = chan->channel;
        }

        ar9003_hw_spur_ofdm_clear(ah);

        for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
                freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
                if (abs(freq_offset) < range) {
                        ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
                        break;
                }
        }
}
static void ar9003_hw_spur_mitigate ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]
static u32 ar9003_hw_compute_pll_control ( struct ath_hw *ah  __unused,
struct ath9k_channel chan 
) [static]

Definition at line 451 of file ath9k_ar9003_phy.c.

References AR_RTC_9300_PLL_CLKSEL, AR_RTC_9300_PLL_DIV, AR_RTC_9300_PLL_REFDIV, IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, and SM.

Referenced by ar9003_hw_attach_phy_ops().

{
        u32 pll;

        pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);

        if (chan && IS_CHAN_HALF_RATE(chan))
                pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
        else if (chan && IS_CHAN_QUARTER_RATE(chan))
                pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);

        pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);

        return pll;
}
static void ar9003_hw_set_channel_regs ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

Definition at line 468 of file ath9k_ar9003_phy.c.

References AR_CST, AR_CST_TIMEOUT_LIMIT_S, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT_S, AR_PHY_GC_DYN2040_EN, AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GC_ENABLE_DAC_FIFO, AR_PHY_GC_GF_DETECT_EN, AR_PHY_GC_HT_EN, AR_PHY_GC_SHORT_GI_40, AR_PHY_GC_SINGLE_HT_LTF1, AR_PHY_GC_WALSH, AR_PHY_GEN_CTRL, ath9k_hw_set11nmac2040(), ath9k_channel::chanmode, CHANNEL_A_HT40PLUS, CHANNEL_G_HT40PLUS, IS_CHAN_HT40, REG_READ, and REG_WRITE.

Referenced by ar9003_hw_attach_phy_ops(), and ar9003_hw_process_ini().

{
        u32 phymode;
        u32 enableDacFifo = 0;

        enableDacFifo =
                (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);

        /* Enable 11n HT, 20 MHz */
        phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
                  AR_PHY_GC_SHORT_GI_40 | enableDacFifo;

        /* Configure baseband for dynamic 20/40 operation */
        if (IS_CHAN_HT40(chan)) {
                phymode |= AR_PHY_GC_DYN2040_EN;
                /* Configure control (primary) channel at +-10MHz */
                if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
                    (chan->chanmode == CHANNEL_G_HT40PLUS))
                        phymode |= AR_PHY_GC_DYN2040_PRI_CH;

        }

        /* make sure we preserve INI settings */
        phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
        /* turn off Green Field detection for STA for now */
        phymode &= ~AR_PHY_GC_GF_DETECT_EN;

        REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);

        /* Configure MAC for 20/40 operation */
        ath9k_hw_set11nmac2040(ah);

        /* global transmit timeout (25 TUs default)*/
        REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
        /* carrier sense timeout */
        REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
}
static void ar9003_hw_init_bb ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

Definition at line 507 of file ath9k_ar9003_phy.c.

References AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY, BASE_ACTIVATE_DELAY, IS_CHAN_B, REG_READ, REG_WRITE, and udelay().

Referenced by ar9003_hw_attach_phy_ops().

{
        u32 synthDelay;

        /*
         * Wait for the frequency synth to settle (synth goes on
         * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
         * Value is in 100ns increments.
         */
        synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
        if (IS_CHAN_B(chan))
                synthDelay = (4 * synthDelay) / 22;
        else
                synthDelay /= 10;

        /* Activate the PHY (includes baseband activate + synthesizer on) */
        REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);

        /*
         * There is an issue if the AP starts the calibration before
         * the base band timeout completes.  This could result in the
         * rx_clear false triggering.  As a workaround we add delay an
         * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
         * does not happen.
         */
        udelay(synthDelay + BASE_ACTIVATE_DELAY);
}
void ar9003_hw_set_chain_masks ( struct ath_hw ah,
u8  rx,
u8  tx 
)
static void ar9003_hw_override_ini ( struct ath_hw ah) [static]

Definition at line 568 of file ath9k_ar9003_phy.c.

References AR_ADHOC_MCAST_KEYID_ENABLE, AR_AGG_WEP_ENABLE, AR_AGG_WEP_ENABLE_FIX, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, AR_PCU_MISC_MODE2, REG_READ, REG_SET_BIT, REG_WRITE, and val.

Referenced by ar9003_hw_process_ini().

{
        u32 val;

        /*
         * Set the RX_ABORT and RX_DIS and clear it only after
         * RXE is set for MAC. This prevents frames with
         * corrupted descriptor status.
         */
        REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

        /*
         * For AR9280 and above, there is a new feature that allows
         * Multicast search based on both MAC Address and Key ID. By default,
         * this feature is enabled. But since the driver is not using this
         * feature, we switch it off; otherwise multicast search based on
         * MAC addr only will fail.
         */
        val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
        REG_WRITE(ah, AR_PCU_MISC_MODE2,
                  val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
}
static void ar9003_hw_prog_ini ( struct ath_hw ah,
struct ar5416IniArray iniArr,
int  column 
) [static]

Definition at line 591 of file ath9k_ar9003_phy.c.

References DO_DELAY, ar5416IniArray::ia_array, ar5416IniArray::ia_columns, ar5416IniArray::ia_rows, INI_RA, reg, REG_WRITE, and val.

Referenced by ar9003_hw_process_ini().

{
        unsigned int i, regWrites = 0;

        /* New INI format: Array may be undefined (pre, core, post arrays) */
        if (!iniArr->ia_array)
                return;

        /*
         * New INI format: Pre, core, and post arrays for a given subsystem
         * may be modal (> 2 columns) or non-modal (2 columns). Determine if
         * the array is non-modal and force the column to 1.
         */
        if ((unsigned int)column >= iniArr->ia_columns)
                column = 1;

        for (i = 0; i < iniArr->ia_rows; i++) {
                u32 reg = INI_RA(iniArr, i, 0);
                u32 val = INI_RA(iniArr, i, column);

                REG_WRITE(ah, reg, val);

                DO_DELAY(regWrites);
        }
}
static int ar9003_hw_process_ini ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

Definition at line 619 of file ath9k_ar9003_phy.c.

References ar9003_hw_override_ini(), ar9003_hw_prog_ini(), ar9003_hw_set_chain_masks(), ar9003_hw_set_channel_regs(), AR_SREV_9340, ath9k_hw_regulatory(), ath9k_regd_get_ctl(), ATH_INI_NUM_SPLIT, ath9k_channel::chan, ath9k_channel::chanmode, channel, CHANNEL_A, CHANNEL_A_HT20, CHANNEL_A_HT40MINUS, CHANNEL_A_HT40PLUS, CHANNEL_B, CHANNEL_G, CHANNEL_G_HT20, CHANNEL_G_HT40MINUS, CHANNEL_G_HT40PLUS, ath_hw::eep_ops, EINVAL, ath_hw::iniBB, ath_hw::iniMac, ath_hw::iniModesAdditional, ath_hw::iniModesAdditional_40M, ath_hw::iniModesRxGain, ath_hw::iniModesTxGain, ath_hw::iniRadio, ath_hw::iniSOC, IS_CHAN_A_FAST_CLOCK, ath_hw::is_clk_25mhz, MAX_RATE_POWER, net80211_channel::maxpower, min, ath_regulatory::power_limit, REG_WRITE_ARRAY, ath_hw::rxchainmask, eeprom_ops::set_txpower, and ath_hw::txchainmask.

Referenced by ar9003_hw_attach_phy_ops().

{
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        unsigned int regWrites = 0, i;
        struct net80211_channel *channel = chan->chan;
        u32 modesIndex;

        switch (chan->chanmode) {
        case CHANNEL_A:
        case CHANNEL_A_HT20:
                modesIndex = 1;
                break;
        case CHANNEL_A_HT40PLUS:
        case CHANNEL_A_HT40MINUS:
                modesIndex = 2;
                break;
        case CHANNEL_G:
        case CHANNEL_G_HT20:
        case CHANNEL_B:
                modesIndex = 4;
                break;
        case CHANNEL_G_HT40PLUS:
        case CHANNEL_G_HT40MINUS:
                modesIndex = 3;
                break;

        default:
                return -EINVAL;
        }

        for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
                ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
                ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
                ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
                ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
        }

        REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
        REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);

        /*
         * For 5GHz channels requiring Fast Clock, apply
         * different modal values.
         */
        if (IS_CHAN_A_FAST_CLOCK(ah, chan))
                REG_WRITE_ARRAY(&ah->iniModesAdditional,
                                modesIndex, regWrites);

        if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
                REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);

        ar9003_hw_override_ini(ah);
        ar9003_hw_set_channel_regs(ah, chan);
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);

        /* Set TX power */
        ah->eep_ops->set_txpower(ah, chan,
                                 ath9k_regd_get_ctl(regulatory, chan),
                                 0,
                                 channel->maxpower * 2,
                                 min((u32) MAX_RATE_POWER,
                                 (u32) regulatory->power_limit), 0);

        return 0;
}
static void ar9003_hw_set_rfmode ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]
static void ar9003_hw_mark_phy_inactive ( struct ath_hw ah) [static]
static void ar9003_hw_set_delta_slope ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

Definition at line 708 of file ath9k_ar9003_phy.c.

References AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_EXP, AR_PHY_SGI_DSC_MAN, AR_PHY_TIMING3, AR_PHY_TIMING3_DSC_EXP, AR_PHY_TIMING3_DSC_MAN, ath9k_hw_get_channel_centers(), ath9k_hw_get_delta_slope_vals(), IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, REG_RMW_FIELD, and chan_centers::synth_center.

Referenced by ar9003_hw_attach_phy_ops().

{
        u32 coef_scaled, ds_coef_exp, ds_coef_man;
        u32 clockMhzScaled = 0x64000000;
        struct chan_centers centers;

        /*
         * half and quarter rate can divide the scaled clock by 2 or 4
         * scale for selected channel bandwidth
         */
        if (IS_CHAN_HALF_RATE(chan))
                clockMhzScaled = clockMhzScaled >> 1;
        else if (IS_CHAN_QUARTER_RATE(chan))
                clockMhzScaled = clockMhzScaled >> 2;

        /*
         * ALGO -> coef = 1e8/fcarrier*fclock/40;
         * scaled coef to provide precision for this floating calculation
         */
        ath9k_hw_get_channel_centers(ah, chan, &centers);
        coef_scaled = clockMhzScaled / centers.synth_center;

        ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
                                      &ds_coef_exp);

        REG_RMW_FIELD(ah, AR_PHY_TIMING3,
                      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
        REG_RMW_FIELD(ah, AR_PHY_TIMING3,
                      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);

        /*
         * For Short GI,
         * scaled coeff is 9/10 that of normal coeff
         */
        coef_scaled = (9 * coef_scaled) / 10;

        ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
                                      &ds_coef_exp);

        /* for short gi */
        REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
                      AR_PHY_SGI_DSC_MAN, ds_coef_man);
        REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
                      AR_PHY_SGI_DSC_EXP, ds_coef_exp);
}
static int ar9003_hw_rfbus_req ( struct ath_hw ah) [static]
static void ar9003_hw_rfbus_done ( struct ath_hw ah) [static]

Definition at line 766 of file ath9k_ar9003_phy.c.

References AR_PHY_RFBUS_REQ, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY, BASE_ACTIVATE_DELAY, ath_hw::curchan, IS_CHAN_B, REG_READ, REG_WRITE, and udelay().

Referenced by ar9003_hw_attach_phy_ops().

{
        u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
        if (IS_CHAN_B(ah->curchan))
                synthDelay = (4 * synthDelay) / 22;
        else
                synthDelay /= 10;

        udelay(synthDelay + BASE_ACTIVATE_DELAY);

        REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
}
static void ar9003_hw_set_diversity ( struct ath_hw ah,
int  value 
) [static]
static int ar9003_hw_ani_control ( struct ath_hw ah,
enum ath9k_ani_cmd  cmd,
int  param 
) [static]

Definition at line 789 of file ath9k_ar9003_phy.c.

References ath9k_channel::ani, ath_hw::ani_function, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, AR_PHY_MRC_CCK_CTRL, AR_PHY_MRC_CCK_ENABLE, AR_PHY_MRC_CCK_MUX_REG, AR_PHY_SFCORR, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, AR_PHY_SFCORR_EXT_M2_THRESH, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW, AR_PHY_SFCORR_M1_THRESH, AR_PHY_SFCORR_M2_THRESH, AR_PHY_SFCORR_M2COUNT_THR, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, ARRAY_SIZE, ar5416Stats::ast_ani_cckhigh, ar5416Stats::ast_ani_ccklow, ar5416Stats::ast_ani_ofdmoff, ar5416Stats::ast_ani_ofdmon, ar5416Stats::ast_ani_spurdown, ar5416Stats::ast_ani_spurup, ar5416Stats::ast_ani_stepdown, ar5416Stats::ast_ani_stepup, ATH9K_ANI_FIRSTEP_LEVEL, ATH9K_ANI_FIRSTEP_LVL_NEW, ATH9K_ANI_MRC_CCK, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, ATH9K_ANI_PRESENT, ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, ATH9K_SIG_FIRSTEP_SETTING_MAX, ATH9K_SIG_FIRSTEP_SETTING_MIN, ATH9K_SIG_SPUR_IMM_SETTING_MAX, ATH9K_SIG_SPUR_IMM_SETTING_MIN, ar5416AniState::cckPhyErrCount, ath9k_channel::chan, ath9k_channel::channel, ath_hw::curchan, ath9k_ani_default::cycpwrThr1, cycpwrThr1_table, ath9k_ani_default::cycpwrThr1Ext, DBG, DBG2, ath9k_ani_default::firstep, firstep_table, ar5416AniState::firstepLevel, ath9k_ani_default::firstepLow, ar5416AniState::iniDef, ar5416AniState::listenTime, ath9k_ani_default::m1Thresh, m1Thresh_off, ath9k_ani_default::m1ThreshExt, m1ThreshExt_off, ath9k_ani_default::m1ThreshLow, m1ThreshLow_off, ath9k_ani_default::m1ThreshLowExt, m1ThreshLowExt_off, ath9k_ani_default::m2CountThr, m2CountThr_off, ath9k_ani_default::m2CountThrLow, m2CountThrLow_off, ath9k_ani_default::m2Thresh, m2Thresh_off, ath9k_ani_default::m2ThreshExt, m2ThreshExt_off, ath9k_ani_default::m2ThreshLow, m2ThreshLow_off, ath9k_ani_default::m2ThreshLowExt, m2ThreshLowExt_off, ar5416AniState::mrcCCKOff, ar5416AniState::ofdmPhyErrCount, ar5416AniState::ofdmWeakSigDetect, param, REG_CLR_BIT, REG_RMW_FIELD, REG_SET_BIT, ar5416AniState::spurImmunityLevel, ath_hw::stats, and value.

Referenced by ar9003_hw_attach_phy_ops().

{
        struct ath9k_channel *chan = ah->curchan;
        struct ar5416AniState *aniState = &chan->ani;
        s32 value, value2;

        switch (cmd & ah->ani_function) {
        case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
                /*
                 * on == 1 means ofdm weak signal detection is ON
                 * on == 1 is the default, for less noise immunity
                 *
                 * on == 0 means ofdm weak signal detection is OFF
                 * on == 0 means more noise imm
                 */
                u32 on = param ? 1 : 0;
                /*
                 * make register setting for default
                 * (weak sig detect ON) come from INI file
                 */
                int m1ThreshLow = on ?
                        aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
                int m2ThreshLow = on ?
                        aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
                int m1Thresh = on ?
                        aniState->iniDef.m1Thresh : m1Thresh_off;
                int m2Thresh = on ?
                        aniState->iniDef.m2Thresh : m2Thresh_off;
                int m2CountThr = on ?
                        aniState->iniDef.m2CountThr : m2CountThr_off;
                int m2CountThrLow = on ?
                        aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
                int m1ThreshLowExt = on ?
                        aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
                int m2ThreshLowExt = on ?
                        aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
                int m1ThreshExt = on ?
                        aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
                int m2ThreshExt = on ?
                        aniState->iniDef.m2ThreshExt : m2ThreshExt_off;

                REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
                              AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
                              m1ThreshLow);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
                              AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
                              m2ThreshLow);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR,
                              AR_PHY_SFCORR_M1_THRESH, m1Thresh);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR,
                              AR_PHY_SFCORR_M2_THRESH, m2Thresh);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR,
                              AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
                              AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
                              m2CountThrLow);

                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
                              AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
                              AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
                              AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
                              AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);

                if (on)
                        REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
                                    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
                else
                        REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
                                    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);

                if (on != aniState->ofdmWeakSigDetect) {
                        DBG2("ath9k: "
                                "** ch %d: ofdm weak signal: %s=>%s\n",
                                chan->channel,
                                aniState->ofdmWeakSigDetect ?
                                "on" : "off",
                                on ? "on" : "off");
                        if (on)
                                ah->stats.ast_ani_ofdmon++;
                        else
                                ah->stats.ast_ani_ofdmoff++;
                        aniState->ofdmWeakSigDetect = on;
                }
                break;
        }
        case ATH9K_ANI_FIRSTEP_LEVEL:{
                u32 level = param;

                if (level >= ARRAY_SIZE(firstep_table)) {
                        DBG("ath9k: "
                                "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
                                level, ARRAY_SIZE(firstep_table));
                        return 0;
                }

                /*
                 * make register setting relative to default
                 * from INI file & cap value
                 */
                value = firstep_table[level] -
                        firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
                        aniState->iniDef.firstep;
                if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
                        value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
                if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
                        value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
                REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
                              AR_PHY_FIND_SIG_FIRSTEP,
                              value);
                /*
                 * we need to set first step low register too
                 * make register setting relative to default
                 * from INI file & cap value
                 */
                value2 = firstep_table[level] -
                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
                         aniState->iniDef.firstepLow;
                if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
                        value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
                if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
                        value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;

                REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
                              AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);

                if (level != aniState->firstepLevel) {
                        DBG2("ath9k: "
                                "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
                                chan->channel,
                                aniState->firstepLevel,
                                level,
                                ATH9K_ANI_FIRSTEP_LVL_NEW,
                                value,
                                aniState->iniDef.firstep);
                        DBG2("ath9k: "
                                "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
                                chan->channel,
                                aniState->firstepLevel,
                                level,
                                ATH9K_ANI_FIRSTEP_LVL_NEW,
                                value2,
                                aniState->iniDef.firstepLow);
                        if (level > aniState->firstepLevel)
                                ah->stats.ast_ani_stepup++;
                        else if (level < aniState->firstepLevel)
                                ah->stats.ast_ani_stepdown++;
                        aniState->firstepLevel = level;
                }
                break;
        }
        case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
                u32 level = param;

                if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
                        DBG("ath9k: "
                                "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
                                level, ARRAY_SIZE(cycpwrThr1_table));
                        return 0;
                }
                /*
                 * make register setting relative to default
                 * from INI file & cap value
                 */
                value = cycpwrThr1_table[level] -
                        cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
                        aniState->iniDef.cycpwrThr1;
                if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
                        value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
                if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
                        value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
                REG_RMW_FIELD(ah, AR_PHY_TIMING5,
                              AR_PHY_TIMING5_CYCPWR_THR1,
                              value);

                /*
                 * set AR_PHY_EXT_CCA for extension channel
                 * make register setting relative to default
                 * from INI file & cap value
                 */
                value2 = cycpwrThr1_table[level] -
                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
                         aniState->iniDef.cycpwrThr1Ext;
                if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
                        value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
                if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
                        value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
                REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
                              AR_PHY_EXT_CYCPWR_THR1, value2);

                if (level != aniState->spurImmunityLevel) {
                        DBG2("ath9k: "
                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
                                chan->channel,
                                aniState->spurImmunityLevel,
                                level,
                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
                                value,
                                aniState->iniDef.cycpwrThr1);
                        DBG2("ath9k: "
                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
                                chan->channel,
                                aniState->spurImmunityLevel,
                                level,
                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
                                value2,
                                aniState->iniDef.cycpwrThr1Ext);
                        if (level > aniState->spurImmunityLevel)
                                ah->stats.ast_ani_spurup++;
                        else if (level < aniState->spurImmunityLevel)
                                ah->stats.ast_ani_spurdown++;
                        aniState->spurImmunityLevel = level;
                }
                break;
        }
        case ATH9K_ANI_MRC_CCK:{
                /*
                 * is_on == 1 means MRC CCK ON (default, less noise imm)
                 * is_on == 0 means MRC CCK is OFF (more noise imm)
                 */
                int is_on = param ? 1 : 0;
                REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
                              AR_PHY_MRC_CCK_ENABLE, is_on);
                REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
                              AR_PHY_MRC_CCK_MUX_REG, is_on);
                if (!(is_on != aniState->mrcCCKOff)) {
                        DBG2("ath9k: "
                                "** ch %d: MRC CCK: %s=>%s\n",
                                chan->channel,
                                !aniState->mrcCCKOff ? "on" : "off",
                                is_on ? "on" : "off");
                if (is_on)
                        ah->stats.ast_ani_ccklow++;
                else
                        ah->stats.ast_ani_cckhigh++;
                aniState->mrcCCKOff = !is_on;
                }
        break;
        }
        case ATH9K_ANI_PRESENT:
                break;
        default:
                DBG2("ath9k: invalid cmd %d\n", cmd);
                return 0;
        }

        DBG2("ath9k: "
                "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
                aniState->spurImmunityLevel,
                aniState->ofdmWeakSigDetect ? "on" : "off",
                aniState->firstepLevel,
                !aniState->mrcCCKOff ? "on" : "off",
                aniState->listenTime,
                aniState->ofdmPhyErrCount,
                aniState->cckPhyErrCount);
        return 1;
}
static void ar9003_hw_do_getnf ( struct ath_hw ah,
int16_t  nfarray[NUM_NF_READINGS] 
) [static]

Definition at line 1050 of file ath9k_ar9003_phy.c.

References AR9300_MAX_CHAINS, AR_PHY_CH_EXT_MINCCA_PWR, AR_PHY_CH_MINCCA_PWR, BIT, ath_hw::curchan, IS_CHAN_HT40, MS, ath_hw::nf_regs, REG_READ, ath_hw::rxchainmask, and sign_extend32().

Referenced by ar9003_hw_attach_phy_ops().

{
#define AR_PHY_CH_MINCCA_PWR    0x1FF00000
#define AR_PHY_CH_MINCCA_PWR_S  20
#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
#define AR_PHY_CH_EXT_MINCCA_PWR_S 16

        int16_t nf;
        int i;

        for (i = 0; i < AR9300_MAX_CHAINS; i++) {
                if (ah->rxchainmask & BIT(i)) {
                        nf = MS(REG_READ(ah, ah->nf_regs[i]),
                                         AR_PHY_CH_MINCCA_PWR);
                        nfarray[i] = sign_extend32(nf, 8);

                        if (IS_CHAN_HT40(ah->curchan)) {
                                u8 ext_idx = AR9300_MAX_CHAINS + i;

                                nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
                                                 AR_PHY_CH_EXT_MINCCA_PWR);
                                nfarray[ext_idx] = sign_extend32(nf, 8);
                        }
                }
        }
}
static void ar9003_hw_set_nf_limits ( struct ath_hw ah) [static]
static void ar9003_hw_ani_cache_ini_regs ( struct ath_hw ah) [static]

Definition at line 1093 of file ath9k_ar9003_phy.c.

References ath9k_channel::ani, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, AR_PHY_SFCORR, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, AR_PHY_SFCORR_EXT_M2_THRESH, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, AR_PHY_SFCORR_M1_THRESH, AR_PHY_SFCORR_M2_THRESH, AR_PHY_SFCORR_M2COUNT_THR, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, ATH9K_ANI_ENABLE_MRC_CCK, ATH9K_ANI_FIRSTEP_LVL_NEW, ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, ATH9K_ANI_USE_OFDM_WEAK_SIG, ath9k_channel::chan, ath9k_channel::channel, ath9k_channel::channelFlags, ath_hw::curchan, ath9k_ani_default::cycpwrThr1, ath9k_ani_default::cycpwrThr1Ext, DBG2, ath9k_ani_default::firstep, ar5416AniState::firstepLevel, ath9k_ani_default::firstepLow, ath_hw::hw_version, ar5416AniState::iniDef, ath9k_ani_default::m1Thresh, ath9k_ani_default::m1ThreshExt, ath9k_ani_default::m1ThreshLow, ath9k_ani_default::m1ThreshLowExt, ath9k_ani_default::m2CountThr, ath9k_ani_default::m2CountThrLow, ath9k_ani_default::m2Thresh, ath9k_ani_default::m2ThreshExt, ath9k_ani_default::m2ThreshLow, ath9k_ani_default::m2ThreshLowExt, ath9k_hw_version::macRev, ath9k_hw_version::macVersion, ar5416AniState::mrcCCKOff, MS, ar5416AniState::ofdmWeakSigDetect, REG_READ, REG_READ_FIELD, ar5416AniState::spurImmunityLevel, and val.

Referenced by ar9003_hw_attach_phy_ops().

{
        struct ar5416AniState *aniState;
        struct ath9k_channel *chan = ah->curchan;
        struct ath9k_ani_default *iniDef;
        u32 val;

        aniState = &ah->curchan->ani;
        iniDef = &aniState->iniDef;

        DBG2("ath9k: "
                "ver %d.%d chan %d Mhz/0x%x\n",
                ah->hw_version.macVersion,
                ah->hw_version.macRev,
                chan->channel,
                chan->channelFlags);

        val = REG_READ(ah, AR_PHY_SFCORR);
        iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
        iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
        iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);

        val = REG_READ(ah, AR_PHY_SFCORR_LOW);
        iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
        iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
        iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);

        val = REG_READ(ah, AR_PHY_SFCORR_EXT);
        iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
        iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
        iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
        iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
        iniDef->firstep = REG_READ_FIELD(ah,
                                         AR_PHY_FIND_SIG,
                                         AR_PHY_FIND_SIG_FIRSTEP);
        iniDef->firstepLow = REG_READ_FIELD(ah,
                                            AR_PHY_FIND_SIG_LOW,
                                            AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
        iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
                                            AR_PHY_TIMING5,
                                            AR_PHY_TIMING5_CYCPWR_THR1);
        iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
                                               AR_PHY_EXT_CCA,
                                               AR_PHY_EXT_CYCPWR_THR1);

        /* these levels just got reset to defaults by the INI */
        aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
        aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
        aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
        aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
}
static void ar9003_hw_set_radar_params ( struct ath_hw ah,
struct ath_hw_radar_conf conf 
) [static]

Definition at line 1145 of file ath9k_ar9003_phy.c.

References AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA, AR_PHY_RADAR_0_FFT_ENA, AR_PHY_RADAR_0_FIRPWR, AR_PHY_RADAR_0_HEIGHT, AR_PHY_RADAR_0_INBAND, AR_PHY_RADAR_0_PRSSI, AR_PHY_RADAR_0_RRSSI, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK, AR_PHY_RADAR_1_MAX_RRSSI, AR_PHY_RADAR_1_MAXLEN, AR_PHY_RADAR_1_RELPWR_THRESH, AR_PHY_RADAR_1_RELSTEP_THRESH, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA, ath_hw_radar_conf::ext_channel, ath_hw_radar_conf::fir_power, ath_hw_radar_conf::pulse_height, ath_hw_radar_conf::pulse_inband, ath_hw_radar_conf::pulse_inband_step, ath_hw_radar_conf::pulse_maxlen, ath_hw_radar_conf::pulse_rssi, ath_hw_radar_conf::radar_inband, ath_hw_radar_conf::radar_rssi, REG_CLR_BIT, REG_SET_BIT, REG_WRITE, and SM.

Referenced by ar9003_hw_attach_phy_ops().

static void ar9003_hw_set_radar_conf ( struct ath_hw ah) [static]
static void ar9003_hw_antdiv_comb_conf_get ( struct ath_hw ah,
struct ath_hw_antcomb_conf antconf 
) [static]
static void ar9003_hw_antdiv_comb_conf_set ( struct ath_hw ah,
struct ath_hw_antcomb_conf antconf 
) [static]
void ar9003_hw_attach_phy_ops ( struct ath_hw ah)

Definition at line 1232 of file ath9k_ar9003_phy.c.

References ath_hw_private_ops::ani_cache_ini_regs, ath_hw_private_ops::ani_control, ath_hw_ops::antdiv_comb_conf_get, ath_hw_ops::antdiv_comb_conf_set, ar9003_hw_ani_cache_ini_regs(), ar9003_hw_ani_control(), ar9003_hw_antdiv_comb_conf_get(), ar9003_hw_antdiv_comb_conf_set(), ar9003_hw_compute_pll_control(), ar9003_hw_do_getnf(), ar9003_hw_init_bb(), ar9003_hw_mark_phy_inactive(), ar9003_hw_process_ini(), ar9003_hw_rfbus_done(), ar9003_hw_rfbus_req(), ar9003_hw_set_channel(), ar9003_hw_set_channel_regs(), ar9003_hw_set_delta_slope(), ar9003_hw_set_diversity(), ar9003_hw_set_nf_limits(), ar9003_hw_set_radar_conf(), ar9003_hw_set_radar_params(), ar9003_hw_set_rfmode(), ar9003_hw_spur_mitigate(), AR_PHY_CCA_0, AR_PHY_CCA_1, AR_PHY_CCA_2, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_1, AR_PHY_EXT_CCA_2, ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, ath_hw_private_ops::init_bb, ath_hw_private_ops::mark_phy_inactive, memcpy(), ath_hw::nf_regs, ath_hw_private_ops::process_ini, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::rfbus_done, ath_hw_private_ops::rfbus_req, ath_hw_private_ops::set_channel_regs, ath_hw_private_ops::set_delta_slope, ath_hw_private_ops::set_diversity, ath_hw_private_ops::set_radar_params, ath_hw_private_ops::set_rfmode, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9003_hw_attach_ops().

void ar9003_hw_disable_phy_restart ( struct ath_hw ah)

Definition at line 1270 of file ath9k_ar9003_phy.c.

References AR_PHY_RESTART, AR_PHY_RESTART_ENA, REG_READ, REG_WRITE, and val.

Referenced by ath9k_hw_reset().


Variable Documentation

const int firstep_table[] [static]
Initial value:

        { -4, -2,  0,  2,  4,  6,  8, 10, 12 }

Definition at line 25 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int cycpwrThr1_table[] [static]
Initial value:

        { -6, -4, -2,  0,  2,  4,  6,  8 }

Definition at line 29 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m1ThreshLow_off = 127 [static]

Definition at line 36 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m2ThreshLow_off = 127 [static]

Definition at line 37 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m1Thresh_off = 127 [static]

Definition at line 38 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m2Thresh_off = 127 [static]

Definition at line 39 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m2CountThr_off = 31 [static]

Definition at line 40 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m2CountThrLow_off = 63 [static]

Definition at line 41 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m1ThreshLowExt_off = 127 [static]

Definition at line 42 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m2ThreshLowExt_off = 127 [static]

Definition at line 43 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m1ThreshExt_off = 127 [static]

Definition at line 44 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

const int m2ThreshExt_off = 127 [static]

Definition at line 45 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().