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Macros | |
#define | AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ |
#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ |
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static |
Definition at line 25 of file ath9k_mac.c.
References ah, AR_IMR_S0, AR_IMR_S0_QCU_TXDESC, AR_IMR_S0_QCU_TXOK, AR_IMR_S1, AR_IMR_S1_QCU_TXEOL, AR_IMR_S1_QCU_TXERR, AR_IMR_S2, AR_IMR_S2_QCU_TXURN, DBG2, ENABLE_REGWRITE_BUFFER, REG_WRITE, REGWRITE_BUFFER_FLUSH, and SM.
Referenced by ath9k_hw_releasetxqueue(), and ath9k_hw_resettxqueue().
Definition at line 50 of file ath9k_mac.c.
References ah, AR_QTXDP, REG_WRITE, and txdp.
Referenced by ath_tx_txqaddbuf().
Definition at line 55 of file ath9k_mac.c.
References ah, AR_Q_TXE, DBG2, and REG_WRITE.
Referenced by ath_tx_txqaddbuf().
Definition at line 62 of file ath9k_mac.c.
References ah, AR_Q_STS_PEND_FR_CNT, AR_Q_TXE, AR_QSTS, and REG_READ.
Referenced by ath9k_hw_abort_tx_dma(), ath9k_hw_channel_change(), and ath_drain_all_txq().
int ath9k_hw_updatetxtriglevel | ( | struct ath_hw * | ah, |
int | bIncTrigLevel | ||
) |
ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
@ah: atheros hardware struct @bIncTrigLevel: whether or not the frame trigger level should be updated
The frame trigger level specifies the minimum number of bytes, in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO before the PCU will initiate sending the frame on the air. This can mean we initiate transmit before a full frame is on the PCU TX FIFO. Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs first)
Caution must be taken to ensure to set the frame trigger level based on the DMA request size. For example if the DMA request size is set to 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because there need to be enough space in the tx FIFO for the requested transfer size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set the threshold to a value beyond 6, then the transmit will hang.
Current dual stream devices have a PCU TX FIFO size of 8 KB. Current single stream devices have a PCU TX FIFO size of 4 KB, however, there is a hardware issue which forces us to use 2 KB instead so the frame trigger level must not exceed 2 KB for these chipsets.
Definition at line 101 of file ath9k_mac.c.
References ah, AR_FTRIG, AR_TXCFG, ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), MIN_TX_FIFO_THRESHOLD, MS, REG_READ, REG_WRITE, SM, and txcfg.
Referenced by ar9002_hw_proc_txdesc(), ar9003_hw_proc_txdesc(), and ath_isr().
void ath9k_hw_abort_tx_dma | ( | struct ath_hw * | ah | ) |
Definition at line 129 of file ath9k_mac.c.
References ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF, AR_DIAG_FORCE_CH_IDLE_HIGH, AR_DIAG_SW, AR_NUM_QCU, AR_PCU_CLEAR_VMF, AR_PCU_FORCE_QUIET_COLL, AR_PCU_MISC, AR_Q_TXD, AR_Q_TXD_M, ath9k_hw_numtxpending(), REG_CLR_BIT, REG_SET_BIT, REG_WRITE, and udelay().
Referenced by ath_drain_all_txq().
int ath9k_hw_set_txq_props | ( | struct ath_hw * | ah, |
int | q, | ||
const struct ath9k_tx_queue_info * | qinfo | ||
) |
Definition at line 162 of file ath9k_mac.c.
References ah, ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USEDEFAULT, DBG, DBG2, INIT_AIFS, INIT_CWMAX, INIT_LG_RETRY, INIT_SH_RETRY, min, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_burstTime, ath9k_tx_queue_info::tqi_cbrOverflowLimit, ath9k_tx_queue_info::tqi_cbrPeriod, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_lgretry, ath9k_tx_queue_info::tqi_priority, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_readyTime, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_subtype, ath9k_tx_queue_info::tqi_type, and ath9k_tx_queue_info::tqi_ver.
Referenced by ath9k_hw_setuptxqueue().
int ath9k_hw_setuptxqueue | ( | struct ath_hw * | ah, |
enum ath9k_tx_queue | type, | ||
const struct ath9k_tx_queue_info * | qinfo | ||
) |
Definition at line 216 of file ath9k_mac.c.
References ah, ath9k_hw_set_txq_props(), ATH9K_NUM_TX_QUEUES, ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USEDEFAULT, DBG, DBG2, INIT_AIFS, INIT_CWMAX, INIT_LG_RETRY, INIT_SH_RETRY, memset(), NULL, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_lgretry, ath9k_tx_queue_info::tqi_physCompBuf, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_type, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXERRINT_ENABLE, TXQ_FLAG_TXOKINT_ENABLE, TXQ_FLAG_TXURNINT_ENABLE, and type.
Referenced by ath_txq_setup().
Definition at line 259 of file ath9k_mac.c.
References ah, ath9k_hw_set_txq_interrupts(), ATH9K_TX_QUEUE_INACTIVE, DBG, DBG2, and ath9k_tx_queue_info::tqi_type.
Referenced by ath_tx_cleanupq(), and ath_txq_setup().
Definition at line 283 of file ath9k_mac.c.
References __unused, ah, AR_D_CHNTIME_DUR, AR_D_CHNTIME_EN, AR_D_LCL_IFS_AIFS, AR_D_LCL_IFS_CWMAX, AR_D_LCL_IFS_CWMIN, AR_D_MISC_ARB_LOCKOUT_CNTRL, AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, AR_D_MISC_CW_BKOFF_EN, AR_D_MISC_FRAG_BKOFF_EN, AR_D_MISC_FRAG_WAIT_EN, AR_D_MISC_POST_FR_BKOFF_DIS, AR_D_RETRY_LIMIT_FR_SH, AR_D_RETRY_LIMIT_STA_LG, AR_D_RETRY_LIMIT_STA_SH, AR_DCHNTIME, AR_DLCL_IFS, AR_DMISC, AR_DRETRY_LIMIT, AR_Q_CBRCFG_INTERVAL, AR_Q_CBRCFG_OVF_THRESH, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN, AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN, AR_Q_MISC_DCU_EARLY_TERM_REQ, AR_Q_MISC_FSP_CBR, AR_Q_MISC_RDYTIME_EXP_POLICY, AR_Q_RDYTIMECFG_DURATION, AR_Q_RDYTIMECFG_EN, AR_QCBRCFG, AR_QMISC, AR_QRDYTIMECFG, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, ath9k_hw_set_txq_interrupts(), ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS, ATH9K_TXQ_USEDEFAULT, ath9k_channel::chan, DBG, DBG2, ENABLE_REGWRITE_BUFFER, INIT_CWMIN, INIT_CWMIN_11B, INIT_SLG_RETRY, INIT_SSH_RETRY, IS_CHAN_B, REG_SET_BIT, REG_WRITE, REGWRITE_BUFFER_FLUSH, SM, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_burstTime, ath9k_tx_queue_info::tqi_cbrOverflowLimit, ath9k_tx_queue_info::tqi_cbrPeriod, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_intFlags, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_readyTime, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_type, TXQ_FLAG_BACKOFF_DISABLE, TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXEOLINT_ENABLE, TXQ_FLAG_TXERRINT_ENABLE, TXQ_FLAG_TXOKINT_ENABLE, TXQ_FLAG_TXURNINT_ENABLE, and value.
Referenced by ath9k_hw_reset().
int ath9k_hw_rxprocdesc | ( | struct ath_hw * | ah, |
struct ath_desc * | ds, | ||
struct ath_rx_status * | rs, | ||
u64 tsf | __unused | ||
) |
Definition at line 394 of file ath9k_mac.c.
References ah, AR5416DESC, AR_2040, AR_CRCErr, AR_DataLen, AR_DecryptBusyErr, AR_DecryptCRCErr, AR_GI, AR_KeyIdx, AR_KeyMiss, AR_MichaelErr, AR_PHYErr, AR_PHYErrCode, AR_PostDelimCRCErr, AR_PreDelimCRCErr, AR_RxAggr, AR_RxAntenna, AR_RxDone, AR_RxFrameOK, AR_RxKeyIdxValid, AR_RxMore, AR_RxMoreAggr, AR_RxRSSIAnt00, AR_RxRSSIAnt01, AR_RxRSSIAnt02, AR_RxRSSIAnt10, AR_RxRSSIAnt11, AR_RxRSSIAnt12, AR_RxRSSICombined, ATH9K_RSSI_BAD, ATH9K_RX_2040, ATH9K_RX_DECRYPT_BUSY, ATH9K_RX_DELIM_CRC_POST, ATH9K_RX_DELIM_CRC_PRE, ATH9K_RX_GI, ATH9K_RXERR_CRC, ATH9K_RXERR_DECRYPT, ATH9K_RXERR_MIC, ATH9K_RXERR_PHY, ATH9K_RXKEYIX_INVALID, ds, EINPROGRESS, MS, ath_rx_status::rs_antenna, ath_rx_status::rs_datalen, ath_rx_status::rs_flags, ath_rx_status::rs_isaggr, ath_rx_status::rs_keyix, ath_rx_status::rs_more, ath_rx_status::rs_moreaggr, ath_rx_status::rs_phyerr, ath_rx_status::rs_rate, ath_rx_status::rs_rssi, ath_rx_status::rs_rssi_ctl0, ath_rx_status::rs_rssi_ctl1, ath_rx_status::rs_rssi_ctl2, ath_rx_status::rs_rssi_ext0, ath_rx_status::rs_rssi_ext1, ath_rx_status::rs_rssi_ext2, ath_rx_status::rs_status, ath_rx_status::rs_tstamp, ar5416_desc::rx, RXSTATUS_RATE, and ar5416_desc::u.
Referenced by ath_get_next_rx_buf().
int ath9k_hw_setrxabort | ( | struct ath_hw * | ah, |
int | set | ||
) |
Definition at line 490 of file ath9k_mac.c.
References ah, AH_WAIT_TIMEOUT, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, ath9k_hw_wait(), DBG, reg, REG_CLR_BIT, REG_READ, REG_SET_BIT, and set.
Referenced by ath_isr().
Definition at line 519 of file ath9k_mac.c.
References ah, AR_RXDP, REG_WRITE, and rxdp.
Referenced by ath_rx_buf_link(), and ath_startrecv().
void ath9k_hw_startpcureceive | ( | struct ath_hw * | ah, |
int | is_scanning | ||
) |
Definition at line 524 of file ath9k_mac.c.
References ah, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, ath9k_ani_reset(), and REG_CLR_BIT.
Referenced by ath_startrecv().
void ath9k_hw_abortpcurecv | ( | struct ath_hw * | ah | ) |
Definition at line 531 of file ath9k_mac.c.
References ah, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, and REG_SET_BIT.
Referenced by ath_stoprecv().
int ath9k_hw_stopdmarecv | ( | struct ath_hw * | ah, |
int * | reset | ||
) |
Definition at line 536 of file ath9k_mac.c.
References ah, AH_RX_STOP_DMA_TIMEOUT, AH_TIME_QUANTUM, AR_CR, AR_CR_RXD, AR_CR_RXE, AR_DIAG_SW, AR_DMADBG_7, AR_MACMISC, AR_MACMISC_DMA_OBS_LINE_8, AR_MACMISC_DMA_OBS_S, AR_MACMISC_MISC_OBS_BUS_1, AR_MACMISC_MISC_OBS_BUS_MSB_S, AR_SREV_9300_20_OR_LATER, DBG, REG_READ, REG_WRITE, and udelay().
Referenced by ath_stoprecv().
int ath9k_hw_intrpend | ( | struct ath_hw * | ah | ) |
Definition at line 583 of file ath9k_mac.c.
References ah, AR_IER_ENABLE, AR_INTR_ASYNC_CAUSE, AR_INTR_MAC_IRQ, AR_INTR_SPURIOUS, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_DEFAULT, AR_SREV_9100, and REG_READ.
Referenced by ath_isr().
void ath9k_hw_disable_interrupts | ( | struct ath_hw * | ah | ) |
Definition at line 602 of file ath9k_mac.c.
References ah, AR_IER, AR_INTR_ASYNC_ENABLE, AR_INTR_SYNC_ENABLE, AR_SREV_9100, DBG2, REG_READ, and REG_WRITE.
Referenced by ath9k_hw_set_interrupts(), ath9k_hw_updatetxtriglevel(), ath9k_stop(), ath_isr(), ath_radio_disable(), ath_reset(), and ath_set_channel().
void ath9k_hw_enable_interrupts | ( | struct ath_hw * | ah | ) |
Definition at line 616 of file ath9k_mac.c.
References ah, AR_IER, AR_IMR, AR_INTR_ASYNC_ENABLE, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ, AR_INTR_SYNC_DEFAULT, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_HOST1_FATAL, AR_INTR_SYNC_MASK, AR_SREV_9100, AR_SREV_9340, ATH9K_INT_GLOBAL, DBG2, REG_READ, and REG_WRITE.
Referenced by ath9k_hw_set_interrupts(), ath9k_hw_updatetxtriglevel(), and ath9k_tasklet().
void ath9k_hw_set_interrupts | ( | struct ath_hw * | ah, |
unsigned int | ints | ||
) |
Definition at line 641 of file ath9k_mac.c.
References ah, AR_IMR, AR_IMR_BCNMISC, AR_IMR_GENTMR, AR_IMR_RXDESC, AR_IMR_RXERR, AR_IMR_RXINTM, AR_IMR_RXMINTR, AR_IMR_RXOK, AR_IMR_RXOK_HP, AR_IMR_RXOK_LP, AR_IMR_S2, AR_IMR_S2_CABEND, AR_IMR_S2_CABTO, AR_IMR_S2_CST, AR_IMR_S2_DTIM, AR_IMR_S2_DTIMSYNC, AR_IMR_S2_GTT, AR_IMR_S2_TIM, AR_IMR_S2_TSFOOR, AR_IMR_S5, AR_IMR_S5_TIM_TIMER, AR_IMR_TXDESC, AR_IMR_TXEOL, AR_IMR_TXERR, AR_IMR_TXINTM, AR_IMR_TXMINTR, AR_IMR_TXOK, AR_SREV_9300_20_OR_LATER, ATH9K_HW_CAP_AUTOSLEEP, ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), ATH9K_INT_BMISC, ATH9K_INT_CABEND, ATH9K_INT_COMMON, ATH9K_INT_CST, ATH9K_INT_DTIM, ATH9K_INT_DTIMSYNC, ATH9K_INT_GENTIMER, ATH9K_INT_GLOBAL, ATH9K_INT_GTT, ATH9K_INT_RX, ATH9K_INT_TIM, ATH9K_INT_TIM_TIMER, ATH9K_INT_TSFOOR, ATH9K_INT_TX, DBG2, ath9k_hw_capabilities::hw_caps, REG_CLR_BIT, REG_SET_BIT, and REG_WRITE.
Referenced by ath9k_irq(), ath9k_start(), ath_reset(), and ath_set_channel().