iPXE
ath9k_mac.c
Go to the documentation of this file.
00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 #include <ipxe/io.h>
00021 
00022 #include "hw.h"
00023 #include "hw-ops.h"
00024 
00025 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
00026                                         struct ath9k_tx_queue_info *qi __unused)
00027 {
00028         DBG2("ath9k: "
00029                 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
00030                 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
00031                 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
00032                 ah->txurn_interrupt_mask);
00033 
00034         ENABLE_REGWRITE_BUFFER(ah);
00035 
00036         REG_WRITE(ah, AR_IMR_S0,
00037                   SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
00038                   | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
00039         REG_WRITE(ah, AR_IMR_S1,
00040                   SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
00041                   | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
00042 
00043         ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
00044         ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
00045         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
00046 
00047         REGWRITE_BUFFER_FLUSH(ah);
00048 }
00049 
00050 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
00051 {
00052         REG_WRITE(ah, AR_QTXDP(q), txdp);
00053 }
00054 
00055 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
00056 {
00057         DBG2("ath9k: "
00058                 "Enable TXE on queue: %d\n", q);
00059         REG_WRITE(ah, AR_Q_TXE, 1 << q);
00060 }
00061 
00062 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
00063 {
00064         u32 npend;
00065 
00066         npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
00067         if (npend == 0) {
00068 
00069                 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
00070                         npend = 1;
00071         }
00072 
00073         return npend;
00074 }
00075 
00076 /**
00077  * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
00078  *
00079  * @ah: atheros hardware struct
00080  * @bIncTrigLevel: whether or not the frame trigger level should be updated
00081  *
00082  * The frame trigger level specifies the minimum number of bytes,
00083  * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
00084  * before the PCU will initiate sending the frame on the air. This can
00085  * mean we initiate transmit before a full frame is on the PCU TX FIFO.
00086  * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
00087  * first)
00088  *
00089  * Caution must be taken to ensure to set the frame trigger level based
00090  * on the DMA request size. For example if the DMA request size is set to
00091  * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
00092  * there need to be enough space in the tx FIFO for the requested transfer
00093  * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
00094  * the threshold to a value beyond 6, then the transmit will hang.
00095  *
00096  * Current dual   stream devices have a PCU TX FIFO size of 8 KB.
00097  * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
00098  * there is a hardware issue which forces us to use 2 KB instead so the
00099  * frame trigger level must not exceed 2 KB for these chipsets.
00100  */
00101 int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel)
00102 {
00103         u32 txcfg, curLevel, newLevel;
00104 
00105         if (ah->tx_trig_level >= ah->config.max_txtrig_level)
00106                 return 0;
00107 
00108         ath9k_hw_disable_interrupts(ah);
00109 
00110         txcfg = REG_READ(ah, AR_TXCFG);
00111         curLevel = MS(txcfg, AR_FTRIG);
00112         newLevel = curLevel;
00113         if (bIncTrigLevel) {
00114                 if (curLevel < ah->config.max_txtrig_level)
00115                         newLevel++;
00116         } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
00117                 newLevel--;
00118         if (newLevel != curLevel)
00119                 REG_WRITE(ah, AR_TXCFG,
00120                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
00121 
00122         ath9k_hw_enable_interrupts(ah);
00123 
00124         ah->tx_trig_level = newLevel;
00125 
00126         return newLevel != curLevel;
00127 }
00128 
00129 void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
00130 {
00131         int i, q;
00132 
00133         REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
00134 
00135         REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
00136         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
00137         REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
00138 
00139         for (q = 0; q < AR_NUM_QCU; q++) {
00140                 for (i = 0; i < 1000; i++) {
00141                         if (i)
00142                                 udelay(5);
00143 
00144                         if (!ath9k_hw_numtxpending(ah, q))
00145                                 break;
00146                 }
00147         }
00148 
00149         REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
00150         REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
00151         REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
00152 
00153         REG_WRITE(ah, AR_Q_TXD, 0);
00154 }
00155 
00156 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
00157 {
00158         *txqs &= ah->intr_txqs;
00159         ah->intr_txqs &= ~(*txqs);
00160 }
00161 
00162 int ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
00163                             const struct ath9k_tx_queue_info *qinfo)
00164 {
00165         u32 cw;
00166         struct ath9k_tx_queue_info *qi;
00167 
00168         qi = &ah->txq[q];
00169         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
00170                 DBG("ath9k: "
00171                         "Set TXQ properties, inactive queue: %d\n", q);
00172                 return 0;
00173         }
00174 
00175         DBG2("ath9k: Set queue properties for: %d\n", q);
00176 
00177         qi->tqi_ver = qinfo->tqi_ver;
00178         qi->tqi_subtype = qinfo->tqi_subtype;
00179         qi->tqi_qflags = qinfo->tqi_qflags;
00180         qi->tqi_priority = qinfo->tqi_priority;
00181         if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
00182                 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
00183         else
00184                 qi->tqi_aifs = INIT_AIFS;
00185         if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
00186                 cw = min(qinfo->tqi_cwmin, 1024U);
00187                 qi->tqi_cwmin = 1;
00188                 while (qi->tqi_cwmin < cw)
00189                         qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
00190         } else
00191                 qi->tqi_cwmin = qinfo->tqi_cwmin;
00192         if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
00193                 cw = min(qinfo->tqi_cwmax, 1024U);
00194                 qi->tqi_cwmax = 1;
00195                 while (qi->tqi_cwmax < cw)
00196                         qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
00197         } else
00198                 qi->tqi_cwmax = INIT_CWMAX;
00199 
00200         if (qinfo->tqi_shretry != 0)
00201                 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
00202         else
00203                 qi->tqi_shretry = INIT_SH_RETRY;
00204         if (qinfo->tqi_lgretry != 0)
00205                 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
00206         else
00207                 qi->tqi_lgretry = INIT_LG_RETRY;
00208         qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
00209         qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
00210         qi->tqi_burstTime = qinfo->tqi_burstTime;
00211         qi->tqi_readyTime = qinfo->tqi_readyTime;
00212 
00213         return 1;
00214 }
00215 
00216 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
00217                           const struct ath9k_tx_queue_info *qinfo)
00218 {
00219         struct ath9k_tx_queue_info *qi;
00220         int q;
00221 
00222         for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
00223                 if (ah->txq[q].tqi_type ==
00224                     ATH9K_TX_QUEUE_INACTIVE)
00225                         break;
00226         if (q == ATH9K_NUM_TX_QUEUES) {
00227                 DBG("No available TX queue\n");
00228                 return -1;
00229         }
00230 
00231         DBG2("ath9K: Setup TX queue: %d\n", q);
00232 
00233         qi = &ah->txq[q];
00234         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
00235                 DBG("ath9k: TX queue: %d already active\n", q);
00236                 return -1;
00237         }
00238         memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
00239         qi->tqi_type = type;
00240         if (qinfo == NULL) {
00241                 qi->tqi_qflags =
00242                         TXQ_FLAG_TXOKINT_ENABLE
00243                         | TXQ_FLAG_TXERRINT_ENABLE
00244                         | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
00245                 qi->tqi_aifs = INIT_AIFS;
00246                 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
00247                 qi->tqi_cwmax = INIT_CWMAX;
00248                 qi->tqi_shretry = INIT_SH_RETRY;
00249                 qi->tqi_lgretry = INIT_LG_RETRY;
00250                 qi->tqi_physCompBuf = 0;
00251         } else {
00252                 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
00253                 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
00254         }
00255 
00256         return q;
00257 }
00258 
00259 int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
00260 {
00261         struct ath9k_tx_queue_info *qi;
00262 
00263         qi = &ah->txq[q];
00264         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
00265                 DBG("ath9k: "
00266                         "Release TXQ, inactive queue: %d\n", q);
00267                 return 0;
00268         }
00269 
00270         DBG2("ath9k: Release TX queue: %d\n", q);
00271 
00272         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
00273         ah->txok_interrupt_mask &= ~(1 << q);
00274         ah->txerr_interrupt_mask &= ~(1 << q);
00275         ah->txdesc_interrupt_mask &= ~(1 << q);
00276         ah->txeol_interrupt_mask &= ~(1 << q);
00277         ah->txurn_interrupt_mask &= ~(1 << q);
00278         ath9k_hw_set_txq_interrupts(ah, qi);
00279 
00280         return 1;
00281 }
00282 
00283 int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
00284 {
00285         struct ath9k_channel *chan = ah->curchan;
00286         struct ath9k_tx_queue_info *qi;
00287         u32 cwMin, chanCwMin, value __unused;
00288 
00289         qi = &ah->txq[q];
00290         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
00291                 DBG("ath9k: "
00292                         "Reset TXQ, inactive queue: %d\n", q);
00293                 return 1;
00294         }
00295 
00296         DBG2("ath9k: Reset TX queue: %d\n", q);
00297 
00298         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
00299                 if (chan && IS_CHAN_B(chan))
00300                         chanCwMin = INIT_CWMIN_11B;
00301                 else
00302                         chanCwMin = INIT_CWMIN;
00303 
00304                 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
00305         } else
00306                 cwMin = qi->tqi_cwmin;
00307 
00308         ENABLE_REGWRITE_BUFFER(ah);
00309 
00310         REG_WRITE(ah, AR_DLCL_IFS(q),
00311                   SM(cwMin, AR_D_LCL_IFS_CWMIN) |
00312                   SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
00313                   SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
00314 
00315         REG_WRITE(ah, AR_DRETRY_LIMIT(q),
00316                   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
00317                   SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
00318                   SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
00319 
00320         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
00321 
00322         if (AR_SREV_9340(ah))
00323                 REG_WRITE(ah, AR_DMISC(q),
00324                           AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
00325         else
00326                 REG_WRITE(ah, AR_DMISC(q),
00327                           AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
00328 
00329         if (qi->tqi_cbrPeriod) {
00330                 REG_WRITE(ah, AR_QCBRCFG(q),
00331                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
00332                           SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
00333                 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
00334                             (qi->tqi_cbrOverflowLimit ?
00335                              AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
00336         }
00337         if (qi->tqi_readyTime) {
00338                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
00339                           SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
00340                           AR_Q_RDYTIMECFG_EN);
00341         }
00342 
00343         REG_WRITE(ah, AR_DCHNTIME(q),
00344                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
00345                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
00346 
00347         if (qi->tqi_burstTime
00348             && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
00349                 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
00350 
00351         if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
00352                 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
00353 
00354         REGWRITE_BUFFER_FLUSH(ah);
00355 
00356         if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
00357                 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
00358 
00359         if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
00360                 REG_SET_BIT(ah, AR_DMISC(q),
00361                             SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
00362                                AR_D_MISC_ARB_LOCKOUT_CNTRL) |
00363                             AR_D_MISC_POST_FR_BKOFF_DIS);
00364         }
00365 
00366         if (AR_SREV_9300_20_OR_LATER(ah))
00367                 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
00368 
00369         if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
00370                 ah->txok_interrupt_mask |= 1 << q;
00371         else
00372                 ah->txok_interrupt_mask &= ~(1 << q);
00373         if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
00374                 ah->txerr_interrupt_mask |= 1 << q;
00375         else
00376                 ah->txerr_interrupt_mask &= ~(1 << q);
00377         if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
00378                 ah->txdesc_interrupt_mask |= 1 << q;
00379         else
00380                 ah->txdesc_interrupt_mask &= ~(1 << q);
00381         if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
00382                 ah->txeol_interrupt_mask |= 1 << q;
00383         else
00384                 ah->txeol_interrupt_mask &= ~(1 << q);
00385         if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
00386                 ah->txurn_interrupt_mask |= 1 << q;
00387         else
00388                 ah->txurn_interrupt_mask &= ~(1 << q);
00389         ath9k_hw_set_txq_interrupts(ah, qi);
00390 
00391         return 1;
00392 }
00393 
00394 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
00395                         struct ath_rx_status *rs, u64 tsf __unused)
00396 {
00397         struct ar5416_desc ads;
00398         struct ar5416_desc *adsp = AR5416DESC(ds);
00399         u32 phyerr;
00400 
00401         if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
00402                 return -EINPROGRESS;
00403 
00404         ads.u.rx = adsp->u.rx;
00405 
00406         rs->rs_status = 0;
00407         rs->rs_flags = 0;
00408 
00409         rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
00410         rs->rs_tstamp = ads.AR_RcvTimestamp;
00411 
00412         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
00413                 rs->rs_rssi = ATH9K_RSSI_BAD;
00414                 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
00415                 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
00416                 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
00417                 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
00418                 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
00419                 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
00420         } else {
00421                 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
00422                 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
00423                                                 AR_RxRSSIAnt00);
00424                 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
00425                                                 AR_RxRSSIAnt01);
00426                 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
00427                                                 AR_RxRSSIAnt02);
00428                 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
00429                                                 AR_RxRSSIAnt10);
00430                 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
00431                                                 AR_RxRSSIAnt11);
00432                 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
00433                                                 AR_RxRSSIAnt12);
00434         }
00435         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
00436                 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
00437         else
00438                 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
00439 
00440         rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
00441         rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
00442 
00443         rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
00444         rs->rs_moreaggr =
00445                 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
00446         rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
00447         rs->rs_flags =
00448                 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
00449         rs->rs_flags |=
00450                 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
00451 
00452         if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
00453                 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
00454         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
00455                 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
00456         if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
00457                 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
00458 
00459         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
00460                 /*
00461                  * Treat these errors as mutually exclusive to avoid spurious
00462                  * extra error reports from the hardware. If a CRC error is
00463                  * reported, then decryption and MIC errors are irrelevant,
00464                  * the frame is going to be dropped either way
00465                  */
00466                 if (ads.ds_rxstatus8 & AR_CRCErr)
00467                         rs->rs_status |= ATH9K_RXERR_CRC;
00468                 else if (ads.ds_rxstatus8 & AR_PHYErr) {
00469                         rs->rs_status |= ATH9K_RXERR_PHY;
00470                         phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
00471                         rs->rs_phyerr = phyerr;
00472                 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
00473                         rs->rs_status |= ATH9K_RXERR_DECRYPT;
00474                 else if (ads.ds_rxstatus8 & AR_MichaelErr)
00475                         rs->rs_status |= ATH9K_RXERR_MIC;
00476                 else if (ads.ds_rxstatus8 & AR_KeyMiss)
00477                         rs->rs_status |= ATH9K_RXERR_DECRYPT;
00478         }
00479 
00480         return 0;
00481 }
00482 
00483 /*
00484  * This can stop or re-enables RX.
00485  *
00486  * If bool is set this will kill any frame which is currently being
00487  * transferred between the MAC and baseband and also prevent any new
00488  * frames from getting started.
00489  */
00490 int ath9k_hw_setrxabort(struct ath_hw *ah, int set)
00491 {
00492         u32 reg;
00493 
00494         if (set) {
00495                 REG_SET_BIT(ah, AR_DIAG_SW,
00496                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
00497 
00498                 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
00499                                    0, AH_WAIT_TIMEOUT)) {
00500                         REG_CLR_BIT(ah, AR_DIAG_SW,
00501                                     (AR_DIAG_RX_DIS |
00502                                      AR_DIAG_RX_ABORT));
00503 
00504                         reg = REG_READ(ah, AR_OBS_BUS_1);
00505                         DBG("ath9k: "
00506                                 "RX failed to go idle in 10 ms RXSM=0x%x\n",
00507                                 reg);
00508 
00509                         return 0;
00510                 }
00511         } else {
00512                 REG_CLR_BIT(ah, AR_DIAG_SW,
00513                             (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
00514         }
00515 
00516         return 1;
00517 }
00518 
00519 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
00520 {
00521         REG_WRITE(ah, AR_RXDP, rxdp);
00522 }
00523 
00524 void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning)
00525 {
00526         ath9k_ani_reset(ah, is_scanning);
00527 
00528         REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
00529 }
00530 
00531 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
00532 {
00533         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
00534 }
00535 
00536 int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset)
00537 {
00538 #define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
00539         u32 mac_status, last_mac_status = 0;
00540         int i;
00541 
00542         /* Enable access to the DMA observation bus */
00543         REG_WRITE(ah, AR_MACMISC,
00544                   ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
00545                    (AR_MACMISC_MISC_OBS_BUS_1 <<
00546                     AR_MACMISC_MISC_OBS_BUS_MSB_S)));
00547 
00548         REG_WRITE(ah, AR_CR, AR_CR_RXD);
00549 
00550         /* Wait for rx enable bit to go low */
00551         for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
00552                 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
00553                         break;
00554 
00555                 if (!AR_SREV_9300_20_OR_LATER(ah)) {
00556                         mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
00557                         if (mac_status == 0x1c0 && mac_status == last_mac_status) {
00558                                 *reset = 1;
00559                                 break;
00560                         }
00561 
00562                         last_mac_status = mac_status;
00563                 }
00564 
00565                 udelay(AH_TIME_QUANTUM);
00566         }
00567 
00568         if (i == 0) {
00569                 DBG("ath9k: "
00570                         "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
00571                         AH_RX_STOP_DMA_TIMEOUT / 1000,
00572                         REG_READ(ah, AR_CR),
00573                         REG_READ(ah, AR_DIAG_SW),
00574                         REG_READ(ah, AR_DMADBG_7));
00575                 return 0;
00576         } else {
00577                 return 1;
00578         }
00579 
00580 #undef AH_RX_STOP_DMA_TIMEOUT
00581 }
00582 
00583 int ath9k_hw_intrpend(struct ath_hw *ah)
00584 {
00585         u32 host_isr;
00586 
00587         if (AR_SREV_9100(ah) || !(ah->ah_ier & AR_IER_ENABLE))
00588                 return 1;
00589 
00590         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
00591         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
00592                 return 1;
00593 
00594         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
00595         if ((host_isr & AR_INTR_SYNC_DEFAULT)
00596             && (host_isr != AR_INTR_SPURIOUS))
00597                 return 1;
00598 
00599         return 0;
00600 }
00601 
00602 void ath9k_hw_disable_interrupts(struct ath_hw *ah)
00603 {
00604         DBG2("ath9k: disable IER\n");
00605         REG_WRITE(ah, AR_IER, ah->ah_ier);
00606         (void) REG_READ(ah, AR_IER);
00607         if (!AR_SREV_9100(ah)) {
00608                 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
00609                 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
00610 
00611                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
00612                 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
00613         }
00614 }
00615 
00616 void ath9k_hw_enable_interrupts(struct ath_hw *ah)
00617 {
00618         u32 sync_default = AR_INTR_SYNC_DEFAULT;
00619 
00620         if (!(ah->imask & ATH9K_INT_GLOBAL))
00621                 return;
00622 
00623         if (AR_SREV_9340(ah))
00624                 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
00625 
00626         DBG2("ath9k: enable IER\n");
00627         REG_WRITE(ah, AR_IER, ah->ah_ier);
00628         if (!AR_SREV_9100(ah)) {
00629                 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
00630                           AR_INTR_MAC_IRQ);
00631                 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
00632 
00633 
00634                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
00635                 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
00636         }
00637         DBG2("ath9k: AR_IMR 0x%x IER 0x%x\n",
00638                 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
00639 }
00640 
00641 void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints)
00642 {
00643         enum ath9k_int omask = ah->imask;
00644         u32 mask, mask2;
00645         struct ath9k_hw_capabilities *pCap = &ah->caps;
00646 
00647         if (!(ints & ATH9K_INT_GLOBAL))
00648                 ath9k_hw_disable_interrupts(ah);
00649 
00650         DBG2("ath9k: 0x%x => 0x%x\n", omask, ints);
00651 
00652         /* TODO: global int Ref count */
00653         mask = ints & ATH9K_INT_COMMON;
00654         mask2 = 0;
00655 
00656         if (ints & ATH9K_INT_TX) {
00657                 if (ah->config.tx_intr_mitigation)
00658                         mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
00659                 else {
00660                         if (ah->txok_interrupt_mask)
00661                                 mask |= AR_IMR_TXOK;
00662                         if (ah->txdesc_interrupt_mask)
00663                                 mask |= AR_IMR_TXDESC;
00664                 }
00665                 if (ah->txerr_interrupt_mask)
00666                         mask |= AR_IMR_TXERR;
00667                 if (ah->txeol_interrupt_mask)
00668                         mask |= AR_IMR_TXEOL;
00669         }
00670         if (ints & ATH9K_INT_RX) {
00671                 if (AR_SREV_9300_20_OR_LATER(ah)) {
00672                         mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
00673                         if (ah->config.rx_intr_mitigation) {
00674                                 mask &= ~AR_IMR_RXOK_LP;
00675                                 mask |=  AR_IMR_RXMINTR | AR_IMR_RXINTM;
00676                         } else {
00677                                 mask |= AR_IMR_RXOK_LP;
00678                         }
00679                 } else {
00680                         if (ah->config.rx_intr_mitigation)
00681                                 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
00682                         else
00683                                 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
00684                 }
00685                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
00686                         mask |= AR_IMR_GENTMR;
00687         }
00688 
00689         if (ints & ATH9K_INT_GENTIMER)
00690                 mask |= AR_IMR_GENTMR;
00691 
00692         if (ints & (ATH9K_INT_BMISC)) {
00693                 mask |= AR_IMR_BCNMISC;
00694                 if (ints & ATH9K_INT_TIM)
00695                         mask2 |= AR_IMR_S2_TIM;
00696                 if (ints & ATH9K_INT_DTIM)
00697                         mask2 |= AR_IMR_S2_DTIM;
00698                 if (ints & ATH9K_INT_DTIMSYNC)
00699                         mask2 |= AR_IMR_S2_DTIMSYNC;
00700                 if (ints & ATH9K_INT_CABEND)
00701                         mask2 |= AR_IMR_S2_CABEND;
00702                 if (ints & ATH9K_INT_TSFOOR)
00703                         mask2 |= AR_IMR_S2_TSFOOR;
00704         }
00705 
00706         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
00707                 mask |= AR_IMR_BCNMISC;
00708                 if (ints & ATH9K_INT_GTT)
00709                         mask2 |= AR_IMR_S2_GTT;
00710                 if (ints & ATH9K_INT_CST)
00711                         mask2 |= AR_IMR_S2_CST;
00712         }
00713 
00714         DBG2("ath9k: new IMR 0x%x\n", mask);
00715         REG_WRITE(ah, AR_IMR, mask);
00716         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
00717                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
00718                            AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
00719         ah->imrs2_reg |= mask2;
00720         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
00721 
00722         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
00723                 if (ints & ATH9K_INT_TIM_TIMER)
00724                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
00725                 else
00726                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
00727         }
00728 
00729         if (ints & ATH9K_INT_GLOBAL)
00730                 ath9k_hw_enable_interrupts(ah);
00731 
00732         return;
00733 }