iPXE
cs89x0.h
Go to the documentation of this file.
00001 /**
00002    Per an email message from Russ Nelson <nelson@crynwr.com> on
00003    18 March 2008 this file is now licensed under GPL Version 2.
00004 
00005    From: Russ Nelson <nelson@crynwr.com>
00006    Date: Tue, 18 Mar 2008 12:42:00 -0400
00007    Subject: Re: [Etherboot-developers] cs89x0 driver in etherboot
00008    -- quote from email 
00009    As copyright holder, if I say it doesn't conflict with the GPL,
00010    then it doesn't conflict with the GPL.
00011 
00012    However, there's no point in causing people's brains to overheat,
00013    so yes, I grant permission for the code to be relicensed under the
00014    GPLv2.  Please make sure that this change in licensing makes its
00015    way upstream.  -russ 
00016    -- quote from email
00017 **/
00018 
00019 FILE_LICENCE ( GPL2_ONLY );
00020 
00021 /*  Copyright, 1988-1992, Russell Nelson, Crynwr Software
00022 
00023    This program is free software; you can redistribute it and/or modify
00024    it under the terms of the GNU General Public License as published by
00025    the Free Software Foundation, version 1.
00026 
00027    This program is distributed in the hope that it will be useful,
00028    but WITHOUT ANY WARRANTY; without even the implied warranty of
00029    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00030    GNU General Public License for more details.
00031 
00032    You should have received a copy of the GNU General Public License
00033    along with this program; if not, write to the Free Software
00034    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00035    02110-1301, USA. */
00036 
00037 #define PP_ChipID 0x0000        /* offset   0h -> Corp -ID              */
00038                                 /* offset   2h -> Model/Product Number  */
00039                                 /* offset   3h -> Chip Revision Number  */
00040 
00041 #define PP_ISAIOB 0x0020        /*  IO base address */
00042 #define PP_CS8900_ISAINT 0x0022 /*  ISA interrupt select */
00043 #define PP_CS8920_ISAINT 0x0370 /*  ISA interrupt select */
00044 #define PP_CS8900_ISADMA 0x0024 /*  ISA Rec DMA channel */
00045 #define PP_CS8920_ISADMA 0x0374 /*  ISA Rec DMA channel */
00046 #define PP_ISASOF 0x0026        /*  ISA DMA offset */
00047 #define PP_DmaFrameCnt 0x0028   /*  ISA DMA Frame count */
00048 #define PP_DmaByteCnt 0x002A    /*  ISA DMA Byte count */
00049 #define PP_CS8900_ISAMemB 0x002C        /*  Memory base */
00050 #define PP_CS8920_ISAMemB 0x0348 /*  */
00051 
00052 #define PP_ISABootBase 0x0030   /*  Boot Prom base  */
00053 #define PP_ISABootMask 0x0034   /*  Boot Prom Mask */
00054 
00055 /* EEPROM data and command registers */
00056 #define PP_EECMD 0x0040         /*  NVR Interface Command register */
00057 #define PP_EEData 0x0042        /*  NVR Interface Data Register */
00058 #define PP_DebugReg 0x0044      /*  Debug Register */
00059 
00060 #define PP_RxCFG 0x0102         /*  Rx Bus config */
00061 #define PP_RxCTL 0x0104         /*  Receive Control Register */
00062 #define PP_TxCFG 0x0106         /*  Transmit Config Register */
00063 #define PP_TxCMD 0x0108         /*  Transmit Command Register */
00064 #define PP_BufCFG 0x010A        /*  Bus configuration Register */
00065 #define PP_LineCTL 0x0112       /*  Line Config Register */
00066 #define PP_SelfCTL 0x0114       /*  Self Command Register */
00067 #define PP_BusCTL 0x0116        /*  ISA bus control Register */
00068 #define PP_TestCTL 0x0118       /*  Test Register */
00069 #define PP_AutoNegCTL 0x011C    /*  Auto Negotiation Ctrl */
00070 
00071 #define PP_ISQ 0x0120           /*  Interrupt Status */
00072 #define PP_RxEvent 0x0124       /*  Rx Event Register */
00073 #define PP_TxEvent 0x0128       /*  Tx Event Register */
00074 #define PP_BufEvent 0x012C      /*  Bus Event Register */
00075 #define PP_RxMiss 0x0130        /*  Receive Miss Count */
00076 #define PP_TxCol 0x0132         /*  Transmit Collision Count */
00077 #define PP_LineST 0x0134        /*  Line State Register */
00078 #define PP_SelfST 0x0136        /*  Self State register */
00079 #define PP_BusST 0x0138         /*  Bus Status */
00080 #define PP_TDR 0x013C           /*  Time Domain Reflectometry */
00081 #define PP_AutoNegST 0x013E     /*  Auto Neg Status */
00082 #define PP_TxCommand 0x0144     /*  Tx Command */
00083 #define PP_TxLength 0x0146      /*  Tx Length */
00084 #define PP_LAF 0x0150           /*  Hash Table */
00085 #define PP_IA 0x0158            /*  Physical Address Register */
00086 
00087 #define PP_RxStatus 0x0400      /*  Receive start of frame */
00088 #define PP_RxLength 0x0402      /*  Receive Length of frame */
00089 #define PP_RxFrame 0x0404       /*  Receive frame pointer */
00090 #define PP_TxFrame 0x0A00       /*  Transmit frame pointer */
00091 
00092 /*  Primary I/O Base Address. If no I/O base is supplied by the user, then this */
00093 /*  can be used as the default I/O base to access the PacketPage Area. */
00094 #define DEFAULTIOBASE 0x0300
00095 #define FIRST_IO 0x020C         /*  First I/O port to check */
00096 #define LAST_IO 0x037C          /*  Last I/O port to check (+10h) */
00097 #define ADD_MASK 0x3000         /*  Mask it use of the ADD_PORT register */
00098 #define ADD_SIG 0x3000          /*  Expected ID signature */
00099 
00100 #define CHIP_EISA_ID_SIG 0x630E   /*  Product ID Code for Crystal Chip (CS8900 spec 4.3) */
00101 
00102 #ifdef  IBMEIPKT
00103 #define EISA_ID_SIG 0x4D24      /*  IBM */
00104 #define PART_NO_SIG 0x1010      /*  IBM */
00105 #define MONGOOSE_BIT 0x0000     /*  IBM */
00106 #else
00107 #define EISA_ID_SIG 0x630E      /*  PnP Vendor ID (same as chip id for Crystal board) */
00108 #define PART_NO_SIG 0x4000      /*  ID code CS8920 board (PnP Vendor Product code) */
00109 #define MONGOOSE_BIT 0x2000     /*  PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
00110 #endif
00111 
00112 #define PRODUCT_ID_ADD 0x0002   /*  Address of product ID */
00113 
00114 /*  Mask to find out the types of  registers */
00115 #define REG_TYPE_MASK 0x001F
00116 
00117 /*  Eeprom Commands */
00118 #define ERSE_WR_ENBL 0x00F0
00119 #define ERSE_WR_DISABLE 0x0000
00120 
00121 /*  Defines Control/Config register quintuplet numbers */
00122 #define RX_BUF_CFG 0x0003
00123 #define RX_CONTROL 0x0005
00124 #define TX_CFG 0x0007
00125 #define TX_COMMAND 0x0009
00126 #define BUF_CFG 0x000B
00127 #define LINE_CONTROL 0x0013
00128 #define SELF_CONTROL 0x0015
00129 #define BUS_CONTROL 0x0017
00130 #define TEST_CONTROL 0x0019
00131 
00132 /*  Defines Status/Count registers quintuplet numbers */
00133 #define RX_EVENT 0x0004
00134 #define TX_EVENT 0x0008
00135 #define BUF_EVENT 0x000C
00136 #define RX_MISS_COUNT 0x0010
00137 #define TX_COL_COUNT 0x0012
00138 #define LINE_STATUS 0x0014
00139 #define SELF_STATUS 0x0016
00140 #define BUS_STATUS 0x0018
00141 #define TDR 0x001C
00142 
00143 /* PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition -  Read/write */
00144 #define SKIP_1 0x0040
00145 #define RX_STREAM_ENBL 0x0080
00146 #define RX_OK_ENBL 0x0100
00147 #define RX_DMA_ONLY 0x0200
00148 #define AUTO_RX_DMA 0x0400
00149 #define BUFFER_CRC 0x0800
00150 #define RX_CRC_ERROR_ENBL 0x1000
00151 #define RX_RUNT_ENBL 0x2000
00152 #define RX_EXTRA_DATA_ENBL 0x4000
00153 
00154 /* PP_RxCTL - Receive Control bit definition - Read/write */
00155 #define RX_IA_HASH_ACCEPT 0x0040
00156 #define RX_PROM_ACCEPT 0x0080
00157 #define RX_OK_ACCEPT 0x0100
00158 #define RX_MULTCAST_ACCEPT 0x0200
00159 #define RX_IA_ACCEPT 0x0400
00160 #define RX_BROADCAST_ACCEPT 0x0800
00161 #define RX_BAD_CRC_ACCEPT 0x1000
00162 #define RX_RUNT_ACCEPT 0x2000
00163 #define RX_EXTRA_DATA_ACCEPT 0x4000
00164 #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
00165 /*  Default receive mode - individually addressed, broadcast, and error free */
00166 #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
00167 
00168 /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
00169 #define TX_LOST_CRS_ENBL 0x0040
00170 #define TX_SQE_ERROR_ENBL 0x0080
00171 #define TX_OK_ENBL 0x0100
00172 #define TX_LATE_COL_ENBL 0x0200
00173 #define TX_JBR_ENBL 0x0400
00174 #define TX_ANY_COL_ENBL 0x0800
00175 #define TX_16_COL_ENBL 0x8000
00176 
00177 /* PP_TxCMD - Transmit Command bit definition - Read-only */
00178 #define TX_START_4_BYTES 0x0000
00179 #define TX_START_64_BYTES 0x0040
00180 #define TX_START_128_BYTES 0x0080
00181 #define TX_START_ALL_BYTES 0x00C0
00182 #define TX_FORCE 0x0100
00183 #define TX_ONE_COL 0x0200
00184 #define TX_TWO_PART_DEFF_DISABLE 0x0400
00185 #define TX_NO_CRC 0x1000
00186 #define TX_RUNT 0x2000
00187 
00188 /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
00189 #define GENERATE_SW_INTERRUPT 0x0040
00190 #define RX_DMA_ENBL 0x0080
00191 #define READY_FOR_TX_ENBL 0x0100
00192 #define TX_UNDERRUN_ENBL 0x0200
00193 #define RX_MISS_ENBL 0x0400
00194 #define RX_128_BYTE_ENBL 0x0800
00195 #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
00196 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
00197 #define RX_DEST_MATCH_ENBL 0x8000
00198 
00199 /* PP_LineCTL - Line Control bit definition - Read/write */
00200 #define SERIAL_RX_ON 0x0040
00201 #define SERIAL_TX_ON 0x0080
00202 #define AUI_ONLY 0x0100
00203 #define AUTO_AUI_10BASET 0x0200
00204 #define MODIFIED_BACKOFF 0x0800
00205 #define NO_AUTO_POLARITY 0x1000
00206 #define TWO_PART_DEFDIS 0x2000
00207 #define LOW_RX_SQUELCH 0x4000
00208 
00209 /* PP_SelfCTL - Software Self Control bit definition - Read/write */
00210 #define POWER_ON_RESET 0x0040
00211 #define SW_STOP 0x0100
00212 #define SLEEP_ON 0x0200
00213 #define AUTO_WAKEUP 0x0400
00214 #define HCB0_ENBL 0x1000
00215 #define HCB1_ENBL 0x2000
00216 #define HCB0 0x4000
00217 #define HCB1 0x8000
00218 
00219 /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
00220 #define RESET_RX_DMA 0x0040
00221 #define MEMORY_ON 0x0400
00222 #define DMA_BURST_MODE 0x0800
00223 #define IO_CHANNEL_READY_ON 0x1000
00224 #define RX_DMA_SIZE_64K 0x2000
00225 #define ENABLE_IRQ 0x8000
00226 
00227 /* PP_TestCTL - Test Control bit definition - Read/write */
00228 #define LINK_OFF 0x0080
00229 #define ENDEC_LOOPBACK 0x0200
00230 #define AUI_LOOPBACK 0x0400
00231 #define BACKOFF_OFF 0x0800
00232 #define FAST_TEST 0x8000
00233 
00234 /* PP_RxEvent - Receive Event Bit definition - Read-only */
00235 #define RX_IA_HASHED 0x0040
00236 #define RX_DRIBBLE 0x0080
00237 #define RX_OK 0x0100
00238 #define RX_HASHED 0x0200
00239 #define RX_IA 0x0400
00240 #define RX_BROADCAST 0x0800
00241 #define RX_CRC_ERROR 0x1000
00242 #define RX_RUNT 0x2000
00243 #define RX_EXTRA_DATA 0x4000
00244 
00245 #define HASH_INDEX_MASK 0x0FC00
00246 
00247 /* PP_TxEvent - Transmit Event Bit definition - Read-only */
00248 #define TX_LOST_CRS 0x0040
00249 #define TX_SQE_ERROR 0x0080
00250 #define TX_OK 0x0100
00251 #define TX_LATE_COL 0x0200
00252 #define TX_JBR 0x0400
00253 #define TX_16_COL 0x8000
00254 #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
00255 #define TX_COL_COUNT_MASK 0x7800
00256 
00257 /* PP_BufEvent - Buffer Event Bit definition - Read-only */
00258 #define SW_INTERRUPT 0x0040
00259 #define RX_DMA 0x0080
00260 #define READY_FOR_TX 0x0100
00261 #define TX_UNDERRUN 0x0200
00262 #define RX_MISS 0x0400
00263 #define RX_128_BYTE 0x0800
00264 #define TX_COL_OVRFLW 0x1000
00265 #define RX_MISS_OVRFLW 0x2000
00266 #define RX_DEST_MATCH 0x8000
00267 
00268 /* PP_LineST - Ethernet Line Status bit definition - Read-only */
00269 #define LINK_OK 0x0080
00270 #define AUI_ON 0x0100
00271 #define TENBASET_ON 0x0200
00272 #define POLARITY_OK 0x1000
00273 #define CRS_OK 0x4000
00274 
00275 /* PP_SelfST - Chip Software Status bit definition */
00276 #define ACTIVE_33V 0x0040
00277 #define INIT_DONE 0x0080
00278 #define SI_BUSY 0x0100
00279 #define EEPROM_PRESENT 0x0200
00280 #define EEPROM_OK 0x0400
00281 #define EL_PRESENT 0x0800
00282 #define EE_SIZE_64 0x1000
00283 
00284 /* PP_BusST - ISA Bus Status bit definition */
00285 #define TX_BID_ERROR 0x0080
00286 #define READY_FOR_TX_NOW 0x0100
00287 
00288 /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
00289 #define RE_NEG_NOW 0x0040
00290 #define ALLOW_FDX 0x0080
00291 #define AUTO_NEG_ENABLE 0x0100
00292 #define NLP_ENABLE 0x0200
00293 #define FORCE_FDX 0x8000
00294 #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
00295 #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
00296 
00297 /* PP_AutoNegST - Auto Negotiation Status bit definition */
00298 #define AUTO_NEG_BUSY 0x0080
00299 #define FLP_LINK 0x0100
00300 #define FLP_LINK_GOOD 0x0800
00301 #define LINK_FAULT 0x1000
00302 #define HDX_ACTIVE 0x4000
00303 #define FDX_ACTIVE 0x8000
00304 
00305 /*  The following block defines the ISQ event types */
00306 #define ISQ_RECEIVER_EVENT 0x04
00307 #define ISQ_TRANSMITTER_EVENT 0x08
00308 #define ISQ_BUFFER_EVENT 0x0c
00309 #define ISQ_RX_MISS_EVENT 0x10
00310 #define ISQ_TX_COL_EVENT 0x12
00311 
00312 #define ISQ_EVENT_MASK 0x003F   /*  ISQ mask to find out type of event */
00313 #define ISQ_HIST 16             /*  small history buffer */
00314 #define AUTOINCREMENT 0x8000    /*  Bit mask to set bit-15 for autoincrement */
00315 
00316 #define TXRXBUFSIZE 0x0600
00317 #define RXDMABUFSIZE 0x8000
00318 #define RXDMASIZE 0x4000
00319 #define TXRX_LENGTH_MASK 0x07FF
00320 
00321 /*  rx options bits */
00322 #define RCV_WITH_RXON   1       /*  Set SerRx ON */
00323 #define RCV_COUNTS      2       /*  Use Framecnt1 */
00324 #define RCV_PONG        4       /*  Pong respondent */
00325 #define RCV_DONG        8       /*  Dong operation */
00326 #define RCV_POLLING     0x10    /*  Poll RxEvent */
00327 #define RCV_ISQ         0x20    /*  Use ISQ, int */
00328 #define RCV_AUTO_DMA    0x100   /*  Set AutoRxDMAE */
00329 #define RCV_DMA         0x200   /*  Set RxDMA only */
00330 #define RCV_DMA_ALL     0x400   /*  Copy all DMA'ed */
00331 #define RCV_FIXED_DATA  0x800   /*  Every frame same */
00332 #define RCV_IO          0x1000  /*  Use ISA IO only */
00333 #define RCV_MEMORY      0x2000  /*  Use ISA Memory */
00334 
00335 #define RAM_SIZE        0x1000       /*  The card has 4k bytes or RAM */
00336 #define PKT_START PP_TxFrame  /*  Start of packet RAM */
00337 
00338 #define RX_FRAME_PORT   0x0000
00339 #define TX_FRAME_PORT RX_FRAME_PORT
00340 #define TX_CMD_PORT     0x0004
00341 #define TX_NOW          0x0000       /*  Tx packet after   5 bytes copied */
00342 #define TX_AFTER_381    0x0020       /*  Tx packet after 381 bytes copied */
00343 #define TX_AFTER_ALL    0x00C0       /*  Tx packet after all bytes copied */
00344 #define TX_LEN_PORT     0x0006
00345 #define ISQ_PORT        0x0008
00346 #define ADD_PORT        0x000A
00347 #define DATA_PORT       0x000C
00348 
00349 #define EEPROM_WRITE_EN         0x00F0
00350 #define EEPROM_WRITE_DIS        0x0000
00351 #define EEPROM_WRITE_CMD        0x0100
00352 #define EEPROM_READ_CMD         0x0200
00353 
00354 /*  Receive Header */
00355 /*  Description of header of each packet in receive area of memory */
00356 #define RBUF_EVENT_LOW  0   /*  Low byte of RxEvent - status of received frame */
00357 #define RBUF_EVENT_HIGH 1   /*  High byte of RxEvent - status of received frame */
00358 #define RBUF_LEN_LOW    2   /*  Length of received data - low byte */
00359 #define RBUF_LEN_HI     3   /*  Length of received data - high byte */
00360 #define RBUF_HEAD_LEN   4   /*  Length of this header */
00361 
00362 #define CHIP_READ 0x1   /*  Used to mark state of the repins code (chip or dma) */
00363 #define DMA_READ 0x2   /*  Used to mark state of the repins code (chip or dma) */
00364 
00365 /*  for bios scan */
00366 /*  */
00367 #ifdef  CSDEBUG
00368 /*  use these values for debugging bios scan */
00369 #define BIOS_START_SEG 0x00000
00370 #define BIOS_OFFSET_INC 0x0010
00371 #else
00372 #define BIOS_START_SEG 0x0c000
00373 #define BIOS_OFFSET_INC 0x0200
00374 #endif
00375 
00376 #define BIOS_LAST_OFFSET 0x0fc00
00377 
00378 /*  Byte offsets into the EEPROM configuration buffer */
00379 #define ISA_CNF_OFFSET 0x6
00380 #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8)                      /*  8900 eeprom */
00381 #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8)                /*  8920 eeprom */
00382 
00383   /*  the assumption here is that the bits in the eeprom are generally  */
00384   /*  in the same position as those in the autonegctl register. */
00385   /*  Of course the IMM bit is not in that register so it must be  */
00386   /*  masked out */
00387 #define EE_FORCE_FDX  0x8000
00388 #define EE_NLP_ENABLE 0x0200
00389 #define EE_AUTO_NEG_ENABLE 0x0100
00390 #define EE_ALLOW_FDX 0x0080
00391 #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
00392 
00393 #define IMM_BIT 0x0040          /*  ignore missing media */
00394 
00395 #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
00396 #define A_CNF_10B_T 0x0001
00397 #define A_CNF_AUI 0x0002
00398 #define A_CNF_10B_2 0x0004
00399 #define A_CNF_MEDIA_TYPE 0x0060
00400 #define A_CNF_MEDIA_AUTO 0x0000
00401 #define A_CNF_MEDIA_10B_T 0x0020
00402 #define A_CNF_MEDIA_AUI 0x0040
00403 #define A_CNF_MEDIA_10B_2 0x0060
00404 #define A_CNF_DC_DC_POLARITY 0x0080
00405 #define A_CNF_NO_AUTO_POLARITY 0x2000
00406 #define A_CNF_LOW_RX_SQUELCH 0x4000
00407 #define A_CNF_EXTND_10B_2 0x8000
00408 
00409 #define PACKET_PAGE_OFFSET 0x8
00410 
00411 /*  Bit definitions for the ISA configuration word from the EEPROM */
00412 #define INT_NO_MASK 0x000F
00413 #define DMA_NO_MASK 0x0070
00414 #define ISA_DMA_SIZE 0x0200
00415 #define ISA_AUTO_RxDMA 0x0400
00416 #define ISA_RxDMA 0x0800
00417 #define DMA_BURST 0x1000
00418 #define STREAM_TRANSFER 0x2000
00419 #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
00420 
00421 /*  DMA controller registers */
00422 #define DMA_BASE 0x00     /*  DMA controller base */
00423 #define DMA_BASE_2 0x0C0    /*  DMA controller base */
00424 
00425 #define DMA_STAT 0x0D0    /*  DMA controller status register */
00426 #define DMA_MASK 0x0D4    /*  DMA controller mask register */
00427 #define DMA_MODE 0x0D6    /*  DMA controller mode register */
00428 #define DMA_RESETFF 0x0D8    /*  DMA controller first/last flip flop */
00429 
00430 /*  DMA data */
00431 #define DMA_DISABLE 0x04     /*  Disable channel n */
00432 #define DMA_ENABLE 0x00     /*  Enable channel n */
00433 /*  Demand transfers, incr. address, auto init, writes, ch. n */
00434 #define DMA_RX_MODE 0x14
00435 /*  Demand transfers, incr. address, auto init, reads, ch. n */
00436 #define DMA_TX_MODE 0x18
00437 
00438 #define DMA_SIZE (16*1024) /*  Size of dma buffer - 16k */
00439 
00440 #define CS8900 0x0000
00441 #define CS8920 0x4000
00442 #define CS8920M 0x6000
00443 #define REVISON_BITS 0x1F00
00444 #define EEVER_NUMBER 0x12
00445 #define CHKSUM_LEN 0x14
00446 #define CHKSUM_VAL 0x0000
00447 #define START_EEPROM_DATA 0x001c /*  Offset into eeprom for start of data */
00448 #define IRQ_MAP_EEPROM_DATA 0x0046 /*  Offset into eeprom for the IRQ map */
00449 #define IRQ_MAP_LEN 0x0004 /*  No of bytes to read for the IRQ map */
00450 #define PNP_IRQ_FRMT 0x0022 /*  PNP small item IRQ format */
00451 #define CS8900_IRQ_MAP 0x1c20 /*  This IRQ map is fixed */
00452 
00453 #define CS8920_NO_INTS 0x0F   /*  Max CS8920 interrupt select # */
00454 
00455 #define PNP_ADD_PORT 0x0279
00456 #define PNP_WRITE_PORT 0x0A79
00457 
00458 #define GET_PNP_ISA_STRUCT 0x40
00459 #define PNP_ISA_STRUCT_LEN 0x06
00460 #define PNP_CSN_CNT_OFF 0x01
00461 #define PNP_RD_PORT_OFF 0x02
00462 #define PNP_FUNCTION_OK 0x00
00463 #define PNP_WAKE 0x03
00464 #define PNP_RSRC_DATA 0x04
00465 #define PNP_RSRC_READY 0x01
00466 #define PNP_STATUS 0x05
00467 #define PNP_ACTIVATE 0x30
00468 #define PNP_CNF_IO_H 0x60
00469 #define PNP_CNF_IO_L 0x61
00470 #define PNP_CNF_INT 0x70
00471 #define PNP_CNF_DMA 0x74
00472 #define PNP_CNF_MEM 0x48
00473 
00474 /*
00475  * Local variables:
00476  *  c-basic-offset: 8
00477  * End:
00478  */
00479