iPXE
ef10_regs.h
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00001 /****************************************************************************
00002  *
00003  * Driver for Solarflare network controllers and boards
00004  * Copyright 2012-2017 Solarflare Communications Inc.
00005  *
00006  * This program is free software; you can redistribute it and/or
00007  * modify it under the terms of the GNU General Public License as
00008  * published by the Free Software Foundation; either version 2 of the
00009  * License, or any later version.
00010  *
00011  * You can also choose to distribute this program under the terms of
00012  * the Unmodified Binary Distribution Licence (as given in the file
00013  * COPYING.UBDL), provided that you have satisfied its requirements.
00014  */
00015 
00016 #ifndef EFX_EF10_REGS_H
00017 #define EFX_EF10_REGS_H
00018 
00019 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00020 
00021 /** \file ef10_regs.h
00022  * EF10 hardware architecture definitions
00023  *
00024  * EF10 hardware architecture definitions have a name prefix following
00025  * the format:
00026  *
00027  *     E<type>_<min-rev><max-rev>_
00028  *
00029  * The following <type> strings are used:
00030  *
00031  *             MMIO register  Host memory structure
00032  * Address     R
00033  * Bitfield    RF             SF
00034  * Enumerator  FE             SE
00035  *
00036  * <min-rev> is the first revision to which the definition applies:
00037  *
00038  *     D: Huntington A0
00039  *
00040  * If the definition has been changed or removed in later revisions
00041  * then <max-rev> is the last revision to which the definition applies;
00042  * otherwise it is "Z".
00043  */
00044 
00045 /**************************************************************************
00046  *
00047  * EF10 registers and descriptors
00048  *
00049  **************************************************************************
00050  */
00051 
00052 /* BIU_HW_REV_ID_REG:  */
00053 #define ER_DZ_BIU_HW_REV_ID 0x00000000
00054 #define ERF_DZ_HW_REV_ID_LBN 0
00055 #define ERF_DZ_HW_REV_ID_WIDTH 32
00056 
00057 /* BIU_MC_SFT_STATUS_REG:  */
00058 #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010
00059 #define ER_DZ_BIU_MC_SFT_STATUS_STEP 4
00060 #define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8
00061 #define ERF_DZ_MC_SFT_STATUS_LBN 0
00062 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32
00063 
00064 /* BIU_INT_ISR_REG:  */
00065 #define ER_DZ_BIU_INT_ISR 0x00000090
00066 #define ERF_DZ_ISR_REG_LBN 0
00067 #define ERF_DZ_ISR_REG_WIDTH 32
00068 
00069 /* MC_DB_LWRD_REG:  */
00070 #define ER_DZ_MC_DB_LWRD 0x00000200
00071 #define ERF_DZ_MC_DOORBELL_L_LBN 0
00072 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32
00073 
00074 /* MC_DB_HWRD_REG:  */
00075 #define ER_DZ_MC_DB_HWRD 0x00000204
00076 #define ERF_DZ_MC_DOORBELL_H_LBN 0
00077 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32
00078 
00079 /* EVQ_RPTR_REG:  */
00080 #define ER_DZ_EVQ_RPTR 0x00000400
00081 #define ER_DZ_EVQ_RPTR_STEP 8192
00082 #define ER_DZ_EVQ_RPTR_ROWS 2048
00083 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15
00084 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
00085 #define ERF_DZ_EVQ_RPTR_LBN 0
00086 #define ERF_DZ_EVQ_RPTR_WIDTH 15
00087 
00088 /* EVQ_TMR_REG:  */
00089 #define ER_DZ_EVQ_TMR 0x00000420
00090 #define ER_DZ_EVQ_TMR_STEP 8192
00091 #define ER_DZ_EVQ_TMR_ROWS 2048
00092 #define ERF_DZ_TC_TIMER_MODE_LBN 14
00093 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2
00094 #define ERF_DZ_TC_TIMER_VAL_LBN 0
00095 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14
00096 
00097 /* RX_DESC_UPD_REG:  */
00098 #define ER_DZ_RX_DESC_UPD 0x00000830
00099 #define ER_DZ_RX_DESC_UPD_STEP 8192
00100 #define ER_DZ_RX_DESC_UPD_ROWS 2048
00101 #define ERF_DZ_RX_DESC_WPTR_LBN 0
00102 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12
00103 
00104 /* TX_DESC_UPD_REG:  */
00105 #define ER_DZ_TX_DESC_UPD 0x00000a10
00106 #define ER_DZ_TX_DESC_UPD_STEP 8192
00107 #define ER_DZ_TX_DESC_UPD_ROWS 2048
00108 #define ERF_DZ_RSVD_LBN 76
00109 #define ERF_DZ_RSVD_WIDTH 20
00110 #define ERF_DZ_TX_DESC_WPTR_LBN 64
00111 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12
00112 #define ERF_DZ_TX_DESC_HWORD_LBN 32
00113 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32
00114 #define ERF_DZ_TX_DESC_LWORD_LBN 0
00115 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32
00116 
00117 /* DRIVER_EV */
00118 #define ESF_DZ_DRV_CODE_LBN 60
00119 #define ESF_DZ_DRV_CODE_WIDTH 4
00120 #define ESF_DZ_DRV_SUB_CODE_LBN 56
00121 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4
00122 #define ESE_DZ_DRV_TIMER_EV 3
00123 #define ESE_DZ_DRV_START_UP_EV 2
00124 #define ESE_DZ_DRV_WAKE_UP_EV 1
00125 #define ESF_DZ_DRV_SUB_DATA_LBN 0
00126 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56
00127 #define ESF_DZ_DRV_EVQ_ID_LBN 0
00128 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14
00129 #define ESF_DZ_DRV_TMR_ID_LBN 0
00130 #define ESF_DZ_DRV_TMR_ID_WIDTH 14
00131 
00132 /* EVENT_ENTRY */
00133 #define ESF_DZ_EV_CODE_LBN 60
00134 #define ESF_DZ_EV_CODE_WIDTH 4
00135 #define ESE_DZ_EV_CODE_MCDI_EV 12
00136 #define ESE_DZ_EV_CODE_DRIVER_EV 5
00137 #define ESE_DZ_EV_CODE_TX_EV 2
00138 #define ESE_DZ_EV_CODE_RX_EV 0
00139 #define ESE_DZ_OTHER other
00140 #define ESF_DZ_EV_DATA_LBN 0
00141 #define ESF_DZ_EV_DATA_WIDTH 60
00142 
00143 /* MC_EVENT */
00144 #define ESF_DZ_MC_CODE_LBN 60
00145 #define ESF_DZ_MC_CODE_WIDTH 4
00146 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59
00147 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1
00148 #define ESF_DZ_MC_DROP_EVENT_LBN 58
00149 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1
00150 #define ESF_DZ_MC_SOFT_LBN 0
00151 #define ESF_DZ_MC_SOFT_WIDTH 58
00152 
00153 /* RX_EVENT */
00154 #define ESF_DZ_RX_CODE_LBN 60
00155 #define ESF_DZ_RX_CODE_WIDTH 4
00156 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59
00157 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1
00158 #define ESF_DZ_RX_DROP_EVENT_LBN 58
00159 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1
00160 #define ESF_DZ_RX_EV_RSVD2_LBN 54
00161 #define ESF_DZ_RX_EV_RSVD2_WIDTH 4
00162 #define ESF_DZ_RX_EV_SOFT2_LBN 52
00163 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2
00164 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
00165 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
00166 #define ESF_DZ_RX_L4_CLASS_LBN 45
00167 #define ESF_DZ_RX_L4_CLASS_WIDTH 3
00168 #define ESE_DZ_L4_CLASS_RSVD7 7
00169 #define ESE_DZ_L4_CLASS_RSVD6 6
00170 #define ESE_DZ_L4_CLASS_RSVD5 5
00171 #define ESE_DZ_L4_CLASS_RSVD4 4
00172 #define ESE_DZ_L4_CLASS_RSVD3 3
00173 #define ESE_DZ_L4_CLASS_UDP 2
00174 #define ESE_DZ_L4_CLASS_TCP 1
00175 #define ESE_DZ_L4_CLASS_UNKNOWN 0
00176 #define ESF_DZ_RX_L3_CLASS_LBN 42
00177 #define ESF_DZ_RX_L3_CLASS_WIDTH 3
00178 #define ESE_DZ_L3_CLASS_RSVD7 7
00179 #define ESE_DZ_L3_CLASS_IP6_FRAG 6
00180 #define ESE_DZ_L3_CLASS_ARP 5
00181 #define ESE_DZ_L3_CLASS_IP4_FRAG 4
00182 #define ESE_DZ_L3_CLASS_FCOE 3
00183 #define ESE_DZ_L3_CLASS_IP6 2
00184 #define ESE_DZ_L3_CLASS_IP4 1
00185 #define ESE_DZ_L3_CLASS_UNKNOWN 0
00186 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39
00187 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3
00188 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7
00189 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6
00190 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5
00191 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4
00192 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3
00193 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2
00194 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1
00195 #define ESE_DZ_ETH_TAG_CLASS_NONE 0
00196 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36
00197 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3
00198 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2
00199 #define ESE_DZ_ETH_BASE_CLASS_LLC 1
00200 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0
00201 #define ESF_DZ_RX_MAC_CLASS_LBN 35
00202 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1
00203 #define ESE_DZ_MAC_CLASS_MCAST 1
00204 #define ESE_DZ_MAC_CLASS_UCAST 0
00205 #define ESF_DZ_RX_EV_SOFT1_LBN 32
00206 #define ESF_DZ_RX_EV_SOFT1_WIDTH 3
00207 #define ESF_DZ_RX_EV_RSVD1_LBN 31
00208 #define ESF_DZ_RX_EV_RSVD1_WIDTH 1
00209 #define ESF_DZ_RX_ABORT_LBN 30
00210 #define ESF_DZ_RX_ABORT_WIDTH 1
00211 #define ESF_DZ_RX_ECC_ERR_LBN 29
00212 #define ESF_DZ_RX_ECC_ERR_WIDTH 1
00213 #define ESF_DZ_RX_CRC1_ERR_LBN 28
00214 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1
00215 #define ESF_DZ_RX_CRC0_ERR_LBN 27
00216 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1
00217 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26
00218 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1
00219 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25
00220 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1
00221 #define ESF_DZ_RX_ECRC_ERR_LBN 24
00222 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1
00223 #define ESF_DZ_RX_QLABEL_LBN 16
00224 #define ESF_DZ_RX_QLABEL_WIDTH 5
00225 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15
00226 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1
00227 #define ESF_DZ_RX_CONT_LBN 14
00228 #define ESF_DZ_RX_CONT_WIDTH 1
00229 #define ESF_DZ_RX_BYTES_LBN 0
00230 #define ESF_DZ_RX_BYTES_WIDTH 14
00231 
00232 /* RX_KER_DESC */
00233 #define ESF_DZ_RX_KER_RESERVED_LBN 62
00234 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2
00235 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48
00236 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14
00237 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0
00238 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48
00239 
00240 /* TX_CSUM_TSTAMP_DESC */
00241 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
00242 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
00243 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
00244 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
00245 #define ESE_DZ_TX_OPTION_DESC_TSO 7
00246 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
00247 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
00248 #define ESF_DZ_TX_TIMESTAMP_LBN 5
00249 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1
00250 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
00251 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
00252 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
00253 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
00254 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
00255 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
00256 #define ESE_DZ_TX_OPTION_CRC_FCOE 1
00257 #define ESE_DZ_TX_OPTION_CRC_OFF 0
00258 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
00259 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
00260 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
00261 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
00262 
00263 /* TX_EVENT */
00264 #define ESF_DZ_TX_CODE_LBN 60
00265 #define ESF_DZ_TX_CODE_WIDTH 4
00266 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59
00267 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1
00268 #define ESF_DZ_TX_DROP_EVENT_LBN 58
00269 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1
00270 #define ESF_DZ_TX_EV_RSVD_LBN 48
00271 #define ESF_DZ_TX_EV_RSVD_WIDTH 10
00272 #define ESF_DZ_TX_SOFT2_LBN 32
00273 #define ESF_DZ_TX_SOFT2_WIDTH 16
00274 #define ESF_DZ_TX_CAN_MERGE_LBN 31
00275 #define ESF_DZ_TX_CAN_MERGE_WIDTH 1
00276 #define ESF_DZ_TX_SOFT1_LBN 24
00277 #define ESF_DZ_TX_SOFT1_WIDTH 7
00278 #define ESF_DZ_TX_QLABEL_LBN 16
00279 #define ESF_DZ_TX_QLABEL_WIDTH 5
00280 #define ESF_DZ_TX_DESCR_INDX_LBN 0
00281 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16
00282 
00283 /* TX_KER_DESC */
00284 #define ESF_DZ_TX_KER_TYPE_LBN 63
00285 #define ESF_DZ_TX_KER_TYPE_WIDTH 1
00286 #define ESF_DZ_TX_KER_CONT_LBN 62
00287 #define ESF_DZ_TX_KER_CONT_WIDTH 1
00288 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48
00289 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14
00290 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0
00291 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
00292 
00293 /* TX_PIO_DESC */
00294 #define ESF_DZ_TX_PIO_TYPE_LBN 63
00295 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1
00296 #define ESF_DZ_TX_PIO_OPT_LBN 60
00297 #define ESF_DZ_TX_PIO_OPT_WIDTH 3
00298 #define ESF_DZ_TX_PIO_CONT_LBN 59
00299 #define ESF_DZ_TX_PIO_CONT_WIDTH 1
00300 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32
00301 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12
00302 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
00303 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
00304 
00305 /* TX_TSO_DESC */
00306 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
00307 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
00308 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
00309 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
00310 #define ESE_DZ_TX_OPTION_DESC_TSO 7
00311 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
00312 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
00313 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
00314 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8
00315 #define ESF_DZ_TX_TSO_IP_ID_LBN 32
00316 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16
00317 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
00318 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
00319 
00320 /*************************************************************************/
00321 
00322 /* TX_DESC_UPD_REG: Transmit descriptor update register.
00323  * We may write just one dword of these registers.
00324  */
00325 #define ER_DZ_TX_DESC_UPD_DWORD         (ER_DZ_TX_DESC_UPD + 2 * 4)
00326 #define ERF_DZ_TX_DESC_WPTR_DWORD_LBN   (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32)
00327 #define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH
00328 
00329 /* The workaround for bug 35388 requires multiplexing writes through
00330  * the TX_DESC_UPD_DWORD address.
00331  * TX_DESC_UPD: 0ppppppppppp               (bit 11 lost)
00332  * EVQ_RPTR:    1000hhhhhhhh, 1001llllllll (split into high and low bits)
00333  * EVQ_TMR:     11mmvvvvvvvv               (bits 8:13 of value lost)
00334  */
00335 #define ER_DD_EVQ_INDIRECT              ER_DZ_TX_DESC_UPD_DWORD
00336 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN   8
00337 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4
00338 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH  8
00339 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW   9
00340 #define ERF_DD_EVQ_IND_RPTR_LBN         0
00341 #define ERF_DD_EVQ_IND_RPTR_WIDTH       8
00342 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN  10
00343 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2
00344 #define EFE_DD_EVQ_IND_TIMER_FLAGS      3
00345 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN   8
00346 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2
00347 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN    0
00348 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH  8
00349 
00350 /* TX_PIOBUF
00351  * PIO buffer aperture (paged)
00352  */
00353 #define ER_DZ_TX_PIOBUF 4096
00354 #define ER_DZ_TX_PIOBUF_SIZE 2048
00355 
00356 /* RX packet prefix */
00357 #define ES_DZ_RX_PREFIX_HASH_OFST 0
00358 #define ES_DZ_RX_PREFIX_VLAN1_OFST 4
00359 #define ES_DZ_RX_PREFIX_VLAN2_OFST 6
00360 #define ES_DZ_RX_PREFIX_PKTLEN_OFST 8
00361 #define ES_DZ_RX_PREFIX_TSTAMP_OFST 10
00362 #define ES_DZ_RX_PREFIX_SIZE 14
00363 
00364 #endif /* EFX_EF10_REGS_H */