iPXE
epic100.c
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00001 
00002 /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
00003 
00004 FILE_LICENCE ( GPL2_OR_LATER );
00005 
00006 /* 05/06/2003   timlegge        Fixed relocation and implemented Multicast */
00007 #define LINUX_OUT_MACROS
00008 
00009 #include "etherboot.h"
00010 #include <ipxe/pci.h>
00011 #include <ipxe/ethernet.h>
00012 #include "nic.h"
00013 #include "epic100.h"
00014 
00015 /* Condensed operations for readability */
00016 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
00017 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
00018 
00019 #define TX_RING_SIZE    2       /* use at least 2 buffers for TX */
00020 #define RX_RING_SIZE    2
00021 
00022 #define PKT_BUF_SZ      1536    /* Size of each temporary Tx/Rx buffer.*/
00023 
00024 /*
00025 #define DEBUG_RX
00026 #define DEBUG_TX
00027 #define DEBUG_EEPROM
00028 */
00029 
00030 #define EPIC_DEBUG 0    /* debug level */
00031 
00032 /* The EPIC100 Rx and Tx buffer descriptors. */
00033 struct epic_rx_desc {
00034     unsigned long status;
00035     unsigned long bufaddr;
00036     unsigned long buflength;
00037     unsigned long next;
00038 };
00039 /* description of the tx descriptors control bits commonly used */
00040 #define TD_STDFLAGS     TD_LASTDESC
00041 
00042 struct epic_tx_desc {
00043     unsigned long status;
00044     unsigned long bufaddr;
00045     unsigned long buflength;
00046     unsigned long  next;
00047 };
00048 
00049 #define delay(nanosec)   do { int _i = 3; while (--_i > 0) \
00050                                      { __SLOW_DOWN_IO; }} while (0)
00051 
00052 static void     epic100_open(void);
00053 static void     epic100_init_ring(void);
00054 static void     epic100_disable(struct nic *nic);
00055 static int      epic100_poll(struct nic *nic, int retrieve);
00056 static void     epic100_transmit(struct nic *nic, const char *destaddr,
00057                                  unsigned int type, unsigned int len, const char *data);
00058 #ifdef  DEBUG_EEPROM
00059 static int      read_eeprom(int location);
00060 #endif
00061 static int      mii_read(int phy_id, int location);
00062 static void     epic100_irq(struct nic *nic, irq_action_t action);
00063 
00064 static struct nic_operations epic100_operations;
00065 
00066 static int      ioaddr;
00067 
00068 static int      command;
00069 static int      intstat;
00070 static int      intmask;
00071 static int      genctl ;
00072 static int      eectl  ;
00073 static int      test   ;
00074 static int      mmctl  ;
00075 static int      mmdata ;
00076 static int      lan0   ;
00077 static int      mc0    ;
00078 static int      rxcon  ;
00079 static int      txcon  ;
00080 static int      prcdar ;
00081 static int      ptcdar ;
00082 static int      eththr ;
00083 
00084 static unsigned int     cur_rx, cur_tx;         /* The next free ring entry */
00085 #ifdef  DEBUG_EEPROM
00086 static unsigned short   eeprom[64];
00087 #endif
00088 static signed char      phys[4];                /* MII device addresses. */
00089 struct {
00090         struct epic_rx_desc     rx_ring[RX_RING_SIZE]
00091         __attribute__ ((aligned(4)));
00092         struct epic_tx_desc     tx_ring[TX_RING_SIZE]
00093         __attribute__ ((aligned(4)));
00094         unsigned char           rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
00095         unsigned char           tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
00096 } epic100_bufs __shared;
00097 #define rx_ring epic100_bufs.rx_ring
00098 #define tx_ring epic100_bufs.tx_ring
00099 #define rx_packet epic100_bufs.rx_packet
00100 #define tx_packet epic100_bufs.tx_packet
00101 
00102 /***********************************************************************/
00103 /*                    Externally visible functions                     */
00104 /***********************************************************************/
00105 
00106 
00107 static int
00108 epic100_probe ( struct nic *nic, struct pci_device *pci ) {
00109 
00110     int i;
00111     unsigned short* ap;
00112     unsigned int phy, phy_idx;
00113 
00114     if (pci->ioaddr == 0)
00115         return 0;
00116 
00117     /* Ideally we would detect all network cards in slot order.  That would
00118        be best done a central PCI probe dispatch, which wouldn't work
00119        well with the current structure.  So instead we detect just the
00120        Epic cards in slot order. */
00121 
00122     ioaddr = pci->ioaddr;
00123 
00124     nic->irqno  = 0;
00125     nic->ioaddr = pci->ioaddr & ~3;
00126 
00127     /* compute all used static epic100 registers address */
00128     command = ioaddr + COMMAND;         /* Control Register */
00129     intstat = ioaddr + INTSTAT;         /* Interrupt Status */
00130     intmask = ioaddr + INTMASK;         /* Interrupt Mask */
00131     genctl  = ioaddr + GENCTL;          /* General Control */
00132     eectl   = ioaddr + EECTL;           /* EEPROM Control  */
00133     test    = ioaddr + TEST;            /* Test register (clocks) */
00134     mmctl   = ioaddr + MMCTL;           /* MII Management Interface Control */
00135     mmdata  = ioaddr + MMDATA;          /* MII Management Interface Data */
00136     lan0    = ioaddr + LAN0;            /* MAC address. (0x40-0x48) */
00137     mc0     = ioaddr + MC0;             /* Multicast Control */
00138     rxcon   = ioaddr + RXCON;           /* Receive Control */
00139     txcon   = ioaddr + TXCON;           /* Transmit Control */
00140     prcdar  = ioaddr + PRCDAR;          /* PCI Receive Current Descr Address */
00141     ptcdar  = ioaddr + PTCDAR;          /* PCI Transmit Current Descr Address */
00142     eththr  = ioaddr + ETHTHR;          /* Early Transmit Threshold */
00143 
00144     /* Reset the chip & bring it out of low-power mode. */
00145     outl(GC_SOFT_RESET, genctl);
00146 
00147     /* Disable ALL interrupts by setting the interrupt mask. */
00148     outl(INTR_DISABLE, intmask);
00149 
00150     /*
00151      * set the internal clocks:
00152      * Application Note 7.15 says:
00153      *    In order to set the CLOCK TEST bit in the TEST register,
00154      *    perform the following:
00155      *
00156      *        Write 0x0008 to the test register at least sixteen
00157      *        consecutive times.
00158      *
00159      * The CLOCK TEST bit is Write-Only. Writing it several times
00160      * consecutively insures a successful write to the bit...
00161      */
00162 
00163     for (i = 0; i < 16; i++) {
00164         outl(0x00000008, test);
00165     }
00166 
00167 #ifdef  DEBUG_EEPROM
00168 {
00169     unsigned short sum = 0;
00170     unsigned short value;
00171     for (i = 0; i < 64; i++) {
00172         value = read_eeprom(i);
00173         eeprom[i] = value;
00174         sum += value;
00175     }
00176 }
00177 
00178 #if     (EPIC_DEBUG > 1)
00179     printf("EEPROM contents\n");
00180     for (i = 0; i < 64; i++) {
00181         printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
00182     }
00183 #endif
00184 #endif
00185 
00186     /* This could also be read from the EEPROM. */
00187     ap = (unsigned short*)nic->node_addr;
00188     for (i = 0; i < 3; i++)
00189         *ap++ = inw(lan0 + i*4);
00190 
00191     DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) );
00192 
00193     /* Find the connected MII xcvrs. */
00194     for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
00195         int mii_status = mii_read(phy, 0);
00196 
00197         if (mii_status != 0xffff  && mii_status != 0x0000) {
00198             phys[phy_idx++] = phy;
00199 #if     (EPIC_DEBUG > 1)
00200             printf("MII transceiver found at address %d.\n", phy);
00201 #endif
00202         }
00203     }
00204     if (phy_idx == 0) {
00205 #if     (EPIC_DEBUG > 1)
00206         printf("***WARNING***: No MII transceiver found!\n");
00207 #endif
00208         /* Use the known PHY address of the EPII. */
00209         phys[0] = 3;
00210     }
00211 
00212     epic100_open();
00213     nic->nic_op = &epic100_operations;
00214 
00215     return 1;
00216 }
00217 
00218 static void set_rx_mode(void)
00219 {
00220         unsigned char mc_filter[8];
00221         int i;
00222         memset(mc_filter, 0xff, sizeof(mc_filter));
00223         outl(0x0C, rxcon);
00224         for(i = 0; i < 4; i++)
00225                 outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
00226         return;
00227 }
00228         
00229    static void
00230 epic100_open(void)
00231 {
00232     int mii_reg5;
00233     unsigned long tmp;
00234 
00235     epic100_init_ring();
00236 
00237     /* Pull the chip out of low-power mode, and set for PCI read multiple. */
00238     outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl);
00239 
00240     outl(TX_FIFO_THRESH, eththr);
00241 
00242     tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME;
00243 
00244     mii_reg5 = mii_read(phys[0], 5);
00245     if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
00246         printf(" full-duplex mode");
00247         tmp |= TC_LM_FULL_DPX;
00248     } else
00249         tmp |= TC_LM_NORMAL;
00250 
00251     outl(tmp, txcon);
00252 
00253     /* Give address of RX and TX ring to the chip */
00254     outl(virt_to_le32desc(&rx_ring), prcdar);
00255     outl(virt_to_le32desc(&tx_ring), ptcdar);
00256 
00257     /* Start the chip's Rx process: receive unicast and broadcast */
00258     set_rx_mode();
00259     outl(CR_START_RX | CR_QUEUE_RX, command);
00260 
00261     putchar('\n');
00262 }
00263 
00264 /* Initialize the Rx and Tx rings. */
00265     static void
00266 epic100_init_ring(void)
00267 {
00268     int i;
00269 
00270     cur_rx = cur_tx = 0;
00271 
00272     for (i = 0; i < RX_RING_SIZE; i++) {
00273         rx_ring[i].status    = cpu_to_le32(RRING_OWN);  /* Owned by Epic chip */
00274         rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
00275         rx_ring[i].bufaddr   = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
00276         rx_ring[i].next      = virt_to_le32desc(&rx_ring[i + 1]) ;
00277     }
00278     /* Mark the last entry as wrapping the ring. */
00279     rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
00280 
00281     /*
00282      *The Tx buffer descriptor is filled in as needed,
00283      * but we do need to clear the ownership bit.
00284      */
00285 
00286     for (i = 0; i < TX_RING_SIZE; i++) {
00287         tx_ring[i].status  = 0x0000;                    /* Owned by CPU */
00288         tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
00289         tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
00290         tx_ring[i].next    = virt_to_le32desc(&tx_ring[i + 1]);
00291     }
00292         tx_ring[i-1].next    = virt_to_le32desc(&tx_ring[0]);
00293 }
00294 
00295 /* function: epic100_transmit
00296  * This transmits a packet.
00297  *
00298  * Arguments: char d[6]:          destination ethernet address.
00299  *            unsigned short t:   ethernet protocol type.
00300  *            unsigned short s:   size of the data-part of the packet.
00301  *            char *p:            the data for the packet.
00302  * returns:   void.
00303  */
00304     static void
00305 epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
00306                  unsigned int len, const char *data)
00307 {
00308     unsigned short nstype;
00309     unsigned char *txp;
00310     int entry;
00311     unsigned long ct;
00312 
00313     /* Calculate the next Tx descriptor entry. */
00314     entry = cur_tx % TX_RING_SIZE;
00315 
00316     if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
00317         printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n",
00318                tx_ring[entry].status);
00319 
00320         epic100_open();
00321         return;
00322     }
00323 
00324     txp = tx_packet + (entry * PKT_BUF_SZ);
00325 
00326     memcpy(txp, destaddr, ETH_ALEN);
00327     memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
00328     nstype = htons(type);
00329     memcpy(txp + 12, (char*)&nstype, 2);
00330     memcpy(txp + ETH_HLEN, data, len);
00331 
00332     len += ETH_HLEN;
00333         len &= 0x0FFF;
00334         while(len < ETH_ZLEN)
00335                 txp[len++] = '\0';
00336     /*
00337      * Caution: the write order is important here,
00338      * set the base address with the "ownership"
00339      * bits last.
00340      */
00341    
00342     tx_ring[entry].buflength |= cpu_to_le32(len);
00343     tx_ring[entry].status = cpu_to_le32(len << 16) |
00344             cpu_to_le32(TRING_OWN);     /* Pass ownership to the chip. */
00345 
00346     cur_tx++;
00347 
00348     /* Trigger an immediate transmit demand. */
00349     outl(CR_QUEUE_TX, command);
00350 
00351     ct = currticks();
00352     /* timeout 10 ms for transmit */
00353     while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) &&
00354                 ct + 10*1000 < currticks())
00355         /* Wait */;
00356 
00357     if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
00358         printf("Oops, transmitter timeout, status=%4.4lX\n",
00359             tx_ring[entry].status);
00360 }
00361 
00362 /* function: epic100_poll / eth_poll
00363  * This receives a packet from the network.
00364  *
00365  * Arguments: none
00366  *
00367  * returns:   1 if a packet was received.
00368  *            0 if no packet was received.
00369  * side effects:
00370  *            returns the packet in the array nic->packet.
00371  *            returns the length of the packet in nic->packetlen.
00372  */
00373 
00374     static int
00375 epic100_poll(struct nic *nic, int retrieve)
00376 {
00377     int entry;
00378     int retcode;
00379     unsigned long status;
00380     entry = cur_rx % RX_RING_SIZE;
00381 
00382     if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
00383         return (0);
00384 
00385     if ( ! retrieve ) return 1;
00386 
00387     status = le32_to_cpu(rx_ring[entry].status);
00388     /* We own the next entry, it's a new packet. Send it up. */
00389 
00390 #if     (EPIC_DEBUG > 4)
00391     printf("epic_poll: entry %d status %hX\n", entry, status);
00392 #endif
00393 
00394     cur_rx++;
00395     if (status & 0x2000) {
00396         printf("epic_poll: Giant packet\n");
00397         retcode = 0;
00398     } else if (status & 0x0006) {
00399         /* Rx Frame errors are counted in hardware. */
00400         printf("epic_poll: Frame received with errors\n");
00401         retcode = 0;
00402     } else {
00403         /* Omit the four octet CRC from the length. */
00404         nic->packetlen = (status >> 16) - 4;
00405         memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen);
00406         retcode = 1;
00407     }
00408 
00409     /* Clear all error sources. */
00410     outl(status & INTR_CLEARERRS, intstat);
00411 
00412     /* Give the descriptor back to the chip */
00413     rx_ring[entry].status = RRING_OWN;
00414 
00415     /* Restart Receiver */
00416     outl(CR_START_RX | CR_QUEUE_RX, command); 
00417 
00418     return retcode;
00419 }
00420 
00421 
00422 static void epic100_disable ( struct nic *nic __unused ) {
00423         /* Soft reset the chip. */
00424         outl(GC_SOFT_RESET, genctl);
00425 }
00426 
00427 static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
00428 {
00429   switch ( action ) {
00430   case DISABLE :
00431     break;
00432   case ENABLE :
00433     break;
00434   case FORCE :
00435     break;
00436   }
00437 }
00438 
00439 #ifdef  DEBUG_EEPROM
00440 /* Serial EEPROM section. */
00441 
00442 /*  EEPROM_Ctrl bits. */
00443 #define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
00444 #define EE_CS           0x02    /* EEPROM chip select. */
00445 #define EE_DATA_WRITE   0x08    /* EEPROM chip data in. */
00446 #define EE_WRITE_0      0x01
00447 #define EE_WRITE_1      0x09
00448 #define EE_DATA_READ    0x10    /* EEPROM chip data out. */
00449 #define EE_ENB          (0x0001 | EE_CS)
00450 
00451 /* The EEPROM commands include the alway-set leading bit. */
00452 #define EE_WRITE_CMD    (5 << 6)
00453 #define EE_READ_CMD     (6 << 6)
00454 #define EE_ERASE_CMD    (7 << 6)
00455 
00456 #define eeprom_delay(n) delay(n)
00457 
00458     static int
00459 read_eeprom(int location)
00460 {
00461     int i;
00462     int retval = 0;
00463     int read_cmd = location | EE_READ_CMD;
00464 
00465     outl(EE_ENB & ~EE_CS, eectl);
00466     outl(EE_ENB, eectl);
00467 
00468     /* Shift the read command bits out. */
00469     for (i = 10; i >= 0; i--) {
00470         short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
00471         outl(EE_ENB | dataval, eectl);
00472         eeprom_delay(100);
00473         outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
00474         eeprom_delay(150);
00475         outl(EE_ENB | dataval, eectl);  /* Finish EEPROM a clock tick. */
00476         eeprom_delay(250);
00477     }
00478     outl(EE_ENB, eectl);
00479 
00480     for (i = 16; i > 0; i--) {
00481         outl(EE_ENB | EE_SHIFT_CLK, eectl);
00482         eeprom_delay(100);
00483         retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
00484         outl(EE_ENB, eectl);
00485         eeprom_delay(100);
00486     }
00487 
00488     /* Terminate the EEPROM access. */
00489     outl(EE_ENB & ~EE_CS, eectl);
00490     return retval;
00491 }
00492 #endif
00493 
00494 
00495 #define MII_READOP      1
00496 #define MII_WRITEOP     2
00497 
00498     static int
00499 mii_read(int phy_id, int location)
00500 {
00501     int i;
00502 
00503     outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
00504     /* Typical operation takes < 50 ticks. */
00505 
00506     for (i = 4000; i > 0; i--)
00507         if ((inl(mmctl) & MII_READOP) == 0)
00508             break;
00509     return inw(mmdata);
00510 }
00511 
00512 static struct nic_operations epic100_operations = {
00513         .connect        = dummy_connect,
00514         .poll           = epic100_poll,
00515         .transmit       = epic100_transmit,
00516         .irq            = epic100_irq,
00517 
00518 };
00519 
00520 static struct pci_device_id epic100_nics[] = {
00521 PCI_ROM(0x10b8, 0x0005, "epic100",    "SMC EtherPowerII", 0),           /* SMC 83c170 EPIC/100 */
00522 PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175", 0),
00523 };
00524 
00525 PCI_DRIVER ( epic100_driver, epic100_nics, PCI_NO_CLASS );
00526 
00527 DRIVER ( "EPIC100", nic_driver, pci_driver, epic100_driver,
00528          epic100_probe, epic100_disable );
00529 
00530 /*
00531  * Local variables:
00532  *  c-basic-offset: 8
00533  *  c-indent-level: 8
00534  *  tab-width: 8
00535  * End:
00536  */