iPXE
hw-ops.h
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00001 /*
00002  * Copyright (c) 2010-2011 Atheros Communications Inc.
00003  *
00004  * Permission to use, copy, modify, and/or distribute this software for any
00005  * purpose with or without fee is hereby granted, provided that the above
00006  * copyright notice and this permission notice appear in all copies.
00007  *
00008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00015  */
00016 
00017 #ifndef ATH9K_HW_OPS_H
00018 #define ATH9K_HW_OPS_H
00019 
00020 FILE_LICENCE ( BSD2 );
00021 
00022 #include "hw.h"
00023 
00024 /* Hardware core and driver accessible callbacks */
00025 
00026 static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
00027                                                int restore,
00028                                                int power_off)
00029 {
00030         ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
00031 }
00032 
00033 static inline void ath9k_hw_rxena(struct ath_hw *ah)
00034 {
00035         ath9k_hw_ops(ah)->rx_enable(ah);
00036 }
00037 
00038 static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
00039                                           u32 link)
00040 {
00041         ath9k_hw_ops(ah)->set_desc_link(ds, link);
00042 }
00043 
00044 static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
00045                                           u32 **link)
00046 {
00047         ath9k_hw_ops(ah)->get_desc_link(ds, link);
00048 }
00049 static inline int ath9k_hw_calibrate(struct ath_hw *ah,
00050                                       struct ath9k_channel *chan,
00051                                       u8 rxchainmask,
00052                                       int longcal)
00053 {
00054         return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
00055 }
00056 
00057 static inline int ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
00058 {
00059         return ath9k_hw_ops(ah)->get_isr(ah, masked);
00060 }
00061 
00062 static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
00063                                   int is_firstseg, int is_lastseg,
00064                                   const void *ds0, u32 buf_addr,
00065                                   unsigned int qcu)
00066 {
00067         ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
00068                                       ds0, buf_addr, qcu);
00069 }
00070 
00071 static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
00072                                       struct ath_tx_status *ts)
00073 {
00074         return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
00075 }
00076 
00077 static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
00078                                           u32 pktLen, enum ath9k_pkt_type type,
00079                                           u32 txPower, u32 keyIx,
00080                                           enum ath9k_key_type keyType,
00081                                           u32 flags)
00082 {
00083         ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
00084                                       keyType, flags);
00085 }
00086 
00087 static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
00088                                         void *lastds,
00089                                         u32 durUpdateEn, u32 rtsctsRate,
00090                                         u32 rtsctsDuration,
00091                                         struct ath9k_11n_rate_series series[],
00092                                         u32 nseries, u32 flags)
00093 {
00094         ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
00095                                             rtsctsRate, rtsctsDuration, series,
00096                                             nseries, flags);
00097 }
00098 
00099 static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
00100                                         u32 aggrLen)
00101 {
00102         ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
00103 }
00104 
00105 static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
00106                                                u32 numDelims)
00107 {
00108         ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
00109 }
00110 
00111 static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
00112 {
00113         ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
00114 }
00115 
00116 static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
00117 {
00118         ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
00119 }
00120 
00121 static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, int val)
00122 {
00123         ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
00124 }
00125 
00126 static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
00127                 struct ath_hw_antcomb_conf *antconf)
00128 {
00129         ath9k_hw_ops(ah)->antdiv_comb_conf_get(ah, antconf);
00130 }
00131 
00132 static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
00133                 struct ath_hw_antcomb_conf *antconf)
00134 {
00135         ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);
00136 }
00137 
00138 /* Private hardware call ops */
00139 
00140 /* PHY ops */
00141 
00142 static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
00143                                        struct ath9k_channel *chan)
00144 {
00145         return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
00146 }
00147 
00148 static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
00149                                                struct ath9k_channel *chan)
00150 {
00151         ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
00152 }
00153 
00154 static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
00155 {
00156         if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
00157                 return 0;
00158 
00159         return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
00160 }
00161 
00162 static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
00163 {
00164         if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
00165                 return;
00166 
00167         ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
00168 }
00169 
00170 static inline int ath9k_hw_set_rf_regs(struct ath_hw *ah,
00171                                         struct ath9k_channel *chan,
00172                                         u16 modesIndex)
00173 {
00174         if (!ath9k_hw_private_ops(ah)->set_rf_regs)
00175                 return 1;
00176 
00177         return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
00178 }
00179 
00180 static inline void ath9k_hw_init_bb(struct ath_hw *ah,
00181                                     struct ath9k_channel *chan)
00182 {
00183         return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
00184 }
00185 
00186 static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
00187                                              struct ath9k_channel *chan)
00188 {
00189         return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
00190 }
00191 
00192 static inline int ath9k_hw_process_ini(struct ath_hw *ah,
00193                                         struct ath9k_channel *chan)
00194 {
00195         return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
00196 }
00197 
00198 static inline void ath9k_olc_init(struct ath_hw *ah)
00199 {
00200         if (!ath9k_hw_private_ops(ah)->olc_init)
00201                 return;
00202 
00203         return ath9k_hw_private_ops(ah)->olc_init(ah);
00204 }
00205 
00206 static inline void ath9k_hw_set_rfmode(struct ath_hw *ah,
00207                                        struct ath9k_channel *chan)
00208 {
00209         return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
00210 }
00211 
00212 static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
00213 {
00214         return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
00215 }
00216 
00217 static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
00218                                             struct ath9k_channel *chan)
00219 {
00220         return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
00221 }
00222 
00223 static inline int ath9k_hw_rfbus_req(struct ath_hw *ah)
00224 {
00225         return ath9k_hw_private_ops(ah)->rfbus_req(ah);
00226 }
00227 
00228 static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
00229 {
00230         return ath9k_hw_private_ops(ah)->rfbus_done(ah);
00231 }
00232 
00233 static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
00234 {
00235         if (!ath9k_hw_private_ops(ah)->restore_chainmask)
00236                 return;
00237 
00238         return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
00239 }
00240 
00241 static inline void ath9k_hw_set_diversity(struct ath_hw *ah, int value)
00242 {
00243         return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
00244 }
00245 
00246 static inline int ath9k_hw_ani_control(struct ath_hw *ah,
00247                                         enum ath9k_ani_cmd cmd, int param)
00248 {
00249         return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
00250 }
00251 
00252 static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
00253                                      int16_t nfarray[NUM_NF_READINGS])
00254 {
00255         ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
00256 }
00257 
00258 static inline int ath9k_hw_init_cal(struct ath_hw *ah,
00259                                      struct ath9k_channel *chan)
00260 {
00261         return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
00262 }
00263 
00264 static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
00265                                               struct ath9k_cal_list *currCal)
00266 {
00267         ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
00268 }
00269 
00270 #endif /* ATH9K_HW_OPS_H */