iPXE
i2c.h
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00001 #ifndef _IPXE_I2C_H
00002 #define _IPXE_I2C_H
00003 
00004 /** @file
00005  *
00006  * I2C interface
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/bitbash.h>
00014 
00015 /** An I2C device
00016  *
00017  * An I2C device represents a specific slave device on an I2C bus.  It
00018  * is accessed via an I2C interface.
00019  */
00020 struct i2c_device {
00021         /** Address of this device
00022          *
00023          * The actual address sent on the bus will look like
00024          *
00025          *    <start> <device address> <word address overflow> <r/w>
00026          *
00027          * The "word address overflow" is any excess bits from the
00028          * word address, i.e. any portion that does not fit within the
00029          * defined word address length.
00030          */
00031         unsigned int dev_addr;
00032         /** Device address length, in bytes
00033          *
00034          * This is the number of bytes that comprise the device
00035          * address, defined to be the portion that terminates with the
00036          * read/write bit.
00037          */
00038         unsigned int dev_addr_len;
00039         /** Word adddress length, in bytes
00040          *
00041          * This is the number of bytes that comprise the word address,
00042          * defined to be the portion that starts after the read/write
00043          * bit and ends before the first data byte.
00044          *
00045          * For some devices, this length will be zero (i.e. the word
00046          * address is contained entirely within the "word address
00047          * overflow").
00048          */
00049         unsigned int word_addr_len;
00050 };
00051 
00052 /** An I2C interface
00053  *
00054  * An I2C interface provides access to an I2C bus, via which I2C
00055  * devices may be reached.
00056  */
00057 struct i2c_interface {
00058         /**
00059          * Read data from I2C device
00060          *
00061          * @v i2c               I2C interface
00062          * @v i2cdev            I2C device
00063          * @v offset            Starting offset within the device
00064          * @v data              Data buffer
00065          * @v len               Length of data buffer
00066          * @ret rc              Return status code
00067          */
00068         int ( * read ) ( struct i2c_interface *i2c, struct i2c_device *i2cdev,
00069                          unsigned int offset, uint8_t *data,
00070                          unsigned int len );
00071         /**
00072          * Write data to I2C device
00073          *
00074          * @v i2c               I2C interface
00075          * @v i2cdev            I2C device
00076          * @v offset            Starting offset within the device
00077          * @v data              Data buffer
00078          * @v len               Length of data buffer
00079          * @ret rc              Return status code
00080          */
00081         int ( * write ) ( struct i2c_interface *i2c, struct i2c_device *i2cdev,
00082                           unsigned int offset, const uint8_t *data,
00083                           unsigned int len );
00084 };
00085 
00086 /** A bit-bashing I2C interface
00087  *
00088  * This provides a standardised way to construct I2C buses via a
00089  * bit-bashing interface.
00090  */
00091 struct i2c_bit_basher {
00092         /** I2C interface */
00093         struct i2c_interface i2c;
00094         /** Bit-bashing interface */
00095         struct bit_basher basher;
00096 };
00097 
00098 /** Ten-bit address marker
00099  *
00100  * This value is ORed with the I2C device address to indicate a
00101  * ten-bit address format on the bus.
00102  */
00103 #define I2C_TENBIT_ADDRESS 0x7800
00104 
00105 /** An I2C write command */
00106 #define I2C_WRITE 0
00107 
00108 /** An I2C read command */
00109 #define I2C_READ 1
00110 
00111 /** Bit indices used for I2C bit-bashing interface */
00112 enum {
00113         /** Serial clock */
00114         I2C_BIT_SCL = 0,
00115         /** Serial data */
00116         I2C_BIT_SDA,
00117 };
00118 
00119 /** Delay required for bit-bashing operation */
00120 #define I2C_UDELAY 5
00121 
00122 /** Maximum number of cycles to use when attempting a bus reset */
00123 #define I2C_RESET_MAX_CYCLES 32
00124 
00125 /**
00126  * Check presence of I2C device
00127  *
00128  * @v i2c               I2C interface
00129  * @v i2cdev            I2C device
00130  * @ret rc              Return status code
00131  *
00132  * Checks for the presence of the device on the I2C bus by attempting
00133  * a zero-length write.
00134  */
00135 static inline int i2c_check_presence ( struct i2c_interface *i2c,
00136                                        struct i2c_device *i2cdev ) {
00137         return i2c->write ( i2c, i2cdev, 0, NULL, 0 );
00138 }
00139 
00140 extern int init_i2c_bit_basher ( struct i2c_bit_basher *i2cbit,
00141                                  struct bit_basher_operations *bash_op );
00142 
00143 /**
00144  * Initialise generic I2C EEPROM device
00145  *
00146  * @v i2cdev            I2C device
00147  */
00148 static inline __always_inline void
00149 init_i2c_eeprom ( struct i2c_device *i2cdev, unsigned int dev_addr ) {
00150         i2cdev->dev_addr = dev_addr;
00151         i2cdev->dev_addr_len = 1;
00152         i2cdev->word_addr_len = 1;
00153 }
00154 
00155 /**
00156  * Initialise Atmel AT24C11
00157  *
00158  * @v i2cdev            I2C device
00159  */
00160 static inline __always_inline void
00161 init_at24c11 ( struct i2c_device *i2cdev ) {
00162         /* This chip has no device address; it must be the only chip
00163          * on the bus.  The word address is contained entirely within
00164          * the device address field.
00165          */
00166         i2cdev->dev_addr = 0;
00167         i2cdev->dev_addr_len = 1;
00168         i2cdev->word_addr_len = 0;
00169 }
00170 
00171 #endif /* _IPXE_I2C_H */