iPXE
Defines | Functions
i82365.h File Reference

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Defines

#define _LINUX_I82365_H
#define I365_IDENT   0x00 /* Identification and revision */
#define I365_STATUS   0x01 /* Interface status */
#define I365_POWER   0x02 /* Power and RESETDRV control */
#define I365_INTCTL   0x03 /* Interrupt and general control */
#define I365_CSC   0x04 /* Card status change */
#define I365_CSCINT   0x05 /* Card status change interrupt control */
#define I365_ADDRWIN   0x06 /* Address window enable */
#define I365_IOCTL   0x07 /* I/O control */
#define I365_GENCTL   0x16 /* Card detect and general control */
#define I365_GBLCTL   0x1E /* Global control register */
#define I365_IO(map)   (0x08+((map)<<2))
#define I365_MEM(map)   (0x10+((map)<<3))
#define I365_W_START   0
#define I365_W_STOP   2
#define I365_W_OFF   4
#define I365_CS_BVD1   0x01
#define I365_CS_STSCHG   0x01
#define I365_CS_BVD2   0x02
#define I365_CS_SPKR   0x02
#define I365_CS_DETECT   0x0C
#define I365_CS_WRPROT   0x10
#define I365_CS_READY   0x20 /* Inverted */
#define I365_CS_POWERON   0x40
#define I365_CS_GPI   0x80
#define I365_PWR_OFF   0x00 /* Turn off the socket */
#define I365_PWR_OUT   0x80 /* Output enable */
#define I365_PWR_NORESET   0x40 /* Disable RESETDRV on resume */
#define I365_PWR_AUTO   0x20 /* Auto pwr switch enable */
#define I365_VCC_MASK   0x18 /* Mask for turning off Vcc */
#define I365_VCC_5V   0x10 /* Vcc = 5.0v */
#define I365_VCC_3V   0x18 /* Vcc = 3.3v */
#define I365_VPP2_MASK   0x0c /* Mask for turning off Vpp2 */
#define I365_VPP2_5V   0x04 /* Vpp2 = 5.0v */
#define I365_VPP2_12V   0x08 /* Vpp2 = 12.0v */
#define I365_VPP1_MASK   0x03 /* Mask for turning off Vpp1 */
#define I365_VPP1_5V   0x01 /* Vpp2 = 5.0v */
#define I365_VPP1_12V   0x02 /* Vpp2 = 12.0v */
#define I365_RING_ENA   0x80
#define I365_PC_RESET   0x40
#define I365_PC_IOCARD   0x20
#define I365_INTR_ENA   0x10
#define I365_IRQ_MASK   0x0F
#define I365_CSC_BVD1   0x01
#define I365_CSC_STSCHG   0x01
#define I365_CSC_BVD2   0x02
#define I365_CSC_READY   0x04
#define I365_CSC_DETECT   0x08
#define I365_CSC_ANY   0x0F
#define I365_CSC_GPI   0x10
#define I365_ENA_IO(map)   (0x40 << (map))
#define I365_ENA_MEM(map)   (0x01 << (map))
#define I365_IOCTL_MASK(map)   (0x0F << (map<<2))
#define I365_IOCTL_WAIT(map)   (0x08 << (map<<2))
#define I365_IOCTL_0WS(map)   (0x04 << (map<<2))
#define I365_IOCTL_IOCS16(map)   (0x02 << (map<<2))
#define I365_IOCTL_16BIT(map)   (0x01 << (map<<2))
#define I365_CTL_16DELAY   0x01
#define I365_CTL_RESET   0x02
#define I365_CTL_GPI_ENA   0x04
#define I365_CTL_GPI_CTL   0x08
#define I365_CTL_RESUME   0x10
#define I365_CTL_SW_IRQ   0x20
#define I365_GBL_PWRDOWN   0x01
#define I365_GBL_CSC_LEV   0x02
#define I365_GBL_WRBACK   0x04
#define I365_GBL_IRQ_0_LEV   0x08
#define I365_GBL_IRQ_1_LEV   0x10
#define I365_MEM_16BIT   0x8000 /* In memory start high byte */
#define I365_MEM_0WS   0x4000
#define I365_MEM_WS1   0x8000 /* In memory stop high byte */
#define I365_MEM_WS0   0x4000
#define I365_MEM_WRPROT   0x8000 /* In offset high byte */
#define I365_MEM_REG   0x4000
#define I365_REG(slot, reg)   (((slot) << 6) + reg)
#define _LINUX_VG468_H
#define I365_IDENT_VADEM   0x08
#define VG468_VPP2_MASK   0x0c
#define VG468_VPP2_5V   0x04
#define VG468_VPP2_12V   0x08
#define VG469_VSENSE   0x1f /* Card voltage sense */
#define VG469_VSELECT   0x2f /* Card voltage select */
#define VG468_CTL   0x38 /* Control register */
#define VG468_TIMER   0x39 /* Timer control */
#define VG468_MISC   0x3a /* Miscellaneous */
#define VG468_GPIO_CFG   0x3b /* GPIO configuration */
#define VG469_EXT_MODE   0x3c /* Extended mode register */
#define VG468_SELECT   0x3d /* Programmable chip select */
#define VG468_SELECT_CFG   0x3e /* Chip select configuration */
#define VG468_ATA   0x3f /* ATA control */
#define VG469_VSENSE_A_VS1   0x01
#define VG469_VSENSE_A_VS2   0x02
#define VG469_VSENSE_B_VS1   0x04
#define VG469_VSENSE_B_VS2   0x08
#define VG469_VSEL_VCC   0x03
#define VG469_VSEL_5V   0x00
#define VG469_VSEL_3V   0x03
#define VG469_VSEL_MAX   0x0c
#define VG469_VSEL_EXT_STAT   0x10
#define VG469_VSEL_EXT_BUS   0x20
#define VG469_VSEL_MIXED   0x40
#define VG469_VSEL_ISA   0x80
#define VG468_CTL_SLOW   0x01 /* 600ns memory timing */
#define VG468_CTL_ASYNC   0x02 /* Asynchronous bus clocking */
#define VG468_CTL_TSSI   0x08 /* Tri-state some outputs */
#define VG468_CTL_DELAY   0x10 /* Card detect debounce */
#define VG468_CTL_INPACK   0x20 /* Obey INPACK signal? */
#define VG468_CTL_POLARITY   0x40 /* VCCEN polarity */
#define VG468_CTL_COMPAT   0x80 /* Compatibility stuff */
#define VG469_CTL_WS_COMPAT   0x04 /* Wait state compatibility */
#define VG469_CTL_STRETCH   0x10 /* LED stretch */
#define VG468_TIMER_ZEROPWR   0x10 /* Zero power control */
#define VG468_TIMER_SIGEN   0x20 /* Power up */
#define VG468_TIMER_STATUS   0x40 /* Activity timer status */
#define VG468_TIMER_RES   0x80 /* Timer resolution */
#define VG468_TIMER_MASK   0x0f /* Activity timer timeout */
#define VG468_MISC_GPIO   0x04 /* General-purpose IO */
#define VG468_MISC_DMAWSB   0x08 /* DMA wait state control */
#define VG469_MISC_LEDENA   0x10 /* LED enable */
#define VG468_MISC_VADEMREV   0x40 /* Vadem revision control */
#define VG468_MISC_UNLOCK   0x80 /* Unique register lock */
#define VG469_MODE_VPPST   0x03 /* Vpp steering control */
#define VG469_MODE_INT_SENSE   0x04 /* Internal voltage sense */
#define VG469_MODE_CABLE   0x08
#define VG469_MODE_COMPAT   0x10 /* i82365sl B or DF step */
#define VG469_MODE_TEST   0x20
#define VG469_MODE_RIO   0x40 /* Steer RIO to INTR? */
#define VG469_MODE_B_3V   0x01 /* 3.3v for socket B */
#define _LINUX_RICOH_H
#define RF5C_MODE_CTL   0x1f /* Mode control */
#define RF5C_PWR_CTL   0x2f /* Mixed voltage control */
#define RF5C_CHIP_ID   0x3a /* Chip identification */
#define RF5C_MODE_CTL_3   0x3b /* Mode control 3 */
#define RF5C_IO_OFF(w)   (0x36+((w)<<1))
#define RF5C_MODE_ATA   0x01 /* ATA mode */
#define RF5C_MODE_LED_ENA   0x02 /* IRQ 12 is LED */
#define RF5C_MODE_CA21   0x04
#define RF5C_MODE_CA22   0x08
#define RF5C_MODE_CA23   0x10
#define RF5C_MODE_CA24   0x20
#define RF5C_MODE_CA25   0x40
#define RF5C_MODE_3STATE_BIT7   0x80
#define RF5C_PWR_VCC_3V   0x01
#define RF5C_PWR_IREQ_HIGH   0x02
#define RF5C_PWR_INPACK_ENA   0x04
#define RF5C_PWR_5V_DET   0x08
#define RF5C_PWR_TC_SEL   0x10 /* Terminal Count: irq 11 or 15 */
#define RF5C_PWR_DREQ_LOW   0x20
#define RF5C_PWR_DREQ_OFF   0x00 /* DREQ steering control */
#define RF5C_PWR_DREQ_INPACK   0x40
#define RF5C_PWR_DREQ_SPKR   0x80
#define RF5C_PWR_DREQ_IOIS16   0xc0
#define RF5C_CHIP_RF5C296   0x32
#define RF5C_CHIP_RF5C396   0xb2
#define RF5C_MCTL3_DISABLE   0x01 /* Disable PCMCIA interface */
#define RF5C_MCTL3_DMA_ENA   0x02
#define RL5C46X_BCR_3E0_ENA   0x0800
#define RL5C46X_BCR_3E2_ENA   0x1000
#define RL5C4XX_CONFIG   0x80 /* 16 bit */
#define RL5C4XX_CONFIG_IO_1_MODE   0x0200
#define RL5C4XX_CONFIG_IO_0_MODE   0x0100
#define RL5C4XX_CONFIG_PREFETCH   0x0001
#define RL5C4XX_MISC   0x0082 /* 16 bit */
#define RL5C4XX_MISC_HW_SUSPEND_ENA   0x0002
#define RL5C4XX_MISC_VCCEN_POL   0x0100
#define RL5C4XX_MISC_VPPEN_POL   0x0200
#define RL5C46X_MISC_SUSPEND   0x0001
#define RL5C46X_MISC_PWR_SAVE_2   0x0004
#define RL5C46X_MISC_IFACE_BUSY   0x0008
#define RL5C46X_MISC_B_LOCK   0x0010
#define RL5C46X_MISC_A_LOCK   0x0020
#define RL5C46X_MISC_PCI_LOCK   0x0040
#define RL5C47X_MISC_IFACE_BUSY   0x0004
#define RL5C47X_MISC_PCI_INT_MASK   0x0018
#define RL5C47X_MISC_PCI_INT_DIS   0x0020
#define RL5C47X_MISC_SUBSYS_WR   0x0040
#define RL5C47X_MISC_SRIRQ_ENA   0x0080
#define RL5C47X_MISC_5V_DISABLE   0x0400
#define RL5C47X_MISC_LED_POL   0x0800
#define RL5C4XX_16BIT_CTL   0x0084 /* 16 bit */
#define RL5C4XX_16CTL_IO_TIMING   0x0100
#define RL5C4XX_16CTL_MEM_TIMING   0x0200
#define RL5C46X_16CTL_LEVEL_1   0x0010
#define RL5C46X_16CTL_LEVEL_2   0x0020
#define RL5C4XX_16BIT_IO_0   0x0088 /* 16 bit */
#define RL5C4XX_16BIT_MEM_0   0x0088 /* 16 bit */
#define RL5C4XX_SETUP_MASK   0x0007
#define RL5C4XX_SETUP_SHIFT   0
#define RL5C4XX_CMD_MASK   0x01f0
#define RL5C4XX_CMD_SHIFT   4
#define RL5C4XX_HOLD_MASK   0x1c00
#define RL5C4XX_HOLD_SHIFT   10
#define RL5C4XX_MISC_CONTROL   0x2F /* 8 bit */
#define RL5C4XX_ZV_ENABLE   0x08
#define _LINUX_CIRRUS_H
#define PCI_VENDOR_ID_CIRRUS   0x1013
#define PCI_DEVICE_ID_CIRRUS_6729   0x1100
#define PCI_DEVICE_ID_CIRRUS_6832   0x1110
#define PD67_MISC_CTL_1   0x16 /* Misc control 1 */
#define PD67_FIFO_CTL   0x17 /* FIFO control */
#define PD67_MISC_CTL_2   0x1E /* Misc control 2 */
#define PD67_CHIP_INFO   0x1f /* Chip information */
#define PD67_ATA_CTL   0x026 /* 6730: ATA control */
#define PD67_EXT_INDEX   0x2e /* Extension index */
#define PD67_EXT_DATA   0x2f /* Extension data */
#define PD67_DATA_MASK0   0x01 /* Data mask 0 */
#define PD67_DATA_MASK1   0x02 /* Data mask 1 */
#define PD67_DMA_CTL   0x03 /* DMA control */
#define PD67_EXT_CTL_1   0x03 /* Extension control 1 */
#define PD67_MEM_PAGE(n)   ((n)+5) /* PCI window bits 31:24 */
#define PD67_EXTERN_DATA   0x0a
#define PD67_MISC_CTL_3   0x25
#define PD67_SMB_PWR_CTL   0x26
#define PD67_IO_OFF(w)   (0x36+((w)<<1))
#define PD67_TIME_SETUP(n)   (0x3a + 3*(n))
#define PD67_TIME_CMD(n)   (0x3b + 3*(n))
#define PD67_TIME_RECOV(n)   (0x3c + 3*(n))
#define PD67_MC1_5V_DET   0x01 /* 5v detect */
#define PD67_MC1_MEDIA_ENA   0x01 /* 6730: Multimedia enable */
#define PD67_MC1_VCC_3V   0x02 /* 3.3v Vcc */
#define PD67_MC1_PULSE_MGMT   0x04
#define PD67_MC1_PULSE_IRQ   0x08
#define PD67_MC1_SPKR_ENA   0x10
#define PD67_MC1_INPACK_ENA   0x80
#define PD67_FIFO_EMPTY   0x80
#define PD67_MC2_FREQ_BYPASS   0x01
#define PD67_MC2_DYNAMIC_MODE   0x02
#define PD67_MC2_SUSPEND   0x04
#define PD67_MC2_5V_CORE   0x08
#define PD67_MC2_LED_ENA   0x10 /* IRQ 12 is LED enable */
#define PD67_MC2_FAST_PCI   0x10 /* 6729: PCI bus > 25 MHz */
#define PD67_MC2_3STATE_BIT7   0x20 /* Floppy change bit */
#define PD67_MC2_DMA_MODE   0x40
#define PD67_MC2_IRQ15_RI   0x80 /* IRQ 15 is ring enable */
#define PD67_INFO_SLOTS   0x20 /* 0 = 1 slot, 1 = 2 slots */
#define PD67_INFO_CHIP_ID   0xc0
#define PD67_INFO_REV   0x1c
#define PD67_TIME_SCALE   0xc0
#define PD67_TIME_SCALE_1   0x00
#define PD67_TIME_SCALE_16   0x40
#define PD67_TIME_SCALE_256   0x80
#define PD67_TIME_SCALE_4096   0xc0
#define PD67_TIME_MULT   0x3f
#define PD67_DMA_MODE   0xc0
#define PD67_DMA_OFF   0x00
#define PD67_DMA_DREQ_INPACK   0x40
#define PD67_DMA_DREQ_WP   0x80
#define PD67_DMA_DREQ_BVD2   0xc0
#define PD67_DMA_PULLUP   0x20 /* Disable socket pullups? */
#define PD67_EC1_VCC_PWR_LOCK   0x01
#define PD67_EC1_AUTO_PWR_CLEAR   0x02
#define PD67_EC1_LED_ENA   0x04
#define PD67_EC1_INV_CARD_IRQ   0x08
#define PD67_EC1_INV_MGMT_IRQ   0x10
#define PD67_EC1_PULLUP_CTL   0x20
#define PD67_MC3_IRQ_MASK   0x03
#define PD67_MC3_IRQ_PCPCI   0x00
#define PD67_MC3_IRQ_EXTERN   0x01
#define PD67_MC3_IRQ_PCIWAY   0x02
#define PD67_MC3_IRQ_PCI   0x03
#define PD67_MC3_PWR_MASK   0x0c
#define PD67_MC3_PWR_SERIAL   0x00
#define PD67_MC3_PWR_TI2202   0x08
#define PD67_MC3_PWR_SMB   0x0c
#define PD68_EXT_CTL_2   0x0b
#define PD68_PCI_SPACE   0x22
#define PD68_PCCARD_SPACE   0x23
#define PD68_WINDOW_TYPE   0x24
#define PD68_EXT_CSC   0x2e
#define PD68_MISC_CTL_4   0x2f
#define PD68_MISC_CTL_5   0x30
#define PD68_MISC_CTL_6   0x31
#define PD68_MC3_HW_SUSP   0x10
#define PD68_MC3_MM_EXPAND   0x40
#define PD68_MC3_MM_ARM   0x80
#define PD6832_BCR_MGMT_IRQ_ENA   0x0800
#define PD6832_SOCKET_NUMBER   0x004c /* 8 bit */

Functions

 FILE_LICENCE (GPL2_ONLY)

Define Documentation

#define _LINUX_I82365_H

Definition at line 20 of file i82365.h.

#define I365_IDENT   0x00 /* Identification and revision */

Definition at line 25 of file i82365.h.

#define I365_STATUS   0x01 /* Interface status */

Definition at line 26 of file i82365.h.

#define I365_POWER   0x02 /* Power and RESETDRV control */

Definition at line 27 of file i82365.h.

#define I365_INTCTL   0x03 /* Interrupt and general control */

Definition at line 28 of file i82365.h.

#define I365_CSC   0x04 /* Card status change */

Definition at line 29 of file i82365.h.

#define I365_CSCINT   0x05 /* Card status change interrupt control */

Definition at line 30 of file i82365.h.

#define I365_ADDRWIN   0x06 /* Address window enable */

Definition at line 31 of file i82365.h.

#define I365_IOCTL   0x07 /* I/O control */

Definition at line 32 of file i82365.h.

#define I365_GENCTL   0x16 /* Card detect and general control */

Definition at line 33 of file i82365.h.

#define I365_GBLCTL   0x1E /* Global control register */

Definition at line 34 of file i82365.h.

#define I365_IO (   map)    (0x08+((map)<<2))

Definition at line 37 of file i82365.h.

#define I365_MEM (   map)    (0x10+((map)<<3))

Definition at line 38 of file i82365.h.

#define I365_W_START   0

Definition at line 39 of file i82365.h.

#define I365_W_STOP   2

Definition at line 40 of file i82365.h.

#define I365_W_OFF   4

Definition at line 41 of file i82365.h.

#define I365_CS_BVD1   0x01

Definition at line 44 of file i82365.h.

#define I365_CS_STSCHG   0x01

Definition at line 45 of file i82365.h.

#define I365_CS_BVD2   0x02

Definition at line 46 of file i82365.h.

#define I365_CS_SPKR   0x02

Definition at line 47 of file i82365.h.

#define I365_CS_DETECT   0x0C

Definition at line 48 of file i82365.h.

#define I365_CS_WRPROT   0x10

Definition at line 49 of file i82365.h.

#define I365_CS_READY   0x20 /* Inverted */

Definition at line 50 of file i82365.h.

#define I365_CS_POWERON   0x40

Definition at line 51 of file i82365.h.

#define I365_CS_GPI   0x80

Definition at line 52 of file i82365.h.

#define I365_PWR_OFF   0x00 /* Turn off the socket */

Definition at line 55 of file i82365.h.

#define I365_PWR_OUT   0x80 /* Output enable */

Definition at line 56 of file i82365.h.

#define I365_PWR_NORESET   0x40 /* Disable RESETDRV on resume */

Definition at line 57 of file i82365.h.

#define I365_PWR_AUTO   0x20 /* Auto pwr switch enable */

Definition at line 58 of file i82365.h.

#define I365_VCC_MASK   0x18 /* Mask for turning off Vcc */

Definition at line 59 of file i82365.h.

#define I365_VCC_5V   0x10 /* Vcc = 5.0v */

Definition at line 63 of file i82365.h.

#define I365_VCC_3V   0x18 /* Vcc = 3.3v */

Definition at line 64 of file i82365.h.

#define I365_VPP2_MASK   0x0c /* Mask for turning off Vpp2 */

Definition at line 65 of file i82365.h.

#define I365_VPP2_5V   0x04 /* Vpp2 = 5.0v */

Definition at line 66 of file i82365.h.

#define I365_VPP2_12V   0x08 /* Vpp2 = 12.0v */

Definition at line 67 of file i82365.h.

#define I365_VPP1_MASK   0x03 /* Mask for turning off Vpp1 */

Definition at line 68 of file i82365.h.

#define I365_VPP1_5V   0x01 /* Vpp2 = 5.0v */

Definition at line 69 of file i82365.h.

#define I365_VPP1_12V   0x02 /* Vpp2 = 12.0v */

Definition at line 70 of file i82365.h.

#define I365_RING_ENA   0x80

Definition at line 73 of file i82365.h.

#define I365_PC_RESET   0x40

Definition at line 74 of file i82365.h.

#define I365_PC_IOCARD   0x20

Definition at line 75 of file i82365.h.

#define I365_INTR_ENA   0x10

Definition at line 76 of file i82365.h.

#define I365_IRQ_MASK   0x0F

Definition at line 77 of file i82365.h.

#define I365_CSC_BVD1   0x01

Definition at line 80 of file i82365.h.

#define I365_CSC_STSCHG   0x01

Definition at line 81 of file i82365.h.

#define I365_CSC_BVD2   0x02

Definition at line 82 of file i82365.h.

#define I365_CSC_READY   0x04

Definition at line 83 of file i82365.h.

#define I365_CSC_DETECT   0x08

Definition at line 84 of file i82365.h.

#define I365_CSC_ANY   0x0F

Definition at line 85 of file i82365.h.

#define I365_CSC_GPI   0x10

Definition at line 86 of file i82365.h.

#define I365_ENA_IO (   map)    (0x40 << (map))

Definition at line 89 of file i82365.h.

#define I365_ENA_MEM (   map)    (0x01 << (map))

Definition at line 90 of file i82365.h.

#define I365_IOCTL_MASK (   map)    (0x0F << (map<<2))

Definition at line 93 of file i82365.h.

#define I365_IOCTL_WAIT (   map)    (0x08 << (map<<2))

Definition at line 94 of file i82365.h.

#define I365_IOCTL_0WS (   map)    (0x04 << (map<<2))

Definition at line 95 of file i82365.h.

#define I365_IOCTL_IOCS16 (   map)    (0x02 << (map<<2))

Definition at line 96 of file i82365.h.

#define I365_IOCTL_16BIT (   map)    (0x01 << (map<<2))

Definition at line 97 of file i82365.h.

#define I365_CTL_16DELAY   0x01

Definition at line 100 of file i82365.h.

#define I365_CTL_RESET   0x02

Definition at line 101 of file i82365.h.

#define I365_CTL_GPI_ENA   0x04

Definition at line 102 of file i82365.h.

#define I365_CTL_GPI_CTL   0x08

Definition at line 103 of file i82365.h.

#define I365_CTL_RESUME   0x10

Definition at line 104 of file i82365.h.

#define I365_CTL_SW_IRQ   0x20

Definition at line 105 of file i82365.h.

#define I365_GBL_PWRDOWN   0x01

Definition at line 108 of file i82365.h.

#define I365_GBL_CSC_LEV   0x02

Definition at line 109 of file i82365.h.

#define I365_GBL_WRBACK   0x04

Definition at line 110 of file i82365.h.

#define I365_GBL_IRQ_0_LEV   0x08

Definition at line 111 of file i82365.h.

#define I365_GBL_IRQ_1_LEV   0x10

Definition at line 112 of file i82365.h.

#define I365_MEM_16BIT   0x8000 /* In memory start high byte */

Definition at line 115 of file i82365.h.

#define I365_MEM_0WS   0x4000

Definition at line 116 of file i82365.h.

#define I365_MEM_WS1   0x8000 /* In memory stop high byte */

Definition at line 117 of file i82365.h.

#define I365_MEM_WS0   0x4000

Definition at line 118 of file i82365.h.

#define I365_MEM_WRPROT   0x8000 /* In offset high byte */

Definition at line 119 of file i82365.h.

#define I365_MEM_REG   0x4000

Definition at line 120 of file i82365.h.

#define I365_REG (   slot,
  reg 
)    (((slot) << 6) + reg)

Definition at line 122 of file i82365.h.

#define _LINUX_VG468_H

Definition at line 134 of file i82365.h.

#define I365_IDENT_VADEM   0x08

Definition at line 137 of file i82365.h.

#define VG468_VPP2_MASK   0x0c

Definition at line 140 of file i82365.h.

#define VG468_VPP2_5V   0x04

Definition at line 141 of file i82365.h.

#define VG468_VPP2_12V   0x08

Definition at line 142 of file i82365.h.

#define VG469_VSENSE   0x1f /* Card voltage sense */

Definition at line 145 of file i82365.h.

#define VG469_VSELECT   0x2f /* Card voltage select */

Definition at line 146 of file i82365.h.

#define VG468_CTL   0x38 /* Control register */

Definition at line 147 of file i82365.h.

#define VG468_TIMER   0x39 /* Timer control */

Definition at line 148 of file i82365.h.

#define VG468_MISC   0x3a /* Miscellaneous */

Definition at line 149 of file i82365.h.

#define VG468_GPIO_CFG   0x3b /* GPIO configuration */

Definition at line 150 of file i82365.h.

#define VG469_EXT_MODE   0x3c /* Extended mode register */

Definition at line 151 of file i82365.h.

#define VG468_SELECT   0x3d /* Programmable chip select */

Definition at line 152 of file i82365.h.

#define VG468_SELECT_CFG   0x3e /* Chip select configuration */

Definition at line 153 of file i82365.h.

#define VG468_ATA   0x3f /* ATA control */

Definition at line 154 of file i82365.h.

#define VG469_VSENSE_A_VS1   0x01

Definition at line 157 of file i82365.h.

#define VG469_VSENSE_A_VS2   0x02

Definition at line 158 of file i82365.h.

#define VG469_VSENSE_B_VS1   0x04

Definition at line 159 of file i82365.h.

#define VG469_VSENSE_B_VS2   0x08

Definition at line 160 of file i82365.h.

#define VG469_VSEL_VCC   0x03

Definition at line 163 of file i82365.h.

#define VG469_VSEL_5V   0x00

Definition at line 164 of file i82365.h.

#define VG469_VSEL_3V   0x03

Definition at line 165 of file i82365.h.

#define VG469_VSEL_MAX   0x0c

Definition at line 166 of file i82365.h.

#define VG469_VSEL_EXT_STAT   0x10

Definition at line 167 of file i82365.h.

#define VG469_VSEL_EXT_BUS   0x20

Definition at line 168 of file i82365.h.

#define VG469_VSEL_MIXED   0x40

Definition at line 169 of file i82365.h.

#define VG469_VSEL_ISA   0x80

Definition at line 170 of file i82365.h.

#define VG468_CTL_SLOW   0x01 /* 600ns memory timing */

Definition at line 173 of file i82365.h.

#define VG468_CTL_ASYNC   0x02 /* Asynchronous bus clocking */

Definition at line 174 of file i82365.h.

#define VG468_CTL_TSSI   0x08 /* Tri-state some outputs */

Definition at line 175 of file i82365.h.

#define VG468_CTL_DELAY   0x10 /* Card detect debounce */

Definition at line 176 of file i82365.h.

#define VG468_CTL_INPACK   0x20 /* Obey INPACK signal? */

Definition at line 177 of file i82365.h.

#define VG468_CTL_POLARITY   0x40 /* VCCEN polarity */

Definition at line 178 of file i82365.h.

#define VG468_CTL_COMPAT   0x80 /* Compatibility stuff */

Definition at line 179 of file i82365.h.

#define VG469_CTL_WS_COMPAT   0x04 /* Wait state compatibility */

Definition at line 181 of file i82365.h.

#define VG469_CTL_STRETCH   0x10 /* LED stretch */

Definition at line 182 of file i82365.h.

#define VG468_TIMER_ZEROPWR   0x10 /* Zero power control */

Definition at line 185 of file i82365.h.

#define VG468_TIMER_SIGEN   0x20 /* Power up */

Definition at line 186 of file i82365.h.

#define VG468_TIMER_STATUS   0x40 /* Activity timer status */

Definition at line 187 of file i82365.h.

#define VG468_TIMER_RES   0x80 /* Timer resolution */

Definition at line 188 of file i82365.h.

#define VG468_TIMER_MASK   0x0f /* Activity timer timeout */

Definition at line 189 of file i82365.h.

#define VG468_MISC_GPIO   0x04 /* General-purpose IO */

Definition at line 192 of file i82365.h.

#define VG468_MISC_DMAWSB   0x08 /* DMA wait state control */

Definition at line 193 of file i82365.h.

#define VG469_MISC_LEDENA   0x10 /* LED enable */

Definition at line 194 of file i82365.h.

#define VG468_MISC_VADEMREV   0x40 /* Vadem revision control */

Definition at line 195 of file i82365.h.

#define VG468_MISC_UNLOCK   0x80 /* Unique register lock */

Definition at line 196 of file i82365.h.

#define VG469_MODE_VPPST   0x03 /* Vpp steering control */

Definition at line 199 of file i82365.h.

#define VG469_MODE_INT_SENSE   0x04 /* Internal voltage sense */

Definition at line 200 of file i82365.h.

#define VG469_MODE_CABLE   0x08

Definition at line 201 of file i82365.h.

#define VG469_MODE_COMPAT   0x10 /* i82365sl B or DF step */

Definition at line 202 of file i82365.h.

#define VG469_MODE_TEST   0x20

Definition at line 203 of file i82365.h.

#define VG469_MODE_RIO   0x40 /* Steer RIO to INTR? */

Definition at line 204 of file i82365.h.

#define VG469_MODE_B_3V   0x01 /* 3.3v for socket B */

Definition at line 207 of file i82365.h.

#define _LINUX_RICOH_H

Definition at line 220 of file i82365.h.

#define RF5C_MODE_CTL   0x1f /* Mode control */

Definition at line 223 of file i82365.h.

#define RF5C_PWR_CTL   0x2f /* Mixed voltage control */

Definition at line 224 of file i82365.h.

#define RF5C_CHIP_ID   0x3a /* Chip identification */

Definition at line 225 of file i82365.h.

#define RF5C_MODE_CTL_3   0x3b /* Mode control 3 */

Definition at line 226 of file i82365.h.

#define RF5C_IO_OFF (   w)    (0x36+((w)<<1))

Definition at line 229 of file i82365.h.

#define RF5C_MODE_ATA   0x01 /* ATA mode */

Definition at line 232 of file i82365.h.

#define RF5C_MODE_LED_ENA   0x02 /* IRQ 12 is LED */

Definition at line 233 of file i82365.h.

#define RF5C_MODE_CA21   0x04

Definition at line 234 of file i82365.h.

#define RF5C_MODE_CA22   0x08

Definition at line 235 of file i82365.h.

#define RF5C_MODE_CA23   0x10

Definition at line 236 of file i82365.h.

#define RF5C_MODE_CA24   0x20

Definition at line 237 of file i82365.h.

#define RF5C_MODE_CA25   0x40

Definition at line 238 of file i82365.h.

#define RF5C_MODE_3STATE_BIT7   0x80

Definition at line 239 of file i82365.h.

#define RF5C_PWR_VCC_3V   0x01

Definition at line 242 of file i82365.h.

#define RF5C_PWR_IREQ_HIGH   0x02

Definition at line 243 of file i82365.h.

#define RF5C_PWR_INPACK_ENA   0x04

Definition at line 244 of file i82365.h.

#define RF5C_PWR_5V_DET   0x08

Definition at line 245 of file i82365.h.

#define RF5C_PWR_TC_SEL   0x10 /* Terminal Count: irq 11 or 15 */

Definition at line 246 of file i82365.h.

#define RF5C_PWR_DREQ_LOW   0x20

Definition at line 247 of file i82365.h.

#define RF5C_PWR_DREQ_OFF   0x00 /* DREQ steering control */

Definition at line 248 of file i82365.h.

#define RF5C_PWR_DREQ_INPACK   0x40

Definition at line 249 of file i82365.h.

#define RF5C_PWR_DREQ_SPKR   0x80

Definition at line 250 of file i82365.h.

#define RF5C_PWR_DREQ_IOIS16   0xc0

Definition at line 251 of file i82365.h.

#define RF5C_CHIP_RF5C296   0x32

Definition at line 254 of file i82365.h.

#define RF5C_CHIP_RF5C396   0xb2

Definition at line 255 of file i82365.h.

#define RF5C_MCTL3_DISABLE   0x01 /* Disable PCMCIA interface */

Definition at line 258 of file i82365.h.

#define RF5C_MCTL3_DMA_ENA   0x02

Definition at line 259 of file i82365.h.

#define RL5C46X_BCR_3E0_ENA   0x0800

Definition at line 264 of file i82365.h.

#define RL5C46X_BCR_3E2_ENA   0x1000

Definition at line 265 of file i82365.h.

#define RL5C4XX_CONFIG   0x80 /* 16 bit */

Definition at line 268 of file i82365.h.

#define RL5C4XX_CONFIG_IO_1_MODE   0x0200

Definition at line 269 of file i82365.h.

#define RL5C4XX_CONFIG_IO_0_MODE   0x0100

Definition at line 270 of file i82365.h.

#define RL5C4XX_CONFIG_PREFETCH   0x0001

Definition at line 271 of file i82365.h.

#define RL5C4XX_MISC   0x0082 /* 16 bit */

Definition at line 275 of file i82365.h.

#define RL5C4XX_MISC_HW_SUSPEND_ENA   0x0002

Definition at line 276 of file i82365.h.

#define RL5C4XX_MISC_VCCEN_POL   0x0100

Definition at line 277 of file i82365.h.

#define RL5C4XX_MISC_VPPEN_POL   0x0200

Definition at line 278 of file i82365.h.

#define RL5C46X_MISC_SUSPEND   0x0001

Definition at line 279 of file i82365.h.

#define RL5C46X_MISC_PWR_SAVE_2   0x0004

Definition at line 280 of file i82365.h.

#define RL5C46X_MISC_IFACE_BUSY   0x0008

Definition at line 281 of file i82365.h.

#define RL5C46X_MISC_B_LOCK   0x0010

Definition at line 282 of file i82365.h.

#define RL5C46X_MISC_A_LOCK   0x0020

Definition at line 283 of file i82365.h.

#define RL5C46X_MISC_PCI_LOCK   0x0040

Definition at line 284 of file i82365.h.

#define RL5C47X_MISC_IFACE_BUSY   0x0004

Definition at line 285 of file i82365.h.

#define RL5C47X_MISC_PCI_INT_MASK   0x0018

Definition at line 286 of file i82365.h.

#define RL5C47X_MISC_PCI_INT_DIS   0x0020

Definition at line 287 of file i82365.h.

#define RL5C47X_MISC_SUBSYS_WR   0x0040

Definition at line 288 of file i82365.h.

#define RL5C47X_MISC_SRIRQ_ENA   0x0080

Definition at line 289 of file i82365.h.

#define RL5C47X_MISC_5V_DISABLE   0x0400

Definition at line 290 of file i82365.h.

#define RL5C47X_MISC_LED_POL   0x0800

Definition at line 291 of file i82365.h.

#define RL5C4XX_16BIT_CTL   0x0084 /* 16 bit */

Definition at line 294 of file i82365.h.

#define RL5C4XX_16CTL_IO_TIMING   0x0100

Definition at line 295 of file i82365.h.

#define RL5C4XX_16CTL_MEM_TIMING   0x0200

Definition at line 296 of file i82365.h.

#define RL5C46X_16CTL_LEVEL_1   0x0010

Definition at line 297 of file i82365.h.

#define RL5C46X_16CTL_LEVEL_2   0x0020

Definition at line 298 of file i82365.h.

#define RL5C4XX_16BIT_IO_0   0x0088 /* 16 bit */

Definition at line 301 of file i82365.h.

#define RL5C4XX_16BIT_MEM_0   0x0088 /* 16 bit */

Definition at line 302 of file i82365.h.

#define RL5C4XX_SETUP_MASK   0x0007

Definition at line 303 of file i82365.h.

#define RL5C4XX_SETUP_SHIFT   0

Definition at line 304 of file i82365.h.

#define RL5C4XX_CMD_MASK   0x01f0

Definition at line 305 of file i82365.h.

#define RL5C4XX_CMD_SHIFT   4

Definition at line 306 of file i82365.h.

#define RL5C4XX_HOLD_MASK   0x1c00

Definition at line 307 of file i82365.h.

#define RL5C4XX_HOLD_SHIFT   10

Definition at line 308 of file i82365.h.

#define RL5C4XX_MISC_CONTROL   0x2F /* 8 bit */

Definition at line 309 of file i82365.h.

#define RL5C4XX_ZV_ENABLE   0x08

Definition at line 310 of file i82365.h.

#define _LINUX_CIRRUS_H

Definition at line 323 of file i82365.h.

#define PCI_VENDOR_ID_CIRRUS   0x1013

Definition at line 326 of file i82365.h.

#define PCI_DEVICE_ID_CIRRUS_6729   0x1100

Definition at line 329 of file i82365.h.

#define PCI_DEVICE_ID_CIRRUS_6832   0x1110

Definition at line 332 of file i82365.h.

#define PD67_MISC_CTL_1   0x16 /* Misc control 1 */

Definition at line 335 of file i82365.h.

#define PD67_FIFO_CTL   0x17 /* FIFO control */

Definition at line 336 of file i82365.h.

#define PD67_MISC_CTL_2   0x1E /* Misc control 2 */

Definition at line 337 of file i82365.h.

#define PD67_CHIP_INFO   0x1f /* Chip information */

Definition at line 338 of file i82365.h.

#define PD67_ATA_CTL   0x026 /* 6730: ATA control */

Definition at line 339 of file i82365.h.

#define PD67_EXT_INDEX   0x2e /* Extension index */

Definition at line 340 of file i82365.h.

#define PD67_EXT_DATA   0x2f /* Extension data */

Definition at line 341 of file i82365.h.

#define PD67_DATA_MASK0   0x01 /* Data mask 0 */

Definition at line 344 of file i82365.h.

#define PD67_DATA_MASK1   0x02 /* Data mask 1 */

Definition at line 345 of file i82365.h.

#define PD67_DMA_CTL   0x03 /* DMA control */

Definition at line 346 of file i82365.h.

#define PD67_EXT_CTL_1   0x03 /* Extension control 1 */

Definition at line 349 of file i82365.h.

#define PD67_MEM_PAGE (   n)    ((n)+5) /* PCI window bits 31:24 */

Definition at line 350 of file i82365.h.

#define PD67_EXTERN_DATA   0x0a

Definition at line 351 of file i82365.h.

#define PD67_MISC_CTL_3   0x25

Definition at line 352 of file i82365.h.

#define PD67_SMB_PWR_CTL   0x26

Definition at line 353 of file i82365.h.

#define PD67_IO_OFF (   w)    (0x36+((w)<<1))

Definition at line 356 of file i82365.h.

#define PD67_TIME_SETUP (   n)    (0x3a + 3*(n))

Definition at line 359 of file i82365.h.

#define PD67_TIME_CMD (   n)    (0x3b + 3*(n))

Definition at line 360 of file i82365.h.

#define PD67_TIME_RECOV (   n)    (0x3c + 3*(n))

Definition at line 361 of file i82365.h.

#define PD67_MC1_5V_DET   0x01 /* 5v detect */

Definition at line 364 of file i82365.h.

#define PD67_MC1_MEDIA_ENA   0x01 /* 6730: Multimedia enable */

Definition at line 365 of file i82365.h.

#define PD67_MC1_VCC_3V   0x02 /* 3.3v Vcc */

Definition at line 366 of file i82365.h.

#define PD67_MC1_PULSE_MGMT   0x04

Definition at line 367 of file i82365.h.

#define PD67_MC1_PULSE_IRQ   0x08

Definition at line 368 of file i82365.h.

#define PD67_MC1_SPKR_ENA   0x10

Definition at line 369 of file i82365.h.

#define PD67_MC1_INPACK_ENA   0x80

Definition at line 370 of file i82365.h.

#define PD67_FIFO_EMPTY   0x80

Definition at line 373 of file i82365.h.

#define PD67_MC2_FREQ_BYPASS   0x01

Definition at line 376 of file i82365.h.

#define PD67_MC2_DYNAMIC_MODE   0x02

Definition at line 377 of file i82365.h.

#define PD67_MC2_SUSPEND   0x04

Definition at line 378 of file i82365.h.

#define PD67_MC2_5V_CORE   0x08

Definition at line 379 of file i82365.h.

#define PD67_MC2_LED_ENA   0x10 /* IRQ 12 is LED enable */

Definition at line 380 of file i82365.h.

#define PD67_MC2_FAST_PCI   0x10 /* 6729: PCI bus > 25 MHz */

Definition at line 381 of file i82365.h.

#define PD67_MC2_3STATE_BIT7   0x20 /* Floppy change bit */

Definition at line 382 of file i82365.h.

#define PD67_MC2_DMA_MODE   0x40

Definition at line 383 of file i82365.h.

#define PD67_MC2_IRQ15_RI   0x80 /* IRQ 15 is ring enable */

Definition at line 384 of file i82365.h.

#define PD67_INFO_SLOTS   0x20 /* 0 = 1 slot, 1 = 2 slots */

Definition at line 387 of file i82365.h.

#define PD67_INFO_CHIP_ID   0xc0

Definition at line 388 of file i82365.h.

#define PD67_INFO_REV   0x1c

Definition at line 389 of file i82365.h.

#define PD67_TIME_SCALE   0xc0

Definition at line 392 of file i82365.h.

#define PD67_TIME_SCALE_1   0x00

Definition at line 393 of file i82365.h.

#define PD67_TIME_SCALE_16   0x40

Definition at line 394 of file i82365.h.

#define PD67_TIME_SCALE_256   0x80

Definition at line 395 of file i82365.h.

#define PD67_TIME_SCALE_4096   0xc0

Definition at line 396 of file i82365.h.

#define PD67_TIME_MULT   0x3f

Definition at line 397 of file i82365.h.

#define PD67_DMA_MODE   0xc0

Definition at line 400 of file i82365.h.

#define PD67_DMA_OFF   0x00

Definition at line 401 of file i82365.h.

#define PD67_DMA_DREQ_INPACK   0x40

Definition at line 402 of file i82365.h.

#define PD67_DMA_DREQ_WP   0x80

Definition at line 403 of file i82365.h.

#define PD67_DMA_DREQ_BVD2   0xc0

Definition at line 404 of file i82365.h.

#define PD67_DMA_PULLUP   0x20 /* Disable socket pullups? */

Definition at line 405 of file i82365.h.

#define PD67_EC1_VCC_PWR_LOCK   0x01

Definition at line 408 of file i82365.h.

#define PD67_EC1_AUTO_PWR_CLEAR   0x02

Definition at line 409 of file i82365.h.

#define PD67_EC1_LED_ENA   0x04

Definition at line 410 of file i82365.h.

#define PD67_EC1_INV_CARD_IRQ   0x08

Definition at line 411 of file i82365.h.

#define PD67_EC1_INV_MGMT_IRQ   0x10

Definition at line 412 of file i82365.h.

#define PD67_EC1_PULLUP_CTL   0x20

Definition at line 413 of file i82365.h.

#define PD67_MC3_IRQ_MASK   0x03

Definition at line 416 of file i82365.h.

#define PD67_MC3_IRQ_PCPCI   0x00

Definition at line 417 of file i82365.h.

#define PD67_MC3_IRQ_EXTERN   0x01

Definition at line 418 of file i82365.h.

#define PD67_MC3_IRQ_PCIWAY   0x02

Definition at line 419 of file i82365.h.

#define PD67_MC3_IRQ_PCI   0x03

Definition at line 420 of file i82365.h.

#define PD67_MC3_PWR_MASK   0x0c

Definition at line 421 of file i82365.h.

#define PD67_MC3_PWR_SERIAL   0x00

Definition at line 422 of file i82365.h.

#define PD67_MC3_PWR_TI2202   0x08

Definition at line 423 of file i82365.h.

#define PD67_MC3_PWR_SMB   0x0c

Definition at line 424 of file i82365.h.

#define PD68_EXT_CTL_2   0x0b

Definition at line 429 of file i82365.h.

#define PD68_PCI_SPACE   0x22

Definition at line 430 of file i82365.h.

#define PD68_PCCARD_SPACE   0x23

Definition at line 431 of file i82365.h.

#define PD68_WINDOW_TYPE   0x24

Definition at line 432 of file i82365.h.

#define PD68_EXT_CSC   0x2e

Definition at line 433 of file i82365.h.

#define PD68_MISC_CTL_4   0x2f

Definition at line 434 of file i82365.h.

#define PD68_MISC_CTL_5   0x30

Definition at line 435 of file i82365.h.

#define PD68_MISC_CTL_6   0x31

Definition at line 436 of file i82365.h.

#define PD68_MC3_HW_SUSP   0x10

Definition at line 439 of file i82365.h.

#define PD68_MC3_MM_EXPAND   0x40

Definition at line 440 of file i82365.h.

#define PD68_MC3_MM_ARM   0x80

Definition at line 441 of file i82365.h.

#define PD6832_BCR_MGMT_IRQ_ENA   0x0800

Definition at line 444 of file i82365.h.

#define PD6832_SOCKET_NUMBER   0x004c /* 8 bit */

Definition at line 447 of file i82365.h.


Function Documentation

FILE_LICENCE ( GPL2_ONLY  )