iPXE
i82365.h
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00001 /*
00002  * i82365.h 1.15 1999/10/25 20:03:34
00003  *
00004  * The contents of this file may be used under the
00005  * terms of the GNU General Public License version 2 (the "GPL").
00006  *
00007  * Software distributed under the License is distributed on an "AS IS"
00008  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
00009  * the License for the specific language governing rights and
00010  * limitations under the License. 
00011  *
00012  * The initial developer of the original code is David A. Hinds
00013  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
00014  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
00015  */
00016 
00017 FILE_LICENCE ( GPL2_ONLY );
00018 
00019 #ifndef _LINUX_I82365_H
00020 #define _LINUX_I82365_H
00021 
00022 /* register definitions for the Intel 82365SL PCMCIA controller */
00023 
00024 /* Offsets for PCIC registers */
00025 #define I365_IDENT      0x00    /* Identification and revision */
00026 #define I365_STATUS     0x01    /* Interface status */
00027 #define I365_POWER      0x02    /* Power and RESETDRV control */
00028 #define I365_INTCTL     0x03    /* Interrupt and general control */
00029 #define I365_CSC        0x04    /* Card status change */
00030 #define I365_CSCINT     0x05    /* Card status change interrupt control */
00031 #define I365_ADDRWIN    0x06    /* Address window enable */
00032 #define I365_IOCTL      0x07    /* I/O control */
00033 #define I365_GENCTL     0x16    /* Card detect and general control */
00034 #define I365_GBLCTL     0x1E    /* Global control register */
00035 
00036 /* Offsets for I/O and memory window registers */
00037 #define I365_IO(map)    (0x08+((map)<<2))
00038 #define I365_MEM(map)   (0x10+((map)<<3))
00039 #define I365_W_START    0
00040 #define I365_W_STOP     2
00041 #define I365_W_OFF      4
00042 
00043 /* Flags for I365_STATUS */
00044 #define I365_CS_BVD1    0x01
00045 #define I365_CS_STSCHG  0x01
00046 #define I365_CS_BVD2    0x02
00047 #define I365_CS_SPKR    0x02
00048 #define I365_CS_DETECT  0x0C
00049 #define I365_CS_WRPROT  0x10
00050 #define I365_CS_READY   0x20    /* Inverted */
00051 #define I365_CS_POWERON 0x40
00052 #define I365_CS_GPI     0x80
00053 
00054 /* Flags for I365_POWER */
00055 #define I365_PWR_OFF    0x00    /* Turn off the socket */
00056 #define I365_PWR_OUT    0x80    /* Output enable */
00057 #define I365_PWR_NORESET 0x40   /* Disable RESETDRV on resume */
00058 #define I365_PWR_AUTO   0x20    /* Auto pwr switch enable */
00059 #define I365_VCC_MASK   0x18    /* Mask for turning off Vcc */
00060 /* There are different layouts for B-step and DF-step chips: the B
00061    step has independent Vpp1/Vpp2 control, and the DF step has only
00062    Vpp1 control, plus 3V control */
00063 #define I365_VCC_5V     0x10    /* Vcc = 5.0v */
00064 #define I365_VCC_3V     0x18    /* Vcc = 3.3v */
00065 #define I365_VPP2_MASK  0x0c    /* Mask for turning off Vpp2 */
00066 #define I365_VPP2_5V    0x04    /* Vpp2 = 5.0v */
00067 #define I365_VPP2_12V   0x08    /* Vpp2 = 12.0v */
00068 #define I365_VPP1_MASK  0x03    /* Mask for turning off Vpp1 */
00069 #define I365_VPP1_5V    0x01    /* Vpp2 = 5.0v */
00070 #define I365_VPP1_12V   0x02    /* Vpp2 = 12.0v */
00071 
00072 /* Flags for I365_INTCTL */
00073 #define I365_RING_ENA   0x80
00074 #define I365_PC_RESET   0x40
00075 #define I365_PC_IOCARD  0x20
00076 #define I365_INTR_ENA   0x10
00077 #define I365_IRQ_MASK   0x0F
00078 
00079 /* Flags for I365_CSC and I365_CSCINT*/
00080 #define I365_CSC_BVD1   0x01
00081 #define I365_CSC_STSCHG 0x01
00082 #define I365_CSC_BVD2   0x02
00083 #define I365_CSC_READY  0x04
00084 #define I365_CSC_DETECT 0x08
00085 #define I365_CSC_ANY    0x0F
00086 #define I365_CSC_GPI    0x10
00087 
00088 /* Flags for I365_ADDRWIN */
00089 #define I365_ENA_IO(map)        (0x40 << (map))
00090 #define I365_ENA_MEM(map)       (0x01 << (map))
00091 
00092 /* Flags for I365_IOCTL */
00093 #define I365_IOCTL_MASK(map)    (0x0F << (map<<2))
00094 #define I365_IOCTL_WAIT(map)    (0x08 << (map<<2))
00095 #define I365_IOCTL_0WS(map)     (0x04 << (map<<2))
00096 #define I365_IOCTL_IOCS16(map)  (0x02 << (map<<2))
00097 #define I365_IOCTL_16BIT(map)   (0x01 << (map<<2))
00098 
00099 /* Flags for I365_GENCTL */
00100 #define I365_CTL_16DELAY        0x01
00101 #define I365_CTL_RESET          0x02
00102 #define I365_CTL_GPI_ENA        0x04
00103 #define I365_CTL_GPI_CTL        0x08
00104 #define I365_CTL_RESUME         0x10
00105 #define I365_CTL_SW_IRQ         0x20
00106 
00107 /* Flags for I365_GBLCTL */
00108 #define I365_GBL_PWRDOWN        0x01
00109 #define I365_GBL_CSC_LEV        0x02
00110 #define I365_GBL_WRBACK         0x04
00111 #define I365_GBL_IRQ_0_LEV      0x08
00112 #define I365_GBL_IRQ_1_LEV      0x10
00113 
00114 /* Flags for memory window registers */
00115 #define I365_MEM_16BIT  0x8000  /* In memory start high byte */
00116 #define I365_MEM_0WS    0x4000
00117 #define I365_MEM_WS1    0x8000  /* In memory stop high byte */
00118 #define I365_MEM_WS0    0x4000
00119 #define I365_MEM_WRPROT 0x8000  /* In offset high byte */
00120 #define I365_MEM_REG    0x4000
00121 
00122 #define I365_REG(slot, reg)     (((slot) << 6) + reg)
00123 
00124 #endif /* _LINUX_I82365_H */
00125 
00126 //*****************************************************************************
00127 //*****************************************************************************
00128 //*****************************************************************************
00129 //*****************************************************************************
00130 //*****************************************************************************
00131 // Beginning vg468.h (for VADEM chipset)
00132 
00133 #ifndef _LINUX_VG468_H
00134 #define _LINUX_VG468_H
00135 
00136 /* Special bit in I365_IDENT used for Vadem chip detection */
00137 #define I365_IDENT_VADEM        0x08
00138 
00139 /* Special definitions in I365_POWER */
00140 #define VG468_VPP2_MASK         0x0c
00141 #define VG468_VPP2_5V           0x04
00142 #define VG468_VPP2_12V          0x08
00143 
00144 /* Unique Vadem registers */
00145 #define VG469_VSENSE            0x1f    /* Card voltage sense */
00146 #define VG469_VSELECT           0x2f    /* Card voltage select */
00147 #define VG468_CTL               0x38    /* Control register */
00148 #define VG468_TIMER             0x39    /* Timer control */
00149 #define VG468_MISC              0x3a    /* Miscellaneous */
00150 #define VG468_GPIO_CFG          0x3b    /* GPIO configuration */
00151 #define VG469_EXT_MODE          0x3c    /* Extended mode register */
00152 #define VG468_SELECT            0x3d    /* Programmable chip select */
00153 #define VG468_SELECT_CFG        0x3e    /* Chip select configuration */
00154 #define VG468_ATA               0x3f    /* ATA control */
00155 
00156 /* Flags for VG469_VSENSE */
00157 #define VG469_VSENSE_A_VS1      0x01
00158 #define VG469_VSENSE_A_VS2      0x02
00159 #define VG469_VSENSE_B_VS1      0x04
00160 #define VG469_VSENSE_B_VS2      0x08
00161 
00162 /* Flags for VG469_VSELECT */
00163 #define VG469_VSEL_VCC          0x03
00164 #define VG469_VSEL_5V           0x00
00165 #define VG469_VSEL_3V           0x03
00166 #define VG469_VSEL_MAX          0x0c
00167 #define VG469_VSEL_EXT_STAT     0x10
00168 #define VG469_VSEL_EXT_BUS      0x20
00169 #define VG469_VSEL_MIXED        0x40
00170 #define VG469_VSEL_ISA          0x80
00171 
00172 /* Flags for VG468_CTL */
00173 #define VG468_CTL_SLOW          0x01    /* 600ns memory timing */
00174 #define VG468_CTL_ASYNC         0x02    /* Asynchronous bus clocking */
00175 #define VG468_CTL_TSSI          0x08    /* Tri-state some outputs */
00176 #define VG468_CTL_DELAY         0x10    /* Card detect debounce */
00177 #define VG468_CTL_INPACK        0x20    /* Obey INPACK signal? */
00178 #define VG468_CTL_POLARITY      0x40    /* VCCEN polarity */
00179 #define VG468_CTL_COMPAT        0x80    /* Compatibility stuff */
00180 
00181 #define VG469_CTL_WS_COMPAT     0x04    /* Wait state compatibility */
00182 #define VG469_CTL_STRETCH       0x10    /* LED stretch */
00183 
00184 /* Flags for VG468_TIMER */
00185 #define VG468_TIMER_ZEROPWR     0x10    /* Zero power control */
00186 #define VG468_TIMER_SIGEN       0x20    /* Power up */
00187 #define VG468_TIMER_STATUS      0x40    /* Activity timer status */
00188 #define VG468_TIMER_RES         0x80    /* Timer resolution */
00189 #define VG468_TIMER_MASK        0x0f    /* Activity timer timeout */
00190 
00191 /* Flags for VG468_MISC */
00192 #define VG468_MISC_GPIO         0x04    /* General-purpose IO */
00193 #define VG468_MISC_DMAWSB       0x08    /* DMA wait state control */
00194 #define VG469_MISC_LEDENA       0x10    /* LED enable */
00195 #define VG468_MISC_VADEMREV     0x40    /* Vadem revision control */
00196 #define VG468_MISC_UNLOCK       0x80    /* Unique register lock */
00197 
00198 /* Flags for VG469_EXT_MODE_A */
00199 #define VG469_MODE_VPPST        0x03    /* Vpp steering control */
00200 #define VG469_MODE_INT_SENSE    0x04    /* Internal voltage sense */
00201 #define VG469_MODE_CABLE        0x08
00202 #define VG469_MODE_COMPAT       0x10    /* i82365sl B or DF step */
00203 #define VG469_MODE_TEST         0x20
00204 #define VG469_MODE_RIO          0x40    /* Steer RIO to INTR? */
00205 
00206 /* Flags for VG469_EXT_MODE_B */
00207 #define VG469_MODE_B_3V         0x01    /* 3.3v for socket B */
00208 
00209 #endif /* _LINUX_VG468_H */
00210 
00211 
00212 //*****************************************************************************
00213 //*****************************************************************************
00214 //*****************************************************************************
00215 //*****************************************************************************
00216 //*****************************************************************************
00217 // Beginning ricoh.h (RICOH chipsets)
00218 
00219 #ifndef _LINUX_RICOH_H
00220 #define _LINUX_RICOH_H
00221 
00222 
00223 #define RF5C_MODE_CTL           0x1f    /* Mode control */
00224 #define RF5C_PWR_CTL            0x2f    /* Mixed voltage control */
00225 #define RF5C_CHIP_ID            0x3a    /* Chip identification */
00226 #define RF5C_MODE_CTL_3         0x3b    /* Mode control 3 */
00227 
00228 /* I/O window address offset */
00229 #define RF5C_IO_OFF(w)          (0x36+((w)<<1))
00230 
00231 /* Flags for RF5C_MODE_CTL */
00232 #define RF5C_MODE_ATA           0x01    /* ATA mode */
00233 #define RF5C_MODE_LED_ENA       0x02    /* IRQ 12 is LED */
00234 #define RF5C_MODE_CA21          0x04
00235 #define RF5C_MODE_CA22          0x08
00236 #define RF5C_MODE_CA23          0x10
00237 #define RF5C_MODE_CA24          0x20
00238 #define RF5C_MODE_CA25          0x40
00239 #define RF5C_MODE_3STATE_BIT7   0x80
00240 
00241 /* Flags for RF5C_PWR_CTL */
00242 #define RF5C_PWR_VCC_3V         0x01
00243 #define RF5C_PWR_IREQ_HIGH      0x02
00244 #define RF5C_PWR_INPACK_ENA     0x04
00245 #define RF5C_PWR_5V_DET         0x08
00246 #define RF5C_PWR_TC_SEL         0x10    /* Terminal Count: irq 11 or 15 */
00247 #define RF5C_PWR_DREQ_LOW       0x20
00248 #define RF5C_PWR_DREQ_OFF       0x00    /* DREQ steering control */
00249 #define RF5C_PWR_DREQ_INPACK    0x40
00250 #define RF5C_PWR_DREQ_SPKR      0x80
00251 #define RF5C_PWR_DREQ_IOIS16    0xc0
00252 
00253 /* Values for RF5C_CHIP_ID */
00254 #define RF5C_CHIP_RF5C296       0x32
00255 #define RF5C_CHIP_RF5C396       0xb2
00256 
00257 /* Flags for RF5C_MODE_CTL_3 */
00258 #define RF5C_MCTL3_DISABLE      0x01    /* Disable PCMCIA interface */
00259 #define RF5C_MCTL3_DMA_ENA      0x02
00260 
00261 /* Register definitions for Ricoh PCI-to-CardBus bridges */
00262 
00263 /* Extra bits in CB_BRIDGE_CONTROL */
00264 #define RL5C46X_BCR_3E0_ENA             0x0800
00265 #define RL5C46X_BCR_3E2_ENA             0x1000
00266 
00267 /* Bridge Configuration Register */
00268 #define RL5C4XX_CONFIG                  0x80    /* 16 bit */
00269 #define  RL5C4XX_CONFIG_IO_1_MODE       0x0200
00270 #define  RL5C4XX_CONFIG_IO_0_MODE       0x0100
00271 #define  RL5C4XX_CONFIG_PREFETCH        0x0001
00272 
00273 
00274 /* Misc Control Register */
00275 #define RL5C4XX_MISC                    0x0082  /* 16 bit */
00276 #define  RL5C4XX_MISC_HW_SUSPEND_ENA    0x0002
00277 #define  RL5C4XX_MISC_VCCEN_POL         0x0100
00278 #define  RL5C4XX_MISC_VPPEN_POL         0x0200
00279 #define  RL5C46X_MISC_SUSPEND           0x0001
00280 #define  RL5C46X_MISC_PWR_SAVE_2        0x0004
00281 #define  RL5C46X_MISC_IFACE_BUSY        0x0008
00282 #define  RL5C46X_MISC_B_LOCK            0x0010
00283 #define  RL5C46X_MISC_A_LOCK            0x0020
00284 #define  RL5C46X_MISC_PCI_LOCK          0x0040
00285 #define  RL5C47X_MISC_IFACE_BUSY        0x0004
00286 #define  RL5C47X_MISC_PCI_INT_MASK      0x0018
00287 #define  RL5C47X_MISC_PCI_INT_DIS       0x0020
00288 #define  RL5C47X_MISC_SUBSYS_WR         0x0040
00289 #define  RL5C47X_MISC_SRIRQ_ENA         0x0080
00290 #define  RL5C47X_MISC_5V_DISABLE        0x0400
00291 #define  RL5C47X_MISC_LED_POL           0x0800
00292 
00293 /* 16-bit Interface Control Register */
00294 #define RL5C4XX_16BIT_CTL               0x0084  /* 16 bit */
00295 #define  RL5C4XX_16CTL_IO_TIMING        0x0100
00296 #define  RL5C4XX_16CTL_MEM_TIMING       0x0200
00297 #define  RL5C46X_16CTL_LEVEL_1          0x0010
00298 #define  RL5C46X_16CTL_LEVEL_2          0x0020
00299 
00300 /* 16-bit IO and memory timing registers */
00301 #define RL5C4XX_16BIT_IO_0              0x0088  /* 16 bit */
00302 #define RL5C4XX_16BIT_MEM_0             0x0088  /* 16 bit */
00303 #define  RL5C4XX_SETUP_MASK             0x0007
00304 #define  RL5C4XX_SETUP_SHIFT            0
00305 #define  RL5C4XX_CMD_MASK               0x01f0
00306 #define  RL5C4XX_CMD_SHIFT              4
00307 #define  RL5C4XX_HOLD_MASK              0x1c00
00308 #define  RL5C4XX_HOLD_SHIFT             10
00309 #define  RL5C4XX_MISC_CONTROL           0x2F /* 8 bit */
00310 #define  RL5C4XX_ZV_ENABLE              0x08
00311 
00312 #endif /* _LINUX_RICOH_H */
00313 
00314 
00315 //*****************************************************************************
00316 //*****************************************************************************
00317 //*****************************************************************************
00318 //*****************************************************************************
00319 //*****************************************************************************
00320 // Beginning cirrus.h (CIRRUS chipsets)
00321 
00322 #ifndef _LINUX_CIRRUS_H
00323 #define _LINUX_CIRRUS_H
00324 
00325 #ifndef PCI_VENDOR_ID_CIRRUS
00326 #define PCI_VENDOR_ID_CIRRUS            0x1013
00327 #endif
00328 #ifndef PCI_DEVICE_ID_CIRRUS_6729
00329 #define PCI_DEVICE_ID_CIRRUS_6729       0x1100
00330 #endif
00331 #ifndef PCI_DEVICE_ID_CIRRUS_6832
00332 #define PCI_DEVICE_ID_CIRRUS_6832       0x1110
00333 #endif
00334 
00335 #define PD67_MISC_CTL_1         0x16    /* Misc control 1 */
00336 #define PD67_FIFO_CTL           0x17    /* FIFO control */
00337 #define PD67_MISC_CTL_2         0x1E    /* Misc control 2 */
00338 #define PD67_CHIP_INFO          0x1f    /* Chip information */
00339 #define PD67_ATA_CTL            0x026   /* 6730: ATA control */
00340 #define PD67_EXT_INDEX          0x2e    /* Extension index */
00341 #define PD67_EXT_DATA           0x2f    /* Extension data */
00342 
00343 /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
00344 #define PD67_DATA_MASK0         0x01    /* Data mask 0 */
00345 #define PD67_DATA_MASK1         0x02    /* Data mask 1 */
00346 #define PD67_DMA_CTL            0x03    /* DMA control */
00347 
00348 /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
00349 #define PD67_EXT_CTL_1          0x03    /* Extension control 1 */
00350 #define PD67_MEM_PAGE(n)        ((n)+5) /* PCI window bits 31:24 */
00351 #define PD67_EXTERN_DATA        0x0a
00352 #define PD67_MISC_CTL_3         0x25
00353 #define PD67_SMB_PWR_CTL        0x26
00354 
00355 /* I/O window address offset */
00356 #define PD67_IO_OFF(w)          (0x36+((w)<<1))
00357 
00358 /* Timing register sets */
00359 #define PD67_TIME_SETUP(n)      (0x3a + 3*(n))
00360 #define PD67_TIME_CMD(n)        (0x3b + 3*(n))
00361 #define PD67_TIME_RECOV(n)      (0x3c + 3*(n))
00362 
00363 /* Flags for PD67_MISC_CTL_1 */
00364 #define PD67_MC1_5V_DET         0x01    /* 5v detect */
00365 #define PD67_MC1_MEDIA_ENA      0x01    /* 6730: Multimedia enable */
00366 #define PD67_MC1_VCC_3V         0x02    /* 3.3v Vcc */
00367 #define PD67_MC1_PULSE_MGMT     0x04
00368 #define PD67_MC1_PULSE_IRQ      0x08
00369 #define PD67_MC1_SPKR_ENA       0x10
00370 #define PD67_MC1_INPACK_ENA     0x80
00371 
00372 /* Flags for PD67_FIFO_CTL */
00373 #define PD67_FIFO_EMPTY         0x80
00374 
00375 /* Flags for PD67_MISC_CTL_2 */
00376 #define PD67_MC2_FREQ_BYPASS    0x01
00377 #define PD67_MC2_DYNAMIC_MODE   0x02
00378 #define PD67_MC2_SUSPEND        0x04
00379 #define PD67_MC2_5V_CORE        0x08
00380 #define PD67_MC2_LED_ENA        0x10    /* IRQ 12 is LED enable */
00381 #define PD67_MC2_FAST_PCI       0x10    /* 6729: PCI bus > 25 MHz */
00382 #define PD67_MC2_3STATE_BIT7    0x20    /* Floppy change bit */
00383 #define PD67_MC2_DMA_MODE       0x40
00384 #define PD67_MC2_IRQ15_RI       0x80    /* IRQ 15 is ring enable */
00385 
00386 /* Flags for PD67_CHIP_INFO */
00387 #define PD67_INFO_SLOTS         0x20    /* 0 = 1 slot, 1 = 2 slots */
00388 #define PD67_INFO_CHIP_ID       0xc0
00389 #define PD67_INFO_REV           0x1c
00390 
00391 /* Fields in PD67_TIME_* registers */
00392 #define PD67_TIME_SCALE         0xc0
00393 #define PD67_TIME_SCALE_1       0x00
00394 #define PD67_TIME_SCALE_16      0x40
00395 #define PD67_TIME_SCALE_256     0x80
00396 #define PD67_TIME_SCALE_4096    0xc0
00397 #define PD67_TIME_MULT          0x3f
00398 
00399 /* Fields in PD67_DMA_CTL */
00400 #define PD67_DMA_MODE           0xc0
00401 #define PD67_DMA_OFF            0x00
00402 #define PD67_DMA_DREQ_INPACK    0x40
00403 #define PD67_DMA_DREQ_WP        0x80
00404 #define PD67_DMA_DREQ_BVD2      0xc0
00405 #define PD67_DMA_PULLUP         0x20    /* Disable socket pullups? */
00406 
00407 /* Fields in PD67_EXT_CTL_1 */
00408 #define PD67_EC1_VCC_PWR_LOCK   0x01
00409 #define PD67_EC1_AUTO_PWR_CLEAR 0x02
00410 #define PD67_EC1_LED_ENA        0x04
00411 #define PD67_EC1_INV_CARD_IRQ   0x08
00412 #define PD67_EC1_INV_MGMT_IRQ   0x10
00413 #define PD67_EC1_PULLUP_CTL     0x20
00414 
00415 /* Fields in PD67_MISC_CTL_3 */
00416 #define PD67_MC3_IRQ_MASK       0x03
00417 #define PD67_MC3_IRQ_PCPCI      0x00
00418 #define PD67_MC3_IRQ_EXTERN     0x01
00419 #define PD67_MC3_IRQ_PCIWAY     0x02
00420 #define PD67_MC3_IRQ_PCI        0x03
00421 #define PD67_MC3_PWR_MASK       0x0c
00422 #define PD67_MC3_PWR_SERIAL     0x00
00423 #define PD67_MC3_PWR_TI2202     0x08
00424 #define PD67_MC3_PWR_SMB        0x0c
00425 
00426 /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
00427 
00428 /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
00429 #define PD68_EXT_CTL_2                  0x0b
00430 #define PD68_PCI_SPACE                  0x22
00431 #define PD68_PCCARD_SPACE               0x23
00432 #define PD68_WINDOW_TYPE                0x24
00433 #define PD68_EXT_CSC                    0x2e
00434 #define PD68_MISC_CTL_4                 0x2f
00435 #define PD68_MISC_CTL_5                 0x30
00436 #define PD68_MISC_CTL_6                 0x31
00437 
00438 /* Extra flags in PD67_MISC_CTL_3 */
00439 #define PD68_MC3_HW_SUSP                0x10
00440 #define PD68_MC3_MM_EXPAND              0x40
00441 #define PD68_MC3_MM_ARM                 0x80
00442 
00443 /* Bridge Control Register */
00444 #define  PD6832_BCR_MGMT_IRQ_ENA        0x0800
00445 
00446 /* Socket Number Register */
00447 #define PD6832_SOCKET_NUMBER            0x004c  /* 8 bit */
00448 
00449 #endif /* _LINUX_CIRRUS_H */
00450 
00451 
00452