iPXE
igbvf_defines.h
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00001 /*******************************************************************************
00002 
00003   Intel(R) 82576 Virtual Function Linux driver
00004   Copyright(c) 1999 - 2008 Intel Corporation.
00005 
00006   This program is free software; you can redistribute it and/or modify it
00007   under the terms and conditions of the GNU General Public License,
00008   version 2, as published by the Free Software Foundation.
00009 
00010   This program is distributed in the hope it will be useful, but WITHOUT
00011   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
00012   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
00013   more details.
00014 
00015   You should have received a copy of the GNU General Public License along with
00016   this program; if not, write to the Free Software Foundation, Inc.,
00017   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
00018 
00019   The full GNU General Public License is included in this distribution in
00020   the file called "COPYING".
00021 
00022   Contact Information:
00023   Linux NICS <linux.nics@intel.com>
00024   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
00025   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
00026 
00027 *******************************************************************************/
00028 
00029 FILE_LICENCE ( GPL2_ONLY );
00030 
00031 #ifndef _IGBVF_DEFINES_H_
00032 #define _IGBVF_DEFINES_H_
00033 
00034 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
00035 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
00036 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
00037 
00038 /* Definitions for power management and wakeup registers */
00039 /* Wake Up Control */
00040 #define E1000_WUC_APME       0x00000001 /* APM Enable */
00041 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
00042 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
00043 #define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
00044 #define E1000_WUC_LSCWE      0x00000010 /* Link Status wake up enable */
00045 #define E1000_WUC_LSCWO      0x00000020 /* Link Status wake up override */
00046 #define E1000_WUC_SPM        0x80000000 /* Enable SPM */
00047 #define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
00048 
00049 /* Wake Up Filter Control */
00050 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
00051 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
00052 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
00053 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
00054 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
00055 #define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
00056 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
00057 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
00058 #define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
00059 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
00060 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
00061 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
00062 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
00063 #define E1000_WUFC_ALL_FILTERS  0x000F00FF /* Mask for all wakeup filters */
00064 #define E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
00065 #define E1000_WUFC_FLX_FILTERS  0x000F0000 /*Mask for the 4 flexible filters */
00066 
00067 /* Wake Up Status */
00068 #define E1000_WUS_LNKC         E1000_WUFC_LNKC
00069 #define E1000_WUS_MAG          E1000_WUFC_MAG
00070 #define E1000_WUS_EX           E1000_WUFC_EX
00071 #define E1000_WUS_MC           E1000_WUFC_MC
00072 #define E1000_WUS_BC           E1000_WUFC_BC
00073 #define E1000_WUS_ARP          E1000_WUFC_ARP
00074 #define E1000_WUS_IPV4         E1000_WUFC_IPV4
00075 #define E1000_WUS_IPV6         E1000_WUFC_IPV6
00076 #define E1000_WUS_FLX0         E1000_WUFC_FLX0
00077 #define E1000_WUS_FLX1         E1000_WUFC_FLX1
00078 #define E1000_WUS_FLX2         E1000_WUFC_FLX2
00079 #define E1000_WUS_FLX3         E1000_WUFC_FLX3
00080 #define E1000_WUS_FLX_FILTERS  E1000_WUFC_FLX_FILTERS
00081 
00082 /* Wake Up Packet Length */
00083 #define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
00084 
00085 /* Four Flexible Filters are supported */
00086 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
00087 
00088 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
00089 #define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
00090 
00091 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
00092 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
00093 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
00094 
00095 /* Extended Device Control */
00096 #define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
00097 #define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
00098 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
00099 #define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
00100 #define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
00101 /* Reserved (bits 4,5) in >= 82575 */
00102 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
00103 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
00104 #define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
00105 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
00106 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
00107 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
00108 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
00109 #define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
00110 #define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
00111 #define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* Direction of SDP3 0=in 1=out */
00112 #define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
00113 #define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
00114 #define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
00115 #define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
00116 #define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
00117 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
00118 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
00119 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
00120 #define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
00121 #define E1000_CTRL_EXT_LINK_MODE_KMRN    0x00000000
00122 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
00123 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES  0x00800000
00124 #define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
00125 #define E1000_CTRL_EXT_EIAME          0x01000000
00126 #define E1000_CTRL_EXT_IRCA           0x00000001
00127 #define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
00128 #define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
00129 #define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
00130 #define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
00131 #define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
00132 #define E1000_CTRL_EXT_CANC           0x04000000 /* Int delay cancellation */
00133 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
00134 /* IAME enable bit (27) was removed in >= 82575 */
00135 #define E1000_CTRL_EXT_IAME          0x08000000 /* Int acknowledge Auto-mask */
00136 #define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error
00137                                                   * detection enabled */
00138 #define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity
00139                                                   * error detection enable */
00140 #define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
00141 #define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
00142 #define E1000_I2CCMD_REG_ADDR_SHIFT   16
00143 #define E1000_I2CCMD_REG_ADDR         0x00FF0000
00144 #define E1000_I2CCMD_PHY_ADDR_SHIFT   24
00145 #define E1000_I2CCMD_PHY_ADDR         0x07000000
00146 #define E1000_I2CCMD_OPCODE_READ      0x08000000
00147 #define E1000_I2CCMD_OPCODE_WRITE     0x00000000
00148 #define E1000_I2CCMD_RESET            0x10000000
00149 #define E1000_I2CCMD_READY            0x20000000
00150 #define E1000_I2CCMD_INTERRUPT_ENA    0x40000000
00151 #define E1000_I2CCMD_ERROR            0x80000000
00152 #define E1000_MAX_SGMII_PHY_REG_ADDR  255
00153 #define E1000_I2CCMD_PHY_TIMEOUT      200
00154 
00155 /* Receive Descriptor bit definitions */
00156 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
00157 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
00158 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
00159 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
00160 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
00161 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
00162 #define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
00163 #define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
00164 #define E1000_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
00165 #define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
00166 #define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
00167 #define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
00168 #define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
00169 #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
00170 #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
00171 #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
00172 #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
00173 #define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
00174 #define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
00175 #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
00176 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
00177 #define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
00178 #define E1000_RXD_SPC_PRI_SHIFT 13
00179 #define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
00180 #define E1000_RXD_SPC_CFI_SHIFT 12
00181 
00182 #define E1000_RXDEXT_STATERR_CE    0x01000000
00183 #define E1000_RXDEXT_STATERR_SE    0x02000000
00184 #define E1000_RXDEXT_STATERR_SEQ   0x04000000
00185 #define E1000_RXDEXT_STATERR_CXE   0x10000000
00186 #define E1000_RXDEXT_STATERR_TCPE  0x20000000
00187 #define E1000_RXDEXT_STATERR_IPE   0x40000000
00188 #define E1000_RXDEXT_STATERR_RXE   0x80000000
00189 
00190 /* mask to determine if packets should be dropped due to frame errors */
00191 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
00192     E1000_RXD_ERR_CE  |                \
00193     E1000_RXD_ERR_SE  |                \
00194     E1000_RXD_ERR_SEQ |                \
00195     E1000_RXD_ERR_CXE |                \
00196     E1000_RXD_ERR_RXE)
00197 
00198 /* Same mask, but for extended and packet split descriptors */
00199 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
00200     E1000_RXDEXT_STATERR_CE  |            \
00201     E1000_RXDEXT_STATERR_SE  |            \
00202     E1000_RXDEXT_STATERR_SEQ |            \
00203     E1000_RXDEXT_STATERR_CXE |            \
00204     E1000_RXDEXT_STATERR_RXE)
00205 
00206 #define E1000_MRQC_ENABLE_MASK                 0x00000007
00207 #define E1000_MRQC_ENABLE_RSS_2Q               0x00000001
00208 #define E1000_MRQC_ENABLE_RSS_INT              0x00000004
00209 #define E1000_MRQC_RSS_FIELD_MASK              0xFFFF0000
00210 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
00211 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
00212 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
00213 #define E1000_MRQC_RSS_FIELD_IPV6_EX           0x00080000
00214 #define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
00215 #define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
00216 
00217 #define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
00218 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK        0x000003FF
00219 
00220 /* Management Control */
00221 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
00222 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
00223 #define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
00224 #define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
00225 #define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
00226 #define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
00227 #define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
00228 #define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
00229 #define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
00230 /* Enable Neighbor Discovery Filtering */
00231 #define E1000_MANC_NEIGHBOR_EN   0x00004000
00232 #define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
00233 #define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
00234 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
00235 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
00236 #define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
00237 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
00238 /* Enable MAC address filtering */
00239 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
00240 /* Enable MNG packets to host memory */
00241 #define E1000_MANC_EN_MNG2HOST   0x00200000
00242 /* Enable IP address filtering */
00243 #define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000
00244 #define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
00245 #define E1000_MANC_BR_EN            0x01000000 /* Enable broadcast filtering */
00246 #define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
00247 #define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
00248 #define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
00249 #define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
00250 #define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
00251 #define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
00252 
00253 #define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
00254 #define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
00255 
00256 /* Receive Control */
00257 #define E1000_RCTL_RST            0x00000001    /* Software reset */
00258 #define E1000_RCTL_EN             0x00000002    /* enable */
00259 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
00260 #define E1000_RCTL_UPE            0x00000008    /* unicast promisc enable */
00261 #define E1000_RCTL_MPE            0x00000010    /* multicast promisc enable */
00262 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
00263 #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
00264 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
00265 #define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
00266 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
00267 #define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
00268 #define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
00269 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min thresh size */
00270 #define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min thresh size */
00271 #define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min thresh size */
00272 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
00273 #define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
00274 #define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
00275 #define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
00276 #define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
00277 #define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
00278 #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
00279 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
00280 #define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
00281 #define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
00282 #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
00283 #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
00284 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
00285 #define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
00286 #define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
00287 #define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
00288 #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
00289 #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
00290 #define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
00291 #define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
00292 #define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
00293 #define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
00294 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
00295 #define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
00296 #define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
00297 
00298 /*
00299  * Use byte values for the following shift parameters
00300  * Usage:
00301  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
00302  *                  E1000_PSRCTL_BSIZE0_MASK) |
00303  *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
00304  *                  E1000_PSRCTL_BSIZE1_MASK) |
00305  *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
00306  *                  E1000_PSRCTL_BSIZE2_MASK) |
00307  *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
00308  *                  E1000_PSRCTL_BSIZE3_MASK))
00309  * where value0 = [128..16256],  default=256
00310  *       value1 = [1024..64512], default=4096
00311  *       value2 = [0..64512],    default=4096
00312  *       value3 = [0..64512],    default=0
00313  */
00314 
00315 #define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
00316 #define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
00317 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
00318 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
00319 
00320 #define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
00321 #define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
00322 #define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
00323 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
00324 
00325 /* SWFW_SYNC Definitions */
00326 #define E1000_SWFW_EEP_SM   0x01
00327 #define E1000_SWFW_PHY0_SM  0x02
00328 #define E1000_SWFW_PHY1_SM  0x04
00329 #define E1000_SWFW_CSR_SM   0x08
00330 
00331 /* FACTPS Definitions */
00332 #define E1000_FACTPS_LFS    0x40000000  /* LAN Function Select */
00333 /* Device Control */
00334 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
00335 #define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
00336 #define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
00337 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
00338 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
00339 #define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
00340 #define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
00341 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
00342 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
00343 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
00344 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
00345 #define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
00346 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
00347 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
00348 #define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
00349 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
00350 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
00351 #define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
00352 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
00353                                              * indication in SDP[0] */
00354 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
00355                                                * PHYRST_N pin */
00356 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
00357                                            * LINK_0 and LINK_1 pins */
00358 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
00359 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
00360 #define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
00361 #define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
00362 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
00363 #define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
00364 #define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
00365 #define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
00366 #define E1000_CTRL_RST      0x04000000  /* Global reset */
00367 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
00368 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
00369 #define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
00370 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
00371 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
00372 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
00373 #define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
00374 
00375 /*
00376  * Bit definitions for the Management Data IO (MDIO) and Management Data
00377  * Clock (MDC) pins in the Device Control Register.
00378  */
00379 #define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
00380 #define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
00381 #define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
00382 #define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
00383 #define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
00384 #define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
00385 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
00386 #define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
00387 
00388 #define E1000_CONNSW_ENRGSRC             0x4
00389 #define E1000_PCS_CFG_PCS_EN             8
00390 #define E1000_PCS_LCTL_FLV_LINK_UP       1
00391 #define E1000_PCS_LCTL_FSV_10            0
00392 #define E1000_PCS_LCTL_FSV_100           2
00393 #define E1000_PCS_LCTL_FSV_1000          4
00394 #define E1000_PCS_LCTL_FDV_FULL          8
00395 #define E1000_PCS_LCTL_FSD               0x10
00396 #define E1000_PCS_LCTL_FORCE_LINK        0x20
00397 #define E1000_PCS_LCTL_LOW_LINK_LATCH    0x40
00398 #define E1000_PCS_LCTL_FORCE_FCTRL       0x80
00399 #define E1000_PCS_LCTL_AN_ENABLE         0x10000
00400 #define E1000_PCS_LCTL_AN_RESTART        0x20000
00401 #define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
00402 #define E1000_PCS_LCTL_AN_SGMII_BYPASS   0x80000
00403 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER  0x100000
00404 #define E1000_PCS_LCTL_FAST_LINK_TIMER   0x1000000
00405 #define E1000_PCS_LCTL_LINK_OK_FIX       0x2000000
00406 #define E1000_PCS_LCTL_CRS_ON_NI         0x4000000
00407 #define E1000_ENABLE_SERDES_LOOPBACK     0x0410
00408 
00409 #define E1000_PCS_LSTS_LINK_OK           1
00410 #define E1000_PCS_LSTS_SPEED_10          0
00411 #define E1000_PCS_LSTS_SPEED_100         2
00412 #define E1000_PCS_LSTS_SPEED_1000        4
00413 #define E1000_PCS_LSTS_DUPLEX_FULL       8
00414 #define E1000_PCS_LSTS_SYNK_OK           0x10
00415 #define E1000_PCS_LSTS_AN_COMPLETE       0x10000
00416 #define E1000_PCS_LSTS_AN_PAGE_RX        0x20000
00417 #define E1000_PCS_LSTS_AN_TIMED_OUT      0x40000
00418 #define E1000_PCS_LSTS_AN_REMOTE_FAULT   0x80000
00419 #define E1000_PCS_LSTS_AN_ERROR_RWS      0x100000
00420 
00421 /* Device Status */
00422 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
00423 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
00424 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
00425 #define E1000_STATUS_FUNC_SHIFT 2
00426 #define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
00427 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
00428 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
00429 #define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
00430 #define E1000_STATUS_SPEED_MASK 0x000000C0
00431 #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
00432 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
00433 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
00434 #define E1000_STATUS_LAN_INIT_DONE 0x00000200  /* Lan Init Completion by NVM */
00435 #define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
00436 #define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
00437 #define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state.
00438                                                  * Clear on write '0'. */
00439 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
00440 #define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
00441 #define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
00442 #define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
00443 #define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
00444 #define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
00445 #define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
00446 #define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
00447 #define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
00448 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
00449 #define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution
00450                                             * disabled */
00451 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
00452 #define E1000_STATUS_FUSE_8       0x04000000
00453 #define E1000_STATUS_FUSE_9       0x08000000
00454 #define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
00455 #define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
00456 
00457 /* Constants used to interpret the masked PCI-X bus speed. */
00458 #define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed 50-66 MHz */
00459 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
00460 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
00461 
00462 #define SPEED_10    10
00463 #define SPEED_100   100
00464 #define SPEED_1000  1000
00465 #define HALF_DUPLEX 1
00466 #define FULL_DUPLEX 2
00467 
00468 #define PHY_FORCE_TIME   20
00469 
00470 #define ADVERTISE_10_HALF                 0x0001
00471 #define ADVERTISE_10_FULL                 0x0002
00472 #define ADVERTISE_100_HALF                0x0004
00473 #define ADVERTISE_100_FULL                0x0008
00474 #define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
00475 #define ADVERTISE_1000_FULL               0x0020
00476 
00477 /* 1000/H is not supported, nor spec-compliant. */
00478 #define E1000_ALL_SPEED_DUPLEX  (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
00479                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
00480                                                      ADVERTISE_1000_FULL)
00481 #define E1000_ALL_NOT_GIG       (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
00482                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
00483 #define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
00484 #define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)
00485 #define E1000_ALL_FULL_DUPLEX   (ADVERTISE_10_FULL |  ADVERTISE_100_FULL | \
00486                                                      ADVERTISE_1000_FULL)
00487 #define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)
00488 
00489 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
00490 
00491 /* LED Control */
00492 #define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
00493 #define E1000_LEDCTL_LED0_MODE_SHIFT      0
00494 #define E1000_LEDCTL_LED0_BLINK_RATE      0x00000020
00495 #define E1000_LEDCTL_LED0_IVRT            0x00000040
00496 #define E1000_LEDCTL_LED0_BLINK           0x00000080
00497 #define E1000_LEDCTL_LED1_MODE_MASK       0x00000F00
00498 #define E1000_LEDCTL_LED1_MODE_SHIFT      8
00499 #define E1000_LEDCTL_LED1_BLINK_RATE      0x00002000
00500 #define E1000_LEDCTL_LED1_IVRT            0x00004000
00501 #define E1000_LEDCTL_LED1_BLINK           0x00008000
00502 #define E1000_LEDCTL_LED2_MODE_MASK       0x000F0000
00503 #define E1000_LEDCTL_LED2_MODE_SHIFT      16
00504 #define E1000_LEDCTL_LED2_BLINK_RATE      0x00200000
00505 #define E1000_LEDCTL_LED2_IVRT            0x00400000
00506 #define E1000_LEDCTL_LED2_BLINK           0x00800000
00507 #define E1000_LEDCTL_LED3_MODE_MASK       0x0F000000
00508 #define E1000_LEDCTL_LED3_MODE_SHIFT      24
00509 #define E1000_LEDCTL_LED3_BLINK_RATE      0x20000000
00510 #define E1000_LEDCTL_LED3_IVRT            0x40000000
00511 #define E1000_LEDCTL_LED3_BLINK           0x80000000
00512 
00513 #define E1000_LEDCTL_MODE_LINK_10_1000  0x0
00514 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
00515 #define E1000_LEDCTL_MODE_LINK_UP       0x2
00516 #define E1000_LEDCTL_MODE_ACTIVITY      0x3
00517 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
00518 #define E1000_LEDCTL_MODE_LINK_10       0x5
00519 #define E1000_LEDCTL_MODE_LINK_100      0x6
00520 #define E1000_LEDCTL_MODE_LINK_1000     0x7
00521 #define E1000_LEDCTL_MODE_PCIX_MODE     0x8
00522 #define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
00523 #define E1000_LEDCTL_MODE_COLLISION     0xA
00524 #define E1000_LEDCTL_MODE_BUS_SPEED     0xB
00525 #define E1000_LEDCTL_MODE_BUS_SIZE      0xC
00526 #define E1000_LEDCTL_MODE_PAUSED        0xD
00527 #define E1000_LEDCTL_MODE_LED_ON        0xE
00528 #define E1000_LEDCTL_MODE_LED_OFF       0xF
00529 
00530 /* Transmit Descriptor bit definitions */
00531 #define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
00532 #define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
00533 #define E1000_TXD_POPTS_SHIFT 8         /* POPTS shift */
00534 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
00535 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
00536 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
00537 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
00538 #define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
00539 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
00540 #define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
00541 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
00542 #define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
00543 #define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
00544 #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
00545 #define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
00546 #define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
00547 #define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
00548 #define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
00549 #define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
00550 #define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
00551 #define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
00552 /* Extended desc bits for Linksec and timesync */
00553 
00554 /* Transmit Control */
00555 #define E1000_TCTL_RST    0x00000001    /* software reset */
00556 #define E1000_TCTL_EN     0x00000002    /* enable tx */
00557 #define E1000_TCTL_BCE    0x00000004    /* busy check enable */
00558 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
00559 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
00560 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
00561 #define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
00562 #define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
00563 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
00564 #define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
00565 #define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
00566 
00567 /* Transmit Arbitration Count */
00568 #define E1000_TARC0_ENABLE     0x00000400   /* Enable Tx Queue 0 */
00569 
00570 /* SerDes Control */
00571 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
00572 
00573 /* Receive Checksum Control */
00574 #define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
00575 #define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
00576 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
00577 #define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
00578 #define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */
00579 #define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
00580 #define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
00581 
00582 /* Header split receive */
00583 #define E1000_RFCTL_ISCSI_DIS           0x00000001
00584 #define E1000_RFCTL_ISCSI_DWC_MASK      0x0000003E
00585 #define E1000_RFCTL_ISCSI_DWC_SHIFT     1
00586 #define E1000_RFCTL_NFSW_DIS            0x00000040
00587 #define E1000_RFCTL_NFSR_DIS            0x00000080
00588 #define E1000_RFCTL_NFS_VER_MASK        0x00000300
00589 #define E1000_RFCTL_NFS_VER_SHIFT       8
00590 #define E1000_RFCTL_IPV6_DIS            0x00000400
00591 #define E1000_RFCTL_IPV6_XSUM_DIS       0x00000800
00592 #define E1000_RFCTL_ACK_DIS             0x00001000
00593 #define E1000_RFCTL_ACKD_DIS            0x00002000
00594 #define E1000_RFCTL_IPFRSP_DIS          0x00004000
00595 #define E1000_RFCTL_EXTEN               0x00008000
00596 #define E1000_RFCTL_IPV6_EX_DIS         0x00010000
00597 #define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
00598 #define E1000_RFCTL_LEF                 0x00040000
00599 
00600 /* Collision related configuration parameters */
00601 #define E1000_COLLISION_THRESHOLD       15
00602 #define E1000_CT_SHIFT                  4
00603 #define E1000_COLLISION_DISTANCE        63
00604 #define E1000_COLD_SHIFT                12
00605 
00606 /* Default values for the transmit IPG register */
00607 #define DEFAULT_82543_TIPG_IPGT_FIBER  9
00608 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
00609 
00610 #define E1000_TIPG_IPGT_MASK  0x000003FF
00611 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
00612 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
00613 
00614 #define DEFAULT_82543_TIPG_IPGR1 8
00615 #define E1000_TIPG_IPGR1_SHIFT  10
00616 
00617 #define DEFAULT_82543_TIPG_IPGR2 6
00618 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
00619 #define E1000_TIPG_IPGR2_SHIFT  20
00620 
00621 /* Ethertype field values */
00622 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
00623 
00624 #define ETHERNET_FCS_SIZE       4
00625 #define MAX_JUMBO_FRAME_SIZE    0x3F00
00626 
00627 /* Extended Configuration Control and Size */
00628 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
00629 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
00630 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
00631 #define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
00632 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
00633 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
00634 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
00635 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
00636 
00637 #define E1000_PHY_CTRL_SPD_EN             0x00000001
00638 #define E1000_PHY_CTRL_D0A_LPLU           0x00000002
00639 #define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
00640 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
00641 #define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
00642 
00643 #define E1000_KABGTXD_BGSQLBIAS           0x00050000
00644 
00645 /* PBA constants */
00646 #define E1000_PBA_6K  0x0006    /* 6KB */
00647 #define E1000_PBA_8K  0x0008    /* 8KB */
00648 #define E1000_PBA_10K 0x000A    /* 10KB */
00649 #define E1000_PBA_12K 0x000C    /* 12KB */
00650 #define E1000_PBA_14K 0x000E    /* 14KB */
00651 #define E1000_PBA_16K 0x0010    /* 16KB */
00652 #define E1000_PBA_18K 0x0012
00653 #define E1000_PBA_20K 0x0014
00654 #define E1000_PBA_22K 0x0016
00655 #define E1000_PBA_24K 0x0018
00656 #define E1000_PBA_26K 0x001A
00657 #define E1000_PBA_30K 0x001E
00658 #define E1000_PBA_32K 0x0020
00659 #define E1000_PBA_34K 0x0022
00660 #define E1000_PBA_35K 0x0023
00661 #define E1000_PBA_38K 0x0026
00662 #define E1000_PBA_40K 0x0028
00663 #define E1000_PBA_48K 0x0030    /* 48KB */
00664 #define E1000_PBA_64K 0x0040    /* 64KB */
00665 
00666 #define E1000_PBS_16K E1000_PBA_16K
00667 #define E1000_PBS_24K E1000_PBA_24K
00668 
00669 #define IFS_MAX       80
00670 #define IFS_MIN       40
00671 #define IFS_RATIO     4
00672 #define IFS_STEP      10
00673 #define MIN_NUM_XMITS 1000
00674 
00675 /* SW Semaphore Register */
00676 #define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
00677 #define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
00678 #define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
00679 #define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
00680 
00681 #define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */
00682 
00683 /* Interrupt Cause Read */
00684 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
00685 #define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
00686 #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
00687 #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
00688 #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
00689 #define E1000_ICR_RXO           0x00000040 /* rx overrun */
00690 #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
00691 #define E1000_ICR_VMMB          0x00000100 /* VM MB event */
00692 #define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
00693 #define E1000_ICR_RXCFG         0x00000400 /* Rx /c/ ordered set */
00694 #define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
00695 #define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
00696 #define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
00697 #define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
00698 #define E1000_ICR_TXD_LOW       0x00008000
00699 #define E1000_ICR_SRPD          0x00010000
00700 #define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
00701 #define E1000_ICR_MNG           0x00040000 /* Manageability event */
00702 #define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
00703 #define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver
00704                                             * should claim the interrupt */
00705 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
00706 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
00707 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
00708 #define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
00709 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
00710 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
00711 #define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
00712 #define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW
00713                                             * bit in the FWSM */
00714 #define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates
00715                                             * an interrupt */
00716 #define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
00717 #define E1000_ICR_EPRST         0x00100000 /* ME hardware reset occurs */
00718 
00719 
00720 /*
00721  * This defines the bits that are set in the Interrupt Mask
00722  * Set/Read Register.  Each bit is documented below:
00723  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
00724  *   o RXSEQ  = Receive Sequence Error
00725  */
00726 #define POLL_IMS_ENABLE_MASK ( \
00727     E1000_IMS_RXDMT0 |    \
00728     E1000_IMS_RXSEQ)
00729 
00730 /*
00731  * This defines the bits that are set in the Interrupt Mask
00732  * Set/Read Register.  Each bit is documented below:
00733  *   o RXT0   = Receiver Timer Interrupt (ring 0)
00734  *   o TXDW   = Transmit Descriptor Written Back
00735  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
00736  *   o RXSEQ  = Receive Sequence Error
00737  *   o LSC    = Link Status Change
00738  */
00739 #define IMS_ENABLE_MASK ( \
00740     E1000_IMS_RXT0   |    \
00741     E1000_IMS_TXDW   |    \
00742     E1000_IMS_RXDMT0 |    \
00743     E1000_IMS_RXSEQ  |    \
00744     E1000_IMS_LSC)
00745 
00746 /* Interrupt Mask Set */
00747 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
00748 #define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
00749 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
00750 #define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
00751 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
00752 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
00753 #define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
00754 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
00755 #define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
00756 #define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
00757 #define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
00758 #define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
00759 #define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
00760 #define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
00761 #define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
00762 #define E1000_IMS_SRPD      E1000_ICR_SRPD
00763 #define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
00764 #define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
00765 #define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
00766 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
00767                                                          * parity error */
00768 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
00769                                                          * parity error */
00770 #define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
00771                                                          * parity error */
00772 #define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
00773                                                          * error */
00774 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
00775                                                          * parity error */
00776 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
00777                                                          * parity error */
00778 #define E1000_IMS_DSW       E1000_ICR_DSW
00779 #define E1000_IMS_PHYINT    E1000_ICR_PHYINT
00780 #define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
00781 #define E1000_IMS_EPRST     E1000_ICR_EPRST
00782 
00783 /* Interrupt Cause Set */
00784 #define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
00785 #define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
00786 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
00787 #define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
00788 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
00789 #define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
00790 #define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
00791 #define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
00792 #define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
00793 #define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
00794 #define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
00795 #define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
00796 #define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
00797 #define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
00798 #define E1000_ICS_SRPD      E1000_ICR_SRPD
00799 #define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
00800 #define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
00801 #define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
00802 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
00803                                                          * parity error */
00804 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
00805                                                          * parity error */
00806 #define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
00807                                                          * parity error */
00808 #define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
00809                                                          * error */
00810 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
00811                                                          * parity error */
00812 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
00813                                                          * parity error */
00814 #define E1000_ICS_DSW       E1000_ICR_DSW
00815 #define E1000_ICS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
00816 #define E1000_ICS_PHYINT    E1000_ICR_PHYINT
00817 #define E1000_ICS_EPRST     E1000_ICR_EPRST
00818 
00819 /* Transmit Descriptor Control */
00820 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
00821 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
00822 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
00823 #define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
00824 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
00825 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
00826 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
00827 /* Enable the counting of descriptors still to be processed. */
00828 #define E1000_TXDCTL_COUNT_DESC 0x00400000
00829 
00830 /* Flow Control Constants */
00831 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
00832 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
00833 #define FLOW_CONTROL_TYPE         0x8808
00834 
00835 /* 802.1q VLAN Packet Size */
00836 #define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
00837 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
00838 
00839 /* Receive Address */
00840 /*
00841  * Number of high/low register pairs in the RAR. The RAR (Receive Address
00842  * Registers) holds the directed and multicast addresses that we monitor.
00843  * Technically, we have 16 spots.  However, we reserve one of these spots
00844  * (RAR[15]) for our directed address used by controllers with
00845  * manageability enabled, allowing us room for 15 multicast addresses.
00846  */
00847 #define E1000_RAR_ENTRIES     15
00848 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
00849 #define E1000_RAL_MAC_ADDR_LEN 4
00850 #define E1000_RAH_MAC_ADDR_LEN 2
00851 #define E1000_RAH_POOL_MASK 0x03FC0000
00852 #define E1000_RAH_POOL_1 0x00040000
00853 
00854 /* Error Codes */
00855 #define E1000_SUCCESS      0
00856 #define E1000_ERR_NVM      1
00857 #define E1000_ERR_PHY      2
00858 #define E1000_ERR_CONFIG   3
00859 #define E1000_ERR_PARAM    4
00860 #define E1000_ERR_MAC_INIT 5
00861 #define E1000_ERR_PHY_TYPE 6
00862 #define E1000_ERR_RESET   9
00863 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
00864 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
00865 #define E1000_BLK_PHY_RESET   12
00866 #define E1000_ERR_SWFW_SYNC 13
00867 #define E1000_NOT_IMPLEMENTED 14
00868 #define E1000_ERR_MBX      15
00869 
00870 /* Loop limit on how long we wait for auto-negotiation to complete */
00871 #define FIBER_LINK_UP_LIMIT               50
00872 #define COPPER_LINK_UP_LIMIT              10
00873 #define PHY_AUTO_NEG_LIMIT                45
00874 #define PHY_FORCE_LIMIT                   20
00875 /* Number of 100 microseconds we wait for PCI Express master disable */
00876 #define MASTER_DISABLE_TIMEOUT      800
00877 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
00878 #define PHY_CFG_TIMEOUT             100
00879 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
00880 #define MDIO_OWNERSHIP_TIMEOUT      10
00881 /* Number of milliseconds for NVM auto read done after MAC reset. */
00882 #define AUTO_READ_DONE_TIMEOUT      10
00883 
00884 /* Flow Control */
00885 #define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
00886 #define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
00887 #define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
00888 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
00889 
00890 /* Transmit Configuration Word */
00891 #define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
00892 #define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
00893 #define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
00894 #define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
00895 #define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
00896 #define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
00897 #define E1000_TXCW_NP         0x00008000        /* TXCW next page */
00898 #define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
00899 #define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
00900 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
00901 
00902 /* Receive Configuration Word */
00903 #define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
00904 #define E1000_RXCW_NC         0x04000000        /* Receive config no carrier */
00905 #define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
00906 #define E1000_RXCW_CC         0x10000000        /* Receive config change */
00907 #define E1000_RXCW_C          0x20000000        /* Receive config */
00908 #define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
00909 #define E1000_RXCW_ANC        0x80000000        /* Auto-neg complete */
00910 
00911 
00912 /* PCI Express Control */
00913 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
00914 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
00915 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
00916 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
00917 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
00918 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
00919 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
00920 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
00921 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
00922 #define E1000_GCR_CAP_VER2              0x00040000
00923 
00924 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
00925                            E1000_GCR_RXDSCW_NO_SNOOP      | \
00926                            E1000_GCR_RXDSCR_NO_SNOOP      | \
00927                            E1000_GCR_TXD_NO_SNOOP         | \
00928                            E1000_GCR_TXDSCW_NO_SNOOP      | \
00929                            E1000_GCR_TXDSCR_NO_SNOOP)
00930 
00931 /* PHY Control Register */
00932 #define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
00933 #define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
00934 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
00935 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
00936 #define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
00937 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
00938 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
00939 #define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
00940 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
00941 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
00942 #define MII_CR_SPEED_1000       0x0040
00943 #define MII_CR_SPEED_100        0x2000
00944 #define MII_CR_SPEED_10         0x0000
00945 
00946 /* PHY Status Register */
00947 #define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
00948 #define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
00949 #define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
00950 #define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
00951 #define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
00952 #define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
00953 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
00954 #define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
00955 #define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
00956 #define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
00957 #define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
00958 #define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
00959 #define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
00960 #define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
00961 #define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
00962 
00963 /* Autoneg Advertisement Register */
00964 #define NWAY_AR_SELECTOR_FIELD   0x0001   /* indicates IEEE 802.3 CSMA/CD */
00965 #define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
00966 #define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
00967 #define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
00968 #define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
00969 #define NWAY_AR_100T4_CAPS       0x0200   /* 100T4 Capable */
00970 #define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
00971 #define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
00972 #define NWAY_AR_REMOTE_FAULT     0x2000   /* Remote Fault detected */
00973 #define NWAY_AR_NEXT_PAGE        0x8000   /* Next Page ability supported */
00974 
00975 /* Link Partner Ability Register (Base Page) */
00976 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
00977 #define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
00978 #define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
00979 #define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
00980 #define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
00981 #define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
00982 #define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
00983 #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
00984 #define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
00985 #define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
00986 #define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
00987 
00988 /* Autoneg Expansion Register */
00989 #define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
00990 #define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
00991 #define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
00992 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
00993 #define NWAY_ER_PAR_DETECT_FAULT  0x0010 /* LP is 100TX Full Duplex Capable */
00994 
00995 /* 1000BASE-T Control Register */
00996 #define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
00997 #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
00998 #define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
00999 #define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
01000                                         /* 0=DTE device */
01001 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
01002                                         /* 0=Configure PHY as Slave */
01003 #define CR_1000T_MS_ENABLE      0x1000 /* 1=Master/Slave manual config value */
01004                                         /* 0=Automatic Master/Slave config */
01005 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
01006 #define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
01007 #define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
01008 #define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
01009 #define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
01010 
01011 /* 1000BASE-T Status Register */
01012 #define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
01013 #define SR_1000T_ASYM_PAUSE_DIR  0x0100 /* LP asymmetric pause direction bit */
01014 #define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
01015 #define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
01016 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
01017 #define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
01018 #define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local Tx is Master, 0=Slave */
01019 #define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
01020 
01021 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
01022 
01023 /* PHY 1000 MII Register/Bit Definitions */
01024 /* PHY Registers defined by IEEE */
01025 #define PHY_CONTROL      0x00 /* Control Register */
01026 #define PHY_STATUS       0x01 /* Status Register */
01027 #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
01028 #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
01029 #define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
01030 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
01031 #define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
01032 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
01033 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
01034 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
01035 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
01036 #define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
01037 
01038 #define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
01039 
01040 /* NVM Control */
01041 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
01042 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
01043 #define E1000_EECD_DI        0x00000004 /* NVM Data In */
01044 #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
01045 #define E1000_EECD_FWE_MASK  0x00000030
01046 #define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
01047 #define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
01048 #define E1000_EECD_FWE_SHIFT 4
01049 #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
01050 #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
01051 #define E1000_EECD_PRES      0x00000100 /* NVM Present */
01052 #define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
01053 /* NVM Addressing bits based on type 0=small, 1=large */
01054 #define E1000_EECD_ADDR_BITS 0x00000400
01055 #define E1000_EECD_TYPE      0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
01056 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
01057 #define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
01058 #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
01059 #define E1000_EECD_SIZE_EX_SHIFT     11
01060 #define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
01061 #define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
01062 #define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
01063 #define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
01064 #define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
01065 #define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
01066 #define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
01067 #define E1000_EECD_SECVAL_SHIFT      22
01068 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
01069 
01070 #define E1000_NVM_SWDPIN0   0x0001   /* SWDPIN 0 NVM Value */
01071 #define E1000_NVM_LED_LOGIC 0x0020   /* Led Logic Word */
01072 #define E1000_NVM_RW_REG_DATA   16  /* Offset to data in NVM read/write regs */
01073 #define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
01074 #define E1000_NVM_RW_REG_START  1    /* Start operation */
01075 #define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
01076 #define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */
01077 #define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
01078 #define E1000_FLASH_UPDATES  2000
01079 
01080 /* NVM Word Offsets */
01081 #define NVM_COMPAT                 0x0003
01082 #define NVM_ID_LED_SETTINGS        0x0004
01083 #define NVM_VERSION                0x0005
01084 #define NVM_SERDES_AMPLITUDE       0x0006 /* SERDES output amplitude */
01085 #define NVM_PHY_CLASS_WORD         0x0007
01086 #define NVM_INIT_CONTROL1_REG      0x000A
01087 #define NVM_INIT_CONTROL2_REG      0x000F
01088 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
01089 #define NVM_INIT_CONTROL3_PORT_B   0x0014
01090 #define NVM_INIT_3GIO_3            0x001A
01091 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
01092 #define NVM_INIT_CONTROL3_PORT_A   0x0024
01093 #define NVM_CFG                    0x0012
01094 #define NVM_FLASH_VERSION          0x0032
01095 #define NVM_ALT_MAC_ADDR_PTR       0x0037
01096 #define NVM_CHECKSUM_REG           0x003F
01097 
01098 #define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
01099 #define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
01100 
01101 /* Mask bits for fields in Word 0x0f of the NVM */
01102 #define NVM_WORD0F_PAUSE_MASK       0x3000
01103 #define NVM_WORD0F_PAUSE            0x1000
01104 #define NVM_WORD0F_ASM_DIR          0x2000
01105 #define NVM_WORD0F_ANE              0x0800
01106 #define NVM_WORD0F_SWPDIO_EXT_MASK  0x00F0
01107 #define NVM_WORD0F_LPLU             0x0001
01108 
01109 /* Mask bits for fields in Word 0x1a of the NVM */
01110 #define NVM_WORD1A_ASPM_MASK  0x000C
01111 
01112 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
01113 #define NVM_SUM                    0xBABA
01114 
01115 #define NVM_MAC_ADDR_OFFSET        0
01116 #define NVM_PBA_OFFSET_0           8
01117 #define NVM_PBA_OFFSET_1           9
01118 #define NVM_RESERVED_WORD          0xFFFF
01119 #define NVM_PHY_CLASS_A            0x8000
01120 #define NVM_SERDES_AMPLITUDE_MASK  0x000F
01121 #define NVM_SIZE_MASK              0x1C00
01122 #define NVM_SIZE_SHIFT             10
01123 #define NVM_WORD_SIZE_BASE_SHIFT   6
01124 #define NVM_SWDPIO_EXT_SHIFT       4
01125 
01126 /* NVM Commands - SPI */
01127 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
01128 #define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
01129 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
01130 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
01131 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
01132 #define NVM_WRDI_OPCODE_SPI        0x04 /* NVM reset Write Enable latch */
01133 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
01134 #define NVM_WRSR_OPCODE_SPI        0x01 /* NVM write Status register */
01135 
01136 /* SPI NVM Status Register */
01137 #define NVM_STATUS_RDY_SPI         0x01
01138 #define NVM_STATUS_WEN_SPI         0x02
01139 #define NVM_STATUS_BP0_SPI         0x04
01140 #define NVM_STATUS_BP1_SPI         0x08
01141 #define NVM_STATUS_WPEN_SPI        0x80
01142 
01143 /* Word definitions for ID LED Settings */
01144 #define ID_LED_RESERVED_0000 0x0000
01145 #define ID_LED_RESERVED_FFFF 0xFFFF
01146 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
01147                               (ID_LED_OFF1_OFF2 <<  8) | \
01148                               (ID_LED_DEF1_DEF2 <<  4) | \
01149                               (ID_LED_DEF1_DEF2))
01150 #define ID_LED_DEF1_DEF2     0x1
01151 #define ID_LED_DEF1_ON2      0x2
01152 #define ID_LED_DEF1_OFF2     0x3
01153 #define ID_LED_ON1_DEF2      0x4
01154 #define ID_LED_ON1_ON2       0x5
01155 #define ID_LED_ON1_OFF2      0x6
01156 #define ID_LED_OFF1_DEF2     0x7
01157 #define ID_LED_OFF1_ON2      0x8
01158 #define ID_LED_OFF1_OFF2     0x9
01159 
01160 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
01161 #define IGP_ACTIVITY_LED_ENABLE 0x0300
01162 #define IGP_LED3_MODE           0x07000000
01163 
01164 /* PCI/PCI-X/PCI-EX Config space */
01165 #define PCI_HEADER_TYPE_REGISTER     0x0E
01166 #define PCIE_LINK_STATUS             0x12
01167 #define PCIE_DEVICE_CONTROL2         0x28
01168 
01169 #define PCI_HEADER_TYPE_MULTIFUNC    0x80
01170 #define PCIE_LINK_WIDTH_MASK         0x3F0
01171 #define PCIE_LINK_WIDTH_SHIFT        4
01172 #define PCIE_DEVICE_CONTROL2_16ms    0x0005
01173 
01174 #ifndef ETH_ADDR_LEN
01175 #define ETH_ADDR_LEN                 6
01176 #endif
01177 
01178 #define PHY_REVISION_MASK      0xFFFFFFF0
01179 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
01180 #define MAX_PHY_MULTI_PAGE_REG 0xF
01181 
01182 /* Bit definitions for valid PHY IDs. */
01183 /*
01184  * I = Integrated
01185  * E = External
01186  */
01187 #define M88E1000_E_PHY_ID    0x01410C50
01188 #define M88E1000_I_PHY_ID    0x01410C30
01189 #define M88E1011_I_PHY_ID    0x01410C20
01190 #define IGP01E1000_I_PHY_ID  0x02A80380
01191 #define M88E1011_I_REV_4     0x04
01192 #define M88E1111_I_PHY_ID    0x01410CC0
01193 #define GG82563_E_PHY_ID     0x01410CA0
01194 #define IGP03E1000_E_PHY_ID  0x02A80390
01195 #define IFE_E_PHY_ID         0x02A80330
01196 #define IFE_PLUS_E_PHY_ID    0x02A80320
01197 #define IFE_C_E_PHY_ID       0x02A80310
01198 #define M88_VENDOR           0x0141
01199 
01200 /* M88E1000 Specific Registers */
01201 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
01202 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
01203 #define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
01204 #define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
01205 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
01206 #define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
01207 
01208 #define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
01209 #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
01210 #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
01211 #define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
01212 #define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
01213 
01214 /* M88E1000 PHY Specific Control Register */
01215 #define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
01216 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
01217 #define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
01218 /* 1=CLK125 low, 0=CLK125 toggling */
01219 #define M88E1000_PSCR_CLK125_DISABLE    0x0010
01220 #define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000 /* MDI Crossover Mode bits 6:5 */
01221                                                /* Manual MDI configuration */
01222 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
01223 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
01224 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
01225 /* Auto crossover enabled all speeds */
01226 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
01227 /*
01228  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
01229  * 0=Normal 10BASE-T Rx Threshold
01230  */
01231 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
01232 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
01233 #define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
01234 #define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
01235 #define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
01236 #define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Tx */
01237 
01238 /* M88E1000 PHY Specific Status Register */
01239 #define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
01240 #define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
01241 #define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
01242 #define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
01243 /*
01244  * 0 = <50M
01245  * 1 = 50-80M
01246  * 2 = 80-110M
01247  * 3 = 110-140M
01248  * 4 = >140M
01249  */
01250 #define M88E1000_PSSR_CABLE_LENGTH       0x0380
01251 #define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
01252 #define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
01253 #define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
01254 #define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
01255 #define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
01256 #define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
01257 #define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
01258 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
01259 
01260 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
01261 
01262 /* M88E1000 Extended PHY Specific Control Register */
01263 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
01264 /*
01265  * 1 = Lost lock detect enabled.
01266  * Will assert lost lock and bring
01267  * link down if idle not seen
01268  * within 1ms in 1000BASE-T
01269  */
01270 #define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000
01271 /*
01272  * Number of times we will attempt to autonegotiate before downshifting if we
01273  * are the master
01274  */
01275 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
01276 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
01277 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
01278 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
01279 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
01280 /*
01281  * Number of times we will attempt to autonegotiate before downshifting if we
01282  * are the slave
01283  */
01284 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
01285 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
01286 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
01287 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
01288 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
01289 #define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
01290 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
01291 #define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
01292 
01293 /* M88EC018 Rev 2 specific DownShift settings */
01294 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
01295 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X    0x0000
01296 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X    0x0200
01297 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X    0x0400
01298 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X    0x0600
01299 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
01300 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X    0x0A00
01301 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X    0x0C00
01302 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X    0x0E00
01303 
01304 /*
01305  * Bits...
01306  * 15-5: page
01307  * 4-0: register offset
01308  */
01309 #define GG82563_PAGE_SHIFT        5
01310 #define GG82563_REG(page, reg)    \
01311         (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
01312 #define GG82563_MIN_ALT_REG       30
01313 
01314 /* GG82563 Specific Registers */
01315 #define GG82563_PHY_SPEC_CTRL           \
01316         GG82563_REG(0, 16) /* PHY Specific Control */
01317 #define GG82563_PHY_SPEC_STATUS         \
01318         GG82563_REG(0, 17) /* PHY Specific Status */
01319 #define GG82563_PHY_INT_ENABLE          \
01320         GG82563_REG(0, 18) /* Interrupt Enable */
01321 #define GG82563_PHY_SPEC_STATUS_2       \
01322         GG82563_REG(0, 19) /* PHY Specific Status 2 */
01323 #define GG82563_PHY_RX_ERR_CNTR         \
01324         GG82563_REG(0, 21) /* Receive Error Counter */
01325 #define GG82563_PHY_PAGE_SELECT         \
01326         GG82563_REG(0, 22) /* Page Select */
01327 #define GG82563_PHY_SPEC_CTRL_2         \
01328         GG82563_REG(0, 26) /* PHY Specific Control 2 */
01329 #define GG82563_PHY_PAGE_SELECT_ALT     \
01330         GG82563_REG(0, 29) /* Alternate Page Select */
01331 #define GG82563_PHY_TEST_CLK_CTRL       \
01332         GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
01333 
01334 #define GG82563_PHY_MAC_SPEC_CTRL       \
01335         GG82563_REG(2, 21) /* MAC Specific Control Register */
01336 #define GG82563_PHY_MAC_SPEC_CTRL_2     \
01337         GG82563_REG(2, 26) /* MAC Specific Control 2 */
01338 
01339 #define GG82563_PHY_DSP_DISTANCE    \
01340         GG82563_REG(5, 26) /* DSP Distance */
01341 
01342 /* Page 193 - Port Control Registers */
01343 #define GG82563_PHY_KMRN_MODE_CTRL   \
01344         GG82563_REG(193, 16) /* Kumeran Mode Control */
01345 #define GG82563_PHY_PORT_RESET          \
01346         GG82563_REG(193, 17) /* Port Reset */
01347 #define GG82563_PHY_REVISION_ID         \
01348         GG82563_REG(193, 18) /* Revision ID */
01349 #define GG82563_PHY_DEVICE_ID           \
01350         GG82563_REG(193, 19) /* Device ID */
01351 #define GG82563_PHY_PWR_MGMT_CTRL       \
01352         GG82563_REG(193, 20) /* Power Management Control */
01353 #define GG82563_PHY_RATE_ADAPT_CTRL     \
01354         GG82563_REG(193, 25) /* Rate Adaptation Control */
01355 
01356 /* Page 194 - KMRN Registers */
01357 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
01358         GG82563_REG(194, 16) /* FIFO's Control/Status */
01359 #define GG82563_PHY_KMRN_CTRL           \
01360         GG82563_REG(194, 17) /* Control */
01361 #define GG82563_PHY_INBAND_CTRL         \
01362         GG82563_REG(194, 18) /* Inband Control */
01363 #define GG82563_PHY_KMRN_DIAGNOSTIC     \
01364         GG82563_REG(194, 19) /* Diagnostic */
01365 #define GG82563_PHY_ACK_TIMEOUTS        \
01366         GG82563_REG(194, 20) /* Acknowledge Timeouts */
01367 #define GG82563_PHY_ADV_ABILITY         \
01368         GG82563_REG(194, 21) /* Advertised Ability */
01369 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
01370         GG82563_REG(194, 23) /* Link Partner Advertised Ability */
01371 #define GG82563_PHY_ADV_NEXT_PAGE       \
01372         GG82563_REG(194, 24) /* Advertised Next Page */
01373 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
01374         GG82563_REG(194, 25) /* Link Partner Advertised Next page */
01375 #define GG82563_PHY_KMRN_MISC           \
01376         GG82563_REG(194, 26) /* Misc. */
01377 
01378 /* MDI Control */
01379 #define E1000_MDIC_DATA_MASK 0x0000FFFF
01380 #define E1000_MDIC_REG_MASK  0x001F0000
01381 #define E1000_MDIC_REG_SHIFT 16
01382 #define E1000_MDIC_PHY_MASK  0x03E00000
01383 #define E1000_MDIC_PHY_SHIFT 21
01384 #define E1000_MDIC_OP_WRITE  0x04000000
01385 #define E1000_MDIC_OP_READ   0x08000000
01386 #define E1000_MDIC_READY     0x10000000
01387 #define E1000_MDIC_INT_EN    0x20000000
01388 #define E1000_MDIC_ERROR     0x40000000
01389 
01390 /* SerDes Control */
01391 #define E1000_GEN_CTL_READY             0x80000000
01392 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
01393 #define E1000_GEN_POLL_TIMEOUT          640
01394 
01395 #endif /* _IGBVF_DEFINES_H_ */