Go to the documentation of this file. 31 #ifndef _IGBVF_DEFINES_H_ 32 #define _IGBVF_DEFINES_H_ 35 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 36 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 40 #define E1000_WUC_APME 0x00000001 41 #define E1000_WUC_PME_EN 0x00000002 42 #define E1000_WUC_PME_STATUS 0x00000004 43 #define E1000_WUC_APMPME 0x00000008 44 #define E1000_WUC_LSCWE 0x00000010 45 #define E1000_WUC_LSCWO 0x00000020 46 #define E1000_WUC_SPM 0x80000000 47 #define E1000_WUC_PHY_WAKE 0x00000100 50 #define E1000_WUFC_LNKC 0x00000001 51 #define E1000_WUFC_MAG 0x00000002 52 #define E1000_WUFC_EX 0x00000004 53 #define E1000_WUFC_MC 0x00000008 54 #define E1000_WUFC_BC 0x00000010 55 #define E1000_WUFC_ARP 0x00000020 56 #define E1000_WUFC_IPV4 0x00000040 57 #define E1000_WUFC_IPV6 0x00000080 58 #define E1000_WUFC_IGNORE_TCO 0x00008000 59 #define E1000_WUFC_FLX0 0x00010000 60 #define E1000_WUFC_FLX1 0x00020000 61 #define E1000_WUFC_FLX2 0x00040000 62 #define E1000_WUFC_FLX3 0x00080000 63 #define E1000_WUFC_ALL_FILTERS 0x000F00FF 64 #define E1000_WUFC_FLX_OFFSET 16 65 #define E1000_WUFC_FLX_FILTERS 0x000F0000 68 #define E1000_WUS_LNKC E1000_WUFC_LNKC 69 #define E1000_WUS_MAG E1000_WUFC_MAG 70 #define E1000_WUS_EX E1000_WUFC_EX 71 #define E1000_WUS_MC E1000_WUFC_MC 72 #define E1000_WUS_BC E1000_WUFC_BC 73 #define E1000_WUS_ARP E1000_WUFC_ARP 74 #define E1000_WUS_IPV4 E1000_WUFC_IPV4 75 #define E1000_WUS_IPV6 E1000_WUFC_IPV6 76 #define E1000_WUS_FLX0 E1000_WUFC_FLX0 77 #define E1000_WUS_FLX1 E1000_WUFC_FLX1 78 #define E1000_WUS_FLX2 E1000_WUFC_FLX2 79 #define E1000_WUS_FLX3 E1000_WUFC_FLX3 80 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS 83 #define E1000_WUPL_LENGTH_MASK 0x0FFF 86 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 89 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 91 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 92 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 93 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 96 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 97 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 98 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 99 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 100 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 102 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 103 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 104 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 105 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 106 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 108 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 109 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 110 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 111 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 112 #define E1000_CTRL_EXT_ASDCHK 0x00001000 113 #define E1000_CTRL_EXT_EE_RST 0x00002000 114 #define E1000_CTRL_EXT_IPS 0x00004000 115 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 116 #define E1000_CTRL_EXT_RO_DIS 0x00020000 117 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 118 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 119 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 120 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 121 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 122 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 123 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 124 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 125 #define E1000_CTRL_EXT_EIAME 0x01000000 126 #define E1000_CTRL_EXT_IRCA 0x00000001 127 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 128 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 129 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 130 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 131 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 132 #define E1000_CTRL_EXT_CANC 0x04000000 133 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 135 #define E1000_CTRL_EXT_IAME 0x08000000 136 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 138 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 140 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 141 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 142 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 143 #define E1000_I2CCMD_REG_ADDR 0x00FF0000 144 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 145 #define E1000_I2CCMD_PHY_ADDR 0x07000000 146 #define E1000_I2CCMD_OPCODE_READ 0x08000000 147 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 148 #define E1000_I2CCMD_RESET 0x10000000 149 #define E1000_I2CCMD_READY 0x20000000 150 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 151 #define E1000_I2CCMD_ERROR 0x80000000 152 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 153 #define E1000_I2CCMD_PHY_TIMEOUT 200 156 #define E1000_RXD_STAT_DD 0x01 157 #define E1000_RXD_STAT_EOP 0x02 158 #define E1000_RXD_STAT_IXSM 0x04 159 #define E1000_RXD_STAT_VP 0x08 160 #define E1000_RXD_STAT_UDPCS 0x10 161 #define E1000_RXD_STAT_TCPCS 0x20 162 #define E1000_RXD_STAT_IPCS 0x40 163 #define E1000_RXD_STAT_PIF 0x80 164 #define E1000_RXD_STAT_CRCV 0x100 165 #define E1000_RXD_STAT_IPIDV 0x200 166 #define E1000_RXD_STAT_UDPV 0x400 167 #define E1000_RXD_STAT_DYNINT 0x800 168 #define E1000_RXD_STAT_ACK 0x8000 169 #define E1000_RXD_ERR_CE 0x01 170 #define E1000_RXD_ERR_SE 0x02 171 #define E1000_RXD_ERR_SEQ 0x04 172 #define E1000_RXD_ERR_CXE 0x10 173 #define E1000_RXD_ERR_TCPE 0x20 174 #define E1000_RXD_ERR_IPE 0x40 175 #define E1000_RXD_ERR_RXE 0x80 176 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF 177 #define E1000_RXD_SPC_PRI_MASK 0xE000 178 #define E1000_RXD_SPC_PRI_SHIFT 13 179 #define E1000_RXD_SPC_CFI_MASK 0x1000 180 #define E1000_RXD_SPC_CFI_SHIFT 12 182 #define E1000_RXDEXT_STATERR_CE 0x01000000 183 #define E1000_RXDEXT_STATERR_SE 0x02000000 184 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 185 #define E1000_RXDEXT_STATERR_CXE 0x10000000 186 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 187 #define E1000_RXDEXT_STATERR_IPE 0x40000000 188 #define E1000_RXDEXT_STATERR_RXE 0x80000000 191 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 194 E1000_RXD_ERR_SEQ | \ 195 E1000_RXD_ERR_CXE | \ 199 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 200 E1000_RXDEXT_STATERR_CE | \ 201 E1000_RXDEXT_STATERR_SE | \ 202 E1000_RXDEXT_STATERR_SEQ | \ 203 E1000_RXDEXT_STATERR_CXE | \ 204 E1000_RXDEXT_STATERR_RXE) 206 #define E1000_MRQC_ENABLE_MASK 0x00000007 207 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 208 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004 209 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 210 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 211 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 212 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 213 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 214 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 215 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 217 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 218 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 221 #define E1000_MANC_SMBUS_EN 0x00000001 222 #define E1000_MANC_ASF_EN 0x00000002 223 #define E1000_MANC_R_ON_FORCE 0x00000004 224 #define E1000_MANC_RMCP_EN 0x00000100 225 #define E1000_MANC_0298_EN 0x00000200 226 #define E1000_MANC_IPV4_EN 0x00000400 227 #define E1000_MANC_IPV6_EN 0x00000800 228 #define E1000_MANC_SNAP_EN 0x00001000 229 #define E1000_MANC_ARP_EN 0x00002000 231 #define E1000_MANC_NEIGHBOR_EN 0x00004000 232 #define E1000_MANC_ARP_RES_EN 0x00008000 233 #define E1000_MANC_TCO_RESET 0x00010000 234 #define E1000_MANC_RCV_TCO_EN 0x00020000 235 #define E1000_MANC_REPORT_STATUS 0x00040000 236 #define E1000_MANC_RCV_ALL 0x00080000 237 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 239 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 241 #define E1000_MANC_EN_MNG2HOST 0x00200000 243 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 244 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 245 #define E1000_MANC_BR_EN 0x01000000 246 #define E1000_MANC_SMB_REQ 0x01000000 247 #define E1000_MANC_SMB_GNT 0x02000000 248 #define E1000_MANC_SMB_CLK_IN 0x04000000 249 #define E1000_MANC_SMB_DATA_IN 0x08000000 250 #define E1000_MANC_SMB_DATA_OUT 0x10000000 251 #define E1000_MANC_SMB_CLK_OUT 0x20000000 253 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 254 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 257 #define E1000_RCTL_RST 0x00000001 258 #define E1000_RCTL_EN 0x00000002 259 #define E1000_RCTL_SBP 0x00000004 260 #define E1000_RCTL_UPE 0x00000008 261 #define E1000_RCTL_MPE 0x00000010 262 #define E1000_RCTL_LPE 0x00000020 263 #define E1000_RCTL_LBM_NO 0x00000000 264 #define E1000_RCTL_LBM_MAC 0x00000040 265 #define E1000_RCTL_LBM_SLP 0x00000080 266 #define E1000_RCTL_LBM_TCVR 0x000000C0 267 #define E1000_RCTL_DTYP_MASK 0x00000C00 268 #define E1000_RCTL_DTYP_PS 0x00000400 269 #define E1000_RCTL_RDMTS_HALF 0x00000000 270 #define E1000_RCTL_RDMTS_QUAT 0x00000100 271 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 272 #define E1000_RCTL_MO_SHIFT 12 273 #define E1000_RCTL_MO_0 0x00000000 274 #define E1000_RCTL_MO_1 0x00001000 275 #define E1000_RCTL_MO_2 0x00002000 276 #define E1000_RCTL_MO_3 0x00003000 277 #define E1000_RCTL_MDR 0x00004000 278 #define E1000_RCTL_BAM 0x00008000 280 #define E1000_RCTL_SZ_2048 0x00000000 281 #define E1000_RCTL_SZ_1024 0x00010000 282 #define E1000_RCTL_SZ_512 0x00020000 283 #define E1000_RCTL_SZ_256 0x00030000 285 #define E1000_RCTL_SZ_16384 0x00010000 286 #define E1000_RCTL_SZ_8192 0x00020000 287 #define E1000_RCTL_SZ_4096 0x00030000 288 #define E1000_RCTL_VFE 0x00040000 289 #define E1000_RCTL_CFIEN 0x00080000 290 #define E1000_RCTL_CFI 0x00100000 291 #define E1000_RCTL_DPF 0x00400000 292 #define E1000_RCTL_PMCF 0x00800000 293 #define E1000_RCTL_BSEX 0x02000000 294 #define E1000_RCTL_SECRC 0x04000000 295 #define E1000_RCTL_FLXBUF_MASK 0x78000000 296 #define E1000_RCTL_FLXBUF_SHIFT 27 315 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 316 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 317 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 318 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 320 #define E1000_PSRCTL_BSIZE0_SHIFT 7 321 #define E1000_PSRCTL_BSIZE1_SHIFT 2 322 #define E1000_PSRCTL_BSIZE2_SHIFT 6 323 #define E1000_PSRCTL_BSIZE3_SHIFT 14 326 #define E1000_SWFW_EEP_SM 0x01 327 #define E1000_SWFW_PHY0_SM 0x02 328 #define E1000_SWFW_PHY1_SM 0x04 329 #define E1000_SWFW_CSR_SM 0x08 332 #define E1000_FACTPS_LFS 0x40000000 334 #define E1000_CTRL_FD 0x00000001 335 #define E1000_CTRL_BEM 0x00000002 336 #define E1000_CTRL_PRIOR 0x00000004 337 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 338 #define E1000_CTRL_LRST 0x00000008 339 #define E1000_CTRL_TME 0x00000010 340 #define E1000_CTRL_SLE 0x00000020 341 #define E1000_CTRL_ASDE 0x00000020 342 #define E1000_CTRL_SLU 0x00000040 343 #define E1000_CTRL_ILOS 0x00000080 344 #define E1000_CTRL_SPD_SEL 0x00000300 345 #define E1000_CTRL_SPD_10 0x00000000 346 #define E1000_CTRL_SPD_100 0x00000100 347 #define E1000_CTRL_SPD_1000 0x00000200 348 #define E1000_CTRL_BEM32 0x00000400 349 #define E1000_CTRL_FRCSPD 0x00000800 350 #define E1000_CTRL_FRCDPX 0x00001000 351 #define E1000_CTRL_D_UD_EN 0x00002000 352 #define E1000_CTRL_D_UD_POLARITY 0x00004000 354 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 356 #define E1000_CTRL_EXT_LINK_EN 0x00010000 358 #define E1000_CTRL_SWDPIN0 0x00040000 359 #define E1000_CTRL_SWDPIN1 0x00080000 360 #define E1000_CTRL_SWDPIN2 0x00100000 361 #define E1000_CTRL_SWDPIN3 0x00200000 362 #define E1000_CTRL_SWDPIO0 0x00400000 363 #define E1000_CTRL_SWDPIO1 0x00800000 364 #define E1000_CTRL_SWDPIO2 0x01000000 365 #define E1000_CTRL_SWDPIO3 0x02000000 366 #define E1000_CTRL_RST 0x04000000 367 #define E1000_CTRL_RFCE 0x08000000 368 #define E1000_CTRL_TFCE 0x10000000 369 #define E1000_CTRL_RTE 0x20000000 370 #define E1000_CTRL_VME 0x40000000 371 #define E1000_CTRL_PHY_RST 0x80000000 372 #define E1000_CTRL_SW2FW_INT 0x02000000 373 #define E1000_CTRL_I2C_ENA 0x02000000 379 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 380 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 381 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 382 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 383 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 384 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 385 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 386 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 388 #define E1000_CONNSW_ENRGSRC 0x4 389 #define E1000_PCS_CFG_PCS_EN 8 390 #define E1000_PCS_LCTL_FLV_LINK_UP 1 391 #define E1000_PCS_LCTL_FSV_10 0 392 #define E1000_PCS_LCTL_FSV_100 2 393 #define E1000_PCS_LCTL_FSV_1000 4 394 #define E1000_PCS_LCTL_FDV_FULL 8 395 #define E1000_PCS_LCTL_FSD 0x10 396 #define E1000_PCS_LCTL_FORCE_LINK 0x20 397 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 398 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 399 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 400 #define E1000_PCS_LCTL_AN_RESTART 0x20000 401 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 402 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 403 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 404 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 405 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 406 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 407 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 409 #define E1000_PCS_LSTS_LINK_OK 1 410 #define E1000_PCS_LSTS_SPEED_10 0 411 #define E1000_PCS_LSTS_SPEED_100 2 412 #define E1000_PCS_LSTS_SPEED_1000 4 413 #define E1000_PCS_LSTS_DUPLEX_FULL 8 414 #define E1000_PCS_LSTS_SYNK_OK 0x10 415 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 416 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 417 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 418 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 419 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 422 #define E1000_STATUS_FD 0x00000001 423 #define E1000_STATUS_LU 0x00000002 424 #define E1000_STATUS_FUNC_MASK 0x0000000C 425 #define E1000_STATUS_FUNC_SHIFT 2 426 #define E1000_STATUS_FUNC_0 0x00000000 427 #define E1000_STATUS_FUNC_1 0x00000004 428 #define E1000_STATUS_TXOFF 0x00000010 429 #define E1000_STATUS_TBIMODE 0x00000020 430 #define E1000_STATUS_SPEED_MASK 0x000000C0 431 #define E1000_STATUS_SPEED_10 0x00000000 432 #define E1000_STATUS_SPEED_100 0x00000040 433 #define E1000_STATUS_SPEED_1000 0x00000080 434 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 435 #define E1000_STATUS_ASDV 0x00000300 436 #define E1000_STATUS_PHYRA 0x00000400 437 #define E1000_STATUS_DOCK_CI 0x00000800 439 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 440 #define E1000_STATUS_MTXCKOK 0x00000400 441 #define E1000_STATUS_PCI66 0x00000800 442 #define E1000_STATUS_BUS64 0x00001000 443 #define E1000_STATUS_PCIX_MODE 0x00002000 444 #define E1000_STATUS_PCIX_SPEED 0x0000C000 445 #define E1000_STATUS_BMC_SKU_0 0x00100000 446 #define E1000_STATUS_BMC_SKU_1 0x00200000 447 #define E1000_STATUS_BMC_SKU_2 0x00400000 448 #define E1000_STATUS_BMC_CRYPTO 0x00800000 449 #define E1000_STATUS_BMC_LITE 0x01000000 451 #define E1000_STATUS_RGMII_ENABLE 0x02000000 452 #define E1000_STATUS_FUSE_8 0x04000000 453 #define E1000_STATUS_FUSE_9 0x08000000 454 #define E1000_STATUS_SERDES0_DIS 0x10000000 455 #define E1000_STATUS_SERDES1_DIS 0x20000000 458 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 459 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 460 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 463 #define SPEED_100 100 464 #define SPEED_1000 1000 465 #define HALF_DUPLEX 1 466 #define FULL_DUPLEX 2 468 #define PHY_FORCE_TIME 20 470 #define ADVERTISE_10_HALF 0x0001 471 #define ADVERTISE_10_FULL 0x0002 472 #define ADVERTISE_100_HALF 0x0004 473 #define ADVERTISE_100_FULL 0x0008 474 #define ADVERTISE_1000_HALF 0x0010 475 #define ADVERTISE_1000_FULL 0x0020 478 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 479 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 481 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 482 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 483 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 484 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 485 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 487 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 489 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 492 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 493 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 494 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 495 #define E1000_LEDCTL_LED0_IVRT 0x00000040 496 #define E1000_LEDCTL_LED0_BLINK 0x00000080 497 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 498 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 499 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 500 #define E1000_LEDCTL_LED1_IVRT 0x00004000 501 #define E1000_LEDCTL_LED1_BLINK 0x00008000 502 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 503 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 504 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 505 #define E1000_LEDCTL_LED2_IVRT 0x00400000 506 #define E1000_LEDCTL_LED2_BLINK 0x00800000 507 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 508 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 509 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 510 #define E1000_LEDCTL_LED3_IVRT 0x40000000 511 #define E1000_LEDCTL_LED3_BLINK 0x80000000 513 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 514 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 515 #define E1000_LEDCTL_MODE_LINK_UP 0x2 516 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 517 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 518 #define E1000_LEDCTL_MODE_LINK_10 0x5 519 #define E1000_LEDCTL_MODE_LINK_100 0x6 520 #define E1000_LEDCTL_MODE_LINK_1000 0x7 521 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 522 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 523 #define E1000_LEDCTL_MODE_COLLISION 0xA 524 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 525 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 526 #define E1000_LEDCTL_MODE_PAUSED 0xD 527 #define E1000_LEDCTL_MODE_LED_ON 0xE 528 #define E1000_LEDCTL_MODE_LED_OFF 0xF 531 #define E1000_TXD_DTYP_D 0x00100000 532 #define E1000_TXD_DTYP_C 0x00000000 533 #define E1000_TXD_POPTS_SHIFT 8 534 #define E1000_TXD_POPTS_IXSM 0x01 535 #define E1000_TXD_POPTS_TXSM 0x02 536 #define E1000_TXD_CMD_EOP 0x01000000 537 #define E1000_TXD_CMD_IFCS 0x02000000 538 #define E1000_TXD_CMD_IC 0x04000000 539 #define E1000_TXD_CMD_RS 0x08000000 540 #define E1000_TXD_CMD_RPS 0x10000000 541 #define E1000_TXD_CMD_DEXT 0x20000000 542 #define E1000_TXD_CMD_VLE 0x40000000 543 #define E1000_TXD_CMD_IDE 0x80000000 544 #define E1000_TXD_STAT_DD 0x00000001 545 #define E1000_TXD_STAT_EC 0x00000002 546 #define E1000_TXD_STAT_LC 0x00000004 547 #define E1000_TXD_STAT_TU 0x00000008 548 #define E1000_TXD_CMD_TCP 0x01000000 549 #define E1000_TXD_CMD_IP 0x02000000 550 #define E1000_TXD_CMD_TSE 0x04000000 551 #define E1000_TXD_STAT_TC 0x00000004 555 #define E1000_TCTL_RST 0x00000001 556 #define E1000_TCTL_EN 0x00000002 557 #define E1000_TCTL_BCE 0x00000004 558 #define E1000_TCTL_PSP 0x00000008 559 #define E1000_TCTL_CT 0x00000ff0 560 #define E1000_TCTL_COLD 0x003ff000 561 #define E1000_TCTL_SWXOFF 0x00400000 562 #define E1000_TCTL_PBE 0x00800000 563 #define E1000_TCTL_RTLC 0x01000000 564 #define E1000_TCTL_NRTU 0x02000000 565 #define E1000_TCTL_MULR 0x10000000 568 #define E1000_TARC0_ENABLE 0x00000400 571 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 574 #define E1000_RXCSUM_PCSS_MASK 0x000000FF 575 #define E1000_RXCSUM_IPOFL 0x00000100 576 #define E1000_RXCSUM_TUOFL 0x00000200 577 #define E1000_RXCSUM_IPV6OFL 0x00000400 578 #define E1000_RXCSUM_CRCOFL 0x00000800 579 #define E1000_RXCSUM_IPPCSE 0x00001000 580 #define E1000_RXCSUM_PCSD 0x00002000 583 #define E1000_RFCTL_ISCSI_DIS 0x00000001 584 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 585 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 586 #define E1000_RFCTL_NFSW_DIS 0x00000040 587 #define E1000_RFCTL_NFSR_DIS 0x00000080 588 #define E1000_RFCTL_NFS_VER_MASK 0x00000300 589 #define E1000_RFCTL_NFS_VER_SHIFT 8 590 #define E1000_RFCTL_IPV6_DIS 0x00000400 591 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 592 #define E1000_RFCTL_ACK_DIS 0x00001000 593 #define E1000_RFCTL_ACKD_DIS 0x00002000 594 #define E1000_RFCTL_IPFRSP_DIS 0x00004000 595 #define E1000_RFCTL_EXTEN 0x00008000 596 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 597 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 598 #define E1000_RFCTL_LEF 0x00040000 601 #define E1000_COLLISION_THRESHOLD 15 602 #define E1000_CT_SHIFT 4 603 #define E1000_COLLISION_DISTANCE 63 604 #define E1000_COLD_SHIFT 12 607 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 608 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 610 #define E1000_TIPG_IPGT_MASK 0x000003FF 611 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 612 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 614 #define DEFAULT_82543_TIPG_IPGR1 8 615 #define E1000_TIPG_IPGR1_SHIFT 10 617 #define DEFAULT_82543_TIPG_IPGR2 6 618 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 619 #define E1000_TIPG_IPGR2_SHIFT 20 622 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 624 #define ETHERNET_FCS_SIZE 4 625 #define MAX_JUMBO_FRAME_SIZE 0x3F00 628 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 629 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 630 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 631 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 632 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 633 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 634 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 635 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 637 #define E1000_PHY_CTRL_SPD_EN 0x00000001 638 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 639 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 640 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 641 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 643 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 646 #define E1000_PBA_6K 0x0006 647 #define E1000_PBA_8K 0x0008 648 #define E1000_PBA_10K 0x000A 649 #define E1000_PBA_12K 0x000C 650 #define E1000_PBA_14K 0x000E 651 #define E1000_PBA_16K 0x0010 652 #define E1000_PBA_18K 0x0012 653 #define E1000_PBA_20K 0x0014 654 #define E1000_PBA_22K 0x0016 655 #define E1000_PBA_24K 0x0018 656 #define E1000_PBA_26K 0x001A 657 #define E1000_PBA_30K 0x001E 658 #define E1000_PBA_32K 0x0020 659 #define E1000_PBA_34K 0x0022 660 #define E1000_PBA_35K 0x0023 661 #define E1000_PBA_38K 0x0026 662 #define E1000_PBA_40K 0x0028 663 #define E1000_PBA_48K 0x0030 664 #define E1000_PBA_64K 0x0040 666 #define E1000_PBS_16K E1000_PBA_16K 667 #define E1000_PBS_24K E1000_PBA_24K 673 #define MIN_NUM_XMITS 1000 676 #define E1000_SWSM_SMBI 0x00000001 677 #define E1000_SWSM_SWESMBI 0x00000002 678 #define E1000_SWSM_WMNG 0x00000004 679 #define E1000_SWSM_DRV_LOAD 0x00000008 681 #define E1000_SWSM2_LOCK 0x00000002 684 #define E1000_ICR_TXDW 0x00000001 685 #define E1000_ICR_TXQE 0x00000002 686 #define E1000_ICR_LSC 0x00000004 687 #define E1000_ICR_RXSEQ 0x00000008 688 #define E1000_ICR_RXDMT0 0x00000010 689 #define E1000_ICR_RXO 0x00000040 690 #define E1000_ICR_RXT0 0x00000080 691 #define E1000_ICR_VMMB 0x00000100 692 #define E1000_ICR_MDAC 0x00000200 693 #define E1000_ICR_RXCFG 0x00000400 694 #define E1000_ICR_GPI_EN0 0x00000800 695 #define E1000_ICR_GPI_EN1 0x00001000 696 #define E1000_ICR_GPI_EN2 0x00002000 697 #define E1000_ICR_GPI_EN3 0x00004000 698 #define E1000_ICR_TXD_LOW 0x00008000 699 #define E1000_ICR_SRPD 0x00010000 700 #define E1000_ICR_ACK 0x00020000 701 #define E1000_ICR_MNG 0x00040000 702 #define E1000_ICR_DOCK 0x00080000 703 #define E1000_ICR_INT_ASSERTED 0x80000000 705 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 706 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 707 #define E1000_ICR_HOST_ARB_PAR 0x00400000 708 #define E1000_ICR_PB_PAR 0x00800000 709 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 710 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 711 #define E1000_ICR_ALL_PARITY 0x03F00000 712 #define E1000_ICR_DSW 0x00000020 714 #define E1000_ICR_PHYINT 0x00001000 716 #define E1000_ICR_DOUTSYNC 0x10000000 717 #define E1000_ICR_EPRST 0x00100000 726 #define POLL_IMS_ENABLE_MASK ( \ 739 #define IMS_ENABLE_MASK ( \ 747 #define E1000_IMS_TXDW E1000_ICR_TXDW 748 #define E1000_IMS_TXQE E1000_ICR_TXQE 749 #define E1000_IMS_LSC E1000_ICR_LSC 750 #define E1000_IMS_VMMB E1000_ICR_VMMB 751 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ 752 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 753 #define E1000_IMS_RXO E1000_ICR_RXO 754 #define E1000_IMS_RXT0 E1000_ICR_RXT0 755 #define E1000_IMS_MDAC E1000_ICR_MDAC 756 #define E1000_IMS_RXCFG E1000_ICR_RXCFG 757 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 758 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 759 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 760 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 761 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 762 #define E1000_IMS_SRPD E1000_ICR_SRPD 763 #define E1000_IMS_ACK E1000_ICR_ACK 764 #define E1000_IMS_MNG E1000_ICR_MNG 765 #define E1000_IMS_DOCK E1000_ICR_DOCK 766 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 768 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 770 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR 772 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR 774 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 776 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 778 #define E1000_IMS_DSW E1000_ICR_DSW 779 #define E1000_IMS_PHYINT E1000_ICR_PHYINT 780 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC 781 #define E1000_IMS_EPRST E1000_ICR_EPRST 784 #define E1000_ICS_TXDW E1000_ICR_TXDW 785 #define E1000_ICS_TXQE E1000_ICR_TXQE 786 #define E1000_ICS_LSC E1000_ICR_LSC 787 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ 788 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 789 #define E1000_ICS_RXO E1000_ICR_RXO 790 #define E1000_ICS_RXT0 E1000_ICR_RXT0 791 #define E1000_ICS_MDAC E1000_ICR_MDAC 792 #define E1000_ICS_RXCFG E1000_ICR_RXCFG 793 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 794 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 795 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 796 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 797 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 798 #define E1000_ICS_SRPD E1000_ICR_SRPD 799 #define E1000_ICS_ACK E1000_ICR_ACK 800 #define E1000_ICS_MNG E1000_ICR_MNG 801 #define E1000_ICS_DOCK E1000_ICR_DOCK 802 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 804 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 806 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR 808 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR 810 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 812 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 814 #define E1000_ICS_DSW E1000_ICR_DSW 815 #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC 816 #define E1000_ICS_PHYINT E1000_ICR_PHYINT 817 #define E1000_ICS_EPRST E1000_ICR_EPRST 820 #define E1000_TXDCTL_PTHRESH 0x0000003F 821 #define E1000_TXDCTL_HTHRESH 0x00003F00 822 #define E1000_TXDCTL_WTHRESH 0x003F0000 823 #define E1000_TXDCTL_GRAN 0x01000000 824 #define E1000_TXDCTL_LWTHRESH 0xFE000000 825 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 826 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F 828 #define E1000_TXDCTL_COUNT_DESC 0x00400000 831 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 832 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 833 #define FLOW_CONTROL_TYPE 0x8808 836 #define VLAN_TAG_SIZE 4 837 #define E1000_VLAN_FILTER_TBL_SIZE 128 847 #define E1000_RAR_ENTRIES 15 848 #define E1000_RAH_AV 0x80000000 849 #define E1000_RAL_MAC_ADDR_LEN 4 850 #define E1000_RAH_MAC_ADDR_LEN 2 851 #define E1000_RAH_POOL_MASK 0x03FC0000 852 #define E1000_RAH_POOL_1 0x00040000 855 #define E1000_SUCCESS 0 856 #define E1000_ERR_NVM 1 857 #define E1000_ERR_PHY 2 858 #define E1000_ERR_CONFIG 3 859 #define E1000_ERR_PARAM 4 860 #define E1000_ERR_MAC_INIT 5 861 #define E1000_ERR_PHY_TYPE 6 862 #define E1000_ERR_RESET 9 863 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 864 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 865 #define E1000_BLK_PHY_RESET 12 866 #define E1000_ERR_SWFW_SYNC 13 867 #define E1000_NOT_IMPLEMENTED 14 868 #define E1000_ERR_MBX 15 871 #define FIBER_LINK_UP_LIMIT 50 872 #define COPPER_LINK_UP_LIMIT 10 873 #define PHY_AUTO_NEG_LIMIT 45 874 #define PHY_FORCE_LIMIT 20 876 #define MASTER_DISABLE_TIMEOUT 800 878 #define PHY_CFG_TIMEOUT 100 880 #define MDIO_OWNERSHIP_TIMEOUT 10 882 #define AUTO_READ_DONE_TIMEOUT 10 885 #define E1000_FCRTH_RTH 0x0000FFF8 886 #define E1000_FCRTH_XFCE 0x80000000 887 #define E1000_FCRTL_RTL 0x0000FFF8 888 #define E1000_FCRTL_XONE 0x80000000 891 #define E1000_TXCW_FD 0x00000020 892 #define E1000_TXCW_HD 0x00000040 893 #define E1000_TXCW_PAUSE 0x00000080 894 #define E1000_TXCW_ASM_DIR 0x00000100 895 #define E1000_TXCW_PAUSE_MASK 0x00000180 896 #define E1000_TXCW_RF 0x00003000 897 #define E1000_TXCW_NP 0x00008000 898 #define E1000_TXCW_CW 0x0000ffff 899 #define E1000_TXCW_TXC 0x40000000 900 #define E1000_TXCW_ANE 0x80000000 903 #define E1000_RXCW_CW 0x0000ffff 904 #define E1000_RXCW_NC 0x04000000 905 #define E1000_RXCW_IV 0x08000000 906 #define E1000_RXCW_CC 0x10000000 907 #define E1000_RXCW_C 0x20000000 908 #define E1000_RXCW_SYNCH 0x40000000 909 #define E1000_RXCW_ANC 0x80000000 913 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 914 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 915 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 916 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 917 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 918 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 919 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 920 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 921 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 922 #define E1000_GCR_CAP_VER2 0x00040000 924 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 925 E1000_GCR_RXDSCW_NO_SNOOP | \ 926 E1000_GCR_RXDSCR_NO_SNOOP | \ 927 E1000_GCR_TXD_NO_SNOOP | \ 928 E1000_GCR_TXDSCW_NO_SNOOP | \ 929 E1000_GCR_TXDSCR_NO_SNOOP) 932 #define MII_CR_SPEED_SELECT_MSB 0x0040 933 #define MII_CR_COLL_TEST_ENABLE 0x0080 934 #define MII_CR_FULL_DUPLEX 0x0100 935 #define MII_CR_RESTART_AUTO_NEG 0x0200 936 #define MII_CR_ISOLATE 0x0400 937 #define MII_CR_POWER_DOWN 0x0800 938 #define MII_CR_AUTO_NEG_EN 0x1000 939 #define MII_CR_SPEED_SELECT_LSB 0x2000 940 #define MII_CR_LOOPBACK 0x4000 941 #define MII_CR_RESET 0x8000 942 #define MII_CR_SPEED_1000 0x0040 943 #define MII_CR_SPEED_100 0x2000 944 #define MII_CR_SPEED_10 0x0000 947 #define MII_SR_EXTENDED_CAPS 0x0001 948 #define MII_SR_JABBER_DETECT 0x0002 949 #define MII_SR_LINK_STATUS 0x0004 950 #define MII_SR_AUTONEG_CAPS 0x0008 951 #define MII_SR_REMOTE_FAULT 0x0010 952 #define MII_SR_AUTONEG_COMPLETE 0x0020 953 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 954 #define MII_SR_EXTENDED_STATUS 0x0100 955 #define MII_SR_100T2_HD_CAPS 0x0200 956 #define MII_SR_100T2_FD_CAPS 0x0400 957 #define MII_SR_10T_HD_CAPS 0x0800 958 #define MII_SR_10T_FD_CAPS 0x1000 959 #define MII_SR_100X_HD_CAPS 0x2000 960 #define MII_SR_100X_FD_CAPS 0x4000 961 #define MII_SR_100T4_CAPS 0x8000 964 #define NWAY_AR_SELECTOR_FIELD 0x0001 965 #define NWAY_AR_10T_HD_CAPS 0x0020 966 #define NWAY_AR_10T_FD_CAPS 0x0040 967 #define NWAY_AR_100TX_HD_CAPS 0x0080 968 #define NWAY_AR_100TX_FD_CAPS 0x0100 969 #define NWAY_AR_100T4_CAPS 0x0200 970 #define NWAY_AR_PAUSE 0x0400 971 #define NWAY_AR_ASM_DIR 0x0800 972 #define NWAY_AR_REMOTE_FAULT 0x2000 973 #define NWAY_AR_NEXT_PAGE 0x8000 976 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 977 #define NWAY_LPAR_10T_HD_CAPS 0x0020 978 #define NWAY_LPAR_10T_FD_CAPS 0x0040 979 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 980 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 981 #define NWAY_LPAR_100T4_CAPS 0x0200 982 #define NWAY_LPAR_PAUSE 0x0400 983 #define NWAY_LPAR_ASM_DIR 0x0800 984 #define NWAY_LPAR_REMOTE_FAULT 0x2000 985 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 986 #define NWAY_LPAR_NEXT_PAGE 0x8000 989 #define NWAY_ER_LP_NWAY_CAPS 0x0001 990 #define NWAY_ER_PAGE_RXD 0x0002 991 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 992 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 993 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 996 #define CR_1000T_ASYM_PAUSE 0x0080 997 #define CR_1000T_HD_CAPS 0x0100 998 #define CR_1000T_FD_CAPS 0x0200 999 #define CR_1000T_REPEATER_DTE 0x0400 1001 #define CR_1000T_MS_VALUE 0x0800 1003 #define CR_1000T_MS_ENABLE 0x1000 1005 #define CR_1000T_TEST_MODE_NORMAL 0x0000 1006 #define CR_1000T_TEST_MODE_1 0x2000 1007 #define CR_1000T_TEST_MODE_2 0x4000 1008 #define CR_1000T_TEST_MODE_3 0x6000 1009 #define CR_1000T_TEST_MODE_4 0x8000 1012 #define SR_1000T_IDLE_ERROR_CNT 0x00FF 1013 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 1014 #define SR_1000T_LP_HD_CAPS 0x0400 1015 #define SR_1000T_LP_FD_CAPS 0x0800 1016 #define SR_1000T_REMOTE_RX_STATUS 0x1000 1017 #define SR_1000T_LOCAL_RX_STATUS 0x2000 1018 #define SR_1000T_MS_CONFIG_RES 0x4000 1019 #define SR_1000T_MS_CONFIG_FAULT 0x8000 1021 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1025 #define PHY_CONTROL 0x00 1026 #define PHY_STATUS 0x01 1027 #define PHY_ID1 0x02 1028 #define PHY_ID2 0x03 1029 #define PHY_AUTONEG_ADV 0x04 1030 #define PHY_LP_ABILITY 0x05 1031 #define PHY_AUTONEG_EXP 0x06 1032 #define PHY_NEXT_PAGE_TX 0x07 1033 #define PHY_LP_NEXT_PAGE 0x08 1034 #define PHY_1000T_CTRL 0x09 1035 #define PHY_1000T_STATUS 0x0A 1036 #define PHY_EXT_STATUS 0x0F 1038 #define PHY_CONTROL_LB 0x4000 1041 #define E1000_EECD_SK 0x00000001 1042 #define E1000_EECD_CS 0x00000002 1043 #define E1000_EECD_DI 0x00000004 1044 #define E1000_EECD_DO 0x00000008 1045 #define E1000_EECD_FWE_MASK 0x00000030 1046 #define E1000_EECD_FWE_DIS 0x00000010 1047 #define E1000_EECD_FWE_EN 0x00000020 1048 #define E1000_EECD_FWE_SHIFT 4 1049 #define E1000_EECD_REQ 0x00000040 1050 #define E1000_EECD_GNT 0x00000080 1051 #define E1000_EECD_PRES 0x00000100 1052 #define E1000_EECD_SIZE 0x00000200 1054 #define E1000_EECD_ADDR_BITS 0x00000400 1055 #define E1000_EECD_TYPE 0x00002000 1056 #define E1000_NVM_GRANT_ATTEMPTS 1000 1057 #define E1000_EECD_AUTO_RD 0x00000200 1058 #define E1000_EECD_SIZE_EX_MASK 0x00007800 1059 #define E1000_EECD_SIZE_EX_SHIFT 11 1060 #define E1000_EECD_NVADDS 0x00018000 1061 #define E1000_EECD_SELSHAD 0x00020000 1062 #define E1000_EECD_INITSRAM 0x00040000 1063 #define E1000_EECD_FLUPD 0x00080000 1064 #define E1000_EECD_AUPDEN 0x00100000 1065 #define E1000_EECD_SHADV 0x00200000 1066 #define E1000_EECD_SEC1VAL 0x00400000 1067 #define E1000_EECD_SECVAL_SHIFT 22 1068 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1070 #define E1000_NVM_SWDPIN0 0x0001 1071 #define E1000_NVM_LED_LOGIC 0x0020 1072 #define E1000_NVM_RW_REG_DATA 16 1073 #define E1000_NVM_RW_REG_DONE 2 1074 #define E1000_NVM_RW_REG_START 1 1075 #define E1000_NVM_RW_ADDR_SHIFT 2 1076 #define E1000_NVM_POLL_WRITE 1 1077 #define E1000_NVM_POLL_READ 0 1078 #define E1000_FLASH_UPDATES 2000 1081 #define NVM_COMPAT 0x0003 1082 #define NVM_ID_LED_SETTINGS 0x0004 1083 #define NVM_VERSION 0x0005 1084 #define NVM_SERDES_AMPLITUDE 0x0006 1085 #define NVM_PHY_CLASS_WORD 0x0007 1086 #define NVM_INIT_CONTROL1_REG 0x000A 1087 #define NVM_INIT_CONTROL2_REG 0x000F 1088 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 1089 #define NVM_INIT_CONTROL3_PORT_B 0x0014 1090 #define NVM_INIT_3GIO_3 0x001A 1091 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1092 #define NVM_INIT_CONTROL3_PORT_A 0x0024 1093 #define NVM_CFG 0x0012 1094 #define NVM_FLASH_VERSION 0x0032 1095 #define NVM_ALT_MAC_ADDR_PTR 0x0037 1096 #define NVM_CHECKSUM_REG 0x003F 1098 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 1099 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 1102 #define NVM_WORD0F_PAUSE_MASK 0x3000 1103 #define NVM_WORD0F_PAUSE 0x1000 1104 #define NVM_WORD0F_ASM_DIR 0x2000 1105 #define NVM_WORD0F_ANE 0x0800 1106 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1107 #define NVM_WORD0F_LPLU 0x0001 1110 #define NVM_WORD1A_ASPM_MASK 0x000C 1113 #define NVM_SUM 0xBABA 1115 #define NVM_MAC_ADDR_OFFSET 0 1116 #define NVM_PBA_OFFSET_0 8 1117 #define NVM_PBA_OFFSET_1 9 1118 #define NVM_RESERVED_WORD 0xFFFF 1119 #define NVM_PHY_CLASS_A 0x8000 1120 #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1121 #define NVM_SIZE_MASK 0x1C00 1122 #define NVM_SIZE_SHIFT 10 1123 #define NVM_WORD_SIZE_BASE_SHIFT 6 1124 #define NVM_SWDPIO_EXT_SHIFT 4 1127 #define NVM_MAX_RETRY_SPI 5000 1128 #define NVM_READ_OPCODE_SPI 0x03 1129 #define NVM_WRITE_OPCODE_SPI 0x02 1130 #define NVM_A8_OPCODE_SPI 0x08 1131 #define NVM_WREN_OPCODE_SPI 0x06 1132 #define NVM_WRDI_OPCODE_SPI 0x04 1133 #define NVM_RDSR_OPCODE_SPI 0x05 1134 #define NVM_WRSR_OPCODE_SPI 0x01 1137 #define NVM_STATUS_RDY_SPI 0x01 1138 #define NVM_STATUS_WEN_SPI 0x02 1139 #define NVM_STATUS_BP0_SPI 0x04 1140 #define NVM_STATUS_BP1_SPI 0x08 1141 #define NVM_STATUS_WPEN_SPI 0x80 1144 #define ID_LED_RESERVED_0000 0x0000 1145 #define ID_LED_RESERVED_FFFF 0xFFFF 1146 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1147 (ID_LED_OFF1_OFF2 << 8) | \ 1148 (ID_LED_DEF1_DEF2 << 4) | \ 1150 #define ID_LED_DEF1_DEF2 0x1 1151 #define ID_LED_DEF1_ON2 0x2 1152 #define ID_LED_DEF1_OFF2 0x3 1153 #define ID_LED_ON1_DEF2 0x4 1154 #define ID_LED_ON1_ON2 0x5 1155 #define ID_LED_ON1_OFF2 0x6 1156 #define ID_LED_OFF1_DEF2 0x7 1157 #define ID_LED_OFF1_ON2 0x8 1158 #define ID_LED_OFF1_OFF2 0x9 1160 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1161 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1162 #define IGP_LED3_MODE 0x07000000 1165 #define PCI_HEADER_TYPE_REGISTER 0x0E 1166 #define PCIE_LINK_STATUS 0x12 1167 #define PCIE_DEVICE_CONTROL2 0x28 1169 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1170 #define PCIE_LINK_WIDTH_MASK 0x3F0 1171 #define PCIE_LINK_WIDTH_SHIFT 4 1172 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1174 #ifndef ETH_ADDR_LEN 1175 #define ETH_ADDR_LEN 6 1178 #define PHY_REVISION_MASK 0xFFFFFFF0 1179 #define MAX_PHY_REG_ADDRESS 0x1F 1180 #define MAX_PHY_MULTI_PAGE_REG 0xF 1187 #define M88E1000_E_PHY_ID 0x01410C50 1188 #define M88E1000_I_PHY_ID 0x01410C30 1189 #define M88E1011_I_PHY_ID 0x01410C20 1190 #define IGP01E1000_I_PHY_ID 0x02A80380 1191 #define M88E1011_I_REV_4 0x04 1192 #define M88E1111_I_PHY_ID 0x01410CC0 1193 #define GG82563_E_PHY_ID 0x01410CA0 1194 #define IGP03E1000_E_PHY_ID 0x02A80390 1195 #define IFE_E_PHY_ID 0x02A80330 1196 #define IFE_PLUS_E_PHY_ID 0x02A80320 1197 #define IFE_C_E_PHY_ID 0x02A80310 1198 #define M88_VENDOR 0x0141 1201 #define M88E1000_PHY_SPEC_CTRL 0x10 1202 #define M88E1000_PHY_SPEC_STATUS 0x11 1203 #define M88E1000_INT_ENABLE 0x12 1204 #define M88E1000_INT_STATUS 0x13 1205 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 1206 #define M88E1000_RX_ERR_CNTR 0x15 1208 #define M88E1000_PHY_EXT_CTRL 0x1A 1209 #define M88E1000_PHY_PAGE_SELECT 0x1D 1210 #define M88E1000_PHY_GEN_CONTROL 0x1E 1211 #define M88E1000_PHY_VCO_REG_BIT8 0x100 1212 #define M88E1000_PHY_VCO_REG_BIT11 0x800 1215 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 1216 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 1217 #define M88E1000_PSCR_SQE_TEST 0x0004 1219 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 1220 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 1222 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 1224 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 1226 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 1231 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 1233 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1234 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 1235 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 1236 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 1239 #define M88E1000_PSSR_JABBER 0x0001 1240 #define M88E1000_PSSR_REV_POLARITY 0x0002 1241 #define M88E1000_PSSR_DOWNSHIFT 0x0020 1242 #define M88E1000_PSSR_MDIX 0x0040 1250 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 1251 #define M88E1000_PSSR_LINK 0x0400 1252 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 1253 #define M88E1000_PSSR_PAGE_RCVD 0x1000 1254 #define M88E1000_PSSR_DPLX 0x2000 1255 #define M88E1000_PSSR_SPEED 0xC000 1256 #define M88E1000_PSSR_10MBS 0x0000 1257 #define M88E1000_PSSR_100MBS 0x4000 1258 #define M88E1000_PSSR_1000MBS 0x8000 1260 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1263 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 1270 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 1275 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1276 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1277 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1278 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1279 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1284 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1285 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1286 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1287 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1288 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1289 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 1290 #define M88E1000_EPSCR_TX_CLK_25 0x0070 1291 #define M88E1000_EPSCR_TX_CLK_0 0x0000 1294 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1295 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 1296 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 1297 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 1298 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 1299 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1300 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 1301 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 1302 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 1309 #define GG82563_PAGE_SHIFT 5 1310 #define GG82563_REG(page, reg) \ 1311 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1312 #define GG82563_MIN_ALT_REG 30 1315 #define GG82563_PHY_SPEC_CTRL \ 1317 #define GG82563_PHY_SPEC_STATUS \ 1319 #define GG82563_PHY_INT_ENABLE \ 1321 #define GG82563_PHY_SPEC_STATUS_2 \ 1323 #define GG82563_PHY_RX_ERR_CNTR \ 1325 #define GG82563_PHY_PAGE_SELECT \ 1327 #define GG82563_PHY_SPEC_CTRL_2 \ 1329 #define GG82563_PHY_PAGE_SELECT_ALT \ 1331 #define GG82563_PHY_TEST_CLK_CTRL \ 1334 #define GG82563_PHY_MAC_SPEC_CTRL \ 1336 #define GG82563_PHY_MAC_SPEC_CTRL_2 \ 1339 #define GG82563_PHY_DSP_DISTANCE \ 1343 #define GG82563_PHY_KMRN_MODE_CTRL \ 1344 GG82563_REG(193, 16) 1345 #define GG82563_PHY_PORT_RESET \ 1346 GG82563_REG(193, 17) 1347 #define GG82563_PHY_REVISION_ID \ 1348 GG82563_REG(193, 18) 1349 #define GG82563_PHY_DEVICE_ID \ 1350 GG82563_REG(193, 19) 1351 #define GG82563_PHY_PWR_MGMT_CTRL \ 1352 GG82563_REG(193, 20) 1353 #define GG82563_PHY_RATE_ADAPT_CTRL \ 1354 GG82563_REG(193, 25) 1357 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ 1358 GG82563_REG(194, 16) 1359 #define GG82563_PHY_KMRN_CTRL \ 1360 GG82563_REG(194, 17) 1361 #define GG82563_PHY_INBAND_CTRL \ 1362 GG82563_REG(194, 18) 1363 #define GG82563_PHY_KMRN_DIAGNOSTIC \ 1364 GG82563_REG(194, 19) 1365 #define GG82563_PHY_ACK_TIMEOUTS \ 1366 GG82563_REG(194, 20) 1367 #define GG82563_PHY_ADV_ABILITY \ 1368 GG82563_REG(194, 21) 1369 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ 1370 GG82563_REG(194, 23) 1371 #define GG82563_PHY_ADV_NEXT_PAGE \ 1372 GG82563_REG(194, 24) 1373 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ 1374 GG82563_REG(194, 25) 1375 #define GG82563_PHY_KMRN_MISC \ 1376 GG82563_REG(194, 26) 1379 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1380 #define E1000_MDIC_REG_MASK 0x001F0000 1381 #define E1000_MDIC_REG_SHIFT 16 1382 #define E1000_MDIC_PHY_MASK 0x03E00000 1383 #define E1000_MDIC_PHY_SHIFT 21 1384 #define E1000_MDIC_OP_WRITE 0x04000000 1385 #define E1000_MDIC_OP_READ 0x08000000 1386 #define E1000_MDIC_READY 0x10000000 1387 #define E1000_MDIC_INT_EN 0x20000000 1388 #define E1000_MDIC_ERROR 0x40000000 1391 #define E1000_GEN_CTL_READY 0x80000000 1392 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 1393 #define E1000_GEN_POLL_TIMEOUT 640