iPXE
igbvf_vf.h
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00001 /*******************************************************************************
00002 
00003   Intel(R) 82576 Virtual Function Linux driver
00004   Copyright(c) 1999 - 2008 Intel Corporation.
00005 
00006   This program is free software; you can redistribute it and/or modify it
00007   under the terms and conditions of the GNU General Public License,
00008   version 2, as published by the Free Software Foundation.
00009 
00010   This program is distributed in the hope it will be useful, but WITHOUT
00011   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
00012   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
00013   more details.
00014 
00015   You should have received a copy of the GNU General Public License along with
00016   this program; if not, write to the Free Software Foundation, Inc.,
00017   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
00018 
00019   The full GNU General Public License is included in this distribution in
00020   the file called "COPYING".
00021 
00022   Contact Information:
00023   Linux NICS <linux.nics@intel.com>
00024   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
00025   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
00026 
00027 *******************************************************************************/
00028 
00029 FILE_LICENCE ( GPL2_ONLY );
00030 
00031 #ifndef _IGBVF_VF_H_
00032 #define _IGBVF_VF_H_
00033 
00034 #include <stddef.h>
00035 #include <stdint.h>
00036 #include <stdlib.h>
00037 #include <stdio.h>
00038 #include <string.h>
00039 #include <unistd.h>
00040 #include <byteswap.h>
00041 #include <errno.h>
00042 #include <ipxe/pci.h>
00043 #include <ipxe/malloc.h>
00044 #include <ipxe/if_ether.h>
00045 #include <ipxe/io.h>
00046 #include <ipxe/ethernet.h>
00047 #include <ipxe/iobuf.h>
00048 #include <ipxe/netdevice.h>
00049 
00050 #include "igbvf_osdep.h"
00051 #include "igbvf_regs.h"
00052 #include "igbvf_defines.h"
00053 
00054 struct e1000_hw;
00055 
00056 #define E1000_DEV_ID_82576_VF                 0x10CA
00057 #define E1000_DEV_ID_I350_VF                  0x1520
00058 
00059 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
00060 
00061 /* Additional Descriptor Control definitions */
00062 #define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
00063 #define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
00064 
00065 /* SRRCTL bit definitions */
00066 #define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
00067 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
00068 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
00069 #define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
00070 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
00071 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
00072 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
00073 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
00074 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
00075 #define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
00076 #define E1000_SRRCTL_DROP_EN                            0x80000000
00077 
00078 #define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
00079 #define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
00080 
00081 /* Interrupt Defines */
00082 #define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
00083 #define E1000_EITR(_n) (0x01680 + ((_n) << 2))
00084 #define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
00085 #define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
00086 #define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
00087 #define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
00088 #define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
00089 #define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
00090 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
00091 #define E1000_IVAR_VALID        0x80
00092 
00093 /* Receive Descriptor - Advanced */
00094 union e1000_adv_rx_desc {
00095         struct {
00096                 u64 pkt_addr;             /* Packet buffer address */
00097                 u64 hdr_addr;             /* Header buffer address */
00098         } read;
00099         struct {
00100                 struct {
00101                         union {
00102                                 u32 data;
00103                                 struct {
00104                                         u16 pkt_info; /* RSS type, Packet type */
00105                                         u16 hdr_info; /* Split Header,
00106                                                        * header buffer length */
00107                                 } hs_rss;
00108                         } lo_dword;
00109                         union {
00110                                 u32 rss;          /* RSS Hash */
00111                                 struct {
00112                                         u16 ip_id;    /* IP id */
00113                                         u16 csum;     /* Packet Checksum */
00114                                 } csum_ip;
00115                         } hi_dword;
00116                 } lower;
00117                 struct {
00118                         u32 status_error;     /* ext status/error */
00119                         u16 length;           /* Packet length */
00120                         u16 vlan;             /* VLAN tag */
00121                 } upper;
00122         } wb;  /* writeback */
00123 };
00124 
00125 #define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
00126 #define E1000_RXDADV_HDRBUFLEN_SHIFT     5
00127 
00128 /* Transmit Descriptor - Advanced */
00129 union e1000_adv_tx_desc {
00130         struct {
00131                 u64 buffer_addr;    /* Address of descriptor's data buf */
00132                 u32 cmd_type_len;
00133                 u32 olinfo_status;
00134         } read;
00135         struct {
00136                 u64 rsvd;       /* Reserved */
00137                 u32 nxtseq_seed;
00138                 u32 status;
00139         } wb;
00140 };
00141 
00142 /* Adv Transmit Descriptor Config Masks */
00143 #define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
00144 #define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
00145 #define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
00146 #define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
00147 #define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
00148 #define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
00149 #define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
00150 #define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
00151 #define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
00152 
00153 /* Context descriptors */
00154 struct e1000_adv_tx_context_desc {
00155         u32 vlan_macip_lens;
00156         u32 seqnum_seed;
00157         u32 type_tucmd_mlhl;
00158         u32 mss_l4len_idx;
00159 };
00160 
00161 #define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
00162 #define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
00163 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
00164 #define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
00165 #define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
00166 
00167 enum e1000_mac_type {
00168         e1000_undefined = 0,
00169         e1000_vfadapt,
00170         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
00171 };
00172 
00173 struct e1000_vf_stats {
00174         u64 base_gprc;
00175         u64 base_gptc;
00176         u64 base_gorc;
00177         u64 base_gotc;
00178         u64 base_mprc;
00179         u64 base_gotlbc;
00180         u64 base_gptlbc;
00181         u64 base_gorlbc;
00182         u64 base_gprlbc;
00183 
00184         u32 last_gprc;
00185         u32 last_gptc;
00186         u32 last_gorc;
00187         u32 last_gotc;
00188         u32 last_mprc;
00189         u32 last_gotlbc;
00190         u32 last_gptlbc;
00191         u32 last_gorlbc;
00192         u32 last_gprlbc;
00193 
00194         u64 gprc;
00195         u64 gptc;
00196         u64 gorc;
00197         u64 gotc;
00198         u64 mprc;
00199         u64 gotlbc;
00200         u64 gptlbc;
00201         u64 gorlbc;
00202         u64 gprlbc;
00203 };
00204 
00205 #include "igbvf_mbx.h"
00206 
00207 struct e1000_mac_operations {
00208         /* Function pointers for the MAC. */
00209         s32  (*init_params)(struct e1000_hw *);
00210         s32  (*check_for_link)(struct e1000_hw *);
00211         void (*clear_vfta)(struct e1000_hw *);
00212         s32  (*get_bus_info)(struct e1000_hw *);
00213         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
00214         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
00215         s32  (*reset_hw)(struct e1000_hw *);
00216         s32  (*init_hw)(struct e1000_hw *);
00217         s32  (*setup_link)(struct e1000_hw *);
00218         void (*write_vfta)(struct e1000_hw *, u32, u32);
00219         void (*mta_set)(struct e1000_hw *, u32);
00220         void (*rar_set)(struct e1000_hw *, u8*, u32);
00221         s32  (*read_mac_addr)(struct e1000_hw *);
00222 };
00223 
00224 struct e1000_mac_info {
00225         struct e1000_mac_operations ops;
00226         u8 addr[6];
00227         u8 perm_addr[6];
00228 
00229         enum e1000_mac_type type;
00230 
00231         u16 mta_reg_count;
00232         u16 rar_entry_count;
00233 
00234         bool get_link_status;
00235 };
00236 
00237 enum e1000_bus_type {
00238         e1000_bus_type_unknown = 0,
00239         e1000_bus_type_pci,
00240         e1000_bus_type_pcix,
00241         e1000_bus_type_pci_express,
00242         e1000_bus_type_reserved
00243 };
00244 
00245 enum e1000_bus_speed {
00246         e1000_bus_speed_unknown = 0,
00247         e1000_bus_speed_33,
00248         e1000_bus_speed_66,
00249         e1000_bus_speed_100,
00250         e1000_bus_speed_120,
00251         e1000_bus_speed_133,
00252         e1000_bus_speed_2500,
00253         e1000_bus_speed_5000,
00254         e1000_bus_speed_reserved
00255 };
00256 
00257 enum e1000_bus_width {
00258         e1000_bus_width_unknown = 0,
00259         e1000_bus_width_pcie_x1,
00260         e1000_bus_width_pcie_x2,
00261         e1000_bus_width_pcie_x4 = 4,
00262         e1000_bus_width_pcie_x8 = 8,
00263         e1000_bus_width_32,
00264         e1000_bus_width_64,
00265         e1000_bus_width_reserved
00266 };
00267 
00268 struct e1000_bus_info {
00269         enum e1000_bus_type type;
00270         enum e1000_bus_speed speed;
00271         enum e1000_bus_width width;
00272 
00273         u16 func;
00274         u16 pci_cmd_word;
00275 };
00276 
00277 struct e1000_mbx_operations {
00278         s32 (*init_params)(struct e1000_hw *hw);
00279         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
00280         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
00281         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
00282         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
00283         s32 (*check_for_msg)(struct e1000_hw *, u16);
00284         s32 (*check_for_ack)(struct e1000_hw *, u16);
00285         s32 (*check_for_rst)(struct e1000_hw *, u16);
00286 };
00287 
00288 struct e1000_mbx_stats {
00289         u32 msgs_tx;
00290         u32 msgs_rx;
00291 
00292         u32 acks;
00293         u32 reqs;
00294         u32 rsts;
00295 };
00296 
00297 struct e1000_mbx_info {
00298         struct e1000_mbx_operations ops;
00299         struct e1000_mbx_stats stats;
00300         u32 timeout;
00301         u32 usec_delay;
00302         u16 size;
00303 };
00304 
00305 struct e1000_dev_spec_vf {
00306         u32     vf_number;
00307         u32     v2p_mailbox;
00308 };
00309 
00310 struct e1000_hw {
00311         void *back;
00312 
00313         u8 __iomem *hw_addr;
00314         u8 __iomem *flash_address;
00315         unsigned long io_base;
00316 
00317         struct e1000_mac_info  mac;
00318         struct e1000_bus_info  bus;
00319         struct e1000_mbx_info mbx;
00320 
00321         union {
00322                 struct e1000_dev_spec_vf        vf;
00323         } dev_spec;
00324 
00325         u16 device_id;
00326         u16 subsystem_vendor_id;
00327         u16 subsystem_device_id;
00328         u16 vendor_id;
00329 
00330         u8  revision_id;
00331 };
00332 
00333 enum e1000_promisc_type {
00334         e1000_promisc_disabled = 0,   /* all promisc modes disabled */
00335         e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
00336         e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
00337         e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
00338         e1000_num_promisc_types
00339 };
00340 
00341 /* These functions must be implemented by drivers */
00342 s32  igbvf_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
00343 void igbvf_vfta_set_vf(struct e1000_hw *, u16, bool);
00344 void igbvf_rlpml_set_vf(struct e1000_hw *, u16);
00345 s32 igbvf_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
00346 #endif /* _IGBVF_VF_H_ */