iPXE
intelxlvf.h
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00001 #ifndef _INTELXLVF_H
00002 #define _INTELXLVF_H
00003 
00004 /** @file
00005  *
00006  * Intel 40 Gigabit Ethernet virtual function network card driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include "intelxl.h"
00013 
00014 /** BAR size */
00015 #define INTELXLVF_BAR_SIZE 0x10000
00016 
00017 /** Transmit Queue Tail Register */
00018 #define INTELXLVF_QTX_TAIL 0x00000
00019 
00020 /** Receive Queue Tail Register */
00021 #define INTELXLVF_QRX_TAIL 0x02000
00022 
00023 /** VF Interrupt Zero Dynamic Control Register */
00024 #define INTELXLVF_VFINT_DYN_CTL0 0x5c00
00025 
00026 /** VF Admin Queue register block */
00027 #define INTELXLVF_ADMIN 0x6000
00028 
00029 /** Admin Command Queue Base Address Low Register (offset) */
00030 #define INTELXLVF_ADMIN_CMD_BAL 0x1c00
00031 
00032 /** Admin Command Queue Base Address High Register (offset) */
00033 #define INTELXLVF_ADMIN_CMD_BAH 0x1800
00034 
00035 /** Admin Command Queue Length Register (offset) */
00036 #define INTELXLVF_ADMIN_CMD_LEN 0x0800
00037 
00038 /** Admin Command Queue Head Register (offset) */
00039 #define INTELXLVF_ADMIN_CMD_HEAD 0x0400
00040 
00041 /** Admin Command Queue Tail Register (offset) */
00042 #define INTELXLVF_ADMIN_CMD_TAIL 0x2400
00043 
00044 /** Admin Event Queue Base Address Low Register (offset) */
00045 #define INTELXLVF_ADMIN_EVT_BAL 0x0c00
00046 
00047 /** Admin Event Queue Base Address High Register (offset) */
00048 #define INTELXLVF_ADMIN_EVT_BAH 0x0000
00049 
00050 /** Admin Event Queue Length Register (offset) */
00051 #define INTELXLVF_ADMIN_EVT_LEN 0x2000
00052 
00053 /** Admin Event Queue Head Register (offset) */
00054 #define INTELXLVF_ADMIN_EVT_HEAD 0x1400
00055 
00056 /** Admin Event Queue Tail Register (offset) */
00057 #define INTELXLVF_ADMIN_EVT_TAIL 0x1000
00058 
00059 /** Maximum time to wait for a VF admin request to complete */
00060 #define INTELXLVF_ADMIN_MAX_WAIT_MS 2000
00061 
00062 /** VF Reset Status Register */
00063 #define INTELXLVF_VFGEN_RSTAT 0x8800
00064 #define INTELXLVF_VFGEN_RSTAT_VFR_STATE(x) ( (x) & 0x3 )
00065 #define INTELXLVF_VFGEN_RSTAT_VFR_STATE_ACTIVE 0x2
00066 
00067 /** Maximum time to wait for reset to complete */
00068 #define INTELXLVF_RESET_MAX_WAIT_MS 1000
00069 
00070 /**
00071  * Initialise descriptor ring
00072  *
00073  * @v ring              Descriptor ring
00074  * @v count             Number of descriptors
00075  * @v len               Length of a single descriptor
00076  * @v tail              Tail register offset
00077  */
00078 static inline __attribute__ (( always_inline)) void
00079 intelxlvf_init_ring ( struct intelxl_ring *ring, unsigned int count,
00080                       size_t len, unsigned int tail ) {
00081 
00082         ring->len = ( count * len );
00083         ring->tail = tail;
00084 }
00085 
00086 #endif /* _INTELXLVF_H */