iPXE
linda.h
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00001 #ifndef _LINDA_H
00002 #define _LINDA_H
00003 
00004 /*
00005  * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
00006  *
00007  * This program is free software; you can redistribute it and/or
00008  * modify it under the terms of the GNU General Public License as
00009  * published by the Free Software Foundation; either version 2 of the
00010  * License, or any later version.
00011  *
00012  * This program is distributed in the hope that it will be useful, but
00013  * WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00015  * General Public License for more details.
00016  *
00017  * You should have received a copy of the GNU General Public License
00018  * along with this program; if not, write to the Free Software
00019  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00020  * 02110-1301, USA.
00021  *
00022  * You can also choose to distribute this program under the terms of
00023  * the Unmodified Binary Distribution Licence (as given in the file
00024  * COPYING.UBDL), provided that you have satisfied its requirements.
00025  */
00026 
00027 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00028 
00029 /**
00030  * @file
00031  *
00032  * QLogic Linda Infiniband HCA
00033  *
00034  */
00035 
00036 #define PSEUDOBIT_LITTLE_ENDIAN
00037 #include <ipxe/pseudobit.h>
00038 #include "qib_7220_regs.h"
00039 
00040 struct ib_device;
00041 
00042 /** A Linda GPIO register */
00043 struct QIB_7220_GPIO_pb {
00044         pseudo_bit_t GPIO[16];
00045         pseudo_bit_t Reserved[48];
00046 };
00047 struct QIB_7220_GPIO {
00048         PSEUDO_BIT_STRUCT ( struct QIB_7220_GPIO_pb );
00049 };
00050 
00051 /** A Linda general scalar register */
00052 struct QIB_7220_scalar_pb {
00053         pseudo_bit_t Value[64];
00054 };
00055 struct QIB_7220_scalar {
00056         PSEUDO_BIT_STRUCT ( struct QIB_7220_scalar_pb );
00057 };
00058 
00059 /** Linda send per-buffer control word */
00060 struct QIB_7220_SendPbc_pb {
00061         pseudo_bit_t LengthP1_toibc[11];
00062         pseudo_bit_t Reserved1[4];
00063         pseudo_bit_t LengthP1_trigger[11];
00064         pseudo_bit_t Reserved2[3];
00065         pseudo_bit_t TestEbp[1];
00066         pseudo_bit_t Test[1];
00067         pseudo_bit_t Intr[1];
00068         pseudo_bit_t Reserved3[31];
00069         pseudo_bit_t VL15[1];
00070 };
00071 struct QIB_7220_SendPbc {
00072         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendPbc_pb );
00073 };
00074 
00075 /** Linda send buffer availability */
00076 struct QIB_7220_SendBufAvail_pb {
00077         pseudo_bit_t InUseCheck[144][2];
00078         pseudo_bit_t Reserved[32];
00079 };
00080 struct QIB_7220_SendBufAvail {
00081         PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvail_pb );
00082 };
00083 
00084 /** DMA alignment for send buffer availability */
00085 #define LINDA_SENDBUFAVAIL_ALIGN 64
00086 
00087 /** A Linda eager receive descriptor */
00088 struct QIB_7220_RcvEgr_pb {
00089         pseudo_bit_t Addr[37];
00090         pseudo_bit_t BufSize[3];
00091         pseudo_bit_t Reserved[24];
00092 };
00093 struct QIB_7220_RcvEgr {
00094         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvEgr_pb );
00095 };
00096 
00097 /** Linda receive header flags */
00098 struct QIB_7220_RcvHdrFlags_pb {
00099         pseudo_bit_t PktLen[11];
00100         pseudo_bit_t RcvType[3];
00101         pseudo_bit_t SoftB[1];
00102         pseudo_bit_t SoftA[1];
00103         pseudo_bit_t EgrIndex[12];
00104         pseudo_bit_t Reserved1[3];
00105         pseudo_bit_t UseEgrBfr[1];
00106         pseudo_bit_t RcvSeq[4];
00107         pseudo_bit_t HdrqOffset[11];
00108         pseudo_bit_t Reserved2[8];
00109         pseudo_bit_t IBErr[1];
00110         pseudo_bit_t MKErr[1];
00111         pseudo_bit_t TIDErr[1];
00112         pseudo_bit_t KHdrErr[1];
00113         pseudo_bit_t MTUErr[1];
00114         pseudo_bit_t LenErr[1];
00115         pseudo_bit_t ParityErr[1];
00116         pseudo_bit_t VCRCErr[1];
00117         pseudo_bit_t ICRCErr[1];
00118 };
00119 struct QIB_7220_RcvHdrFlags {
00120         PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrFlags_pb );
00121 };
00122 
00123 /** Linda memory BAR size */
00124 #define LINDA_BAR0_SIZE 0x400000
00125 
00126 /** Linda I2C SCL line GPIO number */
00127 #define LINDA_GPIO_SCL 0
00128 
00129 /** Linda I2C SDA line GPIO number */
00130 #define LINDA_GPIO_SDA 1
00131 
00132 /** GUID offset within EEPROM */
00133 #define LINDA_EEPROM_GUID_OFFSET 3
00134 
00135 /** GUID size within EEPROM */
00136 #define LINDA_EEPROM_GUID_SIZE 8
00137 
00138 /** Board serial number offset within EEPROM */
00139 #define LINDA_EEPROM_SERIAL_OFFSET 12
00140 
00141 /** Board serial number size within EEPROM */
00142 #define LINDA_EEPROM_SERIAL_SIZE 12
00143 
00144 /** Maximum number of send buffers used
00145  *
00146  * This is a policy decision.  Must be less than or equal to the total
00147  * number of send buffers supported by the hardware (128).
00148  */
00149 #define LINDA_MAX_SEND_BUFS 32
00150 
00151 /** Linda send buffer size */
00152 #define LINDA_SEND_BUF_SIZE 4096
00153 
00154 /** Number of contexts (including kernel context)
00155  *
00156  * This is a policy decision.  Must be 5, 9 or 17.
00157  */
00158 #define LINDA_NUM_CONTEXTS 5
00159 
00160 /** PortCfg values for different numbers of contexts */
00161 enum linda_portcfg {
00162         LINDA_PORTCFG_5CTX = 0,
00163         LINDA_PORTCFG_9CTX = 1,
00164         LINDA_PORTCFG_17CTX = 2,
00165 };
00166 
00167 /** PortCfg values for different numbers of contexts */
00168 #define LINDA_EAGER_ARRAY_SIZE_5CTX_0 2048
00169 #define LINDA_EAGER_ARRAY_SIZE_5CTX_OTHER 4096
00170 #define LINDA_EAGER_ARRAY_SIZE_9CTX_0 2048
00171 #define LINDA_EAGER_ARRAY_SIZE_9CTX_OTHER 2048
00172 #define LINDA_EAGER_ARRAY_SIZE_17CTX_0 2048
00173 #define LINDA_EAGER_ARRAY_SIZE_17CTX_OTHER 1024
00174 
00175 /** Eager buffer required alignment */
00176 #define LINDA_EAGER_BUFFER_ALIGN 2048
00177 
00178 /** Eager buffer size encodings */
00179 enum linda_eager_buffer_size {
00180         LINDA_EAGER_BUFFER_NONE = 0,
00181         LINDA_EAGER_BUFFER_2K = 1,
00182         LINDA_EAGER_BUFFER_4K = 2,
00183         LINDA_EAGER_BUFFER_8K = 3,
00184         LINDA_EAGER_BUFFER_16K = 4,
00185         LINDA_EAGER_BUFFER_32K = 5,
00186         LINDA_EAGER_BUFFER_64K = 6,
00187 };
00188 
00189 /** Number of RX headers per context
00190  *
00191  * This is a policy decision.
00192  */
00193 #define LINDA_RECV_HEADER_COUNT 8
00194 
00195 /** Maximum size of each RX header
00196  *
00197  * This is a policy decision.  Must be divisible by 4.
00198  */
00199 #define LINDA_RECV_HEADER_SIZE 96
00200 
00201 /** Total size of an RX header ring */
00202 #define LINDA_RECV_HEADERS_SIZE \
00203         ( LINDA_RECV_HEADER_SIZE * LINDA_RECV_HEADER_COUNT )
00204 
00205 /** RX header alignment */
00206 #define LINDA_RECV_HEADERS_ALIGN 64
00207 
00208 /** RX payload size
00209  *
00210  * This is a policy decision.  Must be a valid eager buffer size.
00211  */
00212 #define LINDA_RECV_PAYLOAD_SIZE 2048
00213 
00214 /** QPN used for Infinipath Packets
00215  *
00216  * This is a policy decision.  Must have bit 0 clear.  Must not be a
00217  * QPN that we will use.
00218  */
00219 #define LINDA_QP_IDETH 0xdead0
00220 
00221 /** Maximum time for wait for external parallel bus request, in us */
00222 #define LINDA_EPB_REQUEST_MAX_WAIT_US 500
00223 
00224 /** Maximum time for wait for external parallel bus transaction, in us */
00225 #define LINDA_EPB_XACT_MAX_WAIT_US 500
00226 
00227 /** Linda external parallel bus chip selects */
00228 #define LINDA_EPB_CS_SERDES 1
00229 #define LINDA_EPB_CS_UC 2
00230 
00231 /** Linda external parallel bus read/write operations */
00232 #define LINDA_EPB_WRITE 0
00233 #define LINDA_EPB_READ 1
00234 
00235 /** Linda external parallel bus register addresses */
00236 #define LINDA_EPB_ADDRESS( _channel, _element, _reg ) \
00237         ( (_element) | ( (_channel) << 4 ) | ( (_reg) << 9 ) )
00238 #define LINDA_EPB_ADDRESS_CHANNEL( _address )   ( ( (_address) >> 4 ) & 0x1f )
00239 #define LINDA_EPB_ADDRESS_ELEMENT( _address )   ( ( (_address) >> 0 ) & 0x0f )
00240 #define LINDA_EPB_ADDRESS_REG( _address )       ( ( (_address) >> 9 ) & 0x3f )
00241 
00242 /** Linda external parallel bus locations
00243  *
00244  * The location is used by the driver to encode both the chip select
00245  * and the EPB address.
00246  */
00247 #define LINDA_EPB_LOC( _cs, _channel, _element, _reg) \
00248         ( ( (_cs) << 16 ) | LINDA_EPB_ADDRESS ( _channel, _element, _reg ) )
00249 #define LINDA_EPB_LOC_ADDRESS( _loc )   ( (_loc) & 0xffff )
00250 #define LINDA_EPB_LOC_CS( _loc )        ( (_loc) >> 16 )
00251 
00252 /** Linda external parallel bus microcontroller register addresses */
00253 #define LINDA_EPB_UC_CHANNEL 6
00254 #define LINDA_EPB_UC_LOC( _reg ) \
00255         LINDA_EPB_LOC ( LINDA_EPB_CS_UC, LINDA_EPB_UC_CHANNEL, 0, (_reg) )
00256 #define LINDA_EPB_UC_CTL        LINDA_EPB_UC_LOC ( 0 )
00257 #define LINDA_EPB_UC_CTL_WRITE  1
00258 #define LINDA_EPB_UC_CTL_READ   2
00259 #define LINDA_EPB_UC_ADDR_LO    LINDA_EPB_UC_LOC ( 2 )
00260 #define LINDA_EPB_UC_ADDR_HI    LINDA_EPB_UC_LOC ( 3 )
00261 #define LINDA_EPB_UC_DATA       LINDA_EPB_UC_LOC ( 4 )
00262 #define LINDA_EPB_UC_CHUNK_SIZE 64
00263 
00264 extern uint8_t linda_ib_fw[8192];
00265 
00266 /** Maximum time to wait for "trim done" signal, in ms */
00267 #define LINDA_TRIM_DONE_MAX_WAIT_MS 1000
00268 
00269 /** Linda link states */
00270 enum linda_link_state {
00271         LINDA_LINK_STATE_DOWN = 0,
00272         LINDA_LINK_STATE_INIT = 1,
00273         LINDA_LINK_STATE_ARM = 2,
00274         LINDA_LINK_STATE_ACTIVE = 3,
00275         LINDA_LINK_STATE_ACT_DEFER = 4,
00276 };
00277 
00278 /** Maximum time to wait for link state changes, in us */
00279 #define LINDA_LINK_STATE_MAX_WAIT_US 20
00280 
00281 #endif /* _LINDA_H */