iPXE
Data Structures | Defines | Enumerations | Functions
mac.h File Reference
#include <unistd.h>

Go to the source code of this file.

Data Structures

struct  ath_tx_status
struct  ath_rx_status
struct  ath_htc_rx_status
struct  ath_desc
struct  ar5416_desc
struct  ath9k_tx_queue_info
struct  ath9k_11n_rate_series

Defines

#define RXSTATUS_RATE(ah, ads)
#define set11nTries(_series, _index)   (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
#define set11nRate(_series, _index)   (SM((_series)[_index].Rate, AR_XmitRate##_index))
#define set11nPktDurRTSCTS(_series, _index)
#define set11nRateFlags(_series, _index)
#define CCK_SIFS_TIME   10
#define CCK_PREAMBLE_BITS   144
#define CCK_PLCP_BITS   48
#define OFDM_SIFS_TIME   16
#define OFDM_PREAMBLE_TIME   20
#define OFDM_PLCP_BITS   22
#define OFDM_SYMBOL_TIME   4
#define OFDM_SIFS_TIME_HALF   32
#define OFDM_PREAMBLE_TIME_HALF   40
#define OFDM_PLCP_BITS_HALF   22
#define OFDM_SYMBOL_TIME_HALF   8
#define OFDM_SIFS_TIME_QUARTER   64
#define OFDM_PREAMBLE_TIME_QUARTER   80
#define OFDM_PLCP_BITS_QUARTER   22
#define OFDM_SYMBOL_TIME_QUARTER   16
#define INIT_AIFS   2
#define INIT_CWMIN   15
#define INIT_CWMIN_11B   31
#define INIT_CWMAX   1023
#define INIT_SH_RETRY   10
#define INIT_LG_RETRY   10
#define INIT_SSH_RETRY   32
#define INIT_SLG_RETRY   32
#define ATH9K_SLOT_TIME_6   6
#define ATH9K_SLOT_TIME_9   9
#define ATH9K_SLOT_TIME_20   20
#define ATH9K_TXERR_XRETRY   0x01
#define ATH9K_TXERR_FILT   0x02
#define ATH9K_TXERR_FIFO   0x04
#define ATH9K_TXERR_XTXOP   0x08
#define ATH9K_TXERR_TIMER_EXPIRED   0x10
#define ATH9K_TX_ACKED   0x20
#define ATH9K_TXERR_MASK
#define ATH9K_TX_BA   0x01
#define ATH9K_TX_PWRMGMT   0x02
#define ATH9K_TX_DESC_CFG_ERR   0x04
#define ATH9K_TX_DATA_UNDERRUN   0x08
#define ATH9K_TX_DELIM_UNDERRUN   0x10
#define ATH9K_TX_SW_FILTERED   0x80
#define MIN_TX_FIFO_THRESHOLD   0x1
#define MAX_TX_FIFO_THRESHOLD   ((4096 / 64) - 1)
#define ATH9K_RXERR_CRC   0x01
#define ATH9K_RXERR_PHY   0x02
#define ATH9K_RXERR_FIFO   0x04
#define ATH9K_RXERR_DECRYPT   0x08
#define ATH9K_RXERR_MIC   0x10
#define ATH9K_RX_MORE   0x01
#define ATH9K_RX_MORE_AGGR   0x02
#define ATH9K_RX_GI   0x04
#define ATH9K_RX_2040   0x08
#define ATH9K_RX_DELIM_CRC_PRE   0x10
#define ATH9K_RX_DELIM_CRC_POST   0x20
#define ATH9K_RX_DECRYPT_BUSY   0x40
#define ATH9K_RXKEYIX_INVALID   ((u8)-1)
#define ATH9K_TXKEYIX_INVALID   ((u32)-1)
#define ATH9K_TXDESC_NOACK   0x0002
#define ATH9K_TXDESC_RTSENA   0x0004
#define ATH9K_TXDESC_CTSENA   0x0008
#define ATH9K_TXDESC_INTREQ   0x0010
#define ATH9K_TXDESC_VEOL   0x0020
#define ATH9K_TXDESC_EXT_ONLY   0x0040
#define ATH9K_TXDESC_EXT_AND_CTL   0x0080
#define ATH9K_TXDESC_VMF   0x0100
#define ATH9K_TXDESC_FRAG_IS_ON   0x0200
#define ATH9K_TXDESC_LOWRXCHAIN   0x0400
#define ATH9K_TXDESC_LDPC   0x00010000
#define ATH9K_RXDESC_INTREQ   0x0020
#define AR5416DESC(_ds)   ((struct ar5416_desc *)(_ds))
#define AR5416DESC_CONST(_ds)   ((const struct ar5416_desc *)(_ds))
#define ds_ctl2   u.tx.ctl2
#define ds_ctl3   u.tx.ctl3
#define ds_ctl4   u.tx.ctl4
#define ds_ctl5   u.tx.ctl5
#define ds_ctl6   u.tx.ctl6
#define ds_ctl7   u.tx.ctl7
#define ds_ctl8   u.tx.ctl8
#define ds_ctl9   u.tx.ctl9
#define ds_ctl10   u.tx.ctl10
#define ds_ctl11   u.tx.ctl11
#define ds_txstatus0   u.tx.status0
#define ds_txstatus1   u.tx.status1
#define ds_txstatus2   u.tx.status2
#define ds_txstatus3   u.tx.status3
#define ds_txstatus4   u.tx.status4
#define ds_txstatus5   u.tx.status5
#define ds_txstatus6   u.tx.status6
#define ds_txstatus7   u.tx.status7
#define ds_txstatus8   u.tx.status8
#define ds_txstatus9   u.tx.status9
#define ds_rxstatus0   u.rx.status0
#define ds_rxstatus1   u.rx.status1
#define ds_rxstatus2   u.rx.status2
#define ds_rxstatus3   u.rx.status3
#define ds_rxstatus4   u.rx.status4
#define ds_rxstatus5   u.rx.status5
#define ds_rxstatus6   u.rx.status6
#define ds_rxstatus7   u.rx.status7
#define ds_rxstatus8   u.rx.status8
#define AR_FrameLen   0x00000fff
#define AR_VirtMoreFrag   0x00001000
#define AR_TxCtlRsvd00   0x0000e000
#define AR_XmitPower   0x003f0000
#define AR_XmitPower_S   16
#define AR_RTSEnable   0x00400000
#define AR_VEOL   0x00800000
#define AR_ClrDestMask   0x01000000
#define AR_TxCtlRsvd01   0x1e000000
#define AR_TxIntrReq   0x20000000
#define AR_DestIdxValid   0x40000000
#define AR_CTSEnable   0x80000000
#define AR_TxMore   0x00001000
#define AR_DestIdx   0x000fe000
#define AR_DestIdx_S   13
#define AR_FrameType   0x00f00000
#define AR_FrameType_S   20
#define AR_NoAck   0x01000000
#define AR_InsertTS   0x02000000
#define AR_CorruptFCS   0x04000000
#define AR_ExtOnly   0x08000000
#define AR_ExtAndCtl   0x10000000
#define AR_MoreAggr   0x20000000
#define AR_IsAggr   0x40000000
#define AR_BurstDur   0x00007fff
#define AR_BurstDur_S   0
#define AR_DurUpdateEna   0x00008000
#define AR_XmitDataTries0   0x000f0000
#define AR_XmitDataTries0_S   16
#define AR_XmitDataTries1   0x00f00000
#define AR_XmitDataTries1_S   20
#define AR_XmitDataTries2   0x0f000000
#define AR_XmitDataTries2_S   24
#define AR_XmitDataTries3   0xf0000000
#define AR_XmitDataTries3_S   28
#define AR_XmitRate0   0x000000ff
#define AR_XmitRate0_S   0
#define AR_XmitRate1   0x0000ff00
#define AR_XmitRate1_S   8
#define AR_XmitRate2   0x00ff0000
#define AR_XmitRate2_S   16
#define AR_XmitRate3   0xff000000
#define AR_XmitRate3_S   24
#define AR_PacketDur0   0x00007fff
#define AR_PacketDur0_S   0
#define AR_RTSCTSQual0   0x00008000
#define AR_PacketDur1   0x7fff0000
#define AR_PacketDur1_S   16
#define AR_RTSCTSQual1   0x80000000
#define AR_PacketDur2   0x00007fff
#define AR_PacketDur2_S   0
#define AR_RTSCTSQual2   0x00008000
#define AR_PacketDur3   0x7fff0000
#define AR_PacketDur3_S   16
#define AR_RTSCTSQual3   0x80000000
#define AR_AggrLen   0x0000ffff
#define AR_AggrLen_S   0
#define AR_TxCtlRsvd60   0x00030000
#define AR_PadDelim   0x03fc0000
#define AR_PadDelim_S   18
#define AR_EncrType   0x0c000000
#define AR_EncrType_S   26
#define AR_TxCtlRsvd61   0xf0000000
#define AR_LDPC   0x80000000
#define AR_2040_0   0x00000001
#define AR_GI0   0x00000002
#define AR_ChainSel0   0x0000001c
#define AR_ChainSel0_S   2
#define AR_2040_1   0x00000020
#define AR_GI1   0x00000040
#define AR_ChainSel1   0x00000380
#define AR_ChainSel1_S   7
#define AR_2040_2   0x00000400
#define AR_GI2   0x00000800
#define AR_ChainSel2   0x00007000
#define AR_ChainSel2_S   12
#define AR_2040_3   0x00008000
#define AR_GI3   0x00010000
#define AR_ChainSel3   0x000e0000
#define AR_ChainSel3_S   17
#define AR_RTSCTSRate   0x0ff00000
#define AR_RTSCTSRate_S   20
#define AR_STBC0   0x10000000
#define AR_STBC1   0x20000000
#define AR_STBC2   0x40000000
#define AR_STBC3   0x80000000
#define AR_TxRSSIAnt00   0x000000ff
#define AR_TxRSSIAnt00_S   0
#define AR_TxRSSIAnt01   0x0000ff00
#define AR_TxRSSIAnt01_S   8
#define AR_TxRSSIAnt02   0x00ff0000
#define AR_TxRSSIAnt02_S   16
#define AR_TxStatusRsvd00   0x3f000000
#define AR_TxBaStatus   0x40000000
#define AR_TxStatusRsvd01   0x80000000
#define AR_FrmXmitOK   0x00000001
#define AR_ExcessiveRetries   0x00000002
#define AR_FIFOUnderrun   0x00000004
#define AR_Filtered   0x00000008
#define AR_RTSFailCnt   0x000000f0
#define AR_RTSFailCnt_S   4
#define AR_DataFailCnt   0x00000f00
#define AR_DataFailCnt_S   8
#define AR_VirtRetryCnt   0x0000f000
#define AR_VirtRetryCnt_S   12
#define AR_TxDelimUnderrun   0x00010000
#define AR_TxDataUnderrun   0x00020000
#define AR_DescCfgErr   0x00040000
#define AR_TxTimerExpired   0x00080000
#define AR_TxStatusRsvd10   0xfff00000
#define AR_SendTimestamp   ds_txstatus2
#define AR_BaBitmapLow   ds_txstatus3
#define AR_BaBitmapHigh   ds_txstatus4
#define AR_TxRSSIAnt10   0x000000ff
#define AR_TxRSSIAnt10_S   0
#define AR_TxRSSIAnt11   0x0000ff00
#define AR_TxRSSIAnt11_S   8
#define AR_TxRSSIAnt12   0x00ff0000
#define AR_TxRSSIAnt12_S   16
#define AR_TxRSSICombined   0xff000000
#define AR_TxRSSICombined_S   24
#define AR_TxTid   0xf0000000
#define AR_TxTid_S   28
#define AR_TxEVM0   ds_txstatus5
#define AR_TxEVM1   ds_txstatus6
#define AR_TxEVM2   ds_txstatus7
#define AR_TxDone   0x00000001
#define AR_SeqNum   0x00001ffe
#define AR_SeqNum_S   1
#define AR_TxStatusRsvd80   0x0001e000
#define AR_TxOpExceeded   0x00020000
#define AR_TxStatusRsvd81   0x001c0000
#define AR_FinalTxIdx   0x00600000
#define AR_FinalTxIdx_S   21
#define AR_TxStatusRsvd82   0x01800000
#define AR_PowerMgmt   0x02000000
#define AR_TxStatusRsvd83   0xfc000000
#define AR_RxCTLRsvd00   0xffffffff
#define AR_RxCtlRsvd00   0x00001000
#define AR_RxIntrReq   0x00002000
#define AR_RxCtlRsvd01   0xffffc000
#define AR_RxRSSIAnt00   0x000000ff
#define AR_RxRSSIAnt00_S   0
#define AR_RxRSSIAnt01   0x0000ff00
#define AR_RxRSSIAnt01_S   8
#define AR_RxRSSIAnt02   0x00ff0000
#define AR_RxRSSIAnt02_S   16
#define AR_RxRate   0xff000000
#define AR_RxRate_S   24
#define AR_RxStatusRsvd00   0xff000000
#define AR_DataLen   0x00000fff
#define AR_RxMore   0x00001000
#define AR_NumDelim   0x003fc000
#define AR_NumDelim_S   14
#define AR_RxStatusRsvd10   0xff800000
#define AR_RcvTimestamp   ds_rxstatus2
#define AR_GI   0x00000001
#define AR_2040   0x00000002
#define AR_Parallel40   0x00000004
#define AR_Parallel40_S   2
#define AR_RxStatusRsvd30   0x000000f8
#define AR_RxAntenna   0xffffff00
#define AR_RxAntenna_S   8
#define AR_RxRSSIAnt10   0x000000ff
#define AR_RxRSSIAnt10_S   0
#define AR_RxRSSIAnt11   0x0000ff00
#define AR_RxRSSIAnt11_S   8
#define AR_RxRSSIAnt12   0x00ff0000
#define AR_RxRSSIAnt12_S   16
#define AR_RxRSSICombined   0xff000000
#define AR_RxRSSICombined_S   24
#define AR_RxEVM0   ds_rxstatus4
#define AR_RxEVM1   ds_rxstatus5
#define AR_RxEVM2   ds_rxstatus6
#define AR_RxDone   0x00000001
#define AR_RxFrameOK   0x00000002
#define AR_CRCErr   0x00000004
#define AR_DecryptCRCErr   0x00000008
#define AR_PHYErr   0x00000010
#define AR_MichaelErr   0x00000020
#define AR_PreDelimCRCErr   0x00000040
#define AR_RxStatusRsvd70   0x00000080
#define AR_RxKeyIdxValid   0x00000100
#define AR_KeyIdx   0x0000fe00
#define AR_KeyIdx_S   9
#define AR_PHYErrCode   0x0000ff00
#define AR_PHYErrCode_S   8
#define AR_RxMoreAggr   0x00010000
#define AR_RxAggr   0x00020000
#define AR_PostDelimCRCErr   0x00040000
#define AR_RxStatusRsvd71   0x3ff80000
#define AR_DecryptBusyErr   0x40000000
#define AR_KeyMiss   0x80000000
#define ATH9K_NUM_TX_QUEUES   1
#define ATH9K_WME_UPSD   4
#define ATH9K_TXQ_USEDEFAULT   ((u32) -1)
#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS   0x00000001
#define ATH9K_DECOMP_MASK_SIZE   128
#define ATH9K_READY_TIME_LO_BOUND   50
#define ATH9K_READY_TIME_HI_BOUND   96
#define ATH9K_RATESERIES_RTS_CTS   0x0001
#define ATH9K_RATESERIES_2040   0x0002
#define ATH9K_RATESERIES_HALFGI   0x0004
#define ATH9K_RATESERIES_STBC   0x0008

Enumerations

enum  ath9k_phyerr {
  ATH9K_PHYERR_UNDERRUN = 0, ATH9K_PHYERR_TIMING = 1, ATH9K_PHYERR_PARITY = 2, ATH9K_PHYERR_RATE = 3,
  ATH9K_PHYERR_LENGTH = 4, ATH9K_PHYERR_RADAR = 5, ATH9K_PHYERR_SERVICE = 6, ATH9K_PHYERR_TOR = 7,
  ATH9K_PHYERR_OFDM_TIMING = 17, ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18, ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19, ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,
  ATH9K_PHYERR_OFDM_POWER_DROP = 21, ATH9K_PHYERR_OFDM_SERVICE = 22, ATH9K_PHYERR_OFDM_RESTART = 23, ATH9K_PHYERR_FALSE_RADAR_EXT = 24,
  ATH9K_PHYERR_CCK_TIMING = 25, ATH9K_PHYERR_CCK_HEADER_CRC = 26, ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27, ATH9K_PHYERR_CCK_SERVICE = 30,
  ATH9K_PHYERR_CCK_RESTART = 31, ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32, ATH9K_PHYERR_CCK_POWER_DROP = 33, ATH9K_PHYERR_HT_CRC_ERROR = 34,
  ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35, ATH9K_PHYERR_HT_RATE_ILLEGAL = 36, ATH9K_PHYERR_MAX = 37
}
enum  ath9k_tx_queue { ATH9K_TX_QUEUE_INACTIVE = 0, ATH9K_TX_QUEUE_DATA }
enum  ath9k_tx_queue_flags {
  TXQ_FLAG_TXOKINT_ENABLE = 0x0001, TXQ_FLAG_TXERRINT_ENABLE = 0x0001, TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
  TXQ_FLAG_TXURNINT_ENABLE = 0x0008, TXQ_FLAG_BACKOFF_DISABLE = 0x0010, TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
  TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080
}
enum  ath9k_pkt_type {
  ATH9K_PKT_TYPE_NORMAL = 0, ATH9K_PKT_TYPE_ATIM, ATH9K_PKT_TYPE_PSPOLL, ATH9K_PKT_TYPE_BEACON,
  ATH9K_PKT_TYPE_PROBE_RESP, ATH9K_PKT_TYPE_CHIRP, ATH9K_PKT_TYPE_GRP_POLL
}
enum  ath9k_rx_filter {
  ATH9K_RX_FILTER_UCAST = 0x00000001, ATH9K_RX_FILTER_MCAST = 0x00000002, ATH9K_RX_FILTER_BCAST = 0x00000004, ATH9K_RX_FILTER_CONTROL = 0x00000008,
  ATH9K_RX_FILTER_BEACON = 0x00000010, ATH9K_RX_FILTER_PROM = 0x00000020, ATH9K_RX_FILTER_PROBEREQ = 0x00000080, ATH9K_RX_FILTER_PHYERR = 0x00000100,
  ATH9K_RX_FILTER_MYBEACON = 0x00000200, ATH9K_RX_FILTER_COMP_BAR = 0x00000400, ATH9K_RX_FILTER_COMP_BA = 0x00000800, ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,
  ATH9K_RX_FILTER_PSPOLL = 0x00004000, ATH9K_RX_FILTER_PHYRADAR = 0x00002000, ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000
}
enum  ath9k_key_type { ATH9K_KEY_TYPE_CLEAR, ATH9K_KEY_TYPE_WEP, ATH9K_KEY_TYPE_AES, ATH9K_KEY_TYPE_TKIP }

Functions

 FILE_LICENCE (BSD2)
u32 ath9k_hw_gettxbuf (struct ath_hw *ah, u32 q)
void ath9k_hw_puttxbuf (struct ath_hw *ah, u32 q, u32 txdp)
void ath9k_hw_txstart (struct ath_hw *ah, u32 q)
void ath9k_hw_cleartxdesc (struct ath_hw *ah, void *ds)
u32 ath9k_hw_numtxpending (struct ath_hw *ah, u32 q)
int ath9k_hw_updatetxtriglevel (struct ath_hw *ah, int bIncTrigLevel)
 ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
int ath9k_hw_stop_dma_queue (struct ath_hw *ah, u32 q)
void ath9k_hw_abort_tx_dma (struct ath_hw *ah)
void ath9k_hw_gettxintrtxqs (struct ath_hw *ah, u32 *txqs)
int ath9k_hw_set_txq_props (struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo)
int ath9k_hw_get_txq_props (struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo)
int ath9k_hw_setuptxqueue (struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo)
int ath9k_hw_releasetxqueue (struct ath_hw *ah, u32 q)
int ath9k_hw_resettxqueue (struct ath_hw *ah, u32 q)
int ath9k_hw_rxprocdesc (struct ath_hw *ah, struct ath_desc *ds, struct ath_rx_status *rs, u64 tsf)
void ath9k_hw_setuprxdesc (struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags)
int ath9k_hw_setrxabort (struct ath_hw *ah, int set)
void ath9k_hw_putrxbuf (struct ath_hw *ah, u32 rxdp)
void ath9k_hw_startpcureceive (struct ath_hw *ah, int is_scanning)
void ath9k_hw_abortpcurecv (struct ath_hw *ah)
int ath9k_hw_stopdmarecv (struct ath_hw *ah, int *reset)
int ath9k_hw_intrpend (struct ath_hw *ah)
void ath9k_hw_set_interrupts (struct ath_hw *ah, unsigned int ints)
void ath9k_hw_enable_interrupts (struct ath_hw *ah)
void ath9k_hw_disable_interrupts (struct ath_hw *ah)
void ar9002_hw_attach_mac_ops (struct ath_hw *ah)

Define Documentation

#define RXSTATUS_RATE (   ah,
  ads 
)
Value:
(AR_SREV_5416_20_OR_LATER(ah) ?         \
                                MS(ads->ds_rxstatus0, AR_RxRate) :      \
                                (ads->ds_rxstatus3 >> 2) & 0xFF)

Definition at line 27 of file mac.h.

Referenced by ath9k_hw_rxprocdesc().

#define set11nTries (   _series,
  _index 
)    (SM((_series)[_index].Tries, AR_XmitDataTries##_index))

Definition at line 31 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define set11nRate (   _series,
  _index 
)    (SM((_series)[_index].Rate, AR_XmitRate##_index))

Definition at line 34 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define set11nPktDurRTSCTS (   _series,
  _index 
)
Value:
(SM((_series)[_index].PktDuration, AR_PacketDur##_index) |      \
         ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS   ?    \
          AR_RTSCTSQual##_index : 0))

Definition at line 37 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define set11nRateFlags (   _series,
  _index 
)
Value:
(((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ?         \
          AR_2040_##_index : 0)                                         \
         |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ?      \
           AR_GI##_index : 0)                                           \
         |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ?        \
           AR_STBC##_index : 0)                                         \
         |SM((_series)[_index].ChSel, AR_ChainSel##_index))

Definition at line 42 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define CCK_SIFS_TIME   10

Definition at line 51 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define CCK_PREAMBLE_BITS   144

Definition at line 52 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define CCK_PLCP_BITS   48

Definition at line 53 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_SIFS_TIME   16

Definition at line 55 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_PREAMBLE_TIME   20

Definition at line 56 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_PLCP_BITS   22

Definition at line 57 of file mac.h.

#define OFDM_SYMBOL_TIME   4

Definition at line 58 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_SIFS_TIME_HALF   32

Definition at line 60 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_PREAMBLE_TIME_HALF   40

Definition at line 61 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_PLCP_BITS_HALF   22

Definition at line 62 of file mac.h.

#define OFDM_SYMBOL_TIME_HALF   8

Definition at line 63 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_SIFS_TIME_QUARTER   64

Definition at line 65 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_PREAMBLE_TIME_QUARTER   80

Definition at line 66 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define OFDM_PLCP_BITS_QUARTER   22

Definition at line 67 of file mac.h.

#define OFDM_SYMBOL_TIME_QUARTER   16

Definition at line 68 of file mac.h.

Referenced by ath9k_hw_computetxtime().

#define INIT_AIFS   2

Definition at line 70 of file mac.h.

Referenced by ath9k_hw_set_txq_props(), and ath9k_hw_setuptxqueue().

#define INIT_CWMIN   15

Definition at line 71 of file mac.h.

Referenced by ath9k_hw_resettxqueue().

#define INIT_CWMIN_11B   31

Definition at line 72 of file mac.h.

Referenced by ath9k_hw_resettxqueue().

#define INIT_CWMAX   1023

Definition at line 73 of file mac.h.

Referenced by ath9k_hw_set_txq_props(), and ath9k_hw_setuptxqueue().

#define INIT_SH_RETRY   10

Definition at line 74 of file mac.h.

Referenced by ath9k_hw_set_txq_props(), and ath9k_hw_setuptxqueue().

#define INIT_LG_RETRY   10

Definition at line 75 of file mac.h.

Referenced by ath9k_hw_set_txq_props(), and ath9k_hw_setuptxqueue().

#define INIT_SSH_RETRY   32

Definition at line 76 of file mac.h.

Referenced by ath9k_hw_resettxqueue().

#define INIT_SLG_RETRY   32

Definition at line 77 of file mac.h.

Referenced by ath9k_hw_resettxqueue().

#define ATH9K_SLOT_TIME_6   6

Definition at line 79 of file mac.h.

#define ATH9K_SLOT_TIME_9   9

Definition at line 80 of file mac.h.

#define ATH9K_SLOT_TIME_20   20

Definition at line 81 of file mac.h.

#define ATH9K_TXERR_XRETRY   0x01

Definition at line 83 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), ar9003_hw_proc_txdesc(), and ath_tx_processq().

#define ATH9K_TXERR_FILT   0x02

Definition at line 84 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TXERR_FIFO   0x04

Definition at line 85 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TXERR_XTXOP   0x08

Definition at line 86 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TXERR_TIMER_EXPIRED   0x10

Definition at line 87 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TX_ACKED   0x20

Definition at line 88 of file mac.h.

Referenced by ar9002_hw_proc_txdesc().

Value:

Definition at line 89 of file mac.h.

Referenced by ath_tx_complete(), and ath_tx_processq().

#define ATH9K_TX_BA   0x01

Definition at line 93 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TX_PWRMGMT   0x02

Definition at line 94 of file mac.h.

#define ATH9K_TX_DESC_CFG_ERR   0x04

Definition at line 95 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TX_DATA_UNDERRUN   0x08

Definition at line 96 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TX_DELIM_UNDERRUN   0x10

Definition at line 97 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define ATH9K_TX_SW_FILTERED   0x80

Definition at line 98 of file mac.h.

#define MIN_TX_FIFO_THRESHOLD   0x1

Definition at line 101 of file mac.h.

Referenced by ath9k_hw_updatetxtriglevel().

#define MAX_TX_FIFO_THRESHOLD   ((4096 / 64) - 1)

Definition at line 108 of file mac.h.

Referenced by __ath9k_hw_init().

#define ATH9K_RXERR_CRC   0x01

Definition at line 189 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), ath9k_hw_rxprocdesc(), and ath9k_rx_accept().

#define ATH9K_RXERR_PHY   0x02

Definition at line 190 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), ath9k_hw_rxprocdesc(), and ath9k_rx_accept().

#define ATH9K_RXERR_FIFO   0x04

Definition at line 191 of file mac.h.

#define ATH9K_RXERR_DECRYPT   0x08

Definition at line 192 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), ath9k_hw_rxprocdesc(), and ath9k_rx_accept().

#define ATH9K_RXERR_MIC   0x10

Definition at line 193 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), ath9k_hw_rxprocdesc(), and ath9k_rx_accept().

#define ATH9K_RX_MORE   0x01

Definition at line 195 of file mac.h.

#define ATH9K_RX_MORE_AGGR   0x02

Definition at line 196 of file mac.h.

#define ATH9K_RX_GI   0x04

Definition at line 197 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define ATH9K_RX_2040   0x08

Definition at line 198 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define ATH9K_RX_DELIM_CRC_PRE   0x10

Definition at line 199 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define ATH9K_RX_DELIM_CRC_POST   0x20

Definition at line 200 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define ATH9K_RX_DECRYPT_BUSY   0x40

Definition at line 201 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define ATH9K_RXKEYIX_INVALID   ((u8)-1)

Definition at line 203 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define ATH9K_TXKEYIX_INVALID   ((u32)-1)

Definition at line 204 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), ar9003_hw_set11n_txdesc(), and ath_tx_setup_buffer().

#define ATH9K_TXDESC_NOACK   0x0002

Definition at line 249 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define ATH9K_TXDESC_RTSENA   0x0004
#define ATH9K_TXDESC_CTSENA   0x0008
#define ATH9K_TXDESC_INTREQ   0x0010

Definition at line 265 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and setup_tx_flags().

#define ATH9K_TXDESC_VEOL   0x0020

Definition at line 266 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define ATH9K_TXDESC_EXT_ONLY   0x0040

Definition at line 267 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define ATH9K_TXDESC_EXT_AND_CTL   0x0080

Definition at line 268 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define ATH9K_TXDESC_VMF   0x0100

Definition at line 269 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define ATH9K_TXDESC_FRAG_IS_ON   0x0200

Definition at line 270 of file mac.h.

#define ATH9K_TXDESC_LOWRXCHAIN   0x0400

Definition at line 271 of file mac.h.

Referenced by ar9003_hw_set11n_txdesc().

#define ATH9K_TXDESC_LDPC   0x00010000

Definition at line 272 of file mac.h.

Referenced by ar9003_hw_set11n_txdesc().

#define ATH9K_RXDESC_INTREQ   0x0020

Definition at line 274 of file mac.h.

Referenced by ath9k_hw_setuprxdesc().

#define AR5416DESC (   _ds)    ((struct ar5416_desc *)(_ds))
#define AR5416DESC_CONST (   _ds)    ((const struct ar5416_desc *)(_ds))

Definition at line 319 of file mac.h.

Referenced by ar9002_hw_fill_txdesc().

#define ds_ctl2   u.tx.ctl2

Definition at line 321 of file mac.h.

#define ds_ctl3   u.tx.ctl3

Definition at line 322 of file mac.h.

#define ds_ctl4   u.tx.ctl4

Definition at line 323 of file mac.h.

#define ds_ctl5   u.tx.ctl5

Definition at line 324 of file mac.h.

#define ds_ctl6   u.tx.ctl6

Definition at line 325 of file mac.h.

#define ds_ctl7   u.tx.ctl7

Definition at line 326 of file mac.h.

#define ds_ctl8   u.tx.ctl8

Definition at line 327 of file mac.h.

#define ds_ctl9   u.tx.ctl9

Definition at line 328 of file mac.h.

#define ds_ctl10   u.tx.ctl10

Definition at line 329 of file mac.h.

#define ds_ctl11   u.tx.ctl11

Definition at line 330 of file mac.h.

#define ds_txstatus0   u.tx.status0

Definition at line 332 of file mac.h.

#define ds_txstatus1   u.tx.status1

Definition at line 333 of file mac.h.

#define ds_txstatus2   u.tx.status2

Definition at line 334 of file mac.h.

#define ds_txstatus3   u.tx.status3

Definition at line 335 of file mac.h.

#define ds_txstatus4   u.tx.status4

Definition at line 336 of file mac.h.

#define ds_txstatus5   u.tx.status5

Definition at line 337 of file mac.h.

#define ds_txstatus6   u.tx.status6

Definition at line 338 of file mac.h.

#define ds_txstatus7   u.tx.status7

Definition at line 339 of file mac.h.

#define ds_txstatus8   u.tx.status8

Definition at line 340 of file mac.h.

#define ds_txstatus9   u.tx.status9

Definition at line 341 of file mac.h.

#define ds_rxstatus0   u.rx.status0

Definition at line 343 of file mac.h.

#define ds_rxstatus1   u.rx.status1

Definition at line 344 of file mac.h.

#define ds_rxstatus2   u.rx.status2

Definition at line 345 of file mac.h.

#define ds_rxstatus3   u.rx.status3

Definition at line 346 of file mac.h.

#define ds_rxstatus4   u.rx.status4

Definition at line 347 of file mac.h.

#define ds_rxstatus5   u.rx.status5

Definition at line 348 of file mac.h.

#define ds_rxstatus6   u.rx.status6

Definition at line 349 of file mac.h.

#define ds_rxstatus7   u.rx.status7

Definition at line 350 of file mac.h.

#define ds_rxstatus8   u.rx.status8

Definition at line 351 of file mac.h.

#define AR_FrameLen   0x00000fff

Definition at line 353 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_VirtMoreFrag   0x00001000

Definition at line 354 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_TxCtlRsvd00   0x0000e000

Definition at line 355 of file mac.h.

#define AR_XmitPower   0x003f0000

Definition at line 356 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_XmitPower_S   16

Definition at line 357 of file mac.h.

#define AR_RTSEnable   0x00400000

Definition at line 358 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define AR_VEOL   0x00800000

Definition at line 359 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_ClrDestMask   0x01000000

Definition at line 360 of file mac.h.

Referenced by ar9002_hw_set_clrdmask(), and ar9003_hw_set_clrdmask().

#define AR_TxCtlRsvd01   0x1e000000

Definition at line 361 of file mac.h.

#define AR_TxIntrReq   0x20000000

Definition at line 362 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc().

#define AR_DestIdxValid   0x40000000

Definition at line 363 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_CTSEnable   0x80000000

Definition at line 364 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define AR_TxMore   0x00001000

Definition at line 366 of file mac.h.

Referenced by ar9002_hw_fill_txdesc(), and ar9003_hw_fill_txdesc().

#define AR_DestIdx   0x000fe000

Definition at line 367 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_DestIdx_S   13

Definition at line 368 of file mac.h.

#define AR_FrameType   0x00f00000

Definition at line 369 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_FrameType_S   20

Definition at line 370 of file mac.h.

#define AR_NoAck   0x01000000

Definition at line 371 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_InsertTS   0x02000000

Definition at line 372 of file mac.h.

#define AR_CorruptFCS   0x04000000

Definition at line 373 of file mac.h.

#define AR_ExtOnly   0x08000000

Definition at line 374 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_ExtAndCtl   0x10000000

Definition at line 375 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_MoreAggr   0x20000000
#define AR_IsAggr   0x40000000
#define AR_BurstDur   0x00007fff

Definition at line 379 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define AR_BurstDur_S   0

Definition at line 380 of file mac.h.

#define AR_DurUpdateEna   0x00008000

Definition at line 381 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define AR_XmitDataTries0   0x000f0000

Definition at line 382 of file mac.h.

#define AR_XmitDataTries0_S   16

Definition at line 383 of file mac.h.

#define AR_XmitDataTries1   0x00f00000

Definition at line 384 of file mac.h.

#define AR_XmitDataTries1_S   20

Definition at line 385 of file mac.h.

#define AR_XmitDataTries2   0x0f000000

Definition at line 386 of file mac.h.

#define AR_XmitDataTries2_S   24

Definition at line 387 of file mac.h.

#define AR_XmitDataTries3   0xf0000000

Definition at line 388 of file mac.h.

#define AR_XmitDataTries3_S   28

Definition at line 389 of file mac.h.

#define AR_XmitRate0   0x000000ff

Definition at line 391 of file mac.h.

#define AR_XmitRate0_S   0

Definition at line 392 of file mac.h.

#define AR_XmitRate1   0x0000ff00

Definition at line 393 of file mac.h.

#define AR_XmitRate1_S   8

Definition at line 394 of file mac.h.

#define AR_XmitRate2   0x00ff0000

Definition at line 395 of file mac.h.

#define AR_XmitRate2_S   16

Definition at line 396 of file mac.h.

#define AR_XmitRate3   0xff000000

Definition at line 397 of file mac.h.

#define AR_XmitRate3_S   24

Definition at line 398 of file mac.h.

#define AR_PacketDur0   0x00007fff

Definition at line 400 of file mac.h.

#define AR_PacketDur0_S   0

Definition at line 401 of file mac.h.

#define AR_RTSCTSQual0   0x00008000

Definition at line 402 of file mac.h.

#define AR_PacketDur1   0x7fff0000

Definition at line 403 of file mac.h.

#define AR_PacketDur1_S   16

Definition at line 404 of file mac.h.

#define AR_RTSCTSQual1   0x80000000

Definition at line 405 of file mac.h.

#define AR_PacketDur2   0x00007fff

Definition at line 407 of file mac.h.

#define AR_PacketDur2_S   0

Definition at line 408 of file mac.h.

#define AR_RTSCTSQual2   0x00008000

Definition at line 409 of file mac.h.

#define AR_PacketDur3   0x7fff0000

Definition at line 410 of file mac.h.

#define AR_PacketDur3_S   16

Definition at line 411 of file mac.h.

#define AR_RTSCTSQual3   0x80000000

Definition at line 412 of file mac.h.

#define AR_AggrLen   0x0000ffff

Definition at line 414 of file mac.h.

Referenced by ar9002_hw_set11n_aggr_first(), and ar9003_hw_set11n_aggr_first().

#define AR_AggrLen_S   0

Definition at line 415 of file mac.h.

#define AR_TxCtlRsvd60   0x00030000

Definition at line 416 of file mac.h.

#define AR_PadDelim   0x03fc0000
#define AR_PadDelim_S   18

Definition at line 418 of file mac.h.

#define AR_EncrType   0x0c000000

Definition at line 419 of file mac.h.

Referenced by ar9002_hw_set11n_txdesc(), and ar9003_hw_set11n_txdesc().

#define AR_EncrType_S   26

Definition at line 420 of file mac.h.

#define AR_TxCtlRsvd61   0xf0000000

Definition at line 421 of file mac.h.

#define AR_LDPC   0x80000000

Definition at line 422 of file mac.h.

Referenced by ar9003_hw_set11n_txdesc().

#define AR_2040_0   0x00000001

Definition at line 424 of file mac.h.

#define AR_GI0   0x00000002

Definition at line 425 of file mac.h.

#define AR_ChainSel0   0x0000001c

Definition at line 426 of file mac.h.

#define AR_ChainSel0_S   2

Definition at line 427 of file mac.h.

#define AR_2040_1   0x00000020

Definition at line 428 of file mac.h.

#define AR_GI1   0x00000040

Definition at line 429 of file mac.h.

#define AR_ChainSel1   0x00000380

Definition at line 430 of file mac.h.

#define AR_ChainSel1_S   7

Definition at line 431 of file mac.h.

#define AR_2040_2   0x00000400

Definition at line 432 of file mac.h.

#define AR_GI2   0x00000800

Definition at line 433 of file mac.h.

#define AR_ChainSel2   0x00007000

Definition at line 434 of file mac.h.

#define AR_ChainSel2_S   12

Definition at line 435 of file mac.h.

#define AR_2040_3   0x00008000

Definition at line 436 of file mac.h.

#define AR_GI3   0x00010000

Definition at line 437 of file mac.h.

#define AR_ChainSel3   0x000e0000

Definition at line 438 of file mac.h.

#define AR_ChainSel3_S   17

Definition at line 439 of file mac.h.

#define AR_RTSCTSRate   0x0ff00000

Definition at line 440 of file mac.h.

Referenced by ar9002_hw_set11n_ratescenario(), and ar9003_hw_set11n_ratescenario().

#define AR_RTSCTSRate_S   20

Definition at line 441 of file mac.h.

#define AR_STBC0   0x10000000

Definition at line 442 of file mac.h.

#define AR_STBC1   0x20000000

Definition at line 443 of file mac.h.

#define AR_STBC2   0x40000000

Definition at line 444 of file mac.h.

#define AR_STBC3   0x80000000

Definition at line 445 of file mac.h.

#define AR_TxRSSIAnt00   0x000000ff

Definition at line 447 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxRSSIAnt00_S   0

Definition at line 448 of file mac.h.

#define AR_TxRSSIAnt01   0x0000ff00

Definition at line 449 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxRSSIAnt01_S   8

Definition at line 450 of file mac.h.

#define AR_TxRSSIAnt02   0x00ff0000

Definition at line 451 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxRSSIAnt02_S   16

Definition at line 452 of file mac.h.

#define AR_TxStatusRsvd00   0x3f000000

Definition at line 453 of file mac.h.

#define AR_TxBaStatus   0x40000000

Definition at line 454 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxStatusRsvd01   0x80000000

Definition at line 455 of file mac.h.

#define AR_FrmXmitOK   0x00000001

Definition at line 462 of file mac.h.

Referenced by ar9002_hw_proc_txdesc().

#define AR_ExcessiveRetries   0x00000002

Definition at line 463 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_FIFOUnderrun   0x00000004

Definition at line 464 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_Filtered   0x00000008

Definition at line 465 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_RTSFailCnt   0x000000f0

Definition at line 466 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_RTSFailCnt_S   4

Definition at line 467 of file mac.h.

#define AR_DataFailCnt   0x00000f00

Definition at line 468 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_DataFailCnt_S   8

Definition at line 469 of file mac.h.

#define AR_VirtRetryCnt   0x0000f000

Definition at line 470 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_VirtRetryCnt_S   12

Definition at line 471 of file mac.h.

#define AR_TxDelimUnderrun   0x00010000

Definition at line 472 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxDataUnderrun   0x00020000

Definition at line 473 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_DescCfgErr   0x00040000

Definition at line 474 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxTimerExpired   0x00080000

Definition at line 475 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxStatusRsvd10   0xfff00000

Definition at line 476 of file mac.h.

Definition at line 478 of file mac.h.

Definition at line 479 of file mac.h.

Definition at line 480 of file mac.h.

#define AR_TxRSSIAnt10   0x000000ff

Definition at line 482 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxRSSIAnt10_S   0

Definition at line 483 of file mac.h.

#define AR_TxRSSIAnt11   0x0000ff00

Definition at line 484 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxRSSIAnt11_S   8

Definition at line 485 of file mac.h.

#define AR_TxRSSIAnt12   0x00ff0000

Definition at line 486 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxRSSIAnt12_S   16

Definition at line 487 of file mac.h.

#define AR_TxRSSICombined   0xff000000

Definition at line 488 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxRSSICombined_S   24

Definition at line 489 of file mac.h.

#define AR_TxTid   0xf0000000

Definition at line 491 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxTid_S   28

Definition at line 492 of file mac.h.

#define AR_TxEVM0   ds_txstatus5

Definition at line 494 of file mac.h.

#define AR_TxEVM1   ds_txstatus6

Definition at line 495 of file mac.h.

#define AR_TxEVM2   ds_txstatus7

Definition at line 496 of file mac.h.

#define AR_TxDone   0x00000001

Definition at line 498 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_SeqNum   0x00001ffe

Definition at line 499 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_SeqNum_S   1

Definition at line 500 of file mac.h.

#define AR_TxStatusRsvd80   0x0001e000

Definition at line 501 of file mac.h.

#define AR_TxOpExceeded   0x00020000

Definition at line 502 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_TxStatusRsvd81   0x001c0000

Definition at line 503 of file mac.h.

#define AR_FinalTxIdx   0x00600000

Definition at line 504 of file mac.h.

Referenced by ar9002_hw_proc_txdesc(), and ar9003_hw_proc_txdesc().

#define AR_FinalTxIdx_S   21

Definition at line 505 of file mac.h.

#define AR_TxStatusRsvd82   0x01800000

Definition at line 506 of file mac.h.

#define AR_PowerMgmt   0x02000000

Definition at line 507 of file mac.h.

#define AR_TxStatusRsvd83   0xfc000000

Definition at line 508 of file mac.h.

#define AR_RxCTLRsvd00   0xffffffff

Definition at line 510 of file mac.h.

#define AR_RxCtlRsvd00   0x00001000

Definition at line 512 of file mac.h.

#define AR_RxIntrReq   0x00002000

Definition at line 513 of file mac.h.

Referenced by ath9k_hw_setuprxdesc().

#define AR_RxCtlRsvd01   0xffffc000

Definition at line 514 of file mac.h.

#define AR_RxRSSIAnt00   0x000000ff

Definition at line 516 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxRSSIAnt00_S   0

Definition at line 517 of file mac.h.

#define AR_RxRSSIAnt01   0x0000ff00

Definition at line 518 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxRSSIAnt01_S   8

Definition at line 519 of file mac.h.

#define AR_RxRSSIAnt02   0x00ff0000

Definition at line 520 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxRSSIAnt02_S   16

Definition at line 521 of file mac.h.

#define AR_RxRate   0xff000000

Definition at line 522 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma().

#define AR_RxRate_S   24

Definition at line 523 of file mac.h.

#define AR_RxStatusRsvd00   0xff000000

Definition at line 524 of file mac.h.

#define AR_DataLen   0x00000fff

Definition at line 526 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxMore   0x00001000

Definition at line 527 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_NumDelim   0x003fc000

Definition at line 528 of file mac.h.

#define AR_NumDelim_S   14

Definition at line 529 of file mac.h.

#define AR_RxStatusRsvd10   0xff800000

Definition at line 530 of file mac.h.

Definition at line 532 of file mac.h.

#define AR_GI   0x00000001

Definition at line 534 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_2040   0x00000002

Definition at line 535 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_Parallel40   0x00000004

Definition at line 536 of file mac.h.

#define AR_Parallel40_S   2

Definition at line 537 of file mac.h.

#define AR_RxStatusRsvd30   0x000000f8

Definition at line 538 of file mac.h.

#define AR_RxAntenna   0xffffff00

Definition at line 539 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxAntenna_S   8

Definition at line 540 of file mac.h.

#define AR_RxRSSIAnt10   0x000000ff

Definition at line 542 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxRSSIAnt10_S   0

Definition at line 543 of file mac.h.

#define AR_RxRSSIAnt11   0x0000ff00

Definition at line 544 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxRSSIAnt11_S   8

Definition at line 545 of file mac.h.

#define AR_RxRSSIAnt12   0x00ff0000

Definition at line 546 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxRSSIAnt12_S   16

Definition at line 547 of file mac.h.

#define AR_RxRSSICombined   0xff000000

Definition at line 548 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxRSSICombined_S   24

Definition at line 549 of file mac.h.

#define AR_RxEVM0   ds_rxstatus4

Definition at line 551 of file mac.h.

#define AR_RxEVM1   ds_rxstatus5

Definition at line 552 of file mac.h.

#define AR_RxEVM2   ds_rxstatus6

Definition at line 553 of file mac.h.

#define AR_RxDone   0x00000001

Definition at line 555 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), ath9k_hw_rxprocdesc(), and ath9k_hw_setuprxdesc().

#define AR_RxFrameOK   0x00000002

Definition at line 556 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_CRCErr   0x00000004

Definition at line 557 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_DecryptCRCErr   0x00000008

Definition at line 558 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_PHYErr   0x00000010

Definition at line 559 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_MichaelErr   0x00000020

Definition at line 560 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_PreDelimCRCErr   0x00000040

Definition at line 561 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxStatusRsvd70   0x00000080

Definition at line 562 of file mac.h.

#define AR_RxKeyIdxValid   0x00000100

Definition at line 563 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_KeyIdx   0x0000fe00

Definition at line 564 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_KeyIdx_S   9

Definition at line 565 of file mac.h.

#define AR_PHYErrCode   0x0000ff00

Definition at line 566 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_PHYErrCode_S   8

Definition at line 567 of file mac.h.

#define AR_RxMoreAggr   0x00010000

Definition at line 568 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxAggr   0x00020000

Definition at line 569 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_PostDelimCRCErr   0x00040000

Definition at line 570 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_RxStatusRsvd71   0x3ff80000

Definition at line 571 of file mac.h.

#define AR_DecryptBusyErr   0x40000000

Definition at line 572 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define AR_KeyMiss   0x80000000

Definition at line 573 of file mac.h.

Referenced by ath9k_hw_process_rxdesc_edma(), and ath9k_hw_rxprocdesc().

#define ATH9K_NUM_TX_QUEUES   1
#define ATH9K_WME_UPSD   4

Definition at line 583 of file mac.h.

#define ATH9K_TXQ_USEDEFAULT   ((u32) -1)
#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS   0x00000001

Definition at line 598 of file mac.h.

Referenced by ath9k_hw_resettxqueue().

#define ATH9K_DECOMP_MASK_SIZE   128

Definition at line 600 of file mac.h.

#define ATH9K_READY_TIME_LO_BOUND   50

Definition at line 601 of file mac.h.

#define ATH9K_READY_TIME_HI_BOUND   96

Definition at line 602 of file mac.h.

#define ATH9K_RATESERIES_RTS_CTS   0x0001

Definition at line 651 of file mac.h.

Referenced by ath_buf_set_rate().

#define ATH9K_RATESERIES_2040   0x0002

Definition at line 652 of file mac.h.

#define ATH9K_RATESERIES_HALFGI   0x0004

Definition at line 653 of file mac.h.

#define ATH9K_RATESERIES_STBC   0x0008

Definition at line 654 of file mac.h.


Enumeration Type Documentation

Enumerator:
ATH9K_PHYERR_UNDERRUN 
ATH9K_PHYERR_TIMING 
ATH9K_PHYERR_PARITY 
ATH9K_PHYERR_RATE 
ATH9K_PHYERR_LENGTH 
ATH9K_PHYERR_RADAR 
ATH9K_PHYERR_SERVICE 
ATH9K_PHYERR_TOR 
ATH9K_PHYERR_OFDM_TIMING 
ATH9K_PHYERR_OFDM_SIGNAL_PARITY 
ATH9K_PHYERR_OFDM_RATE_ILLEGAL 
ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL 
ATH9K_PHYERR_OFDM_POWER_DROP 
ATH9K_PHYERR_OFDM_SERVICE 
ATH9K_PHYERR_OFDM_RESTART 
ATH9K_PHYERR_FALSE_RADAR_EXT 
ATH9K_PHYERR_CCK_TIMING 
ATH9K_PHYERR_CCK_HEADER_CRC 
ATH9K_PHYERR_CCK_RATE_ILLEGAL 
ATH9K_PHYERR_CCK_SERVICE 
ATH9K_PHYERR_CCK_RESTART 
ATH9K_PHYERR_CCK_LENGTH_ILLEGAL 
ATH9K_PHYERR_CCK_POWER_DROP 
ATH9K_PHYERR_HT_CRC_ERROR 
ATH9K_PHYERR_HT_LENGTH_ILLEGAL 
ATH9K_PHYERR_HT_RATE_ILLEGAL 
ATH9K_PHYERR_MAX 

Definition at line 206 of file mac.h.

Enumerator:
ATH9K_TX_QUEUE_INACTIVE 
ATH9K_TX_QUEUE_DATA 

Definition at line 575 of file mac.h.

Enumerator:
TXQ_FLAG_TXOKINT_ENABLE 
TXQ_FLAG_TXERRINT_ENABLE 
TXQ_FLAG_TXDESCINT_ENABLE 
TXQ_FLAG_TXEOLINT_ENABLE 
TXQ_FLAG_TXURNINT_ENABLE 
TXQ_FLAG_BACKOFF_DISABLE 
TXQ_FLAG_COMPRESSION_ENABLE 
TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 
TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 

Definition at line 585 of file mac.h.

Enumerator:
ATH9K_PKT_TYPE_NORMAL 
ATH9K_PKT_TYPE_ATIM 
ATH9K_PKT_TYPE_PSPOLL 
ATH9K_PKT_TYPE_BEACON 
ATH9K_PKT_TYPE_PROBE_RESP 
ATH9K_PKT_TYPE_CHIRP 
ATH9K_PKT_TYPE_GRP_POLL 

Definition at line 604 of file mac.h.

Enumerator:
ATH9K_RX_FILTER_UCAST 
ATH9K_RX_FILTER_MCAST 
ATH9K_RX_FILTER_BCAST 
ATH9K_RX_FILTER_CONTROL 
ATH9K_RX_FILTER_BEACON 
ATH9K_RX_FILTER_PROM 
ATH9K_RX_FILTER_PROBEREQ 
ATH9K_RX_FILTER_PHYERR 
ATH9K_RX_FILTER_MYBEACON 
ATH9K_RX_FILTER_COMP_BAR 
ATH9K_RX_FILTER_COMP_BA 
ATH9K_RX_FILTER_UNCOMP_BA_BAR 
ATH9K_RX_FILTER_PSPOLL 
ATH9K_RX_FILTER_PHYRADAR 
ATH9K_RX_FILTER_MCAST_BCAST_ALL 

Definition at line 633 of file mac.h.

Enumerator:
ATH9K_KEY_TYPE_CLEAR 
ATH9K_KEY_TYPE_WEP 
ATH9K_KEY_TYPE_AES 
ATH9K_KEY_TYPE_TKIP 

Definition at line 664 of file mac.h.


Function Documentation

FILE_LICENCE ( BSD2  )
u32 ath9k_hw_gettxbuf ( struct ath_hw ah,
u32  q 
)

Referenced by ath_tx_processq().

void ath9k_hw_puttxbuf ( struct ath_hw ah,
u32  q,
u32  txdp 
)

Definition at line 50 of file ath9k_mac.c.

References AR_QTXDP, and REG_WRITE.

Referenced by ath_tx_txqaddbuf().

{
        REG_WRITE(ah, AR_QTXDP(q), txdp);
}
void ath9k_hw_txstart ( struct ath_hw ah,
u32  q 
)

Definition at line 55 of file ath9k_mac.c.

References AR_Q_TXE, DBG2, and REG_WRITE.

Referenced by ath_tx_txqaddbuf().

{
        DBG2("ath9k: "
                "Enable TXE on queue: %d\n", q);
        REG_WRITE(ah, AR_Q_TXE, 1 << q);
}
void ath9k_hw_cleartxdesc ( struct ath_hw ah,
void *  ds 
)
u32 ath9k_hw_numtxpending ( struct ath_hw ah,
u32  q 
)

Definition at line 62 of file ath9k_mac.c.

References AR_Q_STS_PEND_FR_CNT, AR_Q_TXE, AR_QSTS, and REG_READ.

Referenced by ath9k_hw_abort_tx_dma(), ath9k_hw_channel_change(), and ath_drain_all_txq().

{
        u32 npend;

        npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
        if (npend == 0) {

                if (REG_READ(ah, AR_Q_TXE) & (1 << q))
                        npend = 1;
        }

        return npend;
}
int ath9k_hw_updatetxtriglevel ( struct ath_hw ah,
int  bIncTrigLevel 
)

ath9k_hw_updatetxtriglevel - adjusts the frame trigger level

: atheros hardware struct : whether or not the frame trigger level should be updated

The frame trigger level specifies the minimum number of bytes, in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO before the PCU will initiate sending the frame on the air. This can mean we initiate transmit before a full frame is on the PCU TX FIFO. Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs first)

Caution must be taken to ensure to set the frame trigger level based on the DMA request size. For example if the DMA request size is set to 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because there need to be enough space in the tx FIFO for the requested transfer size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set the threshold to a value beyond 6, then the transmit will hang.

Current dual stream devices have a PCU TX FIFO size of 8 KB. Current single stream devices have a PCU TX FIFO size of 4 KB, however, there is a hardware issue which forces us to use 2 KB instead so the frame trigger level must not exceed 2 KB for these chipsets.

Definition at line 101 of file ath9k_mac.c.

References AR_FTRIG, AR_TXCFG, ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), ath_hw::config, ath9k_ops_config::max_txtrig_level, MIN_TX_FIFO_THRESHOLD, MS, REG_READ, REG_WRITE, SM, ath_hw::tx_trig_level, and txcfg.

Referenced by ar9002_hw_proc_txdesc(), ar9003_hw_proc_txdesc(), and ath_isr().

{
        u32 txcfg, curLevel, newLevel;

        if (ah->tx_trig_level >= ah->config.max_txtrig_level)
                return 0;

        ath9k_hw_disable_interrupts(ah);

        txcfg = REG_READ(ah, AR_TXCFG);
        curLevel = MS(txcfg, AR_FTRIG);
        newLevel = curLevel;
        if (bIncTrigLevel) {
                if (curLevel < ah->config.max_txtrig_level)
                        newLevel++;
        } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
                newLevel--;
        if (newLevel != curLevel)
                REG_WRITE(ah, AR_TXCFG,
                          (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));

        ath9k_hw_enable_interrupts(ah);

        ah->tx_trig_level = newLevel;

        return newLevel != curLevel;
}
int ath9k_hw_stop_dma_queue ( struct ath_hw ah,
u32  q 
)
void ath9k_hw_abort_tx_dma ( struct ath_hw ah)
void ath9k_hw_gettxintrtxqs ( struct ath_hw ah,
u32 txqs 
)

Definition at line 156 of file ath9k_mac.c.

References ath_hw::intr_txqs.

Referenced by ath_tx_tasklet().

{
        *txqs &= ah->intr_txqs;
        ah->intr_txqs &= ~(*txqs);
}
int ath9k_hw_set_txq_props ( struct ath_hw ah,
int  q,
const struct ath9k_tx_queue_info qinfo 
)

Definition at line 162 of file ath9k_mac.c.

References ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USEDEFAULT, DBG, DBG2, INIT_AIFS, INIT_CWMAX, INIT_LG_RETRY, INIT_SH_RETRY, min, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_burstTime, ath9k_tx_queue_info::tqi_cbrOverflowLimit, ath9k_tx_queue_info::tqi_cbrPeriod, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_lgretry, ath9k_tx_queue_info::tqi_priority, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_readyTime, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_subtype, ath9k_tx_queue_info::tqi_type, ath9k_tx_queue_info::tqi_ver, and ath_hw::txq.

Referenced by ath9k_hw_setuptxqueue().

{
        u32 cw;
        struct ath9k_tx_queue_info *qi;

        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: "
                        "Set TXQ properties, inactive queue: %d\n", q);
                return 0;
        }

        DBG2("ath9k: Set queue properties for: %d\n", q);

        qi->tqi_ver = qinfo->tqi_ver;
        qi->tqi_subtype = qinfo->tqi_subtype;
        qi->tqi_qflags = qinfo->tqi_qflags;
        qi->tqi_priority = qinfo->tqi_priority;
        if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
                qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
        else
                qi->tqi_aifs = INIT_AIFS;
        if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
                cw = min(qinfo->tqi_cwmin, 1024U);
                qi->tqi_cwmin = 1;
                while (qi->tqi_cwmin < cw)
                        qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
        } else
                qi->tqi_cwmin = qinfo->tqi_cwmin;
        if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
                cw = min(qinfo->tqi_cwmax, 1024U);
                qi->tqi_cwmax = 1;
                while (qi->tqi_cwmax < cw)
                        qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
        } else
                qi->tqi_cwmax = INIT_CWMAX;

        if (qinfo->tqi_shretry != 0)
                qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
        else
                qi->tqi_shretry = INIT_SH_RETRY;
        if (qinfo->tqi_lgretry != 0)
                qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
        else
                qi->tqi_lgretry = INIT_LG_RETRY;
        qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
        qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
        qi->tqi_burstTime = qinfo->tqi_burstTime;
        qi->tqi_readyTime = qinfo->tqi_readyTime;

        return 1;
}
int ath9k_hw_get_txq_props ( struct ath_hw ah,
int  q,
struct ath9k_tx_queue_info qinfo 
)
int ath9k_hw_setuptxqueue ( struct ath_hw ah,
enum ath9k_tx_queue  type,
const struct ath9k_tx_queue_info qinfo 
)

Definition at line 216 of file ath9k_mac.c.

References ath9k_hw_set_txq_props(), ATH9K_NUM_TX_QUEUES, ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USEDEFAULT, DBG, DBG2, INIT_AIFS, INIT_CWMAX, INIT_LG_RETRY, INIT_SH_RETRY, memset(), NULL, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_lgretry, ath9k_tx_queue_info::tqi_physCompBuf, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_type, ath_hw::txq, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXERRINT_ENABLE, TXQ_FLAG_TXOKINT_ENABLE, TXQ_FLAG_TXURNINT_ENABLE, and type.

Referenced by ath_txq_setup().

{
        struct ath9k_tx_queue_info *qi;
        int q;

        for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
                if (ah->txq[q].tqi_type ==
                    ATH9K_TX_QUEUE_INACTIVE)
                        break;
        if (q == ATH9K_NUM_TX_QUEUES) {
                DBG("No available TX queue\n");
                return -1;
        }

        DBG2("ath9K: Setup TX queue: %d\n", q);

        qi = &ah->txq[q];
        if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: TX queue: %d already active\n", q);
                return -1;
        }
        memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
        qi->tqi_type = type;
        if (qinfo == NULL) {
                qi->tqi_qflags =
                        TXQ_FLAG_TXOKINT_ENABLE
                        | TXQ_FLAG_TXERRINT_ENABLE
                        | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
                qi->tqi_aifs = INIT_AIFS;
                qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
                qi->tqi_cwmax = INIT_CWMAX;
                qi->tqi_shretry = INIT_SH_RETRY;
                qi->tqi_lgretry = INIT_LG_RETRY;
                qi->tqi_physCompBuf = 0;
        } else {
                qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
                (void) ath9k_hw_set_txq_props(ah, q, qinfo);
        }

        return q;
}
int ath9k_hw_releasetxqueue ( struct ath_hw ah,
u32  q 
)

Definition at line 259 of file ath9k_mac.c.

References ath9k_hw_set_txq_interrupts(), ATH9K_TX_QUEUE_INACTIVE, DBG, DBG2, ath9k_tx_queue_info::tqi_type, ath_hw::txdesc_interrupt_mask, ath_hw::txeol_interrupt_mask, ath_hw::txerr_interrupt_mask, ath_hw::txok_interrupt_mask, ath_hw::txq, and ath_hw::txurn_interrupt_mask.

Referenced by ath_tx_cleanupq(), and ath_txq_setup().

{
        struct ath9k_tx_queue_info *qi;

        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: "
                        "Release TXQ, inactive queue: %d\n", q);
                return 0;
        }

        DBG2("ath9k: Release TX queue: %d\n", q);

        qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
        ah->txok_interrupt_mask &= ~(1 << q);
        ah->txerr_interrupt_mask &= ~(1 << q);
        ah->txdesc_interrupt_mask &= ~(1 << q);
        ah->txeol_interrupt_mask &= ~(1 << q);
        ah->txurn_interrupt_mask &= ~(1 << q);
        ath9k_hw_set_txq_interrupts(ah, qi);

        return 1;
}
int ath9k_hw_resettxqueue ( struct ath_hw ah,
u32  q 
)

Definition at line 283 of file ath9k_mac.c.

References __unused, AR_D_CHNTIME_DUR, AR_D_CHNTIME_EN, AR_D_LCL_IFS_AIFS, AR_D_LCL_IFS_CWMAX, AR_D_LCL_IFS_CWMIN, AR_D_MISC_ARB_LOCKOUT_CNTRL, AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, AR_D_MISC_CW_BKOFF_EN, AR_D_MISC_FRAG_BKOFF_EN, AR_D_MISC_FRAG_WAIT_EN, AR_D_MISC_POST_FR_BKOFF_DIS, AR_D_RETRY_LIMIT_FR_SH, AR_D_RETRY_LIMIT_STA_LG, AR_D_RETRY_LIMIT_STA_SH, AR_DCHNTIME, AR_DLCL_IFS, AR_DMISC, AR_DRETRY_LIMIT, AR_Q_CBRCFG_INTERVAL, AR_Q_CBRCFG_OVF_THRESH, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN, AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN, AR_Q_MISC_DCU_EARLY_TERM_REQ, AR_Q_MISC_FSP_CBR, AR_Q_MISC_RDYTIME_EXP_POLICY, AR_Q_RDYTIMECFG_DURATION, AR_Q_RDYTIMECFG_EN, AR_QCBRCFG, AR_QMISC, AR_QRDYTIMECFG, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, ath9k_hw_set_txq_interrupts(), ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS, ATH9K_TXQ_USEDEFAULT, ath9k_channel::chan, ath_hw::curchan, DBG, DBG2, ENABLE_REGWRITE_BUFFER, INIT_CWMIN, INIT_CWMIN_11B, INIT_SLG_RETRY, INIT_SSH_RETRY, IS_CHAN_B, REG_SET_BIT, REG_WRITE, REGWRITE_BUFFER_FLUSH, SM, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_burstTime, ath9k_tx_queue_info::tqi_cbrOverflowLimit, ath9k_tx_queue_info::tqi_cbrPeriod, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_intFlags, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_readyTime, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_type, ath_hw::txdesc_interrupt_mask, ath_hw::txeol_interrupt_mask, ath_hw::txerr_interrupt_mask, ath_hw::txok_interrupt_mask, ath_hw::txq, TXQ_FLAG_BACKOFF_DISABLE, TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXEOLINT_ENABLE, TXQ_FLAG_TXERRINT_ENABLE, TXQ_FLAG_TXOKINT_ENABLE, TXQ_FLAG_TXURNINT_ENABLE, ath_hw::txurn_interrupt_mask, and value.

Referenced by ath9k_hw_reset().

{
        struct ath9k_channel *chan = ah->curchan;
        struct ath9k_tx_queue_info *qi;
        u32 cwMin, chanCwMin, value __unused;

        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: "
                        "Reset TXQ, inactive queue: %d\n", q);
                return 1;
        }

        DBG2("ath9k: Reset TX queue: %d\n", q);

        if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
                if (chan && IS_CHAN_B(chan))
                        chanCwMin = INIT_CWMIN_11B;
                else
                        chanCwMin = INIT_CWMIN;

                for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
        } else
                cwMin = qi->tqi_cwmin;

        ENABLE_REGWRITE_BUFFER(ah);

        REG_WRITE(ah, AR_DLCL_IFS(q),
                  SM(cwMin, AR_D_LCL_IFS_CWMIN) |
                  SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
                  SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));

        REG_WRITE(ah, AR_DRETRY_LIMIT(q),
                  SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
                  SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
                  SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));

        REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);

        if (AR_SREV_9340(ah))
                REG_WRITE(ah, AR_DMISC(q),
                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
        else
                REG_WRITE(ah, AR_DMISC(q),
                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);

        if (qi->tqi_cbrPeriod) {
                REG_WRITE(ah, AR_QCBRCFG(q),
                          SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
                          SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
                            (qi->tqi_cbrOverflowLimit ?
                             AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
        }
        if (qi->tqi_readyTime) {
                REG_WRITE(ah, AR_QRDYTIMECFG(q),
                          SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
                          AR_Q_RDYTIMECFG_EN);
        }

        REG_WRITE(ah, AR_DCHNTIME(q),
                  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
                  (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));

        if (qi->tqi_burstTime
            && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);

        if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);

        REGWRITE_BUFFER_FLUSH(ah);

        if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);

        if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
                REG_SET_BIT(ah, AR_DMISC(q),
                            SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
                               AR_D_MISC_ARB_LOCKOUT_CNTRL) |
                            AR_D_MISC_POST_FR_BKOFF_DIS);
        }

        if (AR_SREV_9300_20_OR_LATER(ah))
                REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);

        if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
                ah->txok_interrupt_mask |= 1 << q;
        else
                ah->txok_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
                ah->txerr_interrupt_mask |= 1 << q;
        else
                ah->txerr_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
                ah->txdesc_interrupt_mask |= 1 << q;
        else
                ah->txdesc_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
                ah->txeol_interrupt_mask |= 1 << q;
        else
                ah->txeol_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
                ah->txurn_interrupt_mask |= 1 << q;
        else
                ah->txurn_interrupt_mask &= ~(1 << q);
        ath9k_hw_set_txq_interrupts(ah, qi);

        return 1;
}
int ath9k_hw_rxprocdesc ( struct ath_hw ah,
struct ath_desc ds,
struct ath_rx_status rs,
u64  tsf 
)

Definition at line 394 of file ath9k_mac.c.

References AR5416DESC, AR_2040, AR_CRCErr, AR_DataLen, AR_DecryptBusyErr, AR_DecryptCRCErr, AR_GI, AR_KeyIdx, AR_KeyMiss, AR_MichaelErr, AR_PHYErr, AR_PHYErrCode, AR_PostDelimCRCErr, AR_PreDelimCRCErr, AR_RxAggr, AR_RxAntenna, AR_RxDone, AR_RxFrameOK, AR_RxKeyIdxValid, AR_RxMore, AR_RxMoreAggr, AR_RxRSSIAnt00, AR_RxRSSIAnt01, AR_RxRSSIAnt02, AR_RxRSSIAnt10, AR_RxRSSIAnt11, AR_RxRSSIAnt12, AR_RxRSSICombined, ATH9K_RSSI_BAD, ATH9K_RX_2040, ATH9K_RX_DECRYPT_BUSY, ATH9K_RX_DELIM_CRC_POST, ATH9K_RX_DELIM_CRC_PRE, ATH9K_RX_GI, ATH9K_RXERR_CRC, ATH9K_RXERR_DECRYPT, ATH9K_RXERR_MIC, ATH9K_RXERR_PHY, ATH9K_RXKEYIX_INVALID, EINPROGRESS, MS, ath_rx_status::rs_antenna, ath_rx_status::rs_datalen, ath_rx_status::rs_flags, ath_rx_status::rs_isaggr, ath_rx_status::rs_keyix, ath_rx_status::rs_more, ath_rx_status::rs_moreaggr, ath_rx_status::rs_phyerr, ath_rx_status::rs_rate, ath_rx_status::rs_rssi, ath_rx_status::rs_rssi_ctl0, ath_rx_status::rs_rssi_ctl1, ath_rx_status::rs_rssi_ctl2, ath_rx_status::rs_rssi_ext0, ath_rx_status::rs_rssi_ext1, ath_rx_status::rs_rssi_ext2, ath_rx_status::rs_status, ath_rx_status::rs_tstamp, ar5416_desc::rx, RXSTATUS_RATE, and ar5416_desc::u.

Referenced by ath_get_next_rx_buf().

{
        struct ar5416_desc ads;
        struct ar5416_desc *adsp = AR5416DESC(ds);
        u32 phyerr;

        if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
                return -EINPROGRESS;

        ads.u.rx = adsp->u.rx;

        rs->rs_status = 0;
        rs->rs_flags = 0;

        rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
        rs->rs_tstamp = ads.AR_RcvTimestamp;

        if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
                rs->rs_rssi = ATH9K_RSSI_BAD;
                rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
        } else {
                rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
                rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
                                                AR_RxRSSIAnt00);
                rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
                                                AR_RxRSSIAnt01);
                rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
                                                AR_RxRSSIAnt02);
                rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
                                                AR_RxRSSIAnt10);
                rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
                                                AR_RxRSSIAnt11);
                rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
                                                AR_RxRSSIAnt12);
        }
        if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
                rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
        else
                rs->rs_keyix = ATH9K_RXKEYIX_INVALID;

        rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
        rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;

        rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
        rs->rs_moreaggr =
                (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
        rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
        rs->rs_flags =
                (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
        rs->rs_flags |=
                (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;

        if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
                rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
        if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
                rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
        if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
                rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;

        if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
                /*
                 * Treat these errors as mutually exclusive to avoid spurious
                 * extra error reports from the hardware. If a CRC error is
                 * reported, then decryption and MIC errors are irrelevant,
                 * the frame is going to be dropped either way
                 */
                if (ads.ds_rxstatus8 & AR_CRCErr)
                        rs->rs_status |= ATH9K_RXERR_CRC;
                else if (ads.ds_rxstatus8 & AR_PHYErr) {
                        rs->rs_status |= ATH9K_RXERR_PHY;
                        phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
                        rs->rs_phyerr = phyerr;
                } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
                        rs->rs_status |= ATH9K_RXERR_DECRYPT;
                else if (ads.ds_rxstatus8 & AR_MichaelErr)
                        rs->rs_status |= ATH9K_RXERR_MIC;
                else if (ads.ds_rxstatus8 & AR_KeyMiss)
                        rs->rs_status |= ATH9K_RXERR_DECRYPT;
        }

        return 0;
}
void ath9k_hw_setuprxdesc ( struct ath_hw ah,
struct ath_desc ds,
u32  size,
u32  flags 
)
int ath9k_hw_setrxabort ( struct ath_hw ah,
int  set 
)

Definition at line 490 of file ath9k_mac.c.

References AH_WAIT_TIMEOUT, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, ath9k_hw_wait(), DBG, reg, REG_CLR_BIT, REG_READ, and REG_SET_BIT.

Referenced by ath_isr().

{
        u32 reg;

        if (set) {
                REG_SET_BIT(ah, AR_DIAG_SW,
                            (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

                if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
                                   0, AH_WAIT_TIMEOUT)) {
                        REG_CLR_BIT(ah, AR_DIAG_SW,
                                    (AR_DIAG_RX_DIS |
                                     AR_DIAG_RX_ABORT));

                        reg = REG_READ(ah, AR_OBS_BUS_1);
                        DBG("ath9k: "
                                "RX failed to go idle in 10 ms RXSM=0x%x\n",
                                reg);

                        return 0;
                }
        } else {
                REG_CLR_BIT(ah, AR_DIAG_SW,
                            (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
        }

        return 1;
}
void ath9k_hw_putrxbuf ( struct ath_hw ah,
u32  rxdp 
)

Definition at line 519 of file ath9k_mac.c.

References AR_RXDP, and REG_WRITE.

Referenced by ath_rx_buf_link(), and ath_startrecv().

{
        REG_WRITE(ah, AR_RXDP, rxdp);
}
void ath9k_hw_startpcureceive ( struct ath_hw ah,
int  is_scanning 
)

Definition at line 524 of file ath9k_mac.c.

References AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, ath9k_ani_reset(), and REG_CLR_BIT.

Referenced by ath_startrecv().

void ath9k_hw_abortpcurecv ( struct ath_hw ah)

Definition at line 531 of file ath9k_mac.c.

References AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, and REG_SET_BIT.

Referenced by ath_stoprecv().

int ath9k_hw_stopdmarecv ( struct ath_hw ah,
int *  reset 
)

Definition at line 536 of file ath9k_mac.c.

References AH_RX_STOP_DMA_TIMEOUT, AH_TIME_QUANTUM, AR_CR, AR_CR_RXD, AR_CR_RXE, AR_DIAG_SW, AR_DMADBG_7, AR_MACMISC, AR_MACMISC_DMA_OBS_LINE_8, AR_MACMISC_DMA_OBS_S, AR_MACMISC_MISC_OBS_BUS_1, AR_MACMISC_MISC_OBS_BUS_MSB_S, AR_SREV_9300_20_OR_LATER, DBG, REG_READ, REG_WRITE, and udelay().

Referenced by ath_stoprecv().

{
#define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
        u32 mac_status, last_mac_status = 0;
        int i;

        /* Enable access to the DMA observation bus */
        REG_WRITE(ah, AR_MACMISC,
                  ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
                   (AR_MACMISC_MISC_OBS_BUS_1 <<
                    AR_MACMISC_MISC_OBS_BUS_MSB_S)));

        REG_WRITE(ah, AR_CR, AR_CR_RXD);

        /* Wait for rx enable bit to go low */
        for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
                if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
                        break;

                if (!AR_SREV_9300_20_OR_LATER(ah)) {
                        mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
                        if (mac_status == 0x1c0 && mac_status == last_mac_status) {
                                *reset = 1;
                                break;
                        }

                        last_mac_status = mac_status;
                }

                udelay(AH_TIME_QUANTUM);
        }

        if (i == 0) {
                DBG("ath9k: "
                        "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
                        AH_RX_STOP_DMA_TIMEOUT / 1000,
                        REG_READ(ah, AR_CR),
                        REG_READ(ah, AR_DIAG_SW),
                        REG_READ(ah, AR_DMADBG_7));
                return 0;
        } else {
                return 1;
        }

#undef AH_RX_STOP_DMA_TIMEOUT
}
int ath9k_hw_intrpend ( struct ath_hw ah)

Definition at line 583 of file ath9k_mac.c.

References ath_hw::ah_ier, AR_IER_ENABLE, AR_INTR_ASYNC_CAUSE, AR_INTR_MAC_IRQ, AR_INTR_SPURIOUS, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_DEFAULT, AR_SREV_9100, and REG_READ.

Referenced by ath_isr().

{
        u32 host_isr;

        if (AR_SREV_9100(ah) || !(ah->ah_ier & AR_IER_ENABLE))
                return 1;

        host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
        if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
                return 1;

        host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
        if ((host_isr & AR_INTR_SYNC_DEFAULT)
            && (host_isr != AR_INTR_SPURIOUS))
                return 1;

        return 0;
}
void ath9k_hw_set_interrupts ( struct ath_hw ah,
unsigned int  ints 
)

Definition at line 641 of file ath9k_mac.c.

References AR_IMR, AR_IMR_BCNMISC, AR_IMR_GENTMR, AR_IMR_RXDESC, AR_IMR_RXERR, AR_IMR_RXINTM, AR_IMR_RXMINTR, AR_IMR_RXOK, AR_IMR_RXOK_HP, AR_IMR_RXOK_LP, AR_IMR_S2, AR_IMR_S2_CABEND, AR_IMR_S2_CABTO, AR_IMR_S2_CST, AR_IMR_S2_DTIM, AR_IMR_S2_DTIMSYNC, AR_IMR_S2_GTT, AR_IMR_S2_TIM, AR_IMR_S2_TSFOOR, AR_IMR_S5, AR_IMR_S5_TIM_TIMER, AR_IMR_TXDESC, AR_IMR_TXEOL, AR_IMR_TXERR, AR_IMR_TXINTM, AR_IMR_TXMINTR, AR_IMR_TXOK, AR_SREV_9300_20_OR_LATER, ATH9K_HW_CAP_AUTOSLEEP, ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), ATH9K_INT_BMISC, ATH9K_INT_CABEND, ATH9K_INT_COMMON, ATH9K_INT_CST, ATH9K_INT_DTIM, ATH9K_INT_DTIMSYNC, ATH9K_INT_GENTIMER, ATH9K_INT_GLOBAL, ATH9K_INT_GTT, ATH9K_INT_RX, ATH9K_INT_TIM, ATH9K_INT_TIM_TIMER, ATH9K_INT_TSFOOR, ATH9K_INT_TX, ath_hw::caps, ath_hw::config, DBG2, ath9k_hw_capabilities::hw_caps, ath_hw::imask, ath_hw::imrs2_reg, REG_CLR_BIT, REG_SET_BIT, REG_WRITE, ath9k_ops_config::rx_intr_mitigation, ath9k_ops_config::tx_intr_mitigation, ath_hw::txdesc_interrupt_mask, ath_hw::txeol_interrupt_mask, ath_hw::txerr_interrupt_mask, and ath_hw::txok_interrupt_mask.

Referenced by ath9k_irq(), ath9k_start(), ath_reset(), and ath_set_channel().

{
        enum ath9k_int omask = ah->imask;
        u32 mask, mask2;
        struct ath9k_hw_capabilities *pCap = &ah->caps;

        if (!(ints & ATH9K_INT_GLOBAL))
                ath9k_hw_disable_interrupts(ah);

        DBG2("ath9k: 0x%x => 0x%x\n", omask, ints);

        /* TODO: global int Ref count */
        mask = ints & ATH9K_INT_COMMON;
        mask2 = 0;

        if (ints & ATH9K_INT_TX) {
                if (ah->config.tx_intr_mitigation)
                        mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
                else {
                        if (ah->txok_interrupt_mask)
                                mask |= AR_IMR_TXOK;
                        if (ah->txdesc_interrupt_mask)
                                mask |= AR_IMR_TXDESC;
                }
                if (ah->txerr_interrupt_mask)
                        mask |= AR_IMR_TXERR;
                if (ah->txeol_interrupt_mask)
                        mask |= AR_IMR_TXEOL;
        }
        if (ints & ATH9K_INT_RX) {
                if (AR_SREV_9300_20_OR_LATER(ah)) {
                        mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
                        if (ah->config.rx_intr_mitigation) {
                                mask &= ~AR_IMR_RXOK_LP;
                                mask |=  AR_IMR_RXMINTR | AR_IMR_RXINTM;
                        } else {
                                mask |= AR_IMR_RXOK_LP;
                        }
                } else {
                        if (ah->config.rx_intr_mitigation)
                                mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
                        else
                                mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
                }
                if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                        mask |= AR_IMR_GENTMR;
        }

        if (ints & ATH9K_INT_GENTIMER)
                mask |= AR_IMR_GENTMR;

        if (ints & (ATH9K_INT_BMISC)) {
                mask |= AR_IMR_BCNMISC;
                if (ints & ATH9K_INT_TIM)
                        mask2 |= AR_IMR_S2_TIM;
                if (ints & ATH9K_INT_DTIM)
                        mask2 |= AR_IMR_S2_DTIM;
                if (ints & ATH9K_INT_DTIMSYNC)
                        mask2 |= AR_IMR_S2_DTIMSYNC;
                if (ints & ATH9K_INT_CABEND)
                        mask2 |= AR_IMR_S2_CABEND;
                if (ints & ATH9K_INT_TSFOOR)
                        mask2 |= AR_IMR_S2_TSFOOR;
        }

        if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
                mask |= AR_IMR_BCNMISC;
                if (ints & ATH9K_INT_GTT)
                        mask2 |= AR_IMR_S2_GTT;
                if (ints & ATH9K_INT_CST)
                        mask2 |= AR_IMR_S2_CST;
        }

        DBG2("ath9k: new IMR 0x%x\n", mask);
        REG_WRITE(ah, AR_IMR, mask);
        ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
                           AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
                           AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
        ah->imrs2_reg |= mask2;
        REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);

        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
                if (ints & ATH9K_INT_TIM_TIMER)
                        REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
                else
                        REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
        }

        if (ints & ATH9K_INT_GLOBAL)
                ath9k_hw_enable_interrupts(ah);

        return;
}
void ath9k_hw_enable_interrupts ( struct ath_hw ah)
void ath9k_hw_disable_interrupts ( struct ath_hw ah)
void ar9002_hw_attach_mac_ops ( struct ath_hw ah)