iPXE
mc_driver_pcol.h
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00001 /****************************************************************************
00002  * Driver for Solarflare network controllers and boards
00003  * Copyright 2012-2017 Solarflare Communications Inc.
00004  *
00005  * This program is free software; you can redistribute it and/or
00006  * modify it under the terms of the GNU General Public License as
00007  * published by the Free Software Foundation; either version 2 of the
00008  * License, or any later version.
00009  *
00010  * You can also choose to distribute this program under the terms of
00011  * the Unmodified Binary Distribution Licence (as given in the file
00012  * COPYING.UBDL), provided that you have satisfied its requirements.
00013  */
00014 #ifndef SFC_MCDI_PCOL_H
00015 #define SFC_MCDI_PCOL_H
00016 
00017 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00018 
00019 /** \file mc_driver_pcol.h
00020  * This file is a subset of the MCDI headers generated from the yml files.
00021  */
00022 
00023 /* The current version of the MCDI protocol.
00024  *
00025  * Note that the ROM burnt into the card only talks V0, so at the very
00026  * least every driver must support version 0 and MCDI_PCOL_VERSION
00027  */
00028 #ifdef WITH_MCDI_V2
00029 #define MCDI_PCOL_VERSION 2
00030 #else
00031 #define MCDI_PCOL_VERSION 1
00032 #endif
00033 
00034 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
00035 
00036 /* MCDI version 1
00037  *
00038  * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
00039  * structure, filled in by the client.
00040  *
00041  *       0       7  8     16    20     22  23  24    31
00042  *      | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
00043  *               |                      |   |
00044  *               |                      |   \--- Response
00045  *               |                      \------- Error
00046  *               \------------------------------ Resync (always set)
00047  *
00048  * The client writes it's request into MC shared memory, and rings the
00049  * doorbell. Each request is completed by either by the MC writing
00050  * back into shared memory, or by writing out an event.
00051  *
00052  * All MCDI commands support completion by shared memory response. Each
00053  * request may also contain additional data (accounted for by HEADER.LEN),
00054  * and some response's may also contain additional data (again, accounted
00055  * for by HEADER.LEN).
00056  *
00057  * Some MCDI commands support completion by event, in which any associated
00058  * response data is included in the event.
00059  *
00060  * The protocol requires one response to be delivered for every request, a
00061  * request should not be sent unless the response for the previous request
00062  * has been received (either by polling shared memory, or by receiving
00063  * an event).
00064  */
00065 
00066 /** Request/Response structure */
00067 #define MCDI_HEADER_OFST 0
00068 #define MCDI_HEADER_CODE_LBN 0
00069 #define MCDI_HEADER_CODE_WIDTH 7
00070 #define MCDI_HEADER_RESYNC_LBN 7
00071 #define MCDI_HEADER_RESYNC_WIDTH 1
00072 #define MCDI_HEADER_DATALEN_LBN 8
00073 #define MCDI_HEADER_DATALEN_WIDTH 8
00074 #define MCDI_HEADER_SEQ_LBN 16
00075 #define MCDI_HEADER_SEQ_WIDTH 4
00076 #define MCDI_HEADER_RSVD_LBN 20
00077 #define MCDI_HEADER_RSVD_WIDTH 1
00078 #define MCDI_HEADER_NOT_EPOCH_LBN 21
00079 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
00080 #define MCDI_HEADER_ERROR_LBN 22
00081 #define MCDI_HEADER_ERROR_WIDTH 1
00082 #define MCDI_HEADER_RESPONSE_LBN 23
00083 #define MCDI_HEADER_RESPONSE_WIDTH 1
00084 #define MCDI_HEADER_XFLAGS_LBN 24
00085 #define MCDI_HEADER_XFLAGS_WIDTH 8
00086 /* Request response using event */
00087 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
00088 /* Request (and signal) early doorbell return */
00089 #define MCDI_HEADER_XFLAGS_DBRET 0x02
00090 
00091 /* Maximum number of payload bytes */
00092 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
00093 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
00094 
00095 #ifdef WITH_MCDI_V2
00096 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
00097 #else
00098 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1
00099 #endif
00100 
00101 
00102 /* The MC can generate events for two reasons:
00103  *   - To advance a shared memory request if XFLAGS_EVREQ was set
00104  *   - As a notification (link state, i2c event), controlled
00105  *     via MC_CMD_LOG_CTRL
00106  *
00107  * Both events share a common structure:
00108  *
00109  *  0      32     33      36    44     52     60
00110  * | Data | Cont | Level | Src | Code | Rsvd |
00111  *           |
00112  *           \ There is another event pending in this notification
00113  *
00114  * If Code==CMDDONE, then the fields are further interpreted as:
00115  *
00116  *   - LEVEL==INFO    Command succeeded
00117  *   - LEVEL==ERR     Command failed
00118  *
00119  *    0     8         16      24     32
00120  *   | Seq | Datalen | Errno | Rsvd |
00121  *
00122  *   These fields are taken directly out of the standard MCDI header, i.e.,
00123  *   LEVEL==ERR, Datalen == 0 => Reboot
00124  *
00125  * Events can be squirted out of the UART (using LOG_CTRL) without a
00126  * MCDI header.  An event can be distinguished from a MCDI response by
00127  * examining the first byte which is 0xc0.  This corresponds to the
00128  * non-existent MCDI command MC_CMD_DEBUG_LOG.
00129  *
00130  *      0         7        8
00131  *     | command | Resync |     = 0xc0
00132  *
00133  * Since the event is written in big-endian byte order, this works
00134  * providing bits 56-63 of the event are 0xc0.
00135  *
00136  *      56     60  63
00137  *     | Rsvd | Code |    = 0xc0
00138  *
00139  * Which means for convenience the event code is 0xc for all MC
00140  * generated events.
00141  */
00142 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
00143 
00144 
00145 /* Operation not permitted. */
00146 #define MC_CMD_ERR_EPERM 1
00147 /* Non-existent command target */
00148 #define MC_CMD_ERR_ENOENT 2
00149 /* assert() has killed the MC */
00150 #define MC_CMD_ERR_EINTR 4
00151 /* I/O failure */
00152 #define MC_CMD_ERR_EIO 5
00153 /* Already exists */
00154 #define MC_CMD_ERR_EEXIST 6
00155 /* Try again */
00156 #define MC_CMD_ERR_EAGAIN 11
00157 /* Out of memory */
00158 #define MC_CMD_ERR_ENOMEM 12
00159 /* Caller does not hold required locks */
00160 #define MC_CMD_ERR_EACCES 13
00161 /* Resource is currently unavailable (e.g. lock contention) */
00162 #define MC_CMD_ERR_EBUSY 16
00163 /* No such device */
00164 #define MC_CMD_ERR_ENODEV 19
00165 /* Invalid argument to target */
00166 #define MC_CMD_ERR_EINVAL 22
00167 /* Broken pipe */
00168 #define MC_CMD_ERR_EPIPE 32
00169 /* Read-only */
00170 #define MC_CMD_ERR_EROFS 30
00171 /* Out of range */
00172 #define MC_CMD_ERR_ERANGE 34
00173 /* Non-recursive resource is already acquired */
00174 #define MC_CMD_ERR_EDEADLK 35
00175 /* Operation not implemented */
00176 #define MC_CMD_ERR_ENOSYS 38
00177 /* Operation timed out */
00178 #define MC_CMD_ERR_ETIME 62
00179 /* Link has been severed */
00180 #define MC_CMD_ERR_ENOLINK 67
00181 /* Protocol error */
00182 #define MC_CMD_ERR_EPROTO 71
00183 /* Operation not supported */
00184 #define MC_CMD_ERR_ENOTSUP 95
00185 /* Address not available */
00186 #define MC_CMD_ERR_EADDRNOTAVAIL 99
00187 /* Not connected */
00188 #define MC_CMD_ERR_ENOTCONN 107
00189 /* Operation already in progress */
00190 #define MC_CMD_ERR_EALREADY 114
00191 
00192 /* Resource allocation failed. */
00193 #define MC_CMD_ERR_ALLOC_FAIL  0x1000
00194 /* V-adaptor not found. */
00195 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
00196 /* EVB port not found. */
00197 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
00198 /* V-switch not found. */
00199 #define MC_CMD_ERR_NO_VSWITCH  0x1003
00200 /* Too many VLAN tags. */
00201 #define MC_CMD_ERR_VLAN_LIMIT  0x1004
00202 /* Bad PCI function number. */
00203 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
00204 /* Invalid VLAN mode. */
00205 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
00206 /* Invalid v-switch type. */
00207 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
00208 /* Invalid v-port type. */
00209 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
00210 /* MAC address exists. */
00211 #define MC_CMD_ERR_MAC_EXIST 0x1009
00212 /* Slave core not present */
00213 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
00214 /* The datapath is disabled. */
00215 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
00216 /* The requesting client is not a function */
00217 #define MC_CMD_ERR_CLIENT_NOT_FN  0x100c
00218 /* The requested operation might require the
00219  * command to be passed between MCs, and the
00220  * transport doesn't support that.  Should
00221  * only ever been seen over the UART.
00222  */
00223 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
00224 /* VLAN tag(s) exists */
00225 #define MC_CMD_ERR_VLAN_EXIST 0x100e
00226 /* No MAC address assigned to an EVB port */
00227 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
00228 /* Notifies the driver that the request has been relayed
00229  * to an admin function for authorization. The driver should
00230  * wait for a PROXY_RESPONSE event and then resend its request.
00231  * This error code is followed by a 32-bit handle that
00232  * helps matching it with the respective PROXY_RESPONSE event.
00233  */
00234 #define MC_CMD_ERR_PROXY_PENDING 0x1010
00235 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
00236 /* The request cannot be passed for authorization because
00237  * another request from the same function is currently being
00238  * authorized. The drvier should try again later.
00239  */
00240 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
00241 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
00242  * that has enabled proxying or BLOCK_INDEX points to a function that
00243  * doesn't await an authorization.
00244  */
00245 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
00246 /* This code is currently only used internally in FW. Its meaning is that
00247  * an operation failed due to lack of SR-IOV privilege.
00248  * Normally it is translated to EPERM by send_cmd_err(),
00249  * but it may also be used to trigger some special mechanism
00250  * for handling such case, e.g. to relay the failed request
00251  * to a designated admin function for authorization.
00252  */
00253 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
00254 /* Workaround 26807 could not be turned on/off because some functions
00255  * have already installed filters. See the comment at
00256  * MC_CMD_WORKAROUND_BUG26807.
00257  */
00258 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
00259 /* The clock whose frequency you've attempted to set set
00260  * doesn't exist on this NIC
00261  */
00262 #define MC_CMD_ERR_NO_CLOCK 0x1015
00263 /* Returned by MC_CMD_TESTASSERT if the action that should
00264  * have caused an assertion failed to do so.
00265  */
00266 #define MC_CMD_ERR_UNREACHABLE 0x1016
00267 /* This command needs to be processed in the background but there were no
00268  * resources to do so. Send it again after a command has completed.
00269  */
00270 #define MC_CMD_ERR_QUEUE_FULL 0x1017
00271 
00272 #define MC_CMD_ERR_CODE_OFST 0
00273 
00274 
00275 #ifdef WITH_MCDI_V2
00276 
00277 /* Version 2 adds an optional argument to error returns: the errno value
00278  * may be followed by the (0-based) number of the first argument that
00279  * could not be processed.
00280  */
00281 #define MC_CMD_ERR_ARG_OFST 4
00282 
00283 /* No space */
00284 #define MC_CMD_ERR_ENOSPC 28
00285 
00286 #endif
00287 
00288 /* MCDI_EVENT structuredef */
00289 #define    MCDI_EVENT_LEN 8
00290 #define       MCDI_EVENT_CONT_LBN 32
00291 #define       MCDI_EVENT_CONT_WIDTH 1
00292 #define       MCDI_EVENT_LEVEL_LBN 33
00293 #define       MCDI_EVENT_LEVEL_WIDTH 3
00294 /* enum: Info. */
00295 #define          MCDI_EVENT_LEVEL_INFO  0x0
00296 /* enum: Warning. */
00297 #define          MCDI_EVENT_LEVEL_WARN 0x1
00298 /* enum: Error. */
00299 #define          MCDI_EVENT_LEVEL_ERR 0x2
00300 /* enum: Fatal. */
00301 #define          MCDI_EVENT_LEVEL_FATAL 0x3
00302 #define       MCDI_EVENT_DATA_OFST 0
00303 #define        MCDI_EVENT_CMDDONE_SEQ_LBN 0
00304 #define        MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
00305 #define        MCDI_EVENT_CMDDONE_DATALEN_LBN 8
00306 #define        MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
00307 #define        MCDI_EVENT_CMDDONE_ERRNO_LBN 16
00308 #define        MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
00309 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
00310 #define        MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
00311 #define        MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
00312 #define        MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
00313 /* enum: 100Mbs */
00314 #define          MCDI_EVENT_LINKCHANGE_SPEED_100M  0x1
00315 /* enum: 1Gbs */
00316 #define          MCDI_EVENT_LINKCHANGE_SPEED_1G  0x2
00317 /* enum: 10Gbs */
00318 #define          MCDI_EVENT_LINKCHANGE_SPEED_10G  0x3
00319 /* enum: 40Gbs */
00320 #define          MCDI_EVENT_LINKCHANGE_SPEED_40G  0x4
00321 #define        MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
00322 #define        MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
00323 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
00324 #define        MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
00325 #define        MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
00326 #define        MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
00327 #define        MCDI_EVENT_SENSOREVT_STATE_LBN 8
00328 #define        MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
00329 #define        MCDI_EVENT_SENSOREVT_VALUE_LBN 16
00330 #define        MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
00331 #define        MCDI_EVENT_FWALERT_DATA_LBN 8
00332 #define        MCDI_EVENT_FWALERT_DATA_WIDTH 24
00333 #define        MCDI_EVENT_FWALERT_REASON_LBN 0
00334 #define        MCDI_EVENT_FWALERT_REASON_WIDTH 8
00335 /* enum: SRAM Access. */
00336 #define          MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
00337 #define        MCDI_EVENT_FLR_VF_LBN 0
00338 #define        MCDI_EVENT_FLR_VF_WIDTH 8
00339 #define        MCDI_EVENT_TX_ERR_TXQ_LBN 0
00340 #define        MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
00341 #define        MCDI_EVENT_TX_ERR_TYPE_LBN 12
00342 #define        MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
00343 /* enum: Descriptor loader reported failure */
00344 #define          MCDI_EVENT_TX_ERR_DL_FAIL 0x1
00345 /* enum: Descriptor ring empty and no EOP seen for packet */
00346 #define          MCDI_EVENT_TX_ERR_NO_EOP 0x2
00347 /* enum: Overlength packet */
00348 #define          MCDI_EVENT_TX_ERR_2BIG 0x3
00349 /* enum: Malformed option descriptor */
00350 #define          MCDI_EVENT_TX_BAD_OPTDESC 0x5
00351 /* enum: Option descriptor part way through a packet */
00352 #define          MCDI_EVENT_TX_OPT_IN_PKT 0x8
00353 /* enum: DMA or PIO data access error */
00354 #define          MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
00355 #define        MCDI_EVENT_TX_ERR_INFO_LBN 16
00356 #define        MCDI_EVENT_TX_ERR_INFO_WIDTH 16
00357 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
00358 #define        MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
00359 #define        MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
00360 #define        MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
00361 #define        MCDI_EVENT_PTP_ERR_TYPE_LBN 0
00362 #define        MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
00363 /* enum: PLL lost lock */
00364 #define          MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
00365 /* enum: Filter overflow (PDMA) */
00366 #define          MCDI_EVENT_PTP_ERR_FILTER 0x2
00367 /* enum: FIFO overflow (FPGA) */
00368 #define          MCDI_EVENT_PTP_ERR_FIFO 0x3
00369 /* enum: Merge queue overflow */
00370 #define          MCDI_EVENT_PTP_ERR_QUEUE 0x4
00371 #define        MCDI_EVENT_AOE_ERR_TYPE_LBN 0
00372 #define        MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
00373 /* enum: AOE failed to load - no valid image? */
00374 #define          MCDI_EVENT_AOE_NO_LOAD 0x1
00375 /* enum: AOE FC reported an exception */
00376 #define          MCDI_EVENT_AOE_FC_ASSERT 0x2
00377 /* enum: AOE FC watchdogged */
00378 #define          MCDI_EVENT_AOE_FC_WATCHDOG 0x3
00379 /* enum: AOE FC failed to start */
00380 #define          MCDI_EVENT_AOE_FC_NO_START 0x4
00381 /* enum: Generic AOE fault - likely to have been reported via other means too
00382  * but intended for use by aoex driver.
00383  */
00384 #define          MCDI_EVENT_AOE_FAULT 0x5
00385 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
00386 #define          MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
00387 /* enum: AOE loaded successfully */
00388 #define          MCDI_EVENT_AOE_LOAD 0x7
00389 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
00390 #define          MCDI_EVENT_AOE_DMA 0x8
00391 /* enum: AOE byteblaster connected/disconnected (Connection status in
00392  * AOE_ERR_DATA)
00393  */
00394 #define          MCDI_EVENT_AOE_BYTEBLASTER 0x9
00395 /* enum: DDR ECC status update */
00396 #define          MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
00397 /* enum: PTP status update */
00398 #define          MCDI_EVENT_AOE_PTP_STATUS 0xb
00399 /* enum: FPGA header incorrect */
00400 #define          MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
00401 /* enum: FPGA Powered Off due to error in powering up FPGA */
00402 #define          MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
00403 /* enum: AOE FPGA load failed due to MC to MUM communication failure */
00404 #define          MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
00405 /* enum: Notify that invalid flash type detected */
00406 #define          MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
00407 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */
00408 #define          MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
00409 /* enum: Failure to probe one or more FPGA boot flash chips */
00410 #define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
00411 /* enum: FPGA boot-flash contains an invalid image header */
00412 #define          MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
00413 /* enum: Failed to program clocks required by the FPGA */
00414 #define          MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
00415 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */
00416 #define          MCDI_EVENT_AOE_FC_RUNNING 0x14
00417 #define        MCDI_EVENT_AOE_ERR_DATA_LBN 8
00418 #define        MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
00419 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
00420 #define        MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
00421 /* enum: FC Assert happened, but the register information is not available */
00422 #define          MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
00423 /* enum: The register information for FC Assert is ready for readinng by driver
00424  */
00425 #define          MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
00426 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
00427 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
00428 /* enum: Reading from NV failed */
00429 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
00430 /* enum: Invalid Magic Number if FPGA header */
00431 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
00432 /* enum: Invalid Silicon type detected in header */
00433 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
00434 /* enum: Unsupported VRatio */
00435 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
00436 /* enum: Unsupported DDR Type */
00437 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
00438 /* enum: DDR Voltage out of supported range */
00439 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
00440 /* enum: Unsupported DDR speed */
00441 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
00442 /* enum: Unsupported DDR size */
00443 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
00444 /* enum: Unsupported DDR rank */
00445 #define          MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
00446 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
00447 #define        MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
00448 /* enum: Primary boot flash */
00449 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
00450 /* enum: Secondary boot flash */
00451 #define          MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
00452 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
00453 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
00454 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
00455 #define        MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
00456 #define        MCDI_EVENT_RX_ERR_RXQ_LBN 0
00457 #define        MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
00458 #define        MCDI_EVENT_RX_ERR_TYPE_LBN 12
00459 #define        MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
00460 #define        MCDI_EVENT_RX_ERR_INFO_LBN 16
00461 #define        MCDI_EVENT_RX_ERR_INFO_WIDTH 16
00462 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
00463 #define        MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
00464 #define        MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
00465 #define        MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
00466 #define        MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
00467 #define        MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
00468 #define        MCDI_EVENT_MUM_ERR_TYPE_LBN 0
00469 #define        MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
00470 /* enum: MUM failed to load - no valid image? */
00471 #define          MCDI_EVENT_MUM_NO_LOAD 0x1
00472 /* enum: MUM f/w reported an exception */
00473 #define          MCDI_EVENT_MUM_ASSERT 0x2
00474 /* enum: MUM not kicking watchdog */
00475 #define          MCDI_EVENT_MUM_WATCHDOG 0x3
00476 #define        MCDI_EVENT_MUM_ERR_DATA_LBN 8
00477 #define        MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
00478 #define       MCDI_EVENT_DATA_LBN 0
00479 #define       MCDI_EVENT_DATA_WIDTH 32
00480 #define       MCDI_EVENT_SRC_LBN 36
00481 #define       MCDI_EVENT_SRC_WIDTH 8
00482 #define       MCDI_EVENT_EV_CODE_LBN 60
00483 #define       MCDI_EVENT_EV_CODE_WIDTH 4
00484 #define       MCDI_EVENT_CODE_LBN 44
00485 #define       MCDI_EVENT_CODE_WIDTH 8
00486 /* enum: Event generated by host software */
00487 #define          MCDI_EVENT_SW_EVENT 0x0
00488 /* enum: Bad assert. */
00489 #define          MCDI_EVENT_CODE_BADSSERT 0x1
00490 /* enum: PM Notice. */
00491 #define          MCDI_EVENT_CODE_PMNOTICE 0x2
00492 /* enum: Command done. */
00493 #define          MCDI_EVENT_CODE_CMDDONE 0x3
00494 /* enum: Link change. */
00495 #define          MCDI_EVENT_CODE_LINKCHANGE 0x4
00496 /* enum: Sensor Event. */
00497 #define          MCDI_EVENT_CODE_SENSOREVT 0x5
00498 /* enum: Schedule error. */
00499 #define          MCDI_EVENT_CODE_SCHEDERR 0x6
00500 /* enum: Reboot. */
00501 #define          MCDI_EVENT_CODE_REBOOT 0x7
00502 /* enum: Mac stats DMA. */
00503 #define          MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
00504 /* enum: Firmware alert. */
00505 #define          MCDI_EVENT_CODE_FWALERT 0x9
00506 /* enum: Function level reset. */
00507 #define          MCDI_EVENT_CODE_FLR 0xa
00508 /* enum: Transmit error */
00509 #define          MCDI_EVENT_CODE_TX_ERR 0xb
00510 /* enum: Tx flush has completed */
00511 #define          MCDI_EVENT_CODE_TX_FLUSH  0xc
00512 /* enum: PTP packet received timestamp */
00513 #define          MCDI_EVENT_CODE_PTP_RX  0xd
00514 /* enum: PTP NIC failure */
00515 #define          MCDI_EVENT_CODE_PTP_FAULT  0xe
00516 /* enum: PTP PPS event */
00517 #define          MCDI_EVENT_CODE_PTP_PPS  0xf
00518 /* enum: Rx flush has completed */
00519 #define          MCDI_EVENT_CODE_RX_FLUSH  0x10
00520 /* enum: Receive error */
00521 #define          MCDI_EVENT_CODE_RX_ERR 0x11
00522 /* enum: AOE fault */
00523 #define          MCDI_EVENT_CODE_AOE  0x12
00524 /* enum: Network port calibration failed (VCAL). */
00525 #define          MCDI_EVENT_CODE_VCAL_FAIL  0x13
00526 /* enum: HW PPS event */
00527 #define          MCDI_EVENT_CODE_HW_PPS  0x14
00528 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
00529  * a different format)
00530  */
00531 #define          MCDI_EVENT_CODE_MC_REBOOT 0x15
00532 /* enum: the MC has detected a parity error */
00533 #define          MCDI_EVENT_CODE_PAR_ERR 0x16
00534 /* enum: the MC has detected a correctable error */
00535 #define          MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
00536 /* enum: the MC has detected an uncorrectable error */
00537 #define          MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
00538 /* enum: The MC has entered offline BIST mode */
00539 #define          MCDI_EVENT_CODE_MC_BIST 0x19
00540 /* enum: PTP tick event providing current NIC time */
00541 #define          MCDI_EVENT_CODE_PTP_TIME 0x1a
00542 /* enum: MUM fault */
00543 #define          MCDI_EVENT_CODE_MUM 0x1b
00544 /* enum: notify the designated PF of a new authorization request */
00545 #define          MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
00546 /* enum: notify a function that awaits an authorization that its request has
00547  * been processed and it may now resend the command
00548  */
00549 #define          MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
00550 /* enum: Artificial event generated by host and posted via MC for test
00551  * purposes.
00552  */
00553 #define          MCDI_EVENT_CODE_TESTGEN  0xfa
00554 #define       MCDI_EVENT_CMDDONE_DATA_OFST 0
00555 #define       MCDI_EVENT_CMDDONE_DATA_LBN 0
00556 #define       MCDI_EVENT_CMDDONE_DATA_WIDTH 32
00557 #define       MCDI_EVENT_LINKCHANGE_DATA_OFST 0
00558 #define       MCDI_EVENT_LINKCHANGE_DATA_LBN 0
00559 #define       MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
00560 #define       MCDI_EVENT_SENSOREVT_DATA_OFST 0
00561 #define       MCDI_EVENT_SENSOREVT_DATA_LBN 0
00562 #define       MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
00563 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
00564 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
00565 #define       MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
00566 #define       MCDI_EVENT_TX_ERR_DATA_OFST 0
00567 #define       MCDI_EVENT_TX_ERR_DATA_LBN 0
00568 #define       MCDI_EVENT_TX_ERR_DATA_WIDTH 32
00569 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
00570  * timestamp
00571  */
00572 #define       MCDI_EVENT_PTP_SECONDS_OFST 0
00573 #define       MCDI_EVENT_PTP_SECONDS_LBN 0
00574 #define       MCDI_EVENT_PTP_SECONDS_WIDTH 32
00575 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
00576  * timestamp
00577  */
00578 #define       MCDI_EVENT_PTP_MAJOR_OFST 0
00579 #define       MCDI_EVENT_PTP_MAJOR_LBN 0
00580 #define       MCDI_EVENT_PTP_MAJOR_WIDTH 32
00581 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
00582  * of timestamp
00583  */
00584 #define       MCDI_EVENT_PTP_NANOSECONDS_OFST 0
00585 #define       MCDI_EVENT_PTP_NANOSECONDS_LBN 0
00586 #define       MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
00587 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
00588  * timestamp
00589  */
00590 #define       MCDI_EVENT_PTP_MINOR_OFST 0
00591 #define       MCDI_EVENT_PTP_MINOR_LBN 0
00592 #define       MCDI_EVENT_PTP_MINOR_WIDTH 32
00593 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
00594  */
00595 #define       MCDI_EVENT_PTP_UUID_OFST 0
00596 #define       MCDI_EVENT_PTP_UUID_LBN 0
00597 #define       MCDI_EVENT_PTP_UUID_WIDTH 32
00598 #define       MCDI_EVENT_RX_ERR_DATA_OFST 0
00599 #define       MCDI_EVENT_RX_ERR_DATA_LBN 0
00600 #define       MCDI_EVENT_RX_ERR_DATA_WIDTH 32
00601 #define       MCDI_EVENT_PAR_ERR_DATA_OFST 0
00602 #define       MCDI_EVENT_PAR_ERR_DATA_LBN 0
00603 #define       MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
00604 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
00605 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
00606 #define       MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
00607 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
00608 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
00609 #define       MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
00610 /* For CODE_PTP_TIME events, the major value of the PTP clock */
00611 #define       MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
00612 #define       MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
00613 #define       MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
00614 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
00615 #define       MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
00616 #define       MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
00617 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
00618  * whether the NIC clock has ever been set
00619  */
00620 #define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
00621 #define       MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
00622 /* For CODE_PTP_TIME events where report sync status is enabled, indicates
00623  * whether the NIC and System clocks are in sync
00624  */
00625 #define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
00626 #define       MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
00627 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
00628  * the minor value of the PTP clock
00629  */
00630 #define       MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
00631 #define       MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
00632 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
00633 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
00634 #define       MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
00635 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
00636 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
00637 #define       MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
00638 /* Zero means that the request has been completed or authorized, and the driver
00639  * should resend it. A non-zero value means that the authorization has been
00640  * denied, and gives the reason. Typically it will be EPERM.
00641  */
00642 #define       MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
00643 #define       MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
00644 
00645 /* EVB_PORT_ID structuredef */
00646 #define    EVB_PORT_ID_LEN 4
00647 #define       EVB_PORT_ID_PORT_ID_OFST 0
00648 /* enum: An invalid port handle. */
00649 #define          EVB_PORT_ID_NULL  0x0
00650 /* enum: The port assigned to this function.. */
00651 #define          EVB_PORT_ID_ASSIGNED  0x1000000
00652 /* enum: External network port 0 */
00653 #define          EVB_PORT_ID_MAC0  0x2000000
00654 /* enum: External network port 1 */
00655 #define          EVB_PORT_ID_MAC1  0x2000001
00656 /* enum: External network port 2 */
00657 #define          EVB_PORT_ID_MAC2  0x2000002
00658 /* enum: External network port 3 */
00659 #define          EVB_PORT_ID_MAC3  0x2000003
00660 #define       EVB_PORT_ID_PORT_ID_LBN 0
00661 #define       EVB_PORT_ID_PORT_ID_WIDTH 32
00662 
00663 
00664 /***********************************/
00665 /* MC_CMD_DRV_ATTACH
00666  * Inform MCPU that this port is managed on the host (i.e. driver active). For
00667  * Huntington, also request the preferred datapath firmware to use if possible
00668  * (it may not be possible for this request to be fulfilled; the driver must
00669  * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
00670  * features are actually available). The FIRMWARE_ID field is ignored by older
00671  * platforms.
00672  */
00673 #define MC_CMD_DRV_ATTACH 0x1c
00674 #undef MC_CMD_0x1c_PRIVILEGE_CTG
00675 
00676 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
00677 
00678 /* MC_CMD_DRV_ATTACH_IN msgrequest */
00679 #define    MC_CMD_DRV_ATTACH_IN_LEN 12
00680 /* new state to set if UPDATE=1 */
00681 #define       MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
00682 #define        MC_CMD_DRV_ATTACH_LBN 0
00683 #define        MC_CMD_DRV_ATTACH_WIDTH 1
00684 #define        MC_CMD_DRV_PREBOOT_LBN 1
00685 #define        MC_CMD_DRV_PREBOOT_WIDTH 1
00686 /* 1 to set new state, or 0 to just report the existing state */
00687 #define       MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
00688 /* preferred datapath firmware (for Huntington; ignored for Siena) */
00689 #define       MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
00690 /* enum: Prefer to use full featured firmware */
00691 #define          MC_CMD_FW_FULL_FEATURED 0x0
00692 /* enum: Prefer to use firmware with fewer features but lower latency */
00693 #define          MC_CMD_FW_LOW_LATENCY 0x1
00694 /* enum: Prefer to use firmware for SolarCapture packed stream mode */
00695 #define          MC_CMD_FW_PACKED_STREAM 0x2
00696 /* enum: Prefer to use firmware with fewer features and simpler TX event
00697  * batching but higher TX packet rate
00698  */
00699 #define          MC_CMD_FW_HIGH_TX_RATE 0x3
00700 /* enum: Reserved value */
00701 #define          MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
00702 /* enum: Prefer to use firmware with additional "rules engine" filtering
00703  * support
00704  */
00705 #define          MC_CMD_FW_RULES_ENGINE 0x5
00706 /* enum: Only this option is allowed for non-admin functions */
00707 #define          MC_CMD_FW_DONT_CARE  0xffffffff
00708 
00709 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
00710 #define    MC_CMD_DRV_ATTACH_OUT_LEN 4
00711 /* previous or existing state, see the bitmask at NEW_STATE */
00712 #define       MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
00713 
00714 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
00715 #define    MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
00716 /* previous or existing state, see the bitmask at NEW_STATE */
00717 #define       MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
00718 /* Flags associated with this function */
00719 #define       MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
00720 /* enum: Labels the lowest-numbered function visible to the OS */
00721 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
00722 /* enum: The function can control the link state of the physical port it is
00723  * bound to.
00724  */
00725 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
00726 /* enum: The function can perform privileged operations */
00727 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
00728 /* enum: The function does not have an active port associated with it. The port
00729  * refers to the Sorrento external FPGA port.
00730  */
00731 #define          MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
00732 
00733 
00734 /***********************************/
00735 /* MC_CMD_ENTITY_RESET
00736  * Generic per-resource reset. There is no equivalent for per-board reset.
00737  * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
00738  * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
00739  */
00740 #define MC_CMD_ENTITY_RESET 0x20
00741 /*      MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
00742 
00743 /* MC_CMD_ENTITY_RESET_IN msgrequest */
00744 #define    MC_CMD_ENTITY_RESET_IN_LEN 4
00745 /* Optional flags field. Omitting this will perform a "legacy" reset action
00746  * (TBD).
00747  */
00748 #define       MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
00749 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
00750 #define        MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
00751 
00752 /* MC_CMD_ENTITY_RESET_OUT msgresponse */
00753 #define    MC_CMD_ENTITY_RESET_OUT_LEN 0
00754 
00755 
00756 /***********************************/
00757 /* MC_CMD_GET_PHY_CFG
00758  * Report PHY configuration. This guarantees to succeed even if the PHY is in a
00759  * 'zombie' state. Locks required: None
00760  */
00761 #define MC_CMD_GET_PHY_CFG 0x24
00762 #undef MC_CMD_0x24_PRIVILEGE_CTG
00763 
00764 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
00765 
00766 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
00767 #define    MC_CMD_GET_PHY_CFG_IN_LEN 0
00768 
00769 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
00770 #define    MC_CMD_GET_PHY_CFG_OUT_LEN 72
00771 /* flags */
00772 #define       MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
00773 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
00774 #define        MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
00775 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
00776 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
00777 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
00778 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
00779 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
00780 #define        MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
00781 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
00782 #define        MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
00783 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
00784 #define        MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
00785 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
00786 #define        MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
00787 /* ?? */
00788 #define       MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
00789 /* Bitmask of supported capabilities */
00790 #define       MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
00791 #define        MC_CMD_PHY_CAP_10HDX_LBN 1
00792 #define        MC_CMD_PHY_CAP_10HDX_WIDTH 1
00793 #define        MC_CMD_PHY_CAP_10FDX_LBN 2
00794 #define        MC_CMD_PHY_CAP_10FDX_WIDTH 1
00795 #define        MC_CMD_PHY_CAP_100HDX_LBN 3
00796 #define        MC_CMD_PHY_CAP_100HDX_WIDTH 1
00797 #define        MC_CMD_PHY_CAP_100FDX_LBN 4
00798 #define        MC_CMD_PHY_CAP_100FDX_WIDTH 1
00799 #define        MC_CMD_PHY_CAP_1000HDX_LBN 5
00800 #define        MC_CMD_PHY_CAP_1000HDX_WIDTH 1
00801 #define        MC_CMD_PHY_CAP_1000FDX_LBN 6
00802 #define        MC_CMD_PHY_CAP_1000FDX_WIDTH 1
00803 #define        MC_CMD_PHY_CAP_10000FDX_LBN 7
00804 #define        MC_CMD_PHY_CAP_10000FDX_WIDTH 1
00805 #define        MC_CMD_PHY_CAP_PAUSE_LBN 8
00806 #define        MC_CMD_PHY_CAP_PAUSE_WIDTH 1
00807 #define        MC_CMD_PHY_CAP_ASYM_LBN 9
00808 #define        MC_CMD_PHY_CAP_ASYM_WIDTH 1
00809 #define        MC_CMD_PHY_CAP_AN_LBN 10
00810 #define        MC_CMD_PHY_CAP_AN_WIDTH 1
00811 #define        MC_CMD_PHY_CAP_40000FDX_LBN 11
00812 #define        MC_CMD_PHY_CAP_40000FDX_WIDTH 1
00813 #define        MC_CMD_PHY_CAP_DDM_LBN 12
00814 #define        MC_CMD_PHY_CAP_DDM_WIDTH 1
00815 #define        MC_CMD_PHY_CAP_100000FDX_LBN 13
00816 #define        MC_CMD_PHY_CAP_100000FDX_WIDTH 1
00817 #define        MC_CMD_PHY_CAP_25000FDX_LBN 14
00818 #define        MC_CMD_PHY_CAP_25000FDX_WIDTH 1
00819 #define        MC_CMD_PHY_CAP_50000FDX_LBN 15
00820 #define        MC_CMD_PHY_CAP_50000FDX_WIDTH 1
00821 #define        MC_CMD_PHY_CAP_BASER_FEC_LBN 16
00822 #define        MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
00823 #define        MC_CMD_PHY_CAP_BASER_FEC_REQ_LBN 17
00824 #define        MC_CMD_PHY_CAP_BASER_FEC_REQ_WIDTH 1
00825 #define        MC_CMD_PHY_CAP_RS_FEC_LBN 17
00826 #define        MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
00827 #define        MC_CMD_PHY_CAP_RS_FEC_REQ_LBN 18
00828 #define        MC_CMD_PHY_CAP_RS_FEC_REQ_WIDTH 1
00829 /* ?? */
00830 #define       MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
00831 /* ?? */
00832 #define       MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
00833 /* ?? */
00834 #define       MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
00835 /* ?? */
00836 #define       MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
00837 #define       MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
00838 /* ?? */
00839 #define       MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
00840 /* enum: Xaui. */
00841 #define          MC_CMD_MEDIA_XAUI 0x1
00842 /* enum: CX4. */
00843 #define          MC_CMD_MEDIA_CX4 0x2
00844 /* enum: KX4. */
00845 #define          MC_CMD_MEDIA_KX4 0x3
00846 /* enum: XFP Far. */
00847 #define          MC_CMD_MEDIA_XFP 0x4
00848 /* enum: SFP+. */
00849 #define          MC_CMD_MEDIA_SFP_PLUS 0x5
00850 /* enum: 10GBaseT. */
00851 #define          MC_CMD_MEDIA_BASE_T 0x6
00852 /* enum: QSFP+. */
00853 #define          MC_CMD_MEDIA_QSFP_PLUS 0x7
00854 #define       MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
00855 /* enum: Native clause 22 */
00856 #define          MC_CMD_MMD_CLAUSE22 0x0
00857 #define          MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
00858 #define          MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
00859 #define          MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
00860 #define          MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
00861 #define          MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
00862 #define          MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
00863 #define          MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
00864 /* enum: Clause22 proxied over clause45 by PHY. */
00865 #define          MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
00866 #define          MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
00867 #define          MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
00868 #define       MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
00869 #define       MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
00870 
00871 
00872 /***********************************/
00873 /* MC_CMD_GET_LINK
00874  * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
00875  * ETIME.
00876  */
00877 #define MC_CMD_GET_LINK 0x29
00878 #undef MC_CMD_0x29_PRIVILEGE_CTG
00879 
00880 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
00881 
00882 /* MC_CMD_GET_LINK_IN msgrequest */
00883 #define    MC_CMD_GET_LINK_IN_LEN 0
00884 
00885 /* MC_CMD_GET_LINK_OUT msgresponse */
00886 #define    MC_CMD_GET_LINK_OUT_LEN 28
00887 /* near-side advertised capabilities */
00888 #define       MC_CMD_GET_LINK_OUT_CAP_OFST 0
00889 /* link-partner advertised capabilities */
00890 #define       MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
00891 /* Autonegotiated speed in mbit/s. The link may still be down even if this
00892  * reads non-zero.
00893  */
00894 #define       MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
00895 /* Current loopback setting. */
00896 #define       MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
00897 /*            Enum values, see field(s): */
00898 /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
00899 #define       MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
00900 #define        MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
00901 #define        MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
00902 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
00903 #define        MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
00904 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
00905 #define        MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
00906 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
00907 #define        MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
00908 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
00909 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
00910 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
00911 #define        MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
00912 /* This returns the negotiated flow control value. */
00913 #define       MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
00914 /*            Enum values, see field(s): */
00915 /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
00916 #define       MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
00917 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
00918 #define        MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
00919 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
00920 #define        MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
00921 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
00922 #define        MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
00923 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
00924 #define        MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
00925 
00926 
00927 /***********************************/
00928 /* MC_CMD_SET_MAC
00929  * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
00930  */
00931 #define MC_CMD_SET_MAC 0x2c
00932 #undef MC_CMD_0x2c_PRIVILEGE_CTG
00933 
00934 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
00935 
00936 /* MC_CMD_SET_MAC_IN msgrequest */
00937 #define    MC_CMD_SET_MAC_IN_LEN 28
00938 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
00939  * EtherII, VLAN, bug16011 padding).
00940  */
00941 #define       MC_CMD_SET_MAC_IN_MTU_OFST 0
00942 #define       MC_CMD_SET_MAC_IN_DRAIN_OFST 4
00943 #define       MC_CMD_SET_MAC_IN_ADDR_OFST 8
00944 #define       MC_CMD_SET_MAC_IN_ADDR_LEN 8
00945 #define       MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
00946 #define       MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
00947 #define       MC_CMD_SET_MAC_IN_REJECT_OFST 16
00948 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
00949 #define        MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
00950 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
00951 #define        MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
00952 #define       MC_CMD_SET_MAC_IN_FCNTL_OFST 20
00953 /* enum: Flow control is off. */
00954 #define          MC_CMD_FCNTL_OFF 0x0
00955 /* enum: Respond to flow control. */
00956 #define          MC_CMD_FCNTL_RESPOND 0x1
00957 /* enum: Respond to and Issue flow control. */
00958 #define          MC_CMD_FCNTL_BIDIR 0x2
00959 /* enum: Auto neg flow control. */
00960 #define          MC_CMD_FCNTL_AUTO 0x3
00961 /* enum: Priority flow control (eftest builds only). */
00962 #define          MC_CMD_FCNTL_QBB 0x4
00963 /* enum: Issue flow control. */
00964 #define          MC_CMD_FCNTL_GENERATE 0x5
00965 #define       MC_CMD_SET_MAC_IN_FLAGS_OFST 24
00966 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
00967 #define        MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
00968 
00969 /* MC_CMD_SET_MAC_EXT_IN msgrequest */
00970 #define    MC_CMD_SET_MAC_EXT_IN_LEN 32
00971 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
00972  * EtherII, VLAN, bug16011 padding).
00973  */
00974 #define       MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
00975 #define       MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
00976 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
00977 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
00978 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
00979 #define       MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
00980 #define       MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
00981 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
00982 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
00983 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
00984 #define        MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
00985 #define       MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
00986 /* enum: Flow control is off. */
00987 /*               MC_CMD_FCNTL_OFF 0x0 */
00988 /* enum: Respond to flow control. */
00989 /*               MC_CMD_FCNTL_RESPOND 0x1 */
00990 /* enum: Respond to and Issue flow control. */
00991 /*               MC_CMD_FCNTL_BIDIR 0x2 */
00992 /* enum: Auto neg flow control. */
00993 /*               MC_CMD_FCNTL_AUTO 0x3 */
00994 /* enum: Priority flow control (eftest builds only). */
00995 /*               MC_CMD_FCNTL_QBB 0x4 */
00996 /* enum: Issue flow control. */
00997 /*               MC_CMD_FCNTL_GENERATE 0x5 */
00998 #define       MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
00999 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
01000 #define        MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
01001 /* Select which parameters to configure. A parameter will only be modified if
01002  * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
01003  * capabilities then this field is ignored (and all flags are assumed to be
01004  * set).
01005  */
01006 #define       MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
01007 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
01008 #define        MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
01009 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
01010 #define        MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
01011 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
01012 #define        MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
01013 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
01014 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
01015 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
01016 #define        MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
01017 
01018 /* MC_CMD_SET_MAC_OUT msgresponse */
01019 #define    MC_CMD_SET_MAC_OUT_LEN 0
01020 
01021 /* MC_CMD_SET_MAC_V2_OUT msgresponse */
01022 #define    MC_CMD_SET_MAC_V2_OUT_LEN 4
01023 /* MTU as configured after processing the request. See comment at
01024  * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
01025  * to 0.
01026  */
01027 #define       MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
01028 
01029 
01030 /***********************************/
01031 /* MC_CMD_REBOOT
01032  * Reboot the MC.
01033  *
01034  * The AFTER_ASSERTION flag is intended to be used when the driver notices an
01035  * assertion failure (at which point it is expected to perform a complete tear
01036  * down and reinitialise), to allow both ports to reset the MC once in an
01037  * atomic fashion.
01038  *
01039  * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
01040  * which means that they will automatically reboot out of the assertion
01041  * handler, so this is in practise an optional operation. It is still
01042  * recommended that drivers execute this to support custom firmwares with
01043  * REBOOT_ON_ASSERT=0.
01044  *
01045  * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
01046  * DATALEN=0
01047  */
01048 #define MC_CMD_REBOOT 0x3d
01049 #undef MC_CMD_0x3d_PRIVILEGE_CTG
01050 
01051 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
01052 
01053 /* MC_CMD_REBOOT_IN msgrequest */
01054 #define    MC_CMD_REBOOT_IN_LEN 4
01055 #define       MC_CMD_REBOOT_IN_FLAGS_OFST 0
01056 #define          MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
01057 
01058 /* MC_CMD_REBOOT_OUT msgresponse */
01059 #define    MC_CMD_REBOOT_OUT_LEN 0
01060 
01061 
01062 /***********************************/
01063 /* MC_CMD_REBOOT_MODE
01064  * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
01065  * mode to the specified value. Returns the old mode.
01066  */
01067 #define MC_CMD_REBOOT_MODE 0x3f
01068 #undef MC_CMD_0x3f_PRIVILEGE_CTG
01069 
01070 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
01071 
01072 /* MC_CMD_REBOOT_MODE_IN msgrequest */
01073 #define    MC_CMD_REBOOT_MODE_IN_LEN 4
01074 #define       MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
01075 /* enum: Normal. */
01076 #define          MC_CMD_REBOOT_MODE_NORMAL 0x0
01077 /* enum: Power-on Reset. */
01078 #define          MC_CMD_REBOOT_MODE_POR 0x2
01079 /* enum: Snapper. */
01080 #define          MC_CMD_REBOOT_MODE_SNAPPER 0x3
01081 /* enum: snapper fake POR */
01082 #define          MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
01083 #define        MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
01084 #define        MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
01085 
01086 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
01087 #define    MC_CMD_REBOOT_MODE_OUT_LEN 4
01088 #define       MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
01089 
01090 
01091 /***********************************/
01092 /* MC_CMD_WORKAROUND
01093  * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
01094  * understand the given workaround number - which should not be treated as a
01095  * hard error by client code. This op does not imply any semantics about each
01096  * workaround, that's between the driver and the mcfw on a per-workaround
01097  * basis. Locks required: None. Returns: 0, EINVAL .
01098  */
01099 #define MC_CMD_WORKAROUND 0x4a
01100 #undef MC_CMD_0x4a_PRIVILEGE_CTG
01101 
01102 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
01103 
01104 /* MC_CMD_WORKAROUND_IN msgrequest */
01105 #define    MC_CMD_WORKAROUND_IN_LEN 8
01106 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
01107 #define       MC_CMD_WORKAROUND_IN_TYPE_OFST 0
01108 /* enum: Bug 17230 work around. */
01109 #define          MC_CMD_WORKAROUND_BUG17230 0x1
01110 /* enum: Bug 35388 work around (unsafe EVQ writes). */
01111 #define          MC_CMD_WORKAROUND_BUG35388 0x2
01112 /* enum: Bug35017 workaround (A64 tables must be identity map) */
01113 #define          MC_CMD_WORKAROUND_BUG35017 0x3
01114 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
01115 #define          MC_CMD_WORKAROUND_BUG41750 0x4
01116 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
01117  * - before adding code that queries this workaround, remember that there's
01118  * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
01119  * and will hence (incorrectly) report that the bug doesn't exist.
01120  */
01121 #define          MC_CMD_WORKAROUND_BUG42008 0x5
01122 /* enum: Bug 26807 features present in firmware (multicast filter chaining)
01123  * This feature cannot be turned on/off while there are any filters already
01124  * present. The behaviour in such case depends on the acting client's privilege
01125  * level. If the client has the admin privilege, then all functions that have
01126  * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
01127  * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
01128  */
01129 #define          MC_CMD_WORKAROUND_BUG26807 0x6
01130 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
01131 #define          MC_CMD_WORKAROUND_BUG61265 0x7
01132 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
01133  * the workaround
01134  */
01135 #define       MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
01136 
01137 /* MC_CMD_WORKAROUND_OUT msgresponse */
01138 #define    MC_CMD_WORKAROUND_OUT_LEN 0
01139 
01140 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
01141  * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
01142  */
01143 #define    MC_CMD_WORKAROUND_EXT_OUT_LEN 4
01144 #define       MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
01145 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
01146 #define        MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
01147 
01148 
01149 /***********************************/
01150 /* MC_CMD_GET_MAC_ADDRESSES
01151  * Returns the base MAC, count and stride for the requesting function
01152  */
01153 #define MC_CMD_GET_MAC_ADDRESSES 0x55
01154 #undef MC_CMD_0x55_PRIVILEGE_CTG
01155 
01156 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01157 
01158 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
01159 #define    MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
01160 
01161 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
01162 #define    MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
01163 /* Base MAC address */
01164 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
01165 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
01166 /* Padding */
01167 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
01168 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
01169 /* Number of allocated MAC addresses */
01170 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
01171 /* Spacing of allocated MAC addresses */
01172 #define       MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
01173 
01174 
01175 /***********************************/
01176 /* MC_CMD_GET_WORKAROUNDS
01177  * Read the list of all implemented and all currently enabled workarounds. The
01178  * enums here must correspond with those in MC_CMD_WORKAROUND.
01179  */
01180 #define MC_CMD_GET_WORKAROUNDS 0x59
01181 #undef MC_CMD_0x59_PRIVILEGE_CTG
01182 
01183 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01184 
01185 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
01186 #define    MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
01187 /* Each workaround is represented by a single bit according to the enums below.
01188  */
01189 #define       MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
01190 #define       MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
01191 /* enum: Bug 17230 work around. */
01192 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
01193 /* enum: Bug 35388 work around (unsafe EVQ writes). */
01194 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
01195 /* enum: Bug35017 workaround (A64 tables must be identity map) */
01196 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
01197 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
01198 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
01199 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
01200  * - before adding code that queries this workaround, remember that there's
01201  * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
01202  * and will hence (incorrectly) report that the bug doesn't exist.
01203  */
01204 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
01205 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */
01206 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
01207 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
01208 #define          MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
01209 
01210 
01211 /***********************************/
01212 /* MC_CMD_V2_EXTN
01213  * Encapsulation for a v2 extended command
01214  */
01215 #define MC_CMD_V2_EXTN 0x7f
01216 
01217 /* MC_CMD_V2_EXTN_IN msgrequest */
01218 #define    MC_CMD_V2_EXTN_IN_LEN 4
01219 /* the extended command number */
01220 #define       MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
01221 #define       MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
01222 #define       MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
01223 #define       MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
01224 /* the actual length of the encapsulated command (which is not in the v1
01225  * header)
01226  */
01227 #define       MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
01228 #define       MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
01229 #define       MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
01230 #define       MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
01231 /* Type of command/response */
01232 #define       MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
01233 #define       MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
01234 /* enum: MCDI command directed to or response originating from the MC. */
01235 #define          MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC  0x0
01236 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type
01237  * are not defined.
01238  */
01239 #define          MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA  0x1
01240 
01241 
01242 /***********************************/
01243 /* MC_CMD_INIT_EVQ
01244  * Set up an event queue according to the supplied parameters. The IN arguments
01245  * end with an address for each 4k of host memory required to back the EVQ.
01246  */
01247 #define MC_CMD_INIT_EVQ 0x80
01248 #undef MC_CMD_0x80_PRIVILEGE_CTG
01249 
01250 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01251 
01252 /* MC_CMD_INIT_EVQ_IN msgrequest */
01253 #define    MC_CMD_INIT_EVQ_IN_LENMIN 44
01254 #define    MC_CMD_INIT_EVQ_IN_LENMAX 548
01255 #define    MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
01256 /* Size, in entries */
01257 #define       MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
01258 /* Desired instance. Must be set to a specific instance, which is a function
01259  * local queue index.
01260  */
01261 #define       MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
01262 /* The initial timer value. The load value is ignored if the timer mode is DIS.
01263  */
01264 #define       MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
01265 /* The reload value is ignored in one-shot modes */
01266 #define       MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
01267 /* tbd */
01268 #define       MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
01269 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
01270 #define        MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
01271 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
01272 #define        MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
01273 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
01274 #define        MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
01275 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
01276 #define        MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
01277 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
01278 #define        MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
01279 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
01280 #define        MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
01281 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
01282 #define        MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
01283 #define       MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
01284 /* enum: Disabled */
01285 #define          MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
01286 /* enum: Immediate */
01287 #define          MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
01288 /* enum: Triggered */
01289 #define          MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
01290 /* enum: Hold-off */
01291 #define          MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
01292 /* Target EVQ for wakeups if in wakeup mode. */
01293 #define       MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
01294 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
01295  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
01296  * purposes.
01297  */
01298 #define       MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
01299 /* Event Counter Mode. */
01300 #define       MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
01301 /* enum: Disabled */
01302 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
01303 /* enum: Disabled */
01304 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
01305 /* enum: Disabled */
01306 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
01307 /* enum: Disabled */
01308 #define          MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
01309 /* Event queue packet count threshold. */
01310 #define       MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
01311 /* 64-bit address of 4k of 4k-aligned host memory buffer */
01312 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
01313 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
01314 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
01315 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
01316 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
01317 #define       MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
01318 
01319 /* MC_CMD_INIT_EVQ_OUT msgresponse */
01320 #define    MC_CMD_INIT_EVQ_OUT_LEN 4
01321 /* Only valid if INTRFLAG was true */
01322 #define       MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
01323 
01324 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */
01325 #define    MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
01326 #define    MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
01327 #define    MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
01328 /* Size, in entries */
01329 #define       MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
01330 /* Desired instance. Must be set to a specific instance, which is a function
01331  * local queue index.
01332  */
01333 #define       MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
01334 /* The initial timer value. The load value is ignored if the timer mode is DIS.
01335  */
01336 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
01337 /* The reload value is ignored in one-shot modes */
01338 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
01339 /* tbd */
01340 #define       MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
01341 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
01342 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
01343 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
01344 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
01345 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
01346 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
01347 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
01348 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
01349 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
01350 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
01351 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
01352 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
01353 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
01354 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
01355 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
01356 #define        MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
01357 /* enum: All initialisation flags specified by host. */
01358 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
01359 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
01360  * over-ridden by firmware based on licenses and firmware variant in order to
01361  * provide the lowest latency achievable. See
01362  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
01363  */
01364 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
01365 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
01366  * over-ridden by firmware based on licenses and firmware variant in order to
01367  * provide the best throughput achievable. See
01368  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
01369  */
01370 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
01371 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
01372  * firmware based on licenses and firmware variant. See
01373  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
01374  */
01375 #define          MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
01376 #define       MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
01377 /* enum: Disabled */
01378 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
01379 /* enum: Immediate */
01380 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
01381 /* enum: Triggered */
01382 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
01383 /* enum: Hold-off */
01384 #define          MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
01385 /* Target EVQ for wakeups if in wakeup mode. */
01386 #define       MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
01387 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
01388  * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
01389  * purposes.
01390  */
01391 #define       MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
01392 /* Event Counter Mode. */
01393 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
01394 /* enum: Disabled */
01395 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
01396 /* enum: Disabled */
01397 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
01398 /* enum: Disabled */
01399 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
01400 /* enum: Disabled */
01401 #define          MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
01402 /* Event queue packet count threshold. */
01403 #define       MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
01404 /* 64-bit address of 4k of 4k-aligned host memory buffer */
01405 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
01406 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
01407 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
01408 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
01409 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
01410 #define       MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
01411 
01412 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
01413 #define    MC_CMD_INIT_EVQ_V2_OUT_LEN 8
01414 /* Only valid if INTRFLAG was true */
01415 #define       MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
01416 /* Actual configuration applied on the card */
01417 #define       MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
01418 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
01419 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
01420 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
01421 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
01422 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
01423 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
01424 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
01425 #define        MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
01426 
01427 /* QUEUE_CRC_MODE structuredef */
01428 #define    QUEUE_CRC_MODE_LEN 1
01429 #define       QUEUE_CRC_MODE_MODE_LBN 0
01430 #define       QUEUE_CRC_MODE_MODE_WIDTH 4
01431 /* enum: No CRC. */
01432 #define          QUEUE_CRC_MODE_NONE  0x0
01433 /* enum: CRC Fiber channel over ethernet. */
01434 #define          QUEUE_CRC_MODE_FCOE  0x1
01435 /* enum: CRC (digest) iSCSI header only. */
01436 #define          QUEUE_CRC_MODE_ISCSI_HDR  0x2
01437 /* enum: CRC (digest) iSCSI header and payload. */
01438 #define          QUEUE_CRC_MODE_ISCSI  0x3
01439 /* enum: CRC Fiber channel over IP over ethernet. */
01440 #define          QUEUE_CRC_MODE_FCOIPOE  0x4
01441 /* enum: CRC MPA. */
01442 #define          QUEUE_CRC_MODE_MPA  0x5
01443 #define       QUEUE_CRC_MODE_SPARE_LBN 4
01444 #define       QUEUE_CRC_MODE_SPARE_WIDTH 4
01445 
01446 
01447 /***********************************/
01448 /* MC_CMD_INIT_RXQ
01449  * set up a receive queue according to the supplied parameters. The IN
01450  * arguments end with an address for each 4k of host memory required to back
01451  * the RXQ.
01452  */
01453 #define MC_CMD_INIT_RXQ 0x81
01454 #undef MC_CMD_0x81_PRIVILEGE_CTG
01455 
01456 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01457 
01458 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
01459  * in new code.
01460  */
01461 #define    MC_CMD_INIT_RXQ_IN_LENMIN 36
01462 #define    MC_CMD_INIT_RXQ_IN_LENMAX 252
01463 #define    MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
01464 /* Size, in entries */
01465 #define       MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
01466 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
01467  */
01468 #define       MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
01469 /* The value to put in the event data. Check hardware spec. for valid range. */
01470 #define       MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
01471 /* Desired instance. Must be set to a specific instance, which is a function
01472  * local queue index.
01473  */
01474 #define       MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
01475 /* There will be more flags here. */
01476 #define       MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
01477 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
01478 #define        MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
01479 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
01480 #define        MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
01481 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
01482 #define        MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
01483 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
01484 #define        MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
01485 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
01486 #define        MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
01487 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
01488 #define        MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
01489 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
01490 #define        MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
01491 #define        MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
01492 #define        MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
01493 /* Owner ID to use if in buffer mode (zero if physical) */
01494 #define       MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
01495 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
01496 #define       MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
01497 /* 64-bit address of 4k of 4k-aligned host memory buffer */
01498 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
01499 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
01500 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
01501 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
01502 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
01503 #define       MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
01504 
01505 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
01506  * flags
01507  */
01508 #define    MC_CMD_INIT_RXQ_EXT_IN_LEN 544
01509 /* Size, in entries */
01510 #define       MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
01511 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
01512  */
01513 #define       MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
01514 /* The value to put in the event data. Check hardware spec. for valid range. */
01515 #define       MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
01516 /* Desired instance. Must be set to a specific instance, which is a function
01517  * local queue index.
01518  */
01519 #define       MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
01520 /* There will be more flags here. */
01521 #define       MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
01522 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
01523 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
01524 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
01525 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
01526 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
01527 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
01528 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
01529 #define        MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
01530 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
01531 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
01532 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
01533 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
01534 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
01535 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
01536 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
01537 #define        MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
01538 /* enum: One packet per descriptor (for normal networking) */
01539 #define          MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET  0x0
01540 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
01541 #define          MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM  0x1
01542 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
01543 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
01544 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
01545 #define        MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
01546 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M  0x0 /* enum */
01547 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K  0x1 /* enum */
01548 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K  0x2 /* enum */
01549 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K  0x3 /* enum */
01550 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K  0x4 /* enum */
01551 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
01552 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
01553 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
01554 #define        MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
01555 /* Owner ID to use if in buffer mode (zero if physical) */
01556 #define       MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
01557 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
01558 #define       MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
01559 /* 64-bit address of 4k of 4k-aligned host memory buffer */
01560 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
01561 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
01562 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
01563 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
01564 #define       MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
01565 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
01566 #define       MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
01567 
01568 /* MC_CMD_INIT_RXQ_OUT msgresponse */
01569 #define    MC_CMD_INIT_RXQ_OUT_LEN 0
01570 
01571 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
01572 #define    MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
01573 
01574 
01575 /***********************************/
01576 /* MC_CMD_INIT_TXQ
01577  */
01578 #define MC_CMD_INIT_TXQ 0x82
01579 #undef MC_CMD_0x82_PRIVILEGE_CTG
01580 
01581 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01582 
01583 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
01584  * in new code.
01585  */
01586 #define    MC_CMD_INIT_TXQ_IN_LENMIN 36
01587 #define    MC_CMD_INIT_TXQ_IN_LENMAX 252
01588 #define    MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
01589 /* Size, in entries */
01590 #define       MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
01591 /* The EVQ to send events to. This is an index originally specified to
01592  * INIT_EVQ.
01593  */
01594 #define       MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
01595 /* The value to put in the event data. Check hardware spec. for valid range. */
01596 #define       MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
01597 /* Desired instance. Must be set to a specific instance, which is a function
01598  * local queue index.
01599  */
01600 #define       MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
01601 /* There will be more flags here. */
01602 #define       MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
01603 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
01604 #define        MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
01605 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
01606 #define        MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
01607 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
01608 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
01609 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
01610 #define        MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
01611 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
01612 #define        MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
01613 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
01614 #define        MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
01615 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
01616 #define        MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
01617 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
01618 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
01619 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
01620 #define        MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
01621 /* Owner ID to use if in buffer mode (zero if physical) */
01622 #define       MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
01623 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
01624 #define       MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
01625 /* 64-bit address of 4k of 4k-aligned host memory buffer */
01626 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
01627 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
01628 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
01629 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
01630 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
01631 #define       MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
01632 
01633 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
01634  * flags
01635  */
01636 #define    MC_CMD_INIT_TXQ_EXT_IN_LEN 544
01637 /* Size, in entries */
01638 #define       MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
01639 /* The EVQ to send events to. This is an index originally specified to
01640  * INIT_EVQ.
01641  */
01642 #define       MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
01643 /* The value to put in the event data. Check hardware spec. for valid range. */
01644 #define       MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
01645 /* Desired instance. Must be set to a specific instance, which is a function
01646  * local queue index.
01647  */
01648 #define       MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
01649 /* There will be more flags here. */
01650 #define       MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
01651 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
01652 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
01653 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
01654 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
01655 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
01656 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
01657 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
01658 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
01659 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
01660 #define        MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
01661 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
01662 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
01663 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
01664 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
01665 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
01666 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
01667 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
01668 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
01669 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
01670 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
01671 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
01672 #define        MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
01673 /* Owner ID to use if in buffer mode (zero if physical) */
01674 #define       MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
01675 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
01676 #define       MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
01677 /* 64-bit address of 4k of 4k-aligned host memory buffer */
01678 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
01679 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
01680 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
01681 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
01682 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
01683 #define       MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
01684 /* Flags related to Qbb flow control mode. */
01685 #define       MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
01686 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
01687 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
01688 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
01689 #define        MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
01690 
01691 /* MC_CMD_INIT_TXQ_OUT msgresponse */
01692 #define    MC_CMD_INIT_TXQ_OUT_LEN 0
01693 
01694 
01695 /***********************************/
01696 /* MC_CMD_FINI_EVQ
01697  * Teardown an EVQ.
01698  *
01699  * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
01700  * or the operation will fail with EBUSY
01701  */
01702 #define MC_CMD_FINI_EVQ 0x83
01703 #undef MC_CMD_0x83_PRIVILEGE_CTG
01704 
01705 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01706 
01707 /* MC_CMD_FINI_EVQ_IN msgrequest */
01708 #define    MC_CMD_FINI_EVQ_IN_LEN 4
01709 /* Instance of EVQ to destroy. Should be the same instance as that previously
01710  * passed to INIT_EVQ
01711  */
01712 #define       MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
01713 
01714 /* MC_CMD_FINI_EVQ_OUT msgresponse */
01715 #define    MC_CMD_FINI_EVQ_OUT_LEN 0
01716 
01717 
01718 /***********************************/
01719 /* MC_CMD_FINI_RXQ
01720  * Teardown a RXQ.
01721  */
01722 #define MC_CMD_FINI_RXQ 0x84
01723 #undef MC_CMD_0x84_PRIVILEGE_CTG
01724 
01725 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01726 
01727 /* MC_CMD_FINI_RXQ_IN msgrequest */
01728 #define    MC_CMD_FINI_RXQ_IN_LEN 4
01729 /* Instance of RXQ to destroy */
01730 #define       MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
01731 
01732 /* MC_CMD_FINI_RXQ_OUT msgresponse */
01733 #define    MC_CMD_FINI_RXQ_OUT_LEN 0
01734 
01735 
01736 /***********************************/
01737 /* MC_CMD_FINI_TXQ
01738  * Teardown a TXQ.
01739  */
01740 #define MC_CMD_FINI_TXQ 0x85
01741 #undef MC_CMD_0x85_PRIVILEGE_CTG
01742 
01743 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01744 
01745 /* MC_CMD_FINI_TXQ_IN msgrequest */
01746 #define    MC_CMD_FINI_TXQ_IN_LEN 4
01747 /* Instance of TXQ to destroy */
01748 #define       MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
01749 
01750 /* MC_CMD_FINI_TXQ_OUT msgresponse */
01751 #define    MC_CMD_FINI_TXQ_OUT_LEN 0
01752 
01753 
01754 /***********************************/
01755 /* MC_CMD_FILTER_OP
01756  * Multiplexed MCDI call for filter operations
01757  */
01758 #define MC_CMD_FILTER_OP 0x8a
01759 #undef MC_CMD_0x8a_PRIVILEGE_CTG
01760 
01761 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
01762 
01763 /* MC_CMD_FILTER_OP_IN msgrequest */
01764 #define    MC_CMD_FILTER_OP_IN_LEN 108
01765 /* identifies the type of operation requested */
01766 #define       MC_CMD_FILTER_OP_IN_OP_OFST 0
01767 /* enum: single-recipient filter insert */
01768 #define          MC_CMD_FILTER_OP_IN_OP_INSERT  0x0
01769 /* enum: single-recipient filter remove */
01770 #define          MC_CMD_FILTER_OP_IN_OP_REMOVE  0x1
01771 /* enum: multi-recipient filter subscribe */
01772 #define          MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE  0x2
01773 /* enum: multi-recipient filter unsubscribe */
01774 #define          MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE  0x3
01775 /* enum: replace one recipient with another (warning - the filter handle may
01776  * change)
01777  */
01778 #define          MC_CMD_FILTER_OP_IN_OP_REPLACE  0x4
01779 /* filter handle (for remove / unsubscribe operations) */
01780 #define       MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
01781 #define       MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
01782 #define       MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
01783 #define       MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
01784 /* The port ID associated with the v-adaptor which should contain this filter.
01785  */
01786 #define       MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
01787 /* fields to include in match criteria */
01788 #define       MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
01789 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
01790 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
01791 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
01792 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
01793 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
01794 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
01795 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
01796 #define        MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
01797 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
01798 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
01799 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
01800 #define        MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
01801 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
01802 #define        MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
01803 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
01804 #define        MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
01805 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
01806 #define        MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
01807 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
01808 #define        MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
01809 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
01810 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
01811 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
01812 #define        MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
01813 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
01814 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
01815 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
01816 #define        MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
01817 /* receive destination */
01818 #define       MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
01819 /* enum: drop packets */
01820 #define          MC_CMD_FILTER_OP_IN_RX_DEST_DROP  0x0
01821 /* enum: receive to host */
01822 #define          MC_CMD_FILTER_OP_IN_RX_DEST_HOST  0x1
01823 /* enum: receive to MC */
01824 #define          MC_CMD_FILTER_OP_IN_RX_DEST_MC  0x2
01825 /* enum: loop back to TXDP 0 */
01826 #define          MC_CMD_FILTER_OP_IN_RX_DEST_TX0  0x3
01827 /* enum: loop back to TXDP 1 */
01828 #define          MC_CMD_FILTER_OP_IN_RX_DEST_TX1  0x4
01829 /* receive queue handle (for multiple queue modes, this is the base queue) */
01830 #define       MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
01831 /* receive mode */
01832 #define       MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
01833 /* enum: receive to just the specified queue */
01834 #define          MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE  0x0
01835 /* enum: receive to multiple queues using RSS context */
01836 #define          MC_CMD_FILTER_OP_IN_RX_MODE_RSS  0x1
01837 /* enum: receive to multiple queues using .1p mapping */
01838 #define          MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING  0x2
01839 /* enum: install a filter entry that will never match; for test purposes only
01840  */
01841 #define          MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH  0x80000000
01842 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
01843  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
01844  * MC_CMD_DOT1P_MAPPING_ALLOC.
01845  */
01846 #define       MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
01847 /* transmit domain (reserved; set to 0) */
01848 #define       MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
01849 /* transmit destination (either set the MAC and/or PM bits for explicit
01850  * control, or set this field to TX_DEST_DEFAULT for sensible default
01851  * behaviour)
01852  */
01853 #define       MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
01854 /* enum: request default behaviour (based on filter type) */
01855 #define          MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT  0xffffffff
01856 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
01857 #define        MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
01858 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
01859 #define        MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
01860 /* source MAC address to match (as bytes in network order) */
01861 #define       MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
01862 #define       MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
01863 /* source port to match (as bytes in network order) */
01864 #define       MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
01865 #define       MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
01866 /* destination MAC address to match (as bytes in network order) */
01867 #define       MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
01868 #define       MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
01869 /* destination port to match (as bytes in network order) */
01870 #define       MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
01871 #define       MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
01872 /* Ethernet type to match (as bytes in network order) */
01873 #define       MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
01874 #define       MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
01875 /* Inner VLAN tag to match (as bytes in network order) */
01876 #define       MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
01877 #define       MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
01878 /* Outer VLAN tag to match (as bytes in network order) */
01879 #define       MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
01880 #define       MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
01881 /* IP protocol to match (in low byte; set high byte to 0) */
01882 #define       MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
01883 #define       MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
01884 /* Firmware defined register 0 to match (reserved; set to 0) */
01885 #define       MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
01886 /* Firmware defined register 1 to match (reserved; set to 0) */
01887 #define       MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
01888 /* source IP address to match (as bytes in network order; set last 12 bytes to
01889  * 0 for IPv4 address)
01890  */
01891 #define       MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
01892 #define       MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
01893 /* destination IP address to match (as bytes in network order; set last 12
01894  * bytes to 0 for IPv4 address)
01895  */
01896 #define       MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
01897 #define       MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
01898 
01899 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
01900  * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
01901  * supported on Medford only).
01902  */
01903 #define    MC_CMD_FILTER_OP_EXT_IN_LEN 172
01904 /* identifies the type of operation requested */
01905 #define       MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
01906 /*            Enum values, see field(s): */
01907 /*               MC_CMD_FILTER_OP_IN/OP */
01908 /* filter handle (for remove / unsubscribe operations) */
01909 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
01910 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
01911 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
01912 #define       MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
01913 /* The port ID associated with the v-adaptor which should contain this filter.
01914  */
01915 #define       MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
01916 /* fields to include in match criteria */
01917 #define       MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
01918 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
01919 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
01920 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
01921 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
01922 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
01923 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
01924 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
01925 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
01926 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
01927 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
01928 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
01929 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
01930 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
01931 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
01932 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
01933 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
01934 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
01935 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
01936 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
01937 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
01938 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
01939 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
01940 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
01941 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
01942 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
01943 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
01944 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
01945 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
01946 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
01947 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
01948 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
01949 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
01950 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
01951 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
01952 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
01953 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
01954 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
01955 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
01956 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
01957 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
01958 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
01959 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
01960 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
01961 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
01962 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
01963 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
01964 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
01965 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
01966 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
01967 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
01968 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
01969 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
01970 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
01971 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
01972 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
01973 #define        MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
01974 /* receive destination */
01975 #define       MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
01976 /* enum: drop packets */
01977 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP  0x0
01978 /* enum: receive to host */
01979 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST  0x1
01980 /* enum: receive to MC */
01981 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC  0x2
01982 /* enum: loop back to TXDP 0 */
01983 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0  0x3
01984 /* enum: loop back to TXDP 1 */
01985 #define          MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1  0x4
01986 /* receive queue handle (for multiple queue modes, this is the base queue) */
01987 #define       MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
01988 /* receive mode */
01989 #define       MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
01990 /* enum: receive to just the specified queue */
01991 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE  0x0
01992 /* enum: receive to multiple queues using RSS context */
01993 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS  0x1
01994 /* enum: receive to multiple queues using .1p mapping */
01995 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING  0x2
01996 /* enum: install a filter entry that will never match; for test purposes only
01997  */
01998 #define          MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH  0x80000000
01999 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
02000  * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
02001  * MC_CMD_DOT1P_MAPPING_ALLOC.
02002  */
02003 #define       MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
02004 /* transmit domain (reserved; set to 0) */
02005 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
02006 /* transmit destination (either set the MAC and/or PM bits for explicit
02007  * control, or set this field to TX_DEST_DEFAULT for sensible default
02008  * behaviour)
02009  */
02010 #define       MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
02011 /* enum: request default behaviour (based on filter type) */
02012 #define          MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT  0xffffffff
02013 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
02014 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
02015 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
02016 #define        MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
02017 /* source MAC address to match (as bytes in network order) */
02018 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
02019 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
02020 /* source port to match (as bytes in network order) */
02021 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
02022 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
02023 /* destination MAC address to match (as bytes in network order) */
02024 #define       MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
02025 #define       MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
02026 /* destination port to match (as bytes in network order) */
02027 #define       MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
02028 #define       MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
02029 /* Ethernet type to match (as bytes in network order) */
02030 #define       MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
02031 #define       MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
02032 /* Inner VLAN tag to match (as bytes in network order) */
02033 #define       MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
02034 #define       MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
02035 /* Outer VLAN tag to match (as bytes in network order) */
02036 #define       MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
02037 #define       MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
02038 /* IP protocol to match (in low byte; set high byte to 0) */
02039 #define       MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
02040 #define       MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
02041 /* Firmware defined register 0 to match (reserved; set to 0) */
02042 #define       MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
02043 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
02044  * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
02045  * VXLAN/NVGRE, or 1 for Geneve)
02046  */
02047 #define       MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
02048 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
02049 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
02050 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
02051 #define        MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
02052 /* enum: Match VXLAN traffic with this VNI */
02053 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN  0x0
02054 /* enum: Match Geneve traffic with this VNI */
02055 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE  0x1
02056 /* enum: Reserved for experimental development use */
02057 #define          MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL  0xfe
02058 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
02059 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
02060 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
02061 #define        MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
02062 /* enum: Match NVGRE traffic with this VSID */
02063 #define          MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE  0x0
02064 /* source IP address to match (as bytes in network order; set last 12 bytes to
02065  * 0 for IPv4 address)
02066  */
02067 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
02068 #define       MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
02069 /* destination IP address to match (as bytes in network order; set last 12
02070  * bytes to 0 for IPv4 address)
02071  */
02072 #define       MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
02073 #define       MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
02074 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
02075  * order)
02076  */
02077 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
02078 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
02079 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
02080 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
02081 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
02082 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
02083  * network order)
02084  */
02085 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
02086 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
02087 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network
02088  * order)
02089  */
02090 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
02091 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
02092 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
02093  */
02094 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
02095 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
02096 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
02097  */
02098 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
02099 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
02100 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
02101  */
02102 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
02103 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
02104 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
02105  * 0)
02106  */
02107 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
02108 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
02109 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
02110  * to 0)
02111  */
02112 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
02113 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
02114  * to 0)
02115  */
02116 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
02117 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
02118  * order; set last 12 bytes to 0 for IPv4 address)
02119  */
02120 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
02121 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
02122 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
02123  * order; set last 12 bytes to 0 for IPv4 address)
02124  */
02125 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
02126 #define       MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
02127 
02128 /* MC_CMD_FILTER_OP_OUT msgresponse */
02129 #define    MC_CMD_FILTER_OP_OUT_LEN 12
02130 /* identifies the type of operation requested */
02131 #define       MC_CMD_FILTER_OP_OUT_OP_OFST 0
02132 /*            Enum values, see field(s): */
02133 /*               MC_CMD_FILTER_OP_IN/OP */
02134 /* Returned filter handle (for insert / subscribe operations). Note that these
02135  * handles should be considered opaque to the host, although a value of
02136  * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
02137  */
02138 #define       MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
02139 #define       MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
02140 #define       MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
02141 #define       MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
02142 /* enum: guaranteed invalid filter handle (low 32 bits) */
02143 #define          MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID  0xffffffff
02144 /* enum: guaranteed invalid filter handle (high 32 bits) */
02145 #define          MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID  0xffffffff
02146 
02147 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
02148 #define    MC_CMD_FILTER_OP_EXT_OUT_LEN 12
02149 /* identifies the type of operation requested */
02150 #define       MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
02151 /*            Enum values, see field(s): */
02152 /*               MC_CMD_FILTER_OP_EXT_IN/OP */
02153 /* Returned filter handle (for insert / subscribe operations). Note that these
02154  * handles should be considered opaque to the host, although a value of
02155  * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
02156  */
02157 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
02158 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
02159 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
02160 #define       MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
02161 /*            Enum values, see field(s): */
02162 /*               MC_CMD_FILTER_OP_OUT/HANDLE */
02163 
02164 
02165 /***********************************/
02166 /* MC_CMD_ALLOC_VIS
02167  * Allocate VIs for current PCI function.
02168  */
02169 #define MC_CMD_ALLOC_VIS 0x8b
02170 #undef MC_CMD_0x8b_PRIVILEGE_CTG
02171 
02172 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
02173 
02174 /* MC_CMD_ALLOC_VIS_IN msgrequest */
02175 #define    MC_CMD_ALLOC_VIS_IN_LEN 8
02176 /* The minimum number of VIs that is acceptable */
02177 #define       MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
02178 /* The maximum number of VIs that would be useful */
02179 #define       MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
02180 
02181 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
02182  * Use extended version in new code.
02183  */
02184 #define    MC_CMD_ALLOC_VIS_OUT_LEN 8
02185 /* The number of VIs allocated on this function */
02186 #define       MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
02187 /* The base absolute VI number allocated to this function. Required to
02188  * correctly interpret wakeup events.
02189  */
02190 #define       MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
02191 
02192 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
02193 #define    MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
02194 /* The number of VIs allocated on this function */
02195 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
02196 /* The base absolute VI number allocated to this function. Required to
02197  * correctly interpret wakeup events.
02198  */
02199 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
02200 /* Function's port vi_shift value (always 0 on Huntington) */
02201 #define       MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
02202 
02203 
02204 /***********************************/
02205 /* MC_CMD_FREE_VIS
02206  * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
02207  * but not freed.
02208  */
02209 #define MC_CMD_FREE_VIS 0x8c
02210 #undef MC_CMD_0x8c_PRIVILEGE_CTG
02211 
02212 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
02213 
02214 /* MC_CMD_FREE_VIS_IN msgrequest */
02215 #define    MC_CMD_FREE_VIS_IN_LEN 0
02216 
02217 /* MC_CMD_FREE_VIS_OUT msgresponse */
02218 #define    MC_CMD_FREE_VIS_OUT_LEN 0
02219 
02220 
02221 /***********************************/
02222 /* MC_CMD_GET_PORT_ASSIGNMENT
02223  * Get port assignment for current PCI function.
02224  */
02225 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
02226 #undef MC_CMD_0xb8_PRIVILEGE_CTG
02227 
02228 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
02229 
02230 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
02231 #define    MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
02232 
02233 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
02234 #define    MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
02235 /* Identifies the port assignment for this function. */
02236 #define       MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
02237 
02238 
02239 /***********************************/
02240 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
02241  * Configure UDP ports for tunnel encapsulation hardware acceleration. The
02242  * parser-dispatcher will attempt to parse traffic on these ports as tunnel
02243  * encapsulation PDUs and filter them using the tunnel encapsulation filter
02244  * chain rather than the standard filter chain. Note that this command can
02245  * cause all functions to see a reset. (Available on Medford only.)
02246  */
02247 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
02248 #undef MC_CMD_0x117_PRIVILEGE_CTG
02249 
02250 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
02251 
02252 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
02253 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
02254 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
02255 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
02256 /* Flags */
02257 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
02258 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
02259 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
02260 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
02261 /* The number of entries in the ENTRIES array */
02262 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
02263 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
02264 /* Entries defining the UDP port to protocol mapping, each laid out as a
02265  * TUNNEL_ENCAP_UDP_PORT_ENTRY
02266  */
02267 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
02268 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
02269 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
02270 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
02271 
02272 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
02273 #define    MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
02274 /* Flags */
02275 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
02276 #define       MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
02277 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
02278 #define        MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
02279 
02280 
02281 #endif  /* SFC_MCDI_PCOL_H */