iPXE
mlx_link_speed.h
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00001 #ifndef MLX_LINK_SPEED_H_
00002 #define MLX_LINK_SPEED_H_
00003 
00004 /*
00005  * Copyright (C) 2015 Mellanox Technologies Ltd.
00006  *
00007  * This program is free software; you can redistribute it and/or
00008  * modify it under the terms of the GNU General Public License as
00009  * published by the Free Software Foundation; either version 2 of the
00010  * License, or any later version.
00011  *
00012  * This program is distributed in the hope that it will be useful, but
00013  * WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00015  * General Public License for more details.
00016  *
00017  * You should have received a copy of the GNU General Public License
00018  * along with this program; if not, write to the Free Software
00019  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00020  * 02110-1301, USA.
00021  */
00022 
00023 FILE_LICENCE ( GPL2_OR_LATER );
00024 
00025 #include "../../mlx_lib/mlx_reg_access/mlx_reg_access.h"
00026 #include "../../include/public/mlx_utils.h"
00027 
00028 #define LINK_SPEED_100GB_MASK        (ETH_SPEED_ENABLE_MASK_100GBASECR4 | ETH_SPEED_ENABLE_MASK_100GBASESR4 | ETH_SPEED_ENABLE_MASK_100GBASEKR4 | ETH_SPEED_ENABLE_MASK_100GBASELR4)
00029 #define LINK_SPEED_56GB_MASK         (ETH_SPEED_ENABLE_MASK_56GBASER4)
00030 #define LINK_SPEED_50GB_MASK         (ETH_SPEED_ENABLE_MASK_50GBASECR2 | ETH_SPEED_ENABLE_MASK_50GBASEKR2)
00031 #define LINK_SPEED_40GB_MASK         (ETH_SPEED_ENABLE_MASK_40GBASECR4 | ETH_SPEED_ENABLE_MASK_40GBASEKR4 | ETH_SPEED_ENABLE_MASK_40GBASESR4 | ETH_SPEED_ENABLE_MASK_40GBASELR4)
00032 #define LINK_SPEED_25GB_MASK         (ETH_SPEED_ENABLE_MASK_25GBASECR | ETH_SPEED_ENABLE_MASK_25GBASEKR | ETH_SPEED_ENABLE_MASK_25GBASESR)
00033 #define LINK_SPEED_20GB_MASK         (ETH_SPEED_ENABLE_MASK_20GBASER2)
00034 #define LINK_SPEED_10GB_MASK         (ETH_SPEED_ENABLE_MASK_10GBASECR | ETH_SPEED_ENABLE_MASK_10GBASESR | ETH_SPEED_ENABLE_MASK_10GBASELR | ETH_SPEED_ENABLE_MASK_10GBASEKR)
00035 #define LINK_SPEED_1GB_MASK          (ETH_SPEED_ENABLE_MASK_1000BASECX | ETH_SPEED_ENABLE_MASK_1000BASEKX | ETH_SPEED_ENABLE_MASK_100BaseTX | ETH_SPEED_ENABLE_MASK_1000BASET)
00036 
00037 #define LINK_SPEED_SDR_MASK 0x1
00038 #define LINK_SPEED_DDR_MASK 0x2
00039 #define LINK_SPEED_QDR_MASK 0xC
00040 #define LINK_SPEED_FDR_MASK 0x10
00041 #define LINK_SPEED_EDR20_MASK 0x200
00042 #define LINK_SPEED_EDR_MASK 0x20
00043 
00044 #define LINK_SPEED_WITDH_1_MASK 0x1
00045 #define LINK_SPEED_WITDH_2_MASK 0x2
00046 #define LINK_SPEED_WITDH_4_MASK 0x4
00047 #define LINK_SPEED_WITDH_8_MASK 0x8
00048 #define LINK_SPEED_WITDH_12_MASK 0x10
00049 
00050 #define GIGA_TO_BIT 0x40000000
00051 
00052 enum {
00053     ETH_SPEED_ENABLE_MASK_1000BASECX  = 0x0001,
00054     ETH_SPEED_ENABLE_MASK_1000BASEKX  = 0x0002,
00055     ETH_SPEED_ENABLE_MASK_10GBASECX4  = 0x0004,
00056     ETH_SPEED_ENABLE_MASK_10GBASEKX4  = 0x0008,
00057     ETH_SPEED_ENABLE_MASK_10GBASEKR   = 0x0010,
00058     ETH_SPEED_ENABLE_MASK_20GBASER2   = 0x0020,
00059     ETH_SPEED_ENABLE_MASK_40GBASECR4  = 0x0040,
00060     ETH_SPEED_ENABLE_MASK_40GBASEKR4  = 0x0080,
00061     ETH_SPEED_ENABLE_MASK_56GBASER4   = 0x0100,
00062     ETH_SPEED_ENABLE_MASK_10GBASECR   = 0x1000,
00063     ETH_SPEED_ENABLE_MASK_10GBASESR   = 0x2000,
00064     ETH_SPEED_ENABLE_MASK_10GBASELR   = 0x4000,
00065     ETH_SPEED_ENABLE_MASK_40GBASESR4  = 0x8000,
00066     ETH_SPEED_ENABLE_MASK_40GBASELR4  = 0x10000,
00067     ETH_SPEED_ENABLE_MASK_50GBASEKR4  = 0x80000,
00068     ETH_SPEED_ENABLE_MASK_100GBASECR4 = 0x100000,
00069     ETH_SPEED_ENABLE_MASK_100GBASESR4 = 0x200000,
00070     ETH_SPEED_ENABLE_MASK_100GBASEKR4 = 0x400000,
00071     ETH_SPEED_ENABLE_MASK_100GBASELR4 = 0x800000,
00072     ETH_SPEED_ENABLE_MASK_100BaseTX   = 0x1000000,
00073     ETH_SPEED_ENABLE_MASK_1000BASET   = 0x2000000,
00074     ETH_SPEED_ENABLE_MASK_10GBASET    = 0x4000000,
00075     ETH_SPEED_ENABLE_MASK_25GBASECR   = 0x8000000,
00076     ETH_SPEED_ENABLE_MASK_25GBASEKR   = 0x10000000,
00077     ETH_SPEED_ENABLE_MASK_25GBASESR   = 0x20000000,
00078     ETH_SPEED_ENABLE_MASK_50GBASECR2  = 0x40000000,
00079     ETH_SPEED_ENABLE_MASK_50GBASEKR2  = 0x80000000,
00080     ETH_SPEED_ENABLE_MASK_BAD         = 0xffff,
00081 };
00082 
00083 
00084 typedef enum {
00085         LINK_SPEED_IB = 0,
00086         LINK_SPEED_FC,
00087         LINK_SPEED_ETH,
00088 } LINK_SPEED_TYPE;
00089 
00090 typedef enum {
00091         LINK_SPEED_1GB = 0,
00092         LINK_SPEED_10GB,
00093         LINK_SPEED_40GB,
00094         LINK_SPEED_100GB,
00095         LINK_SPEED_SDR,
00096         LINK_SPEED_DEFAULT,
00097 } LINK_SPEED;
00098 
00099 struct mlx_link_speed {
00100         mlx_uint32 proto_mask   :3;
00101         mlx_uint32 reserved1    :13;
00102         mlx_uint32 loacl_port   :8;
00103         mlx_uint32 reserved2    :8;
00104         /* -------------- */
00105         mlx_uint32 reserved3    :32;
00106         /* -------------- */
00107         mlx_uint32 reserved4    :32;
00108         /* -------------- */
00109         mlx_uint32 eth_proto_capability :32;
00110         /* -------------- */
00111         mlx_uint32 ib_proto_capability  :16;
00112         mlx_uint32 ib_link_width_capability     :16;
00113         /* -------------- */
00114         mlx_uint32 reserved5    :32;
00115         /* -------------- */
00116         mlx_uint32 eth_proto_admin      :32;
00117         /* -------------- */
00118         mlx_uint32 ib_proto_admin       :16;
00119         mlx_uint32 ib_link_width_admin  :16;
00120         /* -------------- */
00121         mlx_uint32 reserved6    :32;
00122         /* -------------- */
00123         mlx_uint32 eth_proto_oper       :32;
00124         /* -------------- */
00125         mlx_uint32 ib_proto_oper        :16;
00126         mlx_uint32 ib_link_width_oper   :16;
00127         /* -------------- */
00128         mlx_uint32 reserved7    :32;
00129         /* -------------- */
00130         mlx_uint32 eth_proto_lp_advertise       :32;
00131         mlx_uint32 reserved[3];
00132 };
00133 
00134 mlx_status
00135 mlx_set_link_speed(
00136                 IN mlx_utils *utils,
00137                 IN mlx_uint8 port_num,
00138                 IN LINK_SPEED_TYPE type,
00139                 IN LINK_SPEED speed
00140                 );
00141 
00142 mlx_status
00143 mlx_get_max_speed(
00144                 IN mlx_utils *utils,
00145                 IN mlx_uint8 port_num,
00146                 IN LINK_SPEED_TYPE type,
00147                 OUT mlx_uint64 *speed
00148                 );
00149 
00150 #endif /* MLX_LINK_SPEED_H_ */