iPXE
nodnic_shomron_prm.h
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1 /*
2  * Copyright (C) 2015 Mellanox Technologies Ltd.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  */
19 
20 FILE_LICENCE ( GPL2_OR_LATER );
21 
22 #ifndef SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_SHOMRON_PRM_H_
23 #define SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_SHOMRON_PRM_H_
24 
25 
26 
27 #include "nodnic_prm.h"
28 
29 
30 #define SHOMRON_MAX_GATHER 1
31 
32 /* Send wqe segment ctrl */
33 
34 struct shomronprm_wqe_segment_ctrl_send_st { /* Little Endian */
35  pseudo_bit_t opcode[0x00008];
38 /* -------------- */
39  pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */
41  pseudo_bit_t qpn[0x00018];
42 /* -------------- */
44  pseudo_bit_t ce[0x00002];
46 /* -------------- */
48 /* -------------- */
49  pseudo_bit_t mss[0x0000e];
53  pseudo_bit_t cs13[0x00001];
54  pseudo_bit_t cs14[0x00001];
55 /* -------------- */
57 /* -------------- */
59  pseudo_bit_t inline_headers_size[0x0000a]; //sum size of inline_hdr1+inline_hdrs (0x10)
61 /* -------------- */
63 /* -------------- */
65 /* -------------- */
67 /* -------------- */
69 };
70 
71 
72 
73 /* Completion Queue Entry Format #### michal - fixed by gdror */
74 
75 struct shomronprm_completion_queue_entry_st { /* Little Endian */
76 
78 /* -------------- */
82 /* -------------- */
83  pseudo_bit_t slid[0x00010];
85 /* -------------- */
86  pseudo_bit_t rqpn[0x00018];
87  pseudo_bit_t sl[0x00004];
88  pseudo_bit_t l3_hdr[0x00002];
90 /* -------------- */
92 /* -------------- */
93  pseudo_bit_t srqn[0x00018];
95 /* -------------- */
97 /* -------------- */
99 /* -------------- */
101 /* -------------- */
103 /* -------------- */
104  pseudo_bit_t qpn[0x00018];
106 /* -------------- */
107  pseudo_bit_t owner[0x00001];
112 };
113 
114 
115 /* Completion with Error CQE #### michal - gdror fixed */
116 
117 struct shomronprm_completion_with_error_st { /* Little Endian */
119  /* -------------- */
123  /* -------------- */
125 };
126 
127 
128 struct MLX_DECLARE_STRUCT ( shomronprm_wqe_segment_ctrl_send );
129 struct MLX_DECLARE_STRUCT ( shomronprm_completion_queue_entry );
130 struct MLX_DECLARE_STRUCT ( shomronprm_completion_with_error );
131 
133  struct shomronprm_wqe_segment_ctrl_send ctrl;
134  struct nodnic_wqe_segment_data_ptr data[SHOMRON_MAX_GATHER];
135 } __attribute__ (( packed ));
136 
138  struct shomronprm_completion_queue_entry normal;
139  struct shomronprm_completion_with_error error;
140 } __attribute__ (( packed ));
141 
142 
143 #endif /* SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_SHOMRON_PRM_H_ */
pseudo_bit_t vendor_error_syndrome[0x00008]
struct shomronprm_completion_queue_entry normal
pseudo_bit_t opcode[0x00004]
struct shomronprm_completion_with_error error
pseudo_bit_t pkey_index[0x00020]
pseudo_bit_t sl[0x00004]
pseudo_bit_t owner[0x00001]
struct nodnic_wqe_segment_data_ptr data[SHOMRON_MAX_GATHER]
pseudo_bit_t qpn[0x00018]
unsigned char pseudo_bit_t
Datatype used to represent a bit in the pseudo-structures.
Definition: nx_bitops.h:37
pseudo_bit_t reserved4[0x00010]
pseudo_bit_t reserved5[0x00002]
pseudo_bit_t srqn[0x00018]
pseudo_bit_t byte_cnt[0x00020]
pseudo_bit_t reserved10[0x00020]
pseudo_bit_t inline_headers_size[0x0000a]
pseudo_bit_t reserved3[0x00009]
FILE_LICENCE(GPL2_OR_LATER)
pseudo_bit_t wqe_counter[0x00010]
pseudo_bit_t reserved8[0x00003]
pseudo_bit_t l3_hdr[0x00002]
pseudo_bit_t reserved1[0x00080]
pseudo_bit_t ml_path[0x00007]
pseudo_bit_t reserved9[0x00008]
pseudo_bit_t rx_drop_counter[0x00008]
struct MLX_DECLARE_STRUCT(shomronprm_wqe_segment_ctrl_send)
pseudo_bit_t slid[0x00010]
pseudo_bit_t reserved6[0x00020]
pseudo_bit_t reserved7[0x00040]
struct shomronprm_wqe_segment_ctrl_send ctrl
pseudo_bit_t reserved11[0x0008]
#define SHOMRON_MAX_GATHER
pseudo_bit_t reserved2[0x00010]
pseudo_bit_t rqpn[0x00018]
struct shomronprm_wqe_segment_ctrl_send_st __attribute__