iPXE
pci.h
Go to the documentation of this file.
00001 #ifndef _IPXE_PCI_H
00002 #define _IPXE_PCI_H
00003 
00004 /** @file
00005  *
00006  * PCI bus
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/device.h>
00014 #include <ipxe/tables.h>
00015 #include <ipxe/pci_io.h>
00016 
00017 /** PCI vendor ID */
00018 #define PCI_VENDOR_ID           0x00
00019 
00020 /** PCI device ID */
00021 #define PCI_DEVICE_ID           0x02
00022 
00023 /** PCI command */
00024 #define PCI_COMMAND             0x04
00025 #define PCI_COMMAND_IO                  0x0001  /**< I/O space */
00026 #define PCI_COMMAND_MEM                 0x0002  /**< Memory space */
00027 #define PCI_COMMAND_MASTER              0x0004  /**< Bus master */
00028 #define PCI_COMMAND_INVALIDATE          0x0010  /**< Mem. write & invalidate */
00029 #define PCI_COMMAND_PARITY              0x0040  /**< Parity error response */
00030 #define PCI_COMMAND_SERR                0x0100  /**< SERR# enable */
00031 #define PCI_COMMAND_INTX_DISABLE        0x0400  /**< Interrupt disable */
00032 
00033 /** PCI status */
00034 #define PCI_STATUS              0x06
00035 #define PCI_STATUS_CAP_LIST             0x0010  /**< Capabilities list */
00036 #define PCI_STATUS_PARITY               0x0100  /**< Master data parity error */
00037 #define PCI_STATUS_REC_TARGET_ABORT     0x1000  /**< Received target abort */
00038 #define PCI_STATUS_REC_MASTER_ABORT     0x2000  /**< Received master abort */
00039 #define PCI_STATUS_SIG_SYSTEM_ERROR     0x4000  /**< Signalled system error */
00040 #define PCI_STATUS_DETECTED_PARITY      0x8000  /**< Detected parity error */
00041 
00042 /** PCI revision */
00043 #define PCI_REVISION            0x08
00044 
00045 /** PCI cache line size */
00046 #define PCI_CACHE_LINE_SIZE     0x0c
00047 
00048 /** PCI latency timer */
00049 #define PCI_LATENCY_TIMER       0x0d
00050 
00051 /** PCI header type */
00052 #define PCI_HEADER_TYPE         0x0e
00053 #define PCI_HEADER_TYPE_NORMAL          0x00    /**< Normal header */
00054 #define PCI_HEADER_TYPE_BRIDGE          0x01    /**< PCI-to-PCI bridge header */
00055 #define PCI_HEADER_TYPE_CARDBUS         0x02    /**< CardBus header */
00056 #define PCI_HEADER_TYPE_MASK            0x7f    /**< Header type mask */
00057 #define PCI_HEADER_TYPE_MULTI           0x80    /**< Multi-function device */
00058 
00059 /** PCI base address registers */
00060 #define PCI_BASE_ADDRESS(n)     ( 0x10 + ( 4 * (n) ) )
00061 #define PCI_BASE_ADDRESS_0      PCI_BASE_ADDRESS ( 0 )
00062 #define PCI_BASE_ADDRESS_1      PCI_BASE_ADDRESS ( 1 )
00063 #define PCI_BASE_ADDRESS_2      PCI_BASE_ADDRESS ( 2 )
00064 #define PCI_BASE_ADDRESS_3      PCI_BASE_ADDRESS ( 3 )
00065 #define PCI_BASE_ADDRESS_4      PCI_BASE_ADDRESS ( 4 )
00066 #define PCI_BASE_ADDRESS_5      PCI_BASE_ADDRESS ( 5 )
00067 #define PCI_BASE_ADDRESS_SPACE_IO       0x00000001UL    /**< I/O BAR */
00068 #define PCI_BASE_ADDRESS_IO_MASK        0x00000003UL    /**< I/O BAR mask */
00069 #define PCI_BASE_ADDRESS_MEM_TYPE_64    0x00000004UL    /**< 64-bit memory */
00070 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK  0x00000006UL    /**< Memory type mask */
00071 #define PCI_BASE_ADDRESS_MEM_MASK       0x0000000fUL    /**< Memory BAR mask */
00072 
00073 /** PCI subsystem vendor ID */
00074 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
00075 
00076 /** PCI subsystem ID */
00077 #define PCI_SUBSYSTEM_ID        0x2e  
00078 
00079 /** PCI expansion ROM base address */
00080 #define PCI_ROM_ADDRESS         0x30
00081 
00082 /** PCI capabilities pointer */
00083 #define PCI_CAPABILITY_LIST     0x34
00084 
00085 /** CardBus capabilities pointer */
00086 #define PCI_CB_CAPABILITY_LIST  0x14
00087 
00088 /** PCI interrupt line */
00089 #define PCI_INTERRUPT_LINE      0x3c
00090 
00091 /** Capability ID */
00092 #define PCI_CAP_ID              0x00
00093 #define PCI_CAP_ID_PM                   0x01    /**< Power management */
00094 #define PCI_CAP_ID_VPD                  0x03    /**< Vital product data */
00095 #define PCI_CAP_ID_VNDR                 0x09    /**< Vendor-specific */
00096 #define PCI_CAP_ID_EXP                  0x10    /**< PCI Express */
00097 #define PCI_CAP_ID_MSIX                 0x11    /**< MSI-X */
00098 #define PCI_CAP_ID_EA                   0x14    /**< Enhanced Allocation */
00099 
00100 /** Next capability */
00101 #define PCI_CAP_NEXT            0x01
00102 
00103 /** Power management control and status */
00104 #define PCI_PM_CTRL             0x04
00105 #define PCI_PM_CTRL_STATE_MASK          0x0003  /**< Current power state */
00106 #define PCI_PM_CTRL_PME_ENABLE          0x0100  /**< PME pin enable */
00107 #define PCI_PM_CTRL_PME_STATUS          0x8000  /**< PME pin status */
00108 
00109 /** PCI Express */
00110 #define PCI_EXP_DEVCTL          0x08
00111 #define PCI_EXP_DEVCTL_FLR              0x8000  /**< Function level reset */
00112 
00113 /** MSI-X interrupts */
00114 #define PCI_MSIX_CTRL           0x02
00115 #define PCI_MSIX_CTRL_ENABLE            0x8000  /**< Enable MSI-X */
00116 #define PCI_MSIX_CTRL_MASK              0x4000  /**< Mask all interrupts */
00117 #define PCI_MSIX_CTRL_SIZE(x)   ( (x) & 0x07ff ) /**< Table size */
00118 #define PCI_MSIX_DESC_TABLE     0x04
00119 #define PCI_MSIX_DESC_PBA       0x08
00120 #define PCI_MSIX_DESC_BIR(x)    ( (x) & 0x00000007 ) /**< BAR index */
00121 #define PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 ) /**< BAR offset */
00122 
00123 /** Uncorrectable error status */
00124 #define PCI_ERR_UNCOR_STATUS    0x04
00125 
00126 /** Network controller */
00127 #define PCI_CLASS_NETWORK       0x02
00128 
00129 /** Serial bus controller */
00130 #define PCI_CLASS_SERIAL        0x0c
00131 #define PCI_CLASS_SERIAL_USB            0x03    /**< USB controller */
00132 #define PCI_CLASS_SERIAL_USB_UHCI        0x00   /**< UHCI USB controller */
00133 #define PCI_CLASS_SERIAL_USB_OHCI        0x10   /**< OHCI USB controller */
00134 #define PCI_CLASS_SERIAL_USB_EHCI        0x20   /**< ECHI USB controller */
00135 #define PCI_CLASS_SERIAL_USB_XHCI        0x30   /**< xHCI USB controller */
00136 
00137 /** Construct PCI class
00138  *
00139  * @v base              Base class (or PCI_ANY_ID)
00140  * @v sub               Subclass (or PCI_ANY_ID)
00141  * @v progif            Programming interface (or PCI_ANY_ID)
00142  */
00143 #define PCI_CLASS( base, sub, progif )                                  \
00144         ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) |     \
00145           ( ( (progif) & 0xff) << 0 ) )
00146 
00147 /** PCI Express function level reset delay (in ms) */
00148 #define PCI_EXP_FLR_DELAY_MS 100
00149 
00150 /** A PCI device ID list entry */
00151 struct pci_device_id {
00152         /** Name */
00153         const char *name;
00154         /** PCI vendor ID */
00155         uint16_t vendor;
00156         /** PCI device ID */
00157         uint16_t device;
00158         /** Arbitrary driver data */
00159         unsigned long driver_data;
00160 };
00161 
00162 /** Match-anything ID */
00163 #define PCI_ANY_ID 0xffff
00164 
00165 /** A PCI class ID */
00166 struct pci_class_id {
00167         /** Class */
00168         uint32_t class;
00169         /** Class mask */
00170         uint32_t mask;
00171 };
00172 
00173 /** Construct PCI class ID
00174  *
00175  * @v base              Base class (or PCI_ANY_ID)
00176  * @v sub               Subclass (or PCI_ANY_ID)
00177  * @v progif            Programming interface (or PCI_ANY_ID)
00178  */
00179 #define PCI_CLASS_ID( base, sub, progif ) {                                \
00180         .class = PCI_CLASS ( base, sub, progif ),                          \
00181         .mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) |   \
00182                   ( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) |     \
00183                   ( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
00184         }
00185 
00186 /** A PCI device */
00187 struct pci_device {
00188         /** Generic device */
00189         struct device dev;
00190         /** Memory base
00191          *
00192          * This is the physical address of the first valid memory BAR.
00193          */
00194         unsigned long membase;
00195         /**
00196          * I/O address
00197          *
00198          * This is the physical address of the first valid I/O BAR.
00199          */
00200         unsigned long ioaddr;
00201         /** Vendor ID */
00202         uint16_t vendor;
00203         /** Device ID */
00204         uint16_t device;
00205         /** Device class */
00206         uint32_t class;
00207         /** Interrupt number */
00208         uint8_t irq;
00209         /** Segment, bus, device, and function (bus:dev.fn) number */
00210         uint32_t busdevfn;
00211         /** Driver for this device */
00212         struct pci_driver *driver;
00213         /** Driver-private data
00214          *
00215          * Use pci_set_drvdata() and pci_get_drvdata() to access this
00216          * field.
00217          */
00218         void *priv;
00219         /** Driver device ID */
00220         struct pci_device_id *id;
00221 };
00222 
00223 /** A PCI driver */
00224 struct pci_driver {
00225         /** PCI ID table */
00226         struct pci_device_id *ids;
00227         /** Number of entries in PCI ID table */
00228         unsigned int id_count;
00229         /** PCI class ID */
00230         struct pci_class_id class;
00231         /**
00232          * Probe device
00233          *
00234          * @v pci       PCI device
00235          * @ret rc      Return status code
00236          */
00237         int ( * probe ) ( struct pci_device *pci );
00238         /**
00239          * Remove device
00240          *
00241          * @v pci       PCI device
00242          */
00243         void ( * remove ) ( struct pci_device *pci );
00244 };
00245 
00246 /** PCI driver table */
00247 #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
00248 
00249 /** Declare a PCI driver */
00250 #define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
00251 
00252 /** Declare a fallback PCI driver */
00253 #define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
00254 
00255 #define PCI_SEG( busdevfn )             ( ( (busdevfn) >> 16 ) & 0xffff )
00256 #define PCI_BUS( busdevfn )             ( ( (busdevfn) >> 8 ) & 0xff )
00257 #define PCI_SLOT( busdevfn )            ( ( (busdevfn) >> 3 ) & 0x1f )
00258 #define PCI_FUNC( busdevfn )            ( ( (busdevfn) >> 0 ) & 0x07 )
00259 #define PCI_BUSDEVFN( segment, bus, slot, func )                        \
00260         ( ( (segment) << 16 ) | ( (bus) << 8 ) |                        \
00261           ( (slot) << 3 ) | ( (func) << 0 ) )
00262 #define PCI_FIRST_FUNC( busdevfn )      ( (busdevfn) & ~0x07 )
00263 #define PCI_LAST_FUNC( busdevfn )       ( (busdevfn) | 0x07 )
00264 
00265 #define PCI_BASE_CLASS( class )         ( (class) >> 16 )
00266 #define PCI_SUB_CLASS( class )          ( ( (class) >> 8 ) & 0xff )
00267 #define PCI_PROG_INTF( class )          ( (class) & 0xff )
00268 
00269 /*
00270  * PCI_ROM is used to build up entries in a struct pci_id array.  It
00271  * is also parsed by parserom.pl to generate Makefile rules and files
00272  * for rom-o-matic.
00273  *
00274  * PCI_ID can be used to generate entries without creating a
00275  * corresponding ROM in the build process.
00276  */
00277 #define PCI_ID( _vendor, _device, _name, _description, _data ) {        \
00278         .vendor = _vendor,                                              \
00279         .device = _device,                                              \
00280         .name = _name,                                                  \
00281         .driver_data = _data                                            \
00282 }
00283 #define PCI_ROM( _vendor, _device, _name, _description, _data ) \
00284         PCI_ID( _vendor, _device, _name, _description, _data )
00285 
00286 /** PCI device debug message format */
00287 #define PCI_FMT "%04x:%02x:%02x.%x"
00288 
00289 /** PCI device debug message arguments */
00290 #define PCI_ARGS( pci )                                                 \
00291         PCI_SEG ( (pci)->busdevfn ), PCI_BUS ( (pci)->busdevfn ),       \
00292         PCI_SLOT ( (pci)->busdevfn ), PCI_FUNC ( (pci)->busdevfn )
00293 
00294 extern void adjust_pci_device ( struct pci_device *pci );
00295 extern unsigned long pci_bar_start ( struct pci_device *pci,
00296                                      unsigned int reg );
00297 extern int pci_read_config ( struct pci_device *pci );
00298 extern int pci_find_next ( struct pci_device *pci, unsigned int busdevfn );
00299 extern int pci_find_driver ( struct pci_device *pci );
00300 extern int pci_probe ( struct pci_device *pci );
00301 extern void pci_remove ( struct pci_device *pci );
00302 extern int pci_find_capability ( struct pci_device *pci, int capability );
00303 extern int pci_find_next_capability ( struct pci_device *pci,
00304                                       int pos, int capability );
00305 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
00306 
00307 /**
00308  * Initialise PCI device
00309  *
00310  * @v pci               PCI device
00311  * @v busdevfn          PCI bus:dev.fn address
00312  */
00313 static inline void pci_init ( struct pci_device *pci, unsigned int busdevfn ) {
00314         pci->busdevfn = busdevfn;
00315 }
00316 
00317 /**
00318  * Set PCI driver
00319  *
00320  * @v pci               PCI device
00321  * @v driver            PCI driver
00322  * @v id                PCI device ID
00323  */
00324 static inline void pci_set_driver ( struct pci_device *pci,
00325                                     struct pci_driver *driver,
00326                                     struct pci_device_id *id ) {
00327         pci->driver = driver;
00328         pci->id = id;
00329         pci->dev.driver_name = id->name;
00330 }
00331 
00332 /**
00333  * Set PCI driver-private data
00334  *
00335  * @v pci               PCI device
00336  * @v priv              Private data
00337  */
00338 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
00339         pci->priv = priv;
00340 }
00341 
00342 /**
00343  * Get PCI driver-private data
00344  *
00345  * @v pci               PCI device
00346  * @ret priv            Private data
00347  */
00348 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
00349         return pci->priv;
00350 }
00351 
00352 #endif  /* _IPXE_PCI_H */