iPXE
pci.h
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00001 #ifndef _IPXE_PCI_H
00002 #define _IPXE_PCI_H
00003 
00004 /** @file
00005  *
00006  * PCI bus
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/device.h>
00014 #include <ipxe/tables.h>
00015 #include <ipxe/pci_io.h>
00016 
00017 /** PCI vendor ID */
00018 #define PCI_VENDOR_ID           0x00
00019 
00020 /** PCI device ID */
00021 #define PCI_DEVICE_ID           0x02
00022 
00023 /** PCI command */
00024 #define PCI_COMMAND             0x04
00025 #define PCI_COMMAND_IO                  0x0001  /**< I/O space */
00026 #define PCI_COMMAND_MEM                 0x0002  /**< Memory space */
00027 #define PCI_COMMAND_MASTER              0x0004  /**< Bus master */
00028 #define PCI_COMMAND_INVALIDATE          0x0010  /**< Mem. write & invalidate */
00029 #define PCI_COMMAND_PARITY              0x0040  /**< Parity error response */
00030 #define PCI_COMMAND_SERR                0x0100  /**< SERR# enable */
00031 #define PCI_COMMAND_INTX_DISABLE        0x0400  /**< Interrupt disable */
00032 
00033 /** PCI status */
00034 #define PCI_STATUS              0x06
00035 #define PCI_STATUS_CAP_LIST             0x0010  /**< Capabilities list */
00036 #define PCI_STATUS_PARITY               0x0100  /**< Master data parity error */
00037 #define PCI_STATUS_REC_TARGET_ABORT     0x1000  /**< Received target abort */
00038 #define PCI_STATUS_REC_MASTER_ABORT     0x2000  /**< Received master abort */
00039 #define PCI_STATUS_SIG_SYSTEM_ERROR     0x4000  /**< Signalled system error */
00040 #define PCI_STATUS_DETECTED_PARITY      0x8000  /**< Detected parity error */
00041 
00042 /** PCI revision */
00043 #define PCI_REVISION            0x08
00044 
00045 /** PCI cache line size */
00046 #define PCI_CACHE_LINE_SIZE     0x0c
00047 
00048 /** PCI latency timer */
00049 #define PCI_LATENCY_TIMER       0x0d
00050 
00051 /** PCI header type */
00052 #define PCI_HEADER_TYPE         0x0e
00053 #define PCI_HEADER_TYPE_NORMAL          0x00    /**< Normal header */
00054 #define PCI_HEADER_TYPE_BRIDGE          0x01    /**< PCI-to-PCI bridge header */
00055 #define PCI_HEADER_TYPE_CARDBUS         0x02    /**< CardBus header */
00056 #define PCI_HEADER_TYPE_MASK            0x7f    /**< Header type mask */
00057 #define PCI_HEADER_TYPE_MULTI           0x80    /**< Multi-function device */
00058 
00059 /** PCI base address registers */
00060 #define PCI_BASE_ADDRESS(n)     ( 0x10 + ( 4 * (n) ) )
00061 #define PCI_BASE_ADDRESS_0      PCI_BASE_ADDRESS ( 0 )
00062 #define PCI_BASE_ADDRESS_1      PCI_BASE_ADDRESS ( 1 )
00063 #define PCI_BASE_ADDRESS_2      PCI_BASE_ADDRESS ( 2 )
00064 #define PCI_BASE_ADDRESS_3      PCI_BASE_ADDRESS ( 3 )
00065 #define PCI_BASE_ADDRESS_4      PCI_BASE_ADDRESS ( 4 )
00066 #define PCI_BASE_ADDRESS_5      PCI_BASE_ADDRESS ( 5 )
00067 #define PCI_BASE_ADDRESS_SPACE_IO       0x00000001UL    /**< I/O BAR */
00068 #define PCI_BASE_ADDRESS_IO_MASK        0x00000003UL    /**< I/O BAR mask */
00069 #define PCI_BASE_ADDRESS_MEM_TYPE_64    0x00000004UL    /**< 64-bit memory */
00070 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK  0x00000006UL    /**< Memory type mask */
00071 #define PCI_BASE_ADDRESS_MEM_MASK       0x0000000fUL    /**< Memory BAR mask */
00072 
00073 /** PCI subsystem vendor ID */
00074 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
00075 
00076 /** PCI subsystem ID */
00077 #define PCI_SUBSYSTEM_ID        0x2e  
00078 
00079 /** PCI expansion ROM base address */
00080 #define PCI_ROM_ADDRESS         0x30
00081 
00082 /** PCI capabilities pointer */
00083 #define PCI_CAPABILITY_LIST     0x34
00084 
00085 /** CardBus capabilities pointer */
00086 #define PCI_CB_CAPABILITY_LIST  0x14
00087 
00088 /** PCI interrupt line */
00089 #define PCI_INTERRUPT_LINE      0x3c
00090 
00091 /** Capability ID */
00092 #define PCI_CAP_ID              0x00
00093 #define PCI_CAP_ID_PM                   0x01    /**< Power management */
00094 #define PCI_CAP_ID_VPD                  0x03    /**< Vital product data */
00095 #define PCI_CAP_ID_VNDR                 0x09    /**< Vendor-specific */
00096 #define PCI_CAP_ID_EXP                  0x10    /**< PCI Express */
00097 #define PCI_CAP_ID_EA                   0x14    /**< Enhanced Allocation */
00098 
00099 /** Next capability */
00100 #define PCI_CAP_NEXT            0x01
00101 
00102 /** Power management control and status */
00103 #define PCI_PM_CTRL             0x04
00104 #define PCI_PM_CTRL_STATE_MASK          0x0003  /**< Current power state */
00105 #define PCI_PM_CTRL_PME_ENABLE          0x0100  /**< PME pin enable */
00106 #define PCI_PM_CTRL_PME_STATUS          0x8000  /**< PME pin status */
00107 
00108 /** PCI Express */
00109 #define PCI_EXP_DEVCTL          0x08
00110 #define PCI_EXP_DEVCTL_FLR              0x8000  /**< Function level reset */
00111 
00112 /** Uncorrectable error status */
00113 #define PCI_ERR_UNCOR_STATUS    0x04
00114 
00115 /** Network controller */
00116 #define PCI_CLASS_NETWORK       0x02
00117 
00118 /** Serial bus controller */
00119 #define PCI_CLASS_SERIAL        0x0c
00120 #define PCI_CLASS_SERIAL_USB            0x03    /**< USB controller */
00121 #define PCI_CLASS_SERIAL_USB_UHCI        0x00   /**< UHCI USB controller */
00122 #define PCI_CLASS_SERIAL_USB_OHCI        0x10   /**< OHCI USB controller */
00123 #define PCI_CLASS_SERIAL_USB_EHCI        0x20   /**< ECHI USB controller */
00124 #define PCI_CLASS_SERIAL_USB_XHCI        0x30   /**< xHCI USB controller */
00125 
00126 /** Construct PCI class
00127  *
00128  * @v base              Base class (or PCI_ANY_ID)
00129  * @v sub               Subclass (or PCI_ANY_ID)
00130  * @v progif            Programming interface (or PCI_ANY_ID)
00131  */
00132 #define PCI_CLASS( base, sub, progif )                                  \
00133         ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) |     \
00134           ( ( (progif) & 0xff) << 0 ) )
00135 
00136 /** PCI Express function level reset delay (in ms) */
00137 #define PCI_EXP_FLR_DELAY_MS 100
00138 
00139 /** A PCI device ID list entry */
00140 struct pci_device_id {
00141         /** Name */
00142         const char *name;
00143         /** PCI vendor ID */
00144         uint16_t vendor;
00145         /** PCI device ID */
00146         uint16_t device;
00147         /** Arbitrary driver data */
00148         unsigned long driver_data;
00149 };
00150 
00151 /** Match-anything ID */
00152 #define PCI_ANY_ID 0xffff
00153 
00154 /** A PCI class ID */
00155 struct pci_class_id {
00156         /** Class */
00157         uint32_t class;
00158         /** Class mask */
00159         uint32_t mask;
00160 };
00161 
00162 /** Construct PCI class ID
00163  *
00164  * @v base              Base class (or PCI_ANY_ID)
00165  * @v sub               Subclass (or PCI_ANY_ID)
00166  * @v progif            Programming interface (or PCI_ANY_ID)
00167  */
00168 #define PCI_CLASS_ID( base, sub, progif ) {                                \
00169         .class = PCI_CLASS ( base, sub, progif ),                          \
00170         .mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) |   \
00171                   ( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) |     \
00172                   ( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
00173         }
00174 
00175 /** A PCI device */
00176 struct pci_device {
00177         /** Generic device */
00178         struct device dev;
00179         /** Memory base
00180          *
00181          * This is the physical address of the first valid memory BAR.
00182          */
00183         unsigned long membase;
00184         /**
00185          * I/O address
00186          *
00187          * This is the physical address of the first valid I/O BAR.
00188          */
00189         unsigned long ioaddr;
00190         /** Vendor ID */
00191         uint16_t vendor;
00192         /** Device ID */
00193         uint16_t device;
00194         /** Device class */
00195         uint32_t class;
00196         /** Interrupt number */
00197         uint8_t irq;
00198         /** Segment, bus, device, and function (bus:dev.fn) number */
00199         uint32_t busdevfn;
00200         /** Driver for this device */
00201         struct pci_driver *driver;
00202         /** Driver-private data
00203          *
00204          * Use pci_set_drvdata() and pci_get_drvdata() to access this
00205          * field.
00206          */
00207         void *priv;
00208         /** Driver device ID */
00209         struct pci_device_id *id;
00210 };
00211 
00212 /** A PCI driver */
00213 struct pci_driver {
00214         /** PCI ID table */
00215         struct pci_device_id *ids;
00216         /** Number of entries in PCI ID table */
00217         unsigned int id_count;
00218         /** PCI class ID */
00219         struct pci_class_id class;
00220         /**
00221          * Probe device
00222          *
00223          * @v pci       PCI device
00224          * @ret rc      Return status code
00225          */
00226         int ( * probe ) ( struct pci_device *pci );
00227         /**
00228          * Remove device
00229          *
00230          * @v pci       PCI device
00231          */
00232         void ( * remove ) ( struct pci_device *pci );
00233 };
00234 
00235 /** PCI driver table */
00236 #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
00237 
00238 /** Declare a PCI driver */
00239 #define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
00240 
00241 /** Declare a fallback PCI driver */
00242 #define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
00243 
00244 #define PCI_SEG( busdevfn )             ( ( (busdevfn) >> 16 ) & 0xffff )
00245 #define PCI_BUS( busdevfn )             ( ( (busdevfn) >> 8 ) & 0xff )
00246 #define PCI_SLOT( busdevfn )            ( ( (busdevfn) >> 3 ) & 0x1f )
00247 #define PCI_FUNC( busdevfn )            ( ( (busdevfn) >> 0 ) & 0x07 )
00248 #define PCI_BUSDEVFN( segment, bus, slot, func )                        \
00249         ( ( (segment) << 16 ) | ( (bus) << 8 ) |                        \
00250           ( (slot) << 3 ) | ( (func) << 0 ) )
00251 #define PCI_FIRST_FUNC( busdevfn )      ( (busdevfn) & ~0x07 )
00252 #define PCI_LAST_FUNC( busdevfn )       ( (busdevfn) | 0x07 )
00253 
00254 #define PCI_BASE_CLASS( class )         ( (class) >> 16 )
00255 #define PCI_SUB_CLASS( class )          ( ( (class) >> 8 ) & 0xff )
00256 #define PCI_PROG_INTF( class )          ( (class) & 0xff )
00257 
00258 /*
00259  * PCI_ROM is used to build up entries in a struct pci_id array.  It
00260  * is also parsed by parserom.pl to generate Makefile rules and files
00261  * for rom-o-matic.
00262  *
00263  * PCI_ID can be used to generate entries without creating a
00264  * corresponding ROM in the build process.
00265  */
00266 #define PCI_ID( _vendor, _device, _name, _description, _data ) {        \
00267         .vendor = _vendor,                                              \
00268         .device = _device,                                              \
00269         .name = _name,                                                  \
00270         .driver_data = _data                                            \
00271 }
00272 #define PCI_ROM( _vendor, _device, _name, _description, _data ) \
00273         PCI_ID( _vendor, _device, _name, _description, _data )
00274 
00275 /** PCI device debug message format */
00276 #define PCI_FMT "%04x:%02x:%02x.%x"
00277 
00278 /** PCI device debug message arguments */
00279 #define PCI_ARGS( pci )                                                 \
00280         PCI_SEG ( (pci)->busdevfn ), PCI_BUS ( (pci)->busdevfn ),       \
00281         PCI_SLOT ( (pci)->busdevfn ), PCI_FUNC ( (pci)->busdevfn )
00282 
00283 extern void adjust_pci_device ( struct pci_device *pci );
00284 extern unsigned long pci_bar_start ( struct pci_device *pci,
00285                                      unsigned int reg );
00286 extern int pci_read_config ( struct pci_device *pci );
00287 extern int pci_find_next ( struct pci_device *pci, unsigned int busdevfn );
00288 extern int pci_find_driver ( struct pci_device *pci );
00289 extern int pci_probe ( struct pci_device *pci );
00290 extern void pci_remove ( struct pci_device *pci );
00291 extern int pci_find_capability ( struct pci_device *pci, int capability );
00292 extern int pci_find_next_capability ( struct pci_device *pci,
00293                                       int pos, int capability );
00294 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
00295 
00296 /**
00297  * Initialise PCI device
00298  *
00299  * @v pci               PCI device
00300  * @v busdevfn          PCI bus:dev.fn address
00301  */
00302 static inline void pci_init ( struct pci_device *pci, unsigned int busdevfn ) {
00303         pci->busdevfn = busdevfn;
00304 }
00305 
00306 /**
00307  * Set PCI driver
00308  *
00309  * @v pci               PCI device
00310  * @v driver            PCI driver
00311  * @v id                PCI device ID
00312  */
00313 static inline void pci_set_driver ( struct pci_device *pci,
00314                                     struct pci_driver *driver,
00315                                     struct pci_device_id *id ) {
00316         pci->driver = driver;
00317         pci->id = id;
00318         pci->dev.driver_name = id->name;
00319 }
00320 
00321 /**
00322  * Set PCI driver-private data
00323  *
00324  * @v pci               PCI device
00325  * @v priv              Private data
00326  */
00327 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
00328         pci->priv = priv;
00329 }
00330 
00331 /**
00332  * Get PCI driver-private data
00333  *
00334  * @v pci               PCI device
00335  * @ret priv            Private data
00336  */
00337 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
00338         return pci->priv;
00339 }
00340 
00341 #endif  /* _IPXE_PCI_H */