iPXE
pciea.h
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00001 #ifndef _IPXE_PCIEA_H
00002 #define _IPXE_PCIEA_H
00003 
00004 /** @file
00005  *
00006  * PCI Enhanced Allocation
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <ipxe/pci.h>
00013 
00014 /** Number of entries */
00015 #define PCIEA_ENTRIES 2
00016 #define PCIEA_ENTRIES_MASK 0x3f
00017 
00018 /** First entry */
00019 #define PCIEA_FIRST 4
00020 
00021 /** Entry descriptor */
00022 #define PCIEA_DESC 0
00023 
00024 /** Entry size */
00025 #define PCIEA_DESC_SIZE(desc) ( ( (desc) >> 0 ) & 0x7 )
00026 
00027 /** BAR equivalent indicator */
00028 #define PCIEA_DESC_BEI(desc) ( ( (desc) >> 4 ) & 0xf )
00029 
00030 /** BAR equivalent indicators */
00031 enum pciea_bei {
00032         PCIEA_BEI_BAR_0 = 0,            /**< Standard BAR 0 */
00033         PCIEA_BEI_BAR_1 = 1,            /**< Standard BAR 1 */
00034         PCIEA_BEI_BAR_2 = 2,            /**< Standard BAR 2 */
00035         PCIEA_BEI_BAR_3 = 3,            /**< Standard BAR 3 */
00036         PCIEA_BEI_BAR_4 = 4,            /**< Standard BAR 4 */
00037         PCIEA_BEI_BAR_5 = 5,            /**< Standard BAR 5 */
00038         PCIEA_BEI_ROM = 8,              /**< Expansion ROM BAR */
00039         PCIEA_BEI_VF_BAR_0 = 9,         /**< Virtual function BAR 0 */
00040         PCIEA_BEI_VF_BAR_1 = 10,        /**< Virtual function BAR 1 */
00041         PCIEA_BEI_VF_BAR_2 = 11,        /**< Virtual function BAR 2 */
00042         PCIEA_BEI_VF_BAR_3 = 12,        /**< Virtual function BAR 3 */
00043         PCIEA_BEI_VF_BAR_4 = 13,        /**< Virtual function BAR 4 */
00044         PCIEA_BEI_VF_BAR_5 = 14,        /**< Virtual function BAR 5 */
00045 };
00046 
00047 /** Entry is enabled */
00048 #define PCIEA_DESC_ENABLED 0x80000000UL
00049 
00050 /** Base address low dword */
00051 #define PCIEA_LOW_BASE 4
00052 
00053 /** Limit low dword */
00054 #define PCIEA_LOW_LIMIT 8
00055 
00056 /** BAR is 64-bit */
00057 #define PCIEA_LOW_ATTR_64BIT 0x00000002UL
00058 
00059 /** Low dword attribute bit mask */
00060 #define PCIEA_LOW_ATTR_MASK 0x00000003UL
00061 
00062 /** Offset to high dwords */
00063 #define PCIEA_LOW_HIGH 8
00064 
00065 extern unsigned long pciea_bar_start ( struct pci_device *pci,
00066                                        unsigned int bei );
00067 extern unsigned long pciea_bar_size ( struct pci_device *pci,
00068                                       unsigned int bei );
00069 
00070 #endif /* _IPXE_PCIEA_H */