iPXE
Defines | Functions | Variables
tg3.c File Reference
#include <mii.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <byteswap.h>
#include <ipxe/pci.h>
#include <ipxe/iobuf.h>
#include <ipxe/timer.h>
#include <ipxe/malloc.h>
#include <ipxe/if_ether.h>
#include <ipxe/ethernet.h>
#include <ipxe/netdevice.h>
#include "tg3.h"

Go to the source code of this file.

Defines

#define TG3_DEF_RX_MODE   0
#define TG3_DEF_TX_MODE   0
#define TG3_TX_RING_BYTES
#define TG3_RX_RCB_RING_BYTES(tp)   (sizeof(struct tg3_rx_buffer_desc) * (TG3_RX_RET_MAX_SIZE_5705))
#define TG3_RX_STD_RING_BYTES(tp)   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)
#define TG3_RX_STD_BUFF_RING_BYTES(tp)   (sizeof(struct ring_info) * TG3_RX_STD_MAX_SIZE_5700)
#define TG3_RX_STD_RING_BYTES(tp)   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)
#define NEXT_TX(N)   (((N) + 1) & (TG3_TX_RING_SIZE - 1))
#define TG3_RX_STD_BUFF_RING_BYTES(tp)   (sizeof(struct ring_info) * TG3_RX_STD_MAX_SIZE_5700)
#define TG3_RX_STD_RING_BYTES(tp)   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)
#define TEST_BUFFER_SIZE   0x2000

Functions

 FILE_LICENCE (GPL2_ONLY)
static void tg3_refill_prod_ring (struct tg3 *tp)
void tg3_rx_prodring_fini (struct tg3_rx_prodring_set *tpr)
static void tg3_free_consistent (struct tg3 *tp)
int tg3_alloc_consistent (struct tg3 *tp)
static int tg3_rx_prodring_alloc (struct tg3 __unused *tp, struct tg3_rx_prodring_set *tpr)
static void tg3_rx_iob_free (struct io_buffer *iobs[], int i)
static void tg3_rx_prodring_free (struct tg3_rx_prodring_set *tpr)
int tg3_init_rings (struct tg3 *tp)
static int tg3_open (struct net_device *dev)
static u32 tg3_tx_avail (struct tg3 *tp)
static int tg3_transmit (struct net_device *dev, struct io_buffer *iob)
static void tg3_tx_complete (struct net_device *dev)
static int tg3_alloc_rx_iob (struct tg3_rx_prodring_set *tpr, u32 dest_idx_unmasked)
static void tg3_rx_complete (struct net_device *dev)
static void tg3_poll (struct net_device *dev)
static void tg3_close (struct net_device *dev)
static void tg3_irq (struct net_device *dev, int enable)
int tg3_do_test_dma (struct tg3 *tp, u32 __unused *buf, dma_addr_t buf_dma, int size, int to_device)
void tg3_read_mem (struct tg3 *tp, u32 off, u32 *val)
static int tg3_test_dma (struct tg3 *tp)
static int tg3_init_one (struct pci_device *pdev)
static void tg3_remove_one (struct pci_device *pci)

Variables

static struct net_device_operations tg3_netdev_ops
static struct pci_device_id tg3_nics []
struct pci_driver tg3_pci_driver __pci_driver

Define Documentation

#define TG3_DEF_RX_MODE   0

Definition at line 19 of file tg3.c.

Referenced by tg3_init_one().

#define TG3_DEF_TX_MODE   0

Definition at line 20 of file tg3.c.

Referenced by tg3_init_one().

Value:
(sizeof(struct tg3_tx_buffer_desc) * \
                                 TG3_TX_RING_SIZE)

Definition at line 31 of file tg3.c.

Referenced by tg3_alloc_consistent(), tg3_free_consistent(), and tg3_init_rings().

#define TG3_RX_RCB_RING_BYTES (   tp)    (sizeof(struct tg3_rx_buffer_desc) * (TG3_RX_RET_MAX_SIZE_5705))

Definition at line 35 of file tg3.c.

Referenced by tg3_alloc_consistent(), tg3_free_consistent(), and tg3_init_rings().

#define TG3_RX_STD_RING_BYTES (   tp)    (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)

Definition at line 354 of file tg3.c.

Referenced by tg3_alloc_consistent(), and tg3_rx_prodring_fini().

#define TG3_RX_STD_BUFF_RING_BYTES (   tp)    (sizeof(struct ring_info) * TG3_RX_STD_MAX_SIZE_5700)

Definition at line 352 of file tg3.c.

#define TG3_RX_STD_RING_BYTES (   tp)    (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)

Definition at line 354 of file tg3.c.

#define NEXT_TX (   N)    (((N) + 1) & (TG3_TX_RING_SIZE - 1))

Definition at line 294 of file tg3.c.

Referenced by tg3_transmit(), and tg3_tx_complete().

#define TG3_RX_STD_BUFF_RING_BYTES (   tp)    (sizeof(struct ring_info) * TG3_RX_STD_MAX_SIZE_5700)

Definition at line 352 of file tg3.c.

#define TG3_RX_STD_RING_BYTES (   tp)    (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)

Definition at line 354 of file tg3.c.

#define TEST_BUFFER_SIZE   0x2000

Definition at line 532 of file tg3.c.

Referenced by tg3_test_dma().


Function Documentation

FILE_LICENCE ( GPL2_ONLY  )
static void tg3_refill_prod_ring ( struct tg3 tp) [static]

Definition at line 400 of file tg3.c.

References DBGC, DBGC2, DBGCP, DBGP, tg3::dev, NULL, tg3::prodring, tg3_rx_prodring_set::rx_iobufs, tg3_rx_prodring_set::rx_std_iob_cnt, tg3_rx_prodring_set::rx_std_prod_idx, tg3_alloc_rx_iob(), TG3_DEF_RX_RING_PENDING, TG3_RX_STD_MAX_SIZE_5700, TG3_RX_STD_PROD_IDX_REG, and tw32_rx_mbox.

Referenced by tg3_open(), and tg3_rx_complete().

{       DBGP("%s\n", __func__);

        struct tg3_rx_prodring_set *tpr = &tp->prodring;
        int idx = tpr->rx_std_prod_idx;

        DBGCP(tp->dev, "%s\n", __func__);

        while (tpr->rx_std_iob_cnt < TG3_DEF_RX_RING_PENDING) {
                if (tpr->rx_iobufs[idx % TG3_DEF_RX_RING_PENDING] == NULL) {
                        if (tg3_alloc_rx_iob(tpr, idx) < 0) {
                                DBGC(tp->dev, "alloc_iob() failed for descriptor %d\n", idx);
                                break;
                        }
                        DBGC2(tp->dev, "allocated iob_buffer for descriptor %d\n", idx);
                }

                idx = (idx + 1) % TG3_RX_STD_MAX_SIZE_5700;
                tpr->rx_std_iob_cnt++;
        }

        if ((u32)idx != tpr->rx_std_prod_idx) {
                tpr->rx_std_prod_idx = idx;
                tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
        }
}
void tg3_rx_prodring_fini ( struct tg3_rx_prodring_set tpr)

Definition at line 41 of file tg3.c.

References DBGP, free_dma(), NULL, tg3_rx_prodring_set::rx_std, TG3_RX_STD_RING_BYTES, and tp.

Referenced by tg3_free_consistent().

{       DBGP("%s\n", __func__);

        if (tpr->rx_std) {
                free_dma(tpr->rx_std, TG3_RX_STD_RING_BYTES(tp));
                tpr->rx_std = NULL;
        }
}
static void tg3_free_consistent ( struct tg3 tp) [static]
int tg3_alloc_consistent ( struct tg3 tp)

Definition at line 84 of file tg3.c.

References DBGC, DBGP, tg3::dev, ENOMEM, tg3::hw_status, tg3_hw_status::idx, malloc_dma(), memset(), tg3::prodring, tg3_hw_status::rx_producer, tg3::rx_rcb, tg3::rx_rcb_mapping, tg3::rx_rcb_prod_idx, tg3_rx_prodring_set::rx_std, tg3_rx_prodring_set::rx_std_mapping, tg3::status_mapping, TG3_DMA_ALIGNMENT, tg3_free_consistent(), TG3_HW_STATUS_SIZE, TG3_RX_RCB_RING_BYTES, TG3_RX_STD_RING_BYTES, TG3_TX_RING_BYTES, TG3_TX_RING_SIZE, tg3::tx_buffers, tg3::tx_desc_mapping, tg3::tx_ring, virt_to_bus(), and zalloc().

Referenced by tg3_open().

{       DBGP("%s\n", __func__);

        struct tg3_hw_status *sblk;
        struct tg3_rx_prodring_set *tpr = &tp->prodring;

        tp->hw_status = malloc_dma(TG3_HW_STATUS_SIZE, TG3_DMA_ALIGNMENT);
        if (!tp->hw_status) {
                DBGC(tp->dev, "hw_status alloc failed\n");
                goto err_out;
        }
        tp->status_mapping = virt_to_bus(tp->hw_status);

        memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
        sblk = tp->hw_status;

        tpr->rx_std = malloc_dma(TG3_RX_STD_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
        if (!tpr->rx_std) {
                DBGC(tp->dev, "rx prodring alloc failed\n");
                goto err_out;
        }
        tpr->rx_std_mapping = virt_to_bus(tpr->rx_std);
        memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));

        tp->tx_buffers = zalloc(sizeof(struct ring_info) * TG3_TX_RING_SIZE);
        if (!tp->tx_buffers)
                goto err_out;

        tp->tx_ring = malloc_dma(TG3_TX_RING_BYTES, TG3_DMA_ALIGNMENT);
        if (!tp->tx_ring)
                goto err_out;
        tp->tx_desc_mapping = virt_to_bus(tp->tx_ring);

        /*
         * When RSS is enabled, the status block format changes
         * slightly.  The "rx_jumbo_consumer", "reserved",
         * and "rx_mini_consumer" members get mapped to the
         * other three rx return ring producer indexes.
         */

        tp->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;

        tp->rx_rcb = malloc_dma(TG3_RX_RCB_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
        if (!tp->rx_rcb)
                goto err_out;
        tp->rx_rcb_mapping = virt_to_bus(tp->rx_rcb);

        memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));

        return 0;

err_out:
        tg3_free_consistent(tp);
        return -ENOMEM;
}
static int tg3_rx_prodring_alloc ( struct tg3 __unused tp,
struct tg3_rx_prodring_set tpr 
) [static]

Definition at line 151 of file tg3.c.

References DBGP, tg3_rx_buffer_desc::idx_len, tg3_rx_buffer_desc::opaque, tg3_rx_prodring_set::rx_std, tg3_rx_prodring_set::rx_std_cons_idx, tg3_rx_prodring_set::rx_std_prod_idx, rxd, RXD_FLAG_END, RXD_FLAGS_SHIFT, RXD_LEN_SHIFT, RXD_OPAQUE_INDEX_SHIFT, RXD_OPAQUE_RING_STD, TG3_RX_STD_DMA_SZ, TG3_RX_STD_MAX_SIZE_5700, and tg3_rx_buffer_desc::type_flags.

Referenced by tg3_init_rings().

{       DBGP("%s\n", __func__);

        u32 i;

        tpr->rx_std_cons_idx = 0;
        tpr->rx_std_prod_idx = 0;

        /* Initialize invariants of the rings, we only set this
         * stuff once.  This works because the card does not
         * write into the rx buffer posting rings.
         */
        /* FIXME: does TG3_RX_STD_MAX_SIZE_5700 work on all cards? */
        for (i = 0; i < TG3_RX_STD_MAX_SIZE_5700; i++) {
                struct tg3_rx_buffer_desc *rxd;

                rxd = &tpr->rx_std[i];
                rxd->idx_len = (TG3_RX_STD_DMA_SZ - 64 - 2) << RXD_LEN_SHIFT;
                rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
                rxd->opaque = (RXD_OPAQUE_RING_STD |
                               (i << RXD_OPAQUE_INDEX_SHIFT));
        }

        return 0;
}
static void tg3_rx_iob_free ( struct io_buffer iobs[],
int  i 
) [static]

Definition at line 178 of file tg3.c.

References DBGP, free_iob(), and NULL.

Referenced by tg3_rx_prodring_free().

{       DBGP("%s\n", __func__);

        if (iobs[i] == NULL)
                return;

        free_iob(iobs[i]);
        iobs[i] = NULL;
}
static void tg3_rx_prodring_free ( struct tg3_rx_prodring_set tpr) [static]

Definition at line 188 of file tg3.c.

References DBGP, tg3_rx_prodring_set::rx_iobufs, TG3_DEF_RX_RING_PENDING, and tg3_rx_iob_free().

Referenced by tg3_close(), and tg3_init_rings().

{       DBGP("%s\n", __func__);

        unsigned int i;

        for (i = 0; i < TG3_DEF_RX_RING_PENDING; i++)
                tg3_rx_iob_free(tpr->rx_iobufs, i);
}
int tg3_init_rings ( struct tg3 tp)

tg3_free_rings(tp);

Definition at line 203 of file tg3.c.

References DBGC, DBGP, tg3::dev, ENOMEM, tg3::hw_status, tg3::last_irq_tag, tg3::last_tag, memset(), tg3::prodring, tg3::rx_rcb, tg3::rx_rcb_ptr, tg3_hw_status::status, tg3_hw_status::status_tag, TG3_HW_STATUS_SIZE, tg3_rx_prodring_alloc(), tg3_rx_prodring_free(), TG3_RX_RCB_RING_BYTES, TG3_TX_RING_BYTES, tg3::tx_cons, tg3::tx_prod, and tg3::tx_ring.

Referenced by tg3_reset_hw().

{       DBGP("%s\n", __func__);

        /* Free up all the SKBs. */
///     tg3_free_rings(tp);

        tp->last_tag = 0;
        tp->last_irq_tag = 0;
        tp->hw_status->status = 0;
        tp->hw_status->status_tag = 0;
        memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);

        tp->tx_prod = 0;
        tp->tx_cons = 0;
        if (tp->tx_ring)
                memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);

        tp->rx_rcb_ptr = 0;
        if (tp->rx_rcb)
                memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));

        if (tg3_rx_prodring_alloc(tp, &tp->prodring)) {
                DBGC(tp->dev, "tg3_rx_prodring_alloc() failed\n");
                tg3_rx_prodring_free(&tp->prodring);
                return -ENOMEM;
        }

        return 0;
}
static int tg3_open ( struct net_device dev) [static]

Definition at line 233 of file tg3.c.

References __tg3_set_mac_addr(), DBGC, DBGP, tg3::dev, netdev_priv(), tg3::prodring, tg3_rx_prodring_set::rx_std_iob_cnt, strerror(), tg3_alloc_consistent(), tg3_init_hw(), tg3_refill_prod_ring(), tg3_set_power_state_0(), and tp.

{       DBGP("%s\n", __func__);

        struct tg3 *tp = netdev_priv(dev);
        struct tg3_rx_prodring_set *tpr = &tp->prodring;
        int err = 0;

        tg3_set_power_state_0(tp);

        /* Initialize MAC address and backoff seed. */
        __tg3_set_mac_addr(tp, 0);

        err = tg3_alloc_consistent(tp);
        if (err)
                return err;

        tpr->rx_std_iob_cnt = 0;

        err = tg3_init_hw(tp, 1);
        if (err != 0)
                DBGC(tp->dev, "tg3_init_hw failed: %s\n", strerror(err));
        else
                tg3_refill_prod_ring(tp);

        return err;
}
static u32 tg3_tx_avail ( struct tg3 tp) [inline, static]

Definition at line 260 of file tg3.c.

References barrier, DBGP, TG3_DEF_TX_RING_PENDING, TG3_TX_RING_SIZE, tg3::tx_cons, and tg3::tx_prod.

Referenced by tg3_transmit().

{       DBGP("%s\n", __func__);

        /* Tell compiler to fetch tx indices from memory. */
        barrier();
        return TG3_DEF_TX_RING_PENDING -
               ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1));
}
static int tg3_transmit ( struct net_device dev,
struct io_buffer iob 
) [static]

Definition at line 299 of file tg3.c.

References io_buffer::data, DBGC, DBGP, ENOBUFS, entry, ETH_ZLEN, ring_info::iob, iob_len(), iob_pad(), len, mb(), netdev_priv(), NEXT_TX, tg3::prodmbox, tg3_set_txd(), tg3_tx_avail(), tw32_tx_mbox, tg3::tx_buffers, tg3::tx_prod, TXD_FLAG_END, and virt_to_bus().

{       DBGP("%s\n", __func__);

        struct tg3 *tp = netdev_priv(dev);
        u32 len, entry;
        dma_addr_t mapping;

        if (tg3_tx_avail(tp) < 1) {
                DBGC(dev, "Transmit ring full\n");
                return -ENOBUFS;
        }

        entry = tp->tx_prod;

        iob_pad(iob, ETH_ZLEN);
        mapping = virt_to_bus(iob->data);
        len = iob_len(iob);

        tp->tx_buffers[entry].iob = iob;

        tg3_set_txd(tp, entry, mapping, len, TXD_FLAG_END);

        entry = NEXT_TX(entry);

        /* Packets are ready, update Tx producer idx local and on card. */
        tw32_tx_mbox(tp->prodmbox, entry);

        tp->tx_prod = entry;

        mb();

        return 0;
}
static void tg3_tx_complete ( struct net_device dev) [static]

Definition at line 333 of file tg3.c.

References DBGC2, DBGP, tg3::hw_status, tg3_hw_status::idx, ring_info::iob, iob_len(), netdev_priv(), netdev_tx_complete(), NEXT_TX, tg3::tx_buffers, tg3::tx_cons, and tg3_hw_status::tx_consumer.

Referenced by tg3_poll().

{       DBGP("%s\n", __func__);

        struct tg3 *tp = netdev_priv(dev);
        u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
        u32 sw_idx = tp->tx_cons;

        while (sw_idx != hw_idx) {
                struct io_buffer *iob = tp->tx_buffers[sw_idx].iob;

                DBGC2(dev, "Transmitted packet: %zd bytes\n", iob_len(iob));

                netdev_tx_complete(dev, iob);
                sw_idx = NEXT_TX(sw_idx);
        }

        tp->tx_cons = sw_idx;
}
static int tg3_alloc_rx_iob ( struct tg3_rx_prodring_set tpr,
u32  dest_idx_unmasked 
) [static]

Definition at line 368 of file tg3.c.

References alloc_iob(), io_buffer::data, DBGP, ENOMEM, NULL, tg3_rx_prodring_set::rx_iobufs, tg3_rx_prodring_set::rx_std, TG3_DEF_RX_RING_PENDING, TG3_RX_STD_DMA_SZ, TG3_RX_STD_MAX_SIZE_5700, and virt_to_bus().

Referenced by tg3_refill_prod_ring().

{       DBGP("%s\n", __func__);

        struct tg3_rx_buffer_desc *desc;
        struct io_buffer *iob;
        dma_addr_t mapping;
        int dest_idx, iob_idx;

        dest_idx = dest_idx_unmasked & (TG3_RX_STD_MAX_SIZE_5700 - 1);
        desc = &tpr->rx_std[dest_idx];

        /* Do not overwrite any of the map or rp information
         * until we are sure we can commit to a new buffer.
         *
         * Callers depend upon this behavior and assume that
         * we leave everything unchanged if we fail.
         */
        iob = alloc_iob(TG3_RX_STD_DMA_SZ);
        if (iob == NULL)
                return -ENOMEM;

        iob_idx = dest_idx % TG3_DEF_RX_RING_PENDING;
        tpr->rx_iobufs[iob_idx] = iob;

        mapping = virt_to_bus(iob->data);

        desc->addr_hi = ((u64)mapping >> 32);
        desc->addr_lo = ((u64)mapping & 0xffffffff);

        return 0;
}
static void tg3_rx_complete ( struct net_device dev) [static]

Definition at line 427 of file tg3.c.

References assert, tg3::consmbox, DBGC, DBGC2, DBGP, EINVAL, tg3_rx_buffer_desc::err_vlan, ETH_FCS_LEN, tg3_rx_buffer_desc::idx_len, iob_put, len, netdev_priv(), netdev_rx(), netdev_rx_err(), NULL, tg3_rx_buffer_desc::opaque, tg3::prodring, tg3_rx_prodring_set::rx_iobufs, tg3::rx_rcb, tg3::rx_rcb_prod_idx, tg3::rx_rcb_ptr, tg3_rx_prodring_set::rx_std_iob_cnt, RXD_ERR_MASK, RXD_ERR_ODD_NIBBLE_RCVD_MII, RXD_LEN_MASK, RXD_LEN_SHIFT, RXD_OPAQUE_INDEX_MASK, TG3_DEF_RX_RING_PENDING, tg3_refill_prod_ring(), TG3_RX_RET_MAX_SIZE_5705, and tw32_rx_mbox.

Referenced by tg3_poll().

{       DBGP("%s\n", __func__);

        struct tg3 *tp = netdev_priv(dev);

        u32 sw_idx = tp->rx_rcb_ptr;
        u16 hw_idx;
        struct tg3_rx_prodring_set *tpr = &tp->prodring;

        hw_idx = *(tp->rx_rcb_prod_idx);

        while (sw_idx != hw_idx) {
                struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
                u32 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
                int iob_idx = desc_idx % TG3_DEF_RX_RING_PENDING;
                struct io_buffer *iob = tpr->rx_iobufs[iob_idx];
                unsigned int len;

                DBGC2(dev, "RX - desc_idx: %d sw_idx: %d hw_idx: %d\n", desc_idx, sw_idx, hw_idx);

                assert(iob != NULL);

                if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
                    (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
                        /* drop packet */
                        DBGC(dev, "Corrupted packet received\n");
                        netdev_rx_err(dev, iob, -EINVAL);
                } else {
                        len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
                                ETH_FCS_LEN;
                        iob_put(iob, len);
                        netdev_rx(dev, iob);

                        DBGC2(dev, "Received packet: %d bytes %d %d\n", len, sw_idx, hw_idx);
                }

                sw_idx++;
                sw_idx &= TG3_RX_RET_MAX_SIZE_5705 - 1;

                tpr->rx_iobufs[iob_idx] = NULL;
                tpr->rx_std_iob_cnt--;
        }

        if (tp->rx_rcb_ptr != sw_idx) {
                tw32_rx_mbox(tp->consmbox, sw_idx);
                tp->rx_rcb_ptr = sw_idx;
        }

        tg3_refill_prod_ring(tp);
}
static void tg3_poll ( struct net_device dev) [static]

Definition at line 478 of file tg3.c.

References DBGP, tg3::hw_status, mb(), netdev_priv(), SD_STATUS_UPDATED, tg3_hw_status::status, tg3_poll_link(), tg3_rx_complete(), and tg3_tx_complete().

{       DBGP("%s\n", __func__);

        struct tg3 *tp = netdev_priv(dev);

        /* ACK interrupts */
        /*
         *tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00);
         */
        tp->hw_status->status &= ~SD_STATUS_UPDATED;

        mb();

        tg3_poll_link(tp);
        tg3_tx_complete(dev);
        tg3_rx_complete(dev);
}
static void tg3_close ( struct net_device dev) [static]

Definition at line 496 of file tg3.c.

References DBGP, netdev_priv(), tg3::prodring, tg3_flag_clear, tg3_free_consistent(), tg3_halt(), and tg3_rx_prodring_free().

{       DBGP("%s\n", __func__);

        struct tg3 *tp = netdev_priv(dev);

        DBGP("%s\n", __func__);

        tg3_halt(tp);
        tg3_rx_prodring_free(&tp->prodring);
        tg3_flag_clear(tp, INIT_COMPLETE);

        tg3_free_consistent(tp);

}
static void tg3_irq ( struct net_device dev,
int  enable 
) [static]

Definition at line 511 of file tg3.c.

References DBGP, netdev_priv(), tg3_disable_ints(), and tg3_enable_ints().

{       DBGP("%s\n", __func__);

        struct tg3 *tp = netdev_priv(dev);

        DBGP("%s: %d\n", __func__, enable);

        if (enable)
                tg3_enable_ints(tp);
        else
                tg3_disable_ints(tp);
}
int tg3_do_test_dma ( struct tg3 tp,
u32 __unused buf,
dma_addr_t  buf_dma,
int  size,
int  to_device 
)

Definition at line 2594 of file tg3_hw.c.

References tg3_internal_buffer_desc::addr_hi, tg3_internal_buffer_desc::addr_lo, BUFMGR_MODE, tg3_internal_buffer_desc::cqid_sqid, DBGP, ENODEV, tg3_internal_buffer_desc::flags, FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, FTQ_RCVBD_COMP_FIFO_ENQDEQ, FTQ_RCVDATA_COMP_FIFO_ENQDEQ, FTQ_RESET, tg3_internal_buffer_desc::len, tg3_internal_buffer_desc::nic_mbuf, NIC_SRAM_DMA_DESC_POOL_BASE, pci_write_config_dword(), tg3::pdev, RDMAC_MODE, RDMAC_MODE_ENABLE, RDMAC_STATUS, ret, size, TG3PCI_MEM_WIN_BASE_ADDR, TG3PCI_MEM_WIN_DATA, tr32, tw32, tw32_f, udelay(), val, WDMAC_MODE, WDMAC_MODE_ENABLE, and WDMAC_STATUS.

Referenced by tg3_test_dma().

{       DBGP("%s\n", __func__);

        struct tg3_internal_buffer_desc test_desc;
        u32 sram_dma_descs;
        int ret;
        unsigned int i;

        sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;

        tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
        tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
        tw32(RDMAC_STATUS, 0);
        tw32(WDMAC_STATUS, 0);

        tw32(BUFMGR_MODE, 0);
        tw32(FTQ_RESET, 0);

        test_desc.addr_hi = ((u64) buf_dma) >> 32;
        test_desc.addr_lo = buf_dma & 0xffffffff;
        test_desc.nic_mbuf = 0x00002100;
        test_desc.len = size;

        /*
         * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
         * the *second* time the tg3 driver was getting loaded after an
         * initial scan.
         *
         * Broadcom tells me:
         *   ...the DMA engine is connected to the GRC block and a DMA
         *   reset may affect the GRC block in some unpredictable way...
         *   The behavior of resets to individual blocks has not been tested.
         *
         * Broadcom noted the GRC reset will also reset all sub-components.
         */
        if (to_device) {
                test_desc.cqid_sqid = (13 << 8) | 2;

                tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
                udelay(40);
        } else {
                test_desc.cqid_sqid = (16 << 8) | 7;

                tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
                udelay(40);
        }
        test_desc.flags = 0x00000005;

        for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
                u32 val;

                val = *(((u32 *)&test_desc) + i);
                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
                                       sram_dma_descs + (i * sizeof(u32)));
                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
        }
        pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);

        if (to_device)
                tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
        else
                tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);

        ret = -ENODEV;
        for (i = 0; i < 40; i++) {
                u32 val;

                if (to_device)
                        val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
                else
                        val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
                if ((val & 0xffff) == sram_dma_descs) {
                        ret = 0;
                        break;
                }

                udelay(100);
        }

        return ret;
}
void tg3_read_mem ( struct tg3 tp,
u32  off,
u32 val 
)
static int tg3_test_dma ( struct tg3 tp) [static]

Definition at line 537 of file tg3.c.

References ASIC_REV_5700, ASIC_REV_5701, ASIC_REV_5703, ASIC_REV_5704, ASIC_REV_5705, ASIC_REV_5714, ASIC_REV_5750, ASIC_REV_5780, DBGC, DBGC2, DBGP, pci_device::dev, tg3::dev, tg3::dma_rwctrl, DMA_RWCTRL_ASSERT_ALL_BE, DMA_RWCTRL_DIS_CACHE_ALIGNMENT, DMA_RWCTRL_ONE_DMA, DMA_RWCTRL_PCI_READ_CMD_SHIFT, DMA_RWCTRL_PCI_WRITE_CMD_SHIFT, DMA_RWCTRL_READ_WATER_SHIFT, DMA_RWCTRL_USE_MEM_READ_MULT, DMA_RWCTRL_WRITE_BNDRY_16, DMA_RWCTRL_WRITE_BNDRY_MASK, DMA_RWCTRL_WRITE_WATER_SHIFT, ENODEV, ENOMEM, free_dma(), GET_ASIC_REV, le32_to_cpu, malloc_dma(), out, tg3::pci_chip_rev_id, tg3::pdev, ret, TEST_BUFFER_SIZE, TG3_DMA_ALIGNMENT, tg3_do_test_dma(), tg3_flag, tg3_read_mem(), tg3_switch_clocks(), TG3PCI_CLOCK_CTRL, TG3PCI_DMA_RW_CTRL, tr32, tw32, val, and virt_to_bus().

Referenced by tg3_init_one().

{       DBGP("%s\n", __func__);

        dma_addr_t buf_dma;
        u32 *buf;
        int ret = 0;

        buf = malloc_dma(TEST_BUFFER_SIZE, TG3_DMA_ALIGNMENT);
        if (!buf) {
                ret = -ENOMEM;
                goto out_nofree;
        }
        buf_dma = virt_to_bus(buf);
        DBGC2(tp->dev, "dma test buffer, virt: %p phys: %#016lx\n", buf, buf_dma);

        if (tg3_flag(tp, 57765_PLUS)) {
                tp->dma_rwctrl = DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
                goto out;
        }

        tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));

        if (tg3_flag(tp, PCI_EXPRESS)) {
                /* DMA read watermark not used on PCIE */
                tp->dma_rwctrl |= 0x00180000;
        } else if (!tg3_flag(tp, PCIX_MODE)) {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
                        tp->dma_rwctrl |= 0x003f0000;
                else
                        tp->dma_rwctrl |= 0x003f000f;
        } else {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
                        u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
                        u32 read_water = 0x7;

                        if (ccval == 0x6 || ccval == 0x7)
                                tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;

                        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
                                read_water = 4;
                        /* Set bit 23 to enable PCIX hw bug fix */
                        tp->dma_rwctrl |=
                                (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
                                (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
                                (1 << 23);
                } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
                        /* 5780 always in PCIX mode */
                        tp->dma_rwctrl |= 0x00144000;
                } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
                        /* 5714 always in PCIX mode */
                        tp->dma_rwctrl |= 0x00148000;
                } else {
                        tp->dma_rwctrl |= 0x001b000f;
                }
        }

        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
                tp->dma_rwctrl &= 0xfffffff0;

        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
                /* Remove this if it causes problems for some boards. */
                tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;

                /* On 5700/5701 chips, we need to set this bit.
                 * Otherwise the chip will issue cacheline transactions
                 * to streamable DMA memory with not all the byte
                 * enables turned on.  This is an error on several
                 * RISC PCI controllers, in particular sparc64.
                 *
                 * On 5703/5704 chips, this bit has been reassigned
                 * a different meaning.  In particular, it is used
                 * on those chips to enable a PCI-X workaround.
                 */
                tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
        }

        tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);

#if 0
        /* Unneeded, already done by tg3_get_invariants.  */
        tg3_switch_clocks(tp);
#endif

        if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
                goto out;

        /* It is best to perform DMA test with maximum write burst size
         * to expose the 5700/5701 write DMA bug.
         */
        tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
        tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);

        while (1) {
                u32 *p = buf, i;

                for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
                        p[i] = i;

                /* Send the buffer to the chip. */
                ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
                if (ret) {
                        DBGC(&tp->pdev->dev,
                                "%s: Buffer write failed. err = %d\n",
                                __func__, ret);
                        break;
                }

                /* validate data reached card RAM correctly. */
                for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
                        u32 val;
                        tg3_read_mem(tp, 0x2100 + (i*4), &val);
                        if (le32_to_cpu(val) != p[i]) {
                                DBGC(&tp->pdev->dev,
                                        "%s: Buffer corrupted on device! "
                                        "(%d != %d)\n", __func__, val, i);
                                /* ret = -ENODEV here? */
                        }
                        p[i] = 0;
                }

                /* Now read it back. */
                ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
                if (ret) {
                        DBGC(&tp->pdev->dev, "%s: Buffer read failed. "
                                "err = %d\n", __func__, ret);
                        break;
                }

                /* Verify it. */
                for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
                        if (p[i] == i)
                                continue;

                        if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
                            DMA_RWCTRL_WRITE_BNDRY_16) {
                                tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                                tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
                                tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
                                break;
                        } else {
                                DBGC(&tp->pdev->dev,
                                        "%s: Buffer corrupted on read back! "
                                        "(%d != %d)\n", __func__, p[i], i);
                                ret = -ENODEV;
                                goto out;
                        }
                }

                if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
                        /* Success. */
                        ret = 0;
                        break;
                }
        }

        if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
            DMA_RWCTRL_WRITE_BNDRY_16) {
                /* DMA test passed without adjusting DMA boundary,
                 * now look for chipsets that are known to expose the
                 * DMA bug without failing the test.
                 */
                tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;

                tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
        }

out:
        free_dma(buf, TEST_BUFFER_SIZE);
out_nofree:
        return ret;
}
static int tg3_init_one ( struct pci_device pdev) [static]

Definition at line 716 of file tg3.c.

References adjust_pci_device(), alloc_etherdev(), tg3::coal_now, tg3::consmbox, DBGC, DBGP, pci_device::dev, net_device::dev, tg3::dev, ENOENT, ENOMEM, errno, tg3::grc_mode, GRC_MODE_BSWAP_DATA, GRC_MODE_BSWAP_NONFRM_DATA, GRC_MODE_WSWAP_DATA, GRC_MODE_WSWAP_NONFRM_DATA, HOSTCC_MODE, HOSTCC_MODE_ENABLE, HOSTCC_MODE_NOW, tg3::int_mbox, ioremap(), iounmap(), MAILBOX_INTERRUPT_0, MAILBOX_RCVRET_CON_IDX_0, MAILBOX_SNDHOST_PROD_IDX_0, MEMARB_MODE, MEMARB_MODE_ENABLE, tg3::misc_host_ctrl, MISC_HOST_CTRL_INDIR_ACCESS, MISC_HOST_CTRL_MASK_PCI_INT, MISC_HOST_CTRL_PCISTATE_RW, MISC_HOST_CTRL_WORD_SWAP, netdev_init(), netdev_priv(), netdev_put(), NULL, pci_bar_size(), pci_bar_start(), PCI_BASE_ADDRESS_0, pci_read_config_word(), pci_set_drvdata(), PCI_SUBSYSTEM_ID, PCI_SUBSYSTEM_VENDOR_ID, tg3::pdev, tg3::prodmbox, register_netdev(), tg3::regs, tg3::rx_mode, tg3::subsystem_device, tg3::subsystem_vendor, TG3_64BIT_REG_LOW, TG3_DEF_RX_MODE, TG3_DEF_TX_MODE, tg3_get_device_address(), tg3_get_invariants(), tg3_halt(), tg3_init_bufmgr_config(), tg3_setup_phy(), tg3_test_dma(), tp, tr32, tw32, tg3::tx_mode, WDMAC_MODE, and WDMAC_MODE_ENABLE.

{       DBGP("%s\n", __func__);

        struct net_device *dev;
        struct tg3 *tp;
        int err = 0;
        unsigned long reg_base, reg_size;

        adjust_pci_device(pdev);

        dev = alloc_etherdev(sizeof(*tp));
        if (!dev) {
                DBGC(&pdev->dev, "Failed to allocate etherdev\n");
                err = -ENOMEM;
                goto err_out_disable_pdev;
        }

        netdev_init(dev, &tg3_netdev_ops);
        pci_set_drvdata(pdev, dev);

        dev->dev = &pdev->dev;

        tp = netdev_priv(dev);
        tp->pdev = pdev;
        tp->dev = dev;
        tp->rx_mode = TG3_DEF_RX_MODE;
        tp->tx_mode = TG3_DEF_TX_MODE;

        /* Subsystem IDs are required later */
        pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
        pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);

        /* The word/byte swap controls here control register access byte
         * swapping.  DMA data byte swapping is controlled in the GRC_MODE
         * setting below.
         */
        tp->misc_host_ctrl =
                MISC_HOST_CTRL_MASK_PCI_INT |
                MISC_HOST_CTRL_WORD_SWAP |
                MISC_HOST_CTRL_INDIR_ACCESS |
                MISC_HOST_CTRL_PCISTATE_RW;

        /* The NONFRM (non-frame) byte/word swap controls take effect
         * on descriptor entries, anything which isn't packet data.
         *
         * The StrongARM chips on the board (one for tx, one for rx)
         * are running in big-endian mode.
         */
        tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
                        GRC_MODE_WSWAP_NONFRM_DATA);
#if __BYTE_ORDER == __BIG_ENDIAN
        tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
#endif

        /* FIXME: how can we detect errors here? */
        reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
        reg_size = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);

        tp->regs = ioremap(reg_base, reg_size);
        if (!tp->regs) {
                DBGC(&pdev->dev, "Failed to remap device registers\n");
                errno = -ENOENT;
                goto err_out_disable_pdev;
        }

        err = tg3_get_invariants(tp);
        if (err) {
                DBGC(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
                goto err_out_iounmap;
        }

        tg3_init_bufmgr_config(tp);

        err = tg3_get_device_address(tp);
        if (err) {
                DBGC(&pdev->dev, "Could not obtain valid ethernet address, aborting\n");
                goto err_out_iounmap;
        }

        /*
         * Reset chip in case UNDI or EFI driver did not shutdown
         * DMA self test will enable WDMAC and we'll see (spurious)
         * pending DMA on the PCI bus at that point.
         */
        if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
            (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
                tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
                tg3_halt(tp);
        }

        err = tg3_test_dma(tp);
        if (err) {
                DBGC(&pdev->dev, "DMA engine test failed, aborting\n");
                goto err_out_iounmap;
        }

        tp->int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
        tp->consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
        tp->prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;

        tp->coal_now = HOSTCC_MODE_NOW;

        err = register_netdev(dev);
        if (err) {
                DBGC(&pdev->dev, "Cannot register net device, aborting\n");
                goto err_out_iounmap;
        }

        /* Call tg3_setup_phy() to start autoneg process, which saves time
         * over starting autoneg in tg3_open();
         */
        err = tg3_setup_phy(tp, 0);
        if (err) {
                DBGC(tp->dev, "tg3_setup_phy() call failed in %s\n", __func__);
                goto err_out_iounmap;
        }

        return 0;

err_out_iounmap:
        if (tp->regs) {
                iounmap(tp->regs);
                tp->regs = NULL;
        }

        netdev_put(dev);

err_out_disable_pdev:
        pci_set_drvdata(pdev, NULL);
        return err;
}
static void tg3_remove_one ( struct pci_device pci) [static]

Definition at line 848 of file tg3.c.

References DBGP, netdev, netdev_nullify(), netdev_put(), pci_get_drvdata(), and unregister_netdev().

{       DBGP("%s\n", __func__);

        struct net_device *netdev = pci_get_drvdata(pci);

        unregister_netdev(netdev);
        netdev_nullify(netdev);
        netdev_put(netdev);
}

Variable Documentation

Initial value:
 {
        .open = tg3_open,
        .close = tg3_close,
        .poll = tg3_poll,
        .transmit = tg3_transmit,
        .irq = tg3_irq,
}

Definition at line 524 of file tg3.c.

struct pci_device_id tg3_nics[] [static]

Definition at line 858 of file tg3.c.

struct pci_driver tg3_pci_driver __pci_driver
Initial value:
 {
        .ids = tg3_nics,
        .id_count = ARRAY_SIZE(tg3_nics),
        .probe = tg3_init_one,
        .remove = tg3_remove_one,
}

Definition at line 943 of file tg3.c.