iPXE
tg3.h
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00001 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
00002  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
00003  *
00004  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
00005  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
00006  * Copyright (C) 2004 Sun Microsystems Inc.
00007  * Copyright (C) 2007-2011 Broadcom Corporation.
00008  */
00009 
00010 #ifndef _T3_H
00011 #define _T3_H
00012 
00013 #undef ERRFILE
00014 #define ERRFILE ERRFILE_tg3
00015 
00016 /* From linux/include/linux/pci_regs.h: */
00017 #define PCI_EXP_LNKCTL          16      /* Link Control */
00018 #define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
00019 #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
00020 
00021 #define  PCI_X_CMD_READ_2K      0x0008  /* 2Kbyte maximum read byte count */
00022 #define  PCI_X_CMD_MAX_READ     0x000c  /* Max Memory Read Byte Count */
00023 
00024 #define  PCI_X_CMD_MAX_SPLIT    0x0070  /* Max Outstanding Split Transactions */
00025 /* </pci_regs.h> */
00026 
00027 /* ethtool.h: */
00028 #define ADVERTISED_10baseT_Half         (1 << 0)
00029 #define ADVERTISED_10baseT_Full         (1 << 1)
00030 #define ADVERTISED_100baseT_Half        (1 << 2)
00031 #define ADVERTISED_100baseT_Full        (1 << 3)
00032 #define ADVERTISED_1000baseT_Half       (1 << 4)
00033 #define ADVERTISED_1000baseT_Full       (1 << 5)
00034 #define ADVERTISED_Autoneg              (1 << 6)
00035 /* </ethtool.h> */
00036 
00037 #ifndef ADVERTISED_Pause
00038 #define ADVERTISED_Pause                (1 << 13)
00039 #endif
00040 #ifndef ADVERTISED_Asym_Pause
00041 #define ADVERTISED_Asym_Pause           (1 << 14)
00042 #endif
00043 
00044 /* mdio.h: */
00045 #define MDIO_AN_EEE_ADV         60      /* EEE advertisement */
00046 
00047 #define MDIO_MMD_AN             7       /* Auto-Negotiation */
00048 
00049 #define MDIO_AN_EEE_ADV_100TX           0x0002  /* Advertise 100TX EEE cap */
00050 #define MDIO_AN_EEE_ADV_1000T           0x0004  /* Advertise 1000T EEE cap */
00051 /* </mdio.h> */
00052 
00053 /* mii.h */
00054 #define FLOW_CTRL_TX            0x01
00055 #define FLOW_CTRL_RX            0x02
00056 /* </mii.h> */
00057 
00058 /* pci_regs.h */
00059 #define PCI_X_CMD                       2       /* Modes & Features */
00060 #define PCI_X_CMD_ERO                   0x0002  /* Enable Relaxed Ordering */
00061 
00062 #define PCI_EXP_DEVCTL_RELAX_EN         0x0010 /* Enable relaxed ordering */
00063 #define PCI_EXP_DEVCTL_NOSNOOP_EN       0x0800  /* Enable No Snoop */
00064 #define PCI_EXP_DEVCTL_PAYLOAD          0x00e0  /* Max_Payload_Size */
00065 #define PCI_EXP_DEVSTA                  10      /* Device Status */
00066 #define PCI_EXP_DEVSTA_CED              0x01    /* Correctable Error Detected */
00067 #define PCI_EXP_DEVSTA_NFED             0x02    /* Non-Fatal Error Detected */
00068 #define PCI_EXP_DEVSTA_FED              0x04    /* Fatal Error Detected */
00069 #define PCI_EXP_DEVSTA_URD              0x08    /* Unsupported Request Detected */
00070 /* </pci_regs.h> */
00071 
00072 /* pci_ids.h: */
00073 #define PCI_VENDOR_ID_BROADCOM          0x14e4
00074 #define PCI_DEVICE_ID_TIGON3_5752       0x1600
00075 #define PCI_DEVICE_ID_TIGON3_5752M      0x1601
00076 #define PCI_DEVICE_ID_NX2_5709          0x1639
00077 #define PCI_DEVICE_ID_NX2_5709S         0x163a
00078 #define PCI_DEVICE_ID_TIGON3_5700       0x1644
00079 #define PCI_DEVICE_ID_TIGON3_5701       0x1645
00080 #define PCI_DEVICE_ID_TIGON3_5702       0x1646
00081 #define PCI_DEVICE_ID_TIGON3_5703       0x1647
00082 #define PCI_DEVICE_ID_TIGON3_5704       0x1648
00083 #define PCI_DEVICE_ID_TIGON3_5704S_2    0x1649
00084 #define PCI_DEVICE_ID_NX2_5706          0x164a
00085 #define PCI_DEVICE_ID_NX2_5708          0x164c
00086 #define PCI_DEVICE_ID_TIGON3_5702FE     0x164d
00087 #define PCI_DEVICE_ID_NX2_57710         0x164e
00088 #define PCI_DEVICE_ID_NX2_57711         0x164f
00089 #define PCI_DEVICE_ID_NX2_57711E        0x1650
00090 #define PCI_DEVICE_ID_TIGON3_5705       0x1653
00091 #define PCI_DEVICE_ID_TIGON3_5705_2     0x1654
00092 #define PCI_DEVICE_ID_TIGON3_5721       0x1659
00093 #define PCI_DEVICE_ID_TIGON3_5722       0x165a
00094 #define PCI_DEVICE_ID_TIGON3_5723       0x165b
00095 #define PCI_DEVICE_ID_TIGON3_5705M      0x165d
00096 #define PCI_DEVICE_ID_TIGON3_5705M_2    0x165e
00097 #define PCI_DEVICE_ID_NX2_57712         0x1662
00098 #define PCI_DEVICE_ID_NX2_57712E        0x1663
00099 #define PCI_DEVICE_ID_TIGON3_5714       0x1668
00100 #define PCI_DEVICE_ID_TIGON3_5714S      0x1669
00101 #define PCI_DEVICE_ID_TIGON3_5780       0x166a
00102 #define PCI_DEVICE_ID_TIGON3_5780S      0x166b
00103 #define PCI_DEVICE_ID_TIGON3_5705F      0x166e
00104 #define PCI_DEVICE_ID_TIGON3_5754M      0x1672
00105 #define PCI_DEVICE_ID_TIGON3_5755M      0x1673
00106 #define PCI_DEVICE_ID_TIGON3_5756       0x1674
00107 #define PCI_DEVICE_ID_TIGON3_5751       0x1677
00108 #define PCI_DEVICE_ID_TIGON3_5715       0x1678
00109 #define PCI_DEVICE_ID_TIGON3_5715S      0x1679
00110 #define PCI_DEVICE_ID_TIGON3_5754       0x167a
00111 #define PCI_DEVICE_ID_TIGON3_5755       0x167b
00112 #define PCI_DEVICE_ID_TIGON3_5751M      0x167d
00113 #define PCI_DEVICE_ID_TIGON3_5751F      0x167e
00114 #define PCI_DEVICE_ID_TIGON3_5787F      0x167f
00115 #define PCI_DEVICE_ID_TIGON3_5761E      0x1680
00116 #define PCI_DEVICE_ID_TIGON3_5761       0x1681
00117 #define PCI_DEVICE_ID_TIGON3_5764       0x1684
00118 #define PCI_DEVICE_ID_TIGON3_5787M      0x1693
00119 #define PCI_DEVICE_ID_TIGON3_5782       0x1696
00120 #define PCI_DEVICE_ID_TIGON3_5784       0x1698
00121 #define PCI_DEVICE_ID_TIGON3_5786       0x169a
00122 #define PCI_DEVICE_ID_TIGON3_5787       0x169b
00123 #define PCI_DEVICE_ID_TIGON3_5788       0x169c
00124 #define PCI_DEVICE_ID_TIGON3_5789       0x169d
00125 #define PCI_DEVICE_ID_TIGON3_5702X      0x16a6
00126 #define PCI_DEVICE_ID_TIGON3_5703X      0x16a7
00127 #define PCI_DEVICE_ID_TIGON3_5704S      0x16a8
00128 #define PCI_DEVICE_ID_NX2_5706S         0x16aa
00129 #define PCI_DEVICE_ID_NX2_5708S         0x16ac
00130 #define PCI_DEVICE_ID_TIGON3_5702A3     0x16c6
00131 #define PCI_DEVICE_ID_TIGON3_5703A3     0x16c7
00132 #define PCI_DEVICE_ID_TIGON3_5781       0x16dd
00133 #define PCI_DEVICE_ID_TIGON3_5753       0x16f7
00134 #define PCI_DEVICE_ID_TIGON3_5753M      0x16fd
00135 #define PCI_DEVICE_ID_TIGON3_5753F      0x16fe
00136 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
00137 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
00138 #define PCI_DEVICE_ID_TIGON3_5906       0x1712
00139 #define PCI_DEVICE_ID_TIGON3_5906M      0x1713
00140 #define PCI_VENDOR_ID_COMPAQ            0x0e11
00141 #define PCI_VENDOR_ID_IBM               0x1014
00142 #define PCI_VENDOR_ID_DELL              0x1028
00143 #define PCI_VENDOR_ID_3COM              0x10b7
00144 /* </pci_ids.h> */
00145 
00146 #define SPEED_10                        10
00147 #define SPEED_100                       100
00148 #define SPEED_1000                      1000
00149 #ifndef SPEED_UNKNOWN
00150 #define SPEED_UNKNOWN                   -1
00151 #endif
00152 
00153 #define DUPLEX_HALF                     0x00
00154 #define DUPLEX_FULL                     0x01
00155 #ifndef DUPLEX_UNKNOWN
00156 #define DUPLEX_UNKNOWN                  0xff
00157 #endif
00158 
00159 #define TG3_64BIT_REG_HIGH              0x00UL
00160 #define TG3_64BIT_REG_LOW               0x04UL
00161 
00162 /* Descriptor block info. */
00163 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
00164 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
00165 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
00166 #define  BDINFO_FLAGS_DISABLED           0x00000002
00167 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
00168 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
00169 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
00170 #define TG3_BDINFO_SIZE                 0x10UL
00171 
00172 #define RX_STD_MAX_SIZE                 1536
00173 #define TG3_RX_STD_MAX_SIZE_5700        512
00174 #define TG3_RX_STD_MAX_SIZE_5717        2048
00175 #define TG3_RX_JMB_MAX_SIZE_5700        256
00176 #define TG3_RX_JMB_MAX_SIZE_5717        1024
00177 #define TG3_RX_RET_MAX_SIZE_5700        1024
00178 #define TG3_RX_RET_MAX_SIZE_5705        512
00179 #define TG3_RX_RET_MAX_SIZE_5717        4096
00180 
00181 /* First 256 bytes are a mirror of PCI config space. */
00182 #define TG3PCI_VENDOR                   0x00000000
00183 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
00184 #define TG3PCI_DEVICE                   0x00000002
00185 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
00186 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
00187 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
00188 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
00189 #define  TG3PCI_DEVICE_TIGON3_5761S      0x1688
00190 #define  TG3PCI_DEVICE_TIGON3_5761SE     0x1689
00191 #define  TG3PCI_DEVICE_TIGON3_57780      0x1692
00192 #define  TG3PCI_DEVICE_TIGON3_57760      0x1690
00193 #define  TG3PCI_DEVICE_TIGON3_57790      0x1694
00194 #define  TG3PCI_DEVICE_TIGON3_57788      0x1691
00195 #define  TG3PCI_DEVICE_TIGON3_5785_G     0x1699 /* GPHY */
00196 #define  TG3PCI_DEVICE_TIGON3_5785_F     0x16a0 /* 10/100 only */
00197 #define  TG3PCI_DEVICE_TIGON3_5717       0x1655
00198 #define  TG3PCI_DEVICE_TIGON3_5718       0x1656
00199 #define  TG3PCI_DEVICE_TIGON3_57781      0x16b1
00200 #define  TG3PCI_DEVICE_TIGON3_57785      0x16b5
00201 #define  TG3PCI_DEVICE_TIGON3_57761      0x16b0
00202 #define  TG3PCI_DEVICE_TIGON3_57762      0x1682
00203 #define  TG3PCI_DEVICE_TIGON3_57765      0x16b4
00204 #define  TG3PCI_DEVICE_TIGON3_57766      0x1686
00205 #define  TG3PCI_DEVICE_TIGON3_57791      0x16b2
00206 #define  TG3PCI_DEVICE_TIGON3_57795      0x16b6
00207 #define  TG3PCI_DEVICE_TIGON3_5719       0x1657
00208 #define  TG3PCI_DEVICE_TIGON3_5720       0x165f
00209 /* 0x04 --> 0x2c unused */
00210 #define TG3PCI_SUBVENDOR_ID_BROADCOM            PCI_VENDOR_ID_BROADCOM
00211 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6    0x1644
00212 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5    0x0001
00213 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6    0x0002
00214 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9    0x0003
00215 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1    0x0005
00216 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8    0x0006
00217 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7    0x0007
00218 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10   0x0008
00219 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12   0x8008
00220 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1   0x0009
00221 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2   0x8009
00222 #define TG3PCI_SUBVENDOR_ID_3COM                PCI_VENDOR_ID_3COM
00223 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T         0x1000
00224 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT        0x1006
00225 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX        0x1004
00226 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T        0x1007
00227 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01      0x1008
00228 #define TG3PCI_SUBVENDOR_ID_DELL                PCI_VENDOR_ID_DELL
00229 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER          0x00d1
00230 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR         0x0106
00231 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT         0x0109
00232 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT    0x010a
00233 #define TG3PCI_SUBVENDOR_ID_COMPAQ              PCI_VENDOR_ID_COMPAQ
00234 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE      0x007c
00235 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2    0x009a
00236 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING   0x007d
00237 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780       0x0085
00238 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2     0x0099
00239 #define TG3PCI_SUBVENDOR_ID_IBM                 PCI_VENDOR_ID_IBM
00240 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2        0x0281
00241 /* 0x30 --> 0x64 unused */
00242 #define TG3PCI_MSI_DATA                 0x00000064
00243 /* 0x66 --> 0x68 unused */
00244 #define TG3PCI_MISC_HOST_CTRL           0x00000068
00245 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
00246 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
00247 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
00248 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
00249 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
00250 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
00251 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
00252 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
00253 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
00254 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
00255 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
00256 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
00257 #define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
00258          (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
00259           MISC_HOST_CTRL_CHIPREV_SHIFT)
00260 #define  CHIPREV_ID_5700_A0              0x7000
00261 #define  CHIPREV_ID_5700_A1              0x7001
00262 #define  CHIPREV_ID_5700_B0              0x7100
00263 #define  CHIPREV_ID_5700_B1              0x7101
00264 #define  CHIPREV_ID_5700_B3              0x7102
00265 #define  CHIPREV_ID_5700_ALTIMA          0x7104
00266 #define  CHIPREV_ID_5700_C0              0x7200
00267 #define  CHIPREV_ID_5701_A0              0x0000
00268 #define  CHIPREV_ID_5701_B0              0x0100
00269 #define  CHIPREV_ID_5701_B2              0x0102
00270 #define  CHIPREV_ID_5701_B5              0x0105
00271 #define  CHIPREV_ID_5703_A0              0x1000
00272 #define  CHIPREV_ID_5703_A1              0x1001
00273 #define  CHIPREV_ID_5703_A2              0x1002
00274 #define  CHIPREV_ID_5703_A3              0x1003
00275 #define  CHIPREV_ID_5704_A0              0x2000
00276 #define  CHIPREV_ID_5704_A1              0x2001
00277 #define  CHIPREV_ID_5704_A2              0x2002
00278 #define  CHIPREV_ID_5704_A3              0x2003
00279 #define  CHIPREV_ID_5705_A0              0x3000
00280 #define  CHIPREV_ID_5705_A1              0x3001
00281 #define  CHIPREV_ID_5705_A2              0x3002
00282 #define  CHIPREV_ID_5705_A3              0x3003
00283 #define  CHIPREV_ID_5750_A0              0x4000
00284 #define  CHIPREV_ID_5750_A1              0x4001
00285 #define  CHIPREV_ID_5750_A3              0x4003
00286 #define  CHIPREV_ID_5750_C2              0x4202
00287 #define  CHIPREV_ID_5752_A0_HW           0x5000
00288 #define  CHIPREV_ID_5752_A0              0x6000
00289 #define  CHIPREV_ID_5752_A1              0x6001
00290 #define  CHIPREV_ID_5714_A2              0x9002
00291 #define  CHIPREV_ID_5906_A1              0xc001
00292 #define  CHIPREV_ID_57780_A0             0x57780000
00293 #define  CHIPREV_ID_57780_A1             0x57780001
00294 #define  CHIPREV_ID_5717_A0              0x05717000
00295 #define  CHIPREV_ID_57765_A0             0x57785000
00296 #define  CHIPREV_ID_5719_A0              0x05719000
00297 #define  CHIPREV_ID_5720_A0              0x05720000
00298 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
00299 #define   ASIC_REV_5700                  0x07
00300 #define   ASIC_REV_5701                  0x00
00301 #define   ASIC_REV_5703                  0x01
00302 #define   ASIC_REV_5704                  0x02
00303 #define   ASIC_REV_5705                  0x03
00304 #define   ASIC_REV_5750                  0x04
00305 #define   ASIC_REV_5752                  0x06
00306 #define   ASIC_REV_5780                  0x08
00307 #define   ASIC_REV_5714                  0x09
00308 #define   ASIC_REV_5755                  0x0a
00309 #define   ASIC_REV_5787                  0x0b
00310 #define   ASIC_REV_5906                  0x0c
00311 #define   ASIC_REV_USE_PROD_ID_REG       0x0f
00312 #define   ASIC_REV_5784                  0x5784
00313 #define   ASIC_REV_5761                  0x5761
00314 #define   ASIC_REV_5785                  0x5785
00315 #define   ASIC_REV_57780                 0x57780
00316 #define   ASIC_REV_5717                  0x5717
00317 #define   ASIC_REV_57765                 0x57785
00318 #define   ASIC_REV_57766                 0x57766
00319 #define   ASIC_REV_5719                  0x5719
00320 #define   ASIC_REV_5720                  0x5720
00321 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
00322 #define   CHIPREV_5700_AX                0x70
00323 #define   CHIPREV_5700_BX                0x71
00324 #define   CHIPREV_5700_CX                0x72
00325 #define   CHIPREV_5701_AX                0x00
00326 #define   CHIPREV_5703_AX                0x10
00327 #define   CHIPREV_5704_AX                0x20
00328 #define   CHIPREV_5704_BX                0x21
00329 #define   CHIPREV_5750_AX                0x40
00330 #define   CHIPREV_5750_BX                0x41
00331 #define   CHIPREV_5784_AX                0x57840
00332 #define   CHIPREV_5761_AX                0x57610
00333 #define   CHIPREV_57765_AX               0x577650
00334 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
00335 #define   METAL_REV_A0                   0x00
00336 #define   METAL_REV_A1                   0x01
00337 #define   METAL_REV_B0                   0x00
00338 #define   METAL_REV_B1                   0x01
00339 #define   METAL_REV_B2                   0x02
00340 #define TG3PCI_DMA_RW_CTRL              0x0000006c
00341 #define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
00342 #define  DMA_RWCTRL_TAGGED_STAT_WA       0x00000080
00343 #define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
00344 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
00345 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
00346 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
00347 #define  DMA_RWCTRL_READ_BNDRY_128_PCIX  0x00000100
00348 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
00349 #define  DMA_RWCTRL_READ_BNDRY_256_PCIX  0x00000200
00350 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
00351 #define  DMA_RWCTRL_READ_BNDRY_384_PCIX  0x00000300
00352 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
00353 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
00354 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
00355 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
00356 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
00357 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
00358 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
00359 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
00360 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
00361 #define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
00362 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
00363 #define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
00364 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
00365 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
00366 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
00367 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
00368 #define  DMA_RWCTRL_ONE_DMA              0x00004000
00369 #define  DMA_RWCTRL_READ_WATER           0x00070000
00370 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
00371 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
00372 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
00373 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
00374 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
00375 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
00376 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
00377 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
00378 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
00379 #define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE  0x10000000
00380 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
00381 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
00382 #define TG3PCI_PCISTATE                 0x00000070
00383 #define  PCISTATE_FORCE_RESET            0x00000001
00384 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
00385 #define  PCISTATE_CONV_PCI_MODE          0x00000004
00386 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
00387 #define  PCISTATE_BUS_32BIT              0x00000010
00388 #define  PCISTATE_ROM_ENABLE             0x00000020
00389 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
00390 #define  PCISTATE_FLAT_VIEW              0x00000100
00391 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
00392 #define  PCISTATE_ALLOW_APE_CTLSPC_WR    0x00010000
00393 #define  PCISTATE_ALLOW_APE_SHMEM_WR     0x00020000
00394 #define  PCISTATE_ALLOW_APE_PSPACE_WR    0x00040000
00395 #define TG3PCI_CLOCK_CTRL               0x00000074
00396 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
00397 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
00398 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
00399 #define  CLOCK_CTRL_ALTCLK               0x00001000
00400 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
00401 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
00402 #define  CLOCK_CTRL_625_CORE             0x00100000
00403 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
00404 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
00405 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
00406 #define TG3PCI_REG_BASE_ADDR            0x00000078
00407 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
00408 #define TG3PCI_REG_DATA                 0x00000080
00409 #define TG3PCI_MEM_WIN_DATA             0x00000084
00410 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
00411 /* 0x94 --> 0x98 unused */
00412 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
00413 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
00414 /* 0xa8 --> 0xb8 unused */
00415 #define TG3PCI_DUAL_MAC_CTRL            0x000000b8
00416 #define  DUAL_MAC_CTRL_CH_MASK           0x00000003
00417 #define  DUAL_MAC_CTRL_ID                0x00000004
00418 #define TG3PCI_PRODID_ASICREV           0x000000bc
00419 #define  PROD_ID_ASIC_REV_MASK           0x0fffffff
00420 /* 0xc0 --> 0xf4 unused */
00421 
00422 #define TG3PCI_GEN2_PRODID_ASICREV      0x000000f4
00423 #define TG3PCI_GEN15_PRODID_ASICREV     0x000000fc
00424 /* 0xf8 --> 0x200 unused */
00425 
00426 #define TG3_CORR_ERR_STAT               0x00000110
00427 #define  TG3_CORR_ERR_STAT_CLEAR        0xffffffff
00428 /* 0x114 --> 0x200 unused */
00429 
00430 /* Mailbox registers */
00431 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
00432 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
00433 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
00434 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
00435 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
00436 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
00437 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
00438 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
00439 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
00440 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
00441 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
00442 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
00443 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
00444 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
00445 #define TG3_RX_STD_PROD_IDX_REG         (MAILBOX_RCV_STD_PROD_IDX + \
00446                                          TG3_64BIT_REG_LOW)
00447 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
00448 #define TG3_RX_JMB_PROD_IDX_REG         (MAILBOX_RCV_JUMBO_PROD_IDX + \
00449                                          TG3_64BIT_REG_LOW)
00450 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
00451 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
00452 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
00453 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
00454 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
00455 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
00456 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
00457 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
00458 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
00459 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
00460 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
00461 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
00462 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
00463 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
00464 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
00465 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
00466 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
00467 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
00468 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
00469 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
00470 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
00471 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
00472 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
00473 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
00474 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
00475 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
00476 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
00477 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
00478 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
00479 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
00480 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
00481 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
00482 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
00483 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
00484 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
00485 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
00486 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
00487 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
00488 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
00489 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
00490 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
00491 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
00492 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
00493 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
00494 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
00495 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
00496 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
00497 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
00498 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
00499 
00500 /* MAC control registers */
00501 #define MAC_MODE                        0x00000400
00502 #define  MAC_MODE_RESET                  0x00000001
00503 #define  MAC_MODE_HALF_DUPLEX            0x00000002
00504 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
00505 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
00506 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
00507 #define  MAC_MODE_PORT_MODE_MII          0x00000004
00508 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
00509 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
00510 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
00511 #define  MAC_MODE_TX_BURSTING            0x00000100
00512 #define  MAC_MODE_MAX_DEFER              0x00000200
00513 #define  MAC_MODE_LINK_POLARITY          0x00000400
00514 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
00515 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
00516 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
00517 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
00518 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
00519 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
00520 #define  MAC_MODE_SEND_CONFIGS           0x00020000
00521 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
00522 #define  MAC_MODE_ACPI_ENABLE            0x00080000
00523 #define  MAC_MODE_MIP_ENABLE             0x00100000
00524 #define  MAC_MODE_TDE_ENABLE             0x00200000
00525 #define  MAC_MODE_RDE_ENABLE             0x00400000
00526 #define  MAC_MODE_FHDE_ENABLE            0x00800000
00527 #define  MAC_MODE_KEEP_FRAME_IN_WOL      0x01000000
00528 #define  MAC_MODE_APE_RX_EN              0x08000000
00529 #define  MAC_MODE_APE_TX_EN              0x10000000
00530 #define MAC_STATUS                      0x00000404
00531 #define  MAC_STATUS_PCS_SYNCED           0x00000001
00532 #define  MAC_STATUS_SIGNAL_DET           0x00000002
00533 #define  MAC_STATUS_RCVD_CFG             0x00000004
00534 #define  MAC_STATUS_CFG_CHANGED          0x00000008
00535 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
00536 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
00537 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
00538 #define  MAC_STATUS_MI_COMPLETION        0x00400000
00539 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
00540 #define  MAC_STATUS_AP_ERROR             0x01000000
00541 #define  MAC_STATUS_ODI_ERROR            0x02000000
00542 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
00543 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
00544 #define MAC_EVENT                       0x00000408
00545 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
00546 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
00547 #define  MAC_EVENT_MI_COMPLETION         0x00400000
00548 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
00549 #define  MAC_EVENT_AP_ERROR              0x01000000
00550 #define  MAC_EVENT_ODI_ERROR             0x02000000
00551 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
00552 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
00553 #define MAC_LED_CTRL                    0x0000040c
00554 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
00555 #define  LED_CTRL_1000MBPS_ON            0x00000002
00556 #define  LED_CTRL_100MBPS_ON             0x00000004
00557 #define  LED_CTRL_10MBPS_ON              0x00000008
00558 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
00559 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
00560 #define  LED_CTRL_TRAFFIC_LED            0x00000040
00561 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
00562 #define  LED_CTRL_100MBPS_STATUS         0x00000100
00563 #define  LED_CTRL_10MBPS_STATUS          0x00000200
00564 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
00565 #define  LED_CTRL_MODE_MAC               0x00000000
00566 #define  LED_CTRL_MODE_PHY_1             0x00000800
00567 #define  LED_CTRL_MODE_PHY_2             0x00001000
00568 #define  LED_CTRL_MODE_SHASTA_MAC        0x00002000
00569 #define  LED_CTRL_MODE_SHARED            0x00004000
00570 #define  LED_CTRL_MODE_COMBO             0x00008000
00571 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
00572 #define  LED_CTRL_BLINK_RATE_SHIFT       19
00573 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
00574 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
00575 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
00576 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
00577 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
00578 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
00579 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
00580 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
00581 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
00582 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
00583 #define MAC_ACPI_MBUF_PTR               0x00000430
00584 #define MAC_ACPI_LEN_OFFSET             0x00000434
00585 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
00586 #define  ACPI_LENOFF_LEN_SHIFT           0
00587 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
00588 #define  ACPI_LENOFF_OFF_SHIFT           16
00589 #define MAC_TX_BACKOFF_SEED             0x00000438
00590 #define  TX_BACKOFF_SEED_MASK            0x000003ff
00591 #define MAC_RX_MTU_SIZE                 0x0000043c
00592 #define  RX_MTU_SIZE_MASK                0x0000ffff
00593 #define MAC_PCS_TEST                    0x00000440
00594 #define  PCS_TEST_PATTERN_MASK           0x000fffff
00595 #define  PCS_TEST_PATTERN_SHIFT          0
00596 #define  PCS_TEST_ENABLE                 0x00100000
00597 #define MAC_TX_AUTO_NEG                 0x00000444
00598 #define  TX_AUTO_NEG_MASK                0x0000ffff
00599 #define  TX_AUTO_NEG_SHIFT               0
00600 #define MAC_RX_AUTO_NEG                 0x00000448
00601 #define  RX_AUTO_NEG_MASK                0x0000ffff
00602 #define  RX_AUTO_NEG_SHIFT               0
00603 #define MAC_MI_COM                      0x0000044c
00604 #define  MI_COM_CMD_MASK                 0x0c000000
00605 #define  MI_COM_CMD_WRITE                0x04000000
00606 #define  MI_COM_CMD_READ                 0x08000000
00607 #define  MI_COM_READ_FAILED              0x10000000
00608 #define  MI_COM_START                    0x20000000
00609 #define  MI_COM_BUSY                     0x20000000
00610 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
00611 #define  MI_COM_PHY_ADDR_SHIFT           21
00612 #define  MI_COM_REG_ADDR_MASK            0x001f0000
00613 #define  MI_COM_REG_ADDR_SHIFT           16
00614 #define  MI_COM_DATA_MASK                0x0000ffff
00615 #define MAC_MI_STAT                     0x00000450
00616 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
00617 #define  MAC_MI_STAT_10MBPS_MODE         0x00000002
00618 #define MAC_MI_MODE                     0x00000454
00619 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
00620 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
00621 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
00622 #define  MAC_MI_MODE_500KHZ_CONST        0x00008000
00623 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
00624 #define MAC_AUTO_POLL_STATUS            0x00000458
00625 #define  MAC_AUTO_POLL_ERROR             0x00000001
00626 #define MAC_TX_MODE                     0x0000045c
00627 #define  TX_MODE_RESET                   0x00000001
00628 #define  TX_MODE_ENABLE                  0x00000002
00629 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
00630 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
00631 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
00632 #define  TX_MODE_MBUF_LOCKUP_FIX         0x00000100
00633 #define  TX_MODE_JMB_FRM_LEN             0x00400000
00634 #define  TX_MODE_CNT_DN_MODE             0x00800000
00635 #define MAC_TX_STATUS                   0x00000460
00636 #define  TX_STATUS_XOFFED                0x00000001
00637 #define  TX_STATUS_SENT_XOFF             0x00000002
00638 #define  TX_STATUS_SENT_XON              0x00000004
00639 #define  TX_STATUS_LINK_UP               0x00000008
00640 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
00641 #define  TX_STATUS_ODI_OVERRUN           0x00000020
00642 #define MAC_TX_LENGTHS                  0x00000464
00643 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
00644 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
00645 #define  TX_LENGTHS_IPG_MASK             0x00000f00
00646 #define  TX_LENGTHS_IPG_SHIFT            8
00647 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
00648 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
00649 #define  TX_LENGTHS_JMB_FRM_LEN_MSK      0x00ff0000
00650 #define  TX_LENGTHS_CNT_DWN_VAL_MSK      0xff000000
00651 #define MAC_RX_MODE                     0x00000468
00652 #define  RX_MODE_RESET                   0x00000001
00653 #define  RX_MODE_ENABLE                  0x00000002
00654 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
00655 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
00656 #define  RX_MODE_KEEP_PAUSE              0x00000010
00657 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
00658 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
00659 #define  RX_MODE_LEN_CHECK               0x00000080
00660 #define  RX_MODE_PROMISC                 0x00000100
00661 #define  RX_MODE_NO_CRC_CHECK            0x00000200
00662 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
00663 #define  RX_MODE_RSS_IPV4_HASH_EN        0x00010000
00664 #define  RX_MODE_RSS_TCP_IPV4_HASH_EN    0x00020000
00665 #define  RX_MODE_RSS_IPV6_HASH_EN        0x00040000
00666 #define  RX_MODE_RSS_TCP_IPV6_HASH_EN    0x00080000
00667 #define  RX_MODE_RSS_ITBL_HASH_BITS_7    0x00700000
00668 #define  RX_MODE_RSS_ENABLE              0x00800000
00669 #define  RX_MODE_IPV6_CSUM_ENABLE        0x01000000
00670 #define MAC_RX_STATUS                   0x0000046c
00671 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
00672 #define  RX_STATUS_XOFF_RCVD             0x00000002
00673 #define  RX_STATUS_XON_RCVD              0x00000004
00674 #define MAC_HASH_REG_0                  0x00000470
00675 #define MAC_HASH_REG_1                  0x00000474
00676 #define MAC_HASH_REG_2                  0x00000478
00677 #define MAC_HASH_REG_3                  0x0000047c
00678 #define MAC_RCV_RULE_0                  0x00000480
00679 #define MAC_RCV_VALUE_0                 0x00000484
00680 #define MAC_RCV_RULE_1                  0x00000488
00681 #define MAC_RCV_VALUE_1                 0x0000048c
00682 #define MAC_RCV_RULE_2                  0x00000490
00683 #define MAC_RCV_VALUE_2                 0x00000494
00684 #define MAC_RCV_RULE_3                  0x00000498
00685 #define MAC_RCV_VALUE_3                 0x0000049c
00686 #define MAC_RCV_RULE_4                  0x000004a0
00687 #define MAC_RCV_VALUE_4                 0x000004a4
00688 #define MAC_RCV_RULE_5                  0x000004a8
00689 #define MAC_RCV_VALUE_5                 0x000004ac
00690 #define MAC_RCV_RULE_6                  0x000004b0
00691 #define MAC_RCV_VALUE_6                 0x000004b4
00692 #define MAC_RCV_RULE_7                  0x000004b8
00693 #define MAC_RCV_VALUE_7                 0x000004bc
00694 #define MAC_RCV_RULE_8                  0x000004c0
00695 #define MAC_RCV_VALUE_8                 0x000004c4
00696 #define MAC_RCV_RULE_9                  0x000004c8
00697 #define MAC_RCV_VALUE_9                 0x000004cc
00698 #define MAC_RCV_RULE_10                 0x000004d0
00699 #define MAC_RCV_VALUE_10                0x000004d4
00700 #define MAC_RCV_RULE_11                 0x000004d8
00701 #define MAC_RCV_VALUE_11                0x000004dc
00702 #define MAC_RCV_RULE_12                 0x000004e0
00703 #define MAC_RCV_VALUE_12                0x000004e4
00704 #define MAC_RCV_RULE_13                 0x000004e8
00705 #define MAC_RCV_VALUE_13                0x000004ec
00706 #define MAC_RCV_RULE_14                 0x000004f0
00707 #define MAC_RCV_VALUE_14                0x000004f4
00708 #define MAC_RCV_RULE_15                 0x000004f8
00709 #define MAC_RCV_VALUE_15                0x000004fc
00710 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
00711 #define MAC_RCV_RULE_CFG                0x00000500
00712 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
00713 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
00714 /* 0x508 --> 0x520 unused */
00715 #define MAC_HASHREGU_0                  0x00000520
00716 #define MAC_HASHREGU_1                  0x00000524
00717 #define MAC_HASHREGU_2                  0x00000528
00718 #define MAC_HASHREGU_3                  0x0000052c
00719 #define MAC_EXTADDR_0_HIGH              0x00000530
00720 #define MAC_EXTADDR_0_LOW               0x00000534
00721 #define MAC_EXTADDR_1_HIGH              0x00000538
00722 #define MAC_EXTADDR_1_LOW               0x0000053c
00723 #define MAC_EXTADDR_2_HIGH              0x00000540
00724 #define MAC_EXTADDR_2_LOW               0x00000544
00725 #define MAC_EXTADDR_3_HIGH              0x00000548
00726 #define MAC_EXTADDR_3_LOW               0x0000054c
00727 #define MAC_EXTADDR_4_HIGH              0x00000550
00728 #define MAC_EXTADDR_4_LOW               0x00000554
00729 #define MAC_EXTADDR_5_HIGH              0x00000558
00730 #define MAC_EXTADDR_5_LOW               0x0000055c
00731 #define MAC_EXTADDR_6_HIGH              0x00000560
00732 #define MAC_EXTADDR_6_LOW               0x00000564
00733 #define MAC_EXTADDR_7_HIGH              0x00000568
00734 #define MAC_EXTADDR_7_LOW               0x0000056c
00735 #define MAC_EXTADDR_8_HIGH              0x00000570
00736 #define MAC_EXTADDR_8_LOW               0x00000574
00737 #define MAC_EXTADDR_9_HIGH              0x00000578
00738 #define MAC_EXTADDR_9_LOW               0x0000057c
00739 #define MAC_EXTADDR_10_HIGH             0x00000580
00740 #define MAC_EXTADDR_10_LOW              0x00000584
00741 #define MAC_EXTADDR_11_HIGH             0x00000588
00742 #define MAC_EXTADDR_11_LOW              0x0000058c
00743 #define MAC_SERDES_CFG                  0x00000590
00744 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
00745 #define MAC_SERDES_STAT                 0x00000594
00746 /* 0x598 --> 0x5a0 unused */
00747 #define MAC_PHYCFG1                     0x000005a0
00748 #define  MAC_PHYCFG1_RGMII_INT           0x00000001
00749 #define  MAC_PHYCFG1_RXCLK_TO_MASK       0x00001ff0
00750 #define  MAC_PHYCFG1_RXCLK_TIMEOUT       0x00001000
00751 #define  MAC_PHYCFG1_TXCLK_TO_MASK       0x01ff0000
00752 #define  MAC_PHYCFG1_TXCLK_TIMEOUT       0x01000000
00753 #define  MAC_PHYCFG1_RGMII_EXT_RX_DEC    0x02000000
00754 #define  MAC_PHYCFG1_RGMII_SND_STAT_EN   0x04000000
00755 #define  MAC_PHYCFG1_TXC_DRV             0x20000000
00756 #define MAC_PHYCFG2                     0x000005a4
00757 #define  MAC_PHYCFG2_INBAND_ENABLE       0x00000001
00758 #define  MAC_PHYCFG2_EMODE_MASK_MASK     0x000001c0
00759 #define  MAC_PHYCFG2_EMODE_MASK_AC131    0x000000c0
00760 #define  MAC_PHYCFG2_EMODE_MASK_50610    0x00000100
00761 #define  MAC_PHYCFG2_EMODE_MASK_RT8211   0x00000000
00762 #define  MAC_PHYCFG2_EMODE_MASK_RT8201   0x000001c0
00763 #define  MAC_PHYCFG2_EMODE_COMP_MASK     0x00000e00
00764 #define  MAC_PHYCFG2_EMODE_COMP_AC131    0x00000600
00765 #define  MAC_PHYCFG2_EMODE_COMP_50610    0x00000400
00766 #define  MAC_PHYCFG2_EMODE_COMP_RT8211   0x00000800
00767 #define  MAC_PHYCFG2_EMODE_COMP_RT8201   0x00000000
00768 #define  MAC_PHYCFG2_FMODE_MASK_MASK     0x00007000
00769 #define  MAC_PHYCFG2_FMODE_MASK_AC131    0x00006000
00770 #define  MAC_PHYCFG2_FMODE_MASK_50610    0x00004000
00771 #define  MAC_PHYCFG2_FMODE_MASK_RT8211   0x00000000
00772 #define  MAC_PHYCFG2_FMODE_MASK_RT8201   0x00007000
00773 #define  MAC_PHYCFG2_FMODE_COMP_MASK     0x00038000
00774 #define  MAC_PHYCFG2_FMODE_COMP_AC131    0x00030000
00775 #define  MAC_PHYCFG2_FMODE_COMP_50610    0x00008000
00776 #define  MAC_PHYCFG2_FMODE_COMP_RT8211   0x00038000
00777 #define  MAC_PHYCFG2_FMODE_COMP_RT8201   0x00000000
00778 #define  MAC_PHYCFG2_GMODE_MASK_MASK     0x001c0000
00779 #define  MAC_PHYCFG2_GMODE_MASK_AC131    0x001c0000
00780 #define  MAC_PHYCFG2_GMODE_MASK_50610    0x00100000
00781 #define  MAC_PHYCFG2_GMODE_MASK_RT8211   0x00000000
00782 #define  MAC_PHYCFG2_GMODE_MASK_RT8201   0x001c0000
00783 #define  MAC_PHYCFG2_GMODE_COMP_MASK     0x00e00000
00784 #define  MAC_PHYCFG2_GMODE_COMP_AC131    0x00e00000
00785 #define  MAC_PHYCFG2_GMODE_COMP_50610    0x00000000
00786 #define  MAC_PHYCFG2_GMODE_COMP_RT8211   0x00200000
00787 #define  MAC_PHYCFG2_GMODE_COMP_RT8201   0x00000000
00788 #define  MAC_PHYCFG2_ACT_MASK_MASK       0x03000000
00789 #define  MAC_PHYCFG2_ACT_MASK_AC131      0x03000000
00790 #define  MAC_PHYCFG2_ACT_MASK_50610      0x01000000
00791 #define  MAC_PHYCFG2_ACT_MASK_RT8211     0x03000000
00792 #define  MAC_PHYCFG2_ACT_MASK_RT8201     0x01000000
00793 #define  MAC_PHYCFG2_ACT_COMP_MASK       0x0c000000
00794 #define  MAC_PHYCFG2_ACT_COMP_AC131      0x00000000
00795 #define  MAC_PHYCFG2_ACT_COMP_50610      0x00000000
00796 #define  MAC_PHYCFG2_ACT_COMP_RT8211     0x00000000
00797 #define  MAC_PHYCFG2_ACT_COMP_RT8201     0x08000000
00798 #define  MAC_PHYCFG2_QUAL_MASK_MASK      0x30000000
00799 #define  MAC_PHYCFG2_QUAL_MASK_AC131     0x30000000
00800 #define  MAC_PHYCFG2_QUAL_MASK_50610     0x30000000
00801 #define  MAC_PHYCFG2_QUAL_MASK_RT8211    0x30000000
00802 #define  MAC_PHYCFG2_QUAL_MASK_RT8201    0x30000000
00803 #define  MAC_PHYCFG2_QUAL_COMP_MASK      0xc0000000
00804 #define  MAC_PHYCFG2_QUAL_COMP_AC131     0x00000000
00805 #define  MAC_PHYCFG2_QUAL_COMP_50610     0x00000000
00806 #define  MAC_PHYCFG2_QUAL_COMP_RT8211    0x00000000
00807 #define  MAC_PHYCFG2_QUAL_COMP_RT8201    0x00000000
00808 #define MAC_PHYCFG2_50610_LED_MODES \
00809         (MAC_PHYCFG2_EMODE_MASK_50610 | \
00810          MAC_PHYCFG2_EMODE_COMP_50610 | \
00811          MAC_PHYCFG2_FMODE_MASK_50610 | \
00812          MAC_PHYCFG2_FMODE_COMP_50610 | \
00813          MAC_PHYCFG2_GMODE_MASK_50610 | \
00814          MAC_PHYCFG2_GMODE_COMP_50610 | \
00815          MAC_PHYCFG2_ACT_MASK_50610 | \
00816          MAC_PHYCFG2_ACT_COMP_50610 | \
00817          MAC_PHYCFG2_QUAL_MASK_50610 | \
00818          MAC_PHYCFG2_QUAL_COMP_50610)
00819 #define MAC_PHYCFG2_AC131_LED_MODES \
00820         (MAC_PHYCFG2_EMODE_MASK_AC131 | \
00821          MAC_PHYCFG2_EMODE_COMP_AC131 | \
00822          MAC_PHYCFG2_FMODE_MASK_AC131 | \
00823          MAC_PHYCFG2_FMODE_COMP_AC131 | \
00824          MAC_PHYCFG2_GMODE_MASK_AC131 | \
00825          MAC_PHYCFG2_GMODE_COMP_AC131 | \
00826          MAC_PHYCFG2_ACT_MASK_AC131 | \
00827          MAC_PHYCFG2_ACT_COMP_AC131 | \
00828          MAC_PHYCFG2_QUAL_MASK_AC131 | \
00829          MAC_PHYCFG2_QUAL_COMP_AC131)
00830 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
00831         (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
00832          MAC_PHYCFG2_EMODE_COMP_RT8211 | \
00833          MAC_PHYCFG2_FMODE_MASK_RT8211 | \
00834          MAC_PHYCFG2_FMODE_COMP_RT8211 | \
00835          MAC_PHYCFG2_GMODE_MASK_RT8211 | \
00836          MAC_PHYCFG2_GMODE_COMP_RT8211 | \
00837          MAC_PHYCFG2_ACT_MASK_RT8211 | \
00838          MAC_PHYCFG2_ACT_COMP_RT8211 | \
00839          MAC_PHYCFG2_QUAL_MASK_RT8211 | \
00840          MAC_PHYCFG2_QUAL_COMP_RT8211)
00841 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
00842         (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
00843          MAC_PHYCFG2_EMODE_COMP_RT8201 | \
00844          MAC_PHYCFG2_FMODE_MASK_RT8201 | \
00845          MAC_PHYCFG2_FMODE_COMP_RT8201 | \
00846          MAC_PHYCFG2_GMODE_MASK_RT8201 | \
00847          MAC_PHYCFG2_GMODE_COMP_RT8201 | \
00848          MAC_PHYCFG2_ACT_MASK_RT8201 | \
00849          MAC_PHYCFG2_ACT_COMP_RT8201 | \
00850          MAC_PHYCFG2_QUAL_MASK_RT8201 | \
00851          MAC_PHYCFG2_QUAL_COMP_RT8201)
00852 #define MAC_EXT_RGMII_MODE              0x000005a8
00853 #define  MAC_RGMII_MODE_TX_ENABLE        0x00000001
00854 #define  MAC_RGMII_MODE_TX_LOWPWR        0x00000002
00855 #define  MAC_RGMII_MODE_TX_RESET         0x00000004
00856 #define  MAC_RGMII_MODE_RX_INT_B         0x00000100
00857 #define  MAC_RGMII_MODE_RX_QUALITY       0x00000200
00858 #define  MAC_RGMII_MODE_RX_ACTIVITY      0x00000400
00859 #define  MAC_RGMII_MODE_RX_ENG_DET       0x00000800
00860 /* 0x5ac --> 0x5b0 unused */
00861 #define SERDES_RX_CTRL                  0x000005b0      /* 5780/5714 only */
00862 #define  SERDES_RX_SIG_DETECT            0x00000400
00863 #define SG_DIG_CTRL                     0x000005b0
00864 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
00865 #define  SG_DIG_SOFT_RESET               0x40000000
00866 #define  SG_DIG_DISABLE_LINKRDY          0x20000000
00867 #define  SG_DIG_CRC16_CLEAR_N            0x01000000
00868 #define  SG_DIG_EN10B                    0x00800000
00869 #define  SG_DIG_CLEAR_STATUS             0x00400000
00870 #define  SG_DIG_LOCAL_DUPLEX_STATUS      0x00200000
00871 #define  SG_DIG_LOCAL_LINK_STATUS        0x00100000
00872 #define  SG_DIG_SPEED_STATUS_MASK        0x000c0000
00873 #define  SG_DIG_SPEED_STATUS_SHIFT       18
00874 #define  SG_DIG_JUMBO_PACKET_DISABLE     0x00020000
00875 #define  SG_DIG_RESTART_AUTONEG          0x00010000
00876 #define  SG_DIG_FIBER_MODE               0x00008000
00877 #define  SG_DIG_REMOTE_FAULT_MASK        0x00006000
00878 #define  SG_DIG_PAUSE_MASK               0x00001800
00879 #define  SG_DIG_PAUSE_CAP                0x00000800
00880 #define  SG_DIG_ASYM_PAUSE               0x00001000
00881 #define  SG_DIG_GBIC_ENABLE              0x00000400
00882 #define  SG_DIG_CHECK_END_ENABLE         0x00000200
00883 #define  SG_DIG_SGMII_AUTONEG_TIMER      0x00000100
00884 #define  SG_DIG_CLOCK_PHASE_SELECT       0x00000080
00885 #define  SG_DIG_GMII_INPUT_SELECT        0x00000040
00886 #define  SG_DIG_MRADV_CRC16_SELECT       0x00000020
00887 #define  SG_DIG_COMMA_DETECT_ENABLE      0x00000010
00888 #define  SG_DIG_AUTONEG_TIMER_REDUCE     0x00000008
00889 #define  SG_DIG_AUTONEG_LOW_ENABLE       0x00000004
00890 #define  SG_DIG_REMOTE_LOOPBACK          0x00000002
00891 #define  SG_DIG_LOOPBACK                 0x00000001
00892 #define  SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
00893                               SG_DIG_LOCAL_DUPLEX_STATUS | \
00894                               SG_DIG_LOCAL_LINK_STATUS | \
00895                               (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
00896                               SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
00897 #define SG_DIG_STATUS                   0x000005b4
00898 #define  SG_DIG_CRC16_BUS_MASK           0xffff0000
00899 #define  SG_DIG_PARTNER_FAULT_MASK       0x00600000 /* If !MRADV_CRC16_SELECT */
00900 #define  SG_DIG_PARTNER_ASYM_PAUSE       0x00100000 /* If !MRADV_CRC16_SELECT */
00901 #define  SG_DIG_PARTNER_PAUSE_CAPABLE    0x00080000 /* If !MRADV_CRC16_SELECT */
00902 #define  SG_DIG_PARTNER_HALF_DUPLEX      0x00040000 /* If !MRADV_CRC16_SELECT */
00903 #define  SG_DIG_PARTNER_FULL_DUPLEX      0x00020000 /* If !MRADV_CRC16_SELECT */
00904 #define  SG_DIG_PARTNER_NEXT_PAGE        0x00010000 /* If !MRADV_CRC16_SELECT */
00905 #define  SG_DIG_AUTONEG_STATE_MASK       0x00000ff0
00906 #define  SG_DIG_IS_SERDES                0x00000100
00907 #define  SG_DIG_COMMA_DETECTOR           0x00000008
00908 #define  SG_DIG_MAC_ACK_STATUS           0x00000004
00909 #define  SG_DIG_AUTONEG_COMPLETE         0x00000002
00910 #define  SG_DIG_AUTONEG_ERROR            0x00000001
00911 /* 0x5b8 --> 0x600 unused */
00912 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
00913 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
00914 /* 0x624 --> 0x670 unused */
00915 
00916 #define MAC_RSS_INDIR_TBL_0             0x00000630
00917 
00918 #define MAC_RSS_HASH_KEY_0              0x00000670
00919 #define MAC_RSS_HASH_KEY_1              0x00000674
00920 #define MAC_RSS_HASH_KEY_2              0x00000678
00921 #define MAC_RSS_HASH_KEY_3              0x0000067c
00922 #define MAC_RSS_HASH_KEY_4              0x00000680
00923 #define MAC_RSS_HASH_KEY_5              0x00000684
00924 #define MAC_RSS_HASH_KEY_6              0x00000688
00925 #define MAC_RSS_HASH_KEY_7              0x0000068c
00926 #define MAC_RSS_HASH_KEY_8              0x00000690
00927 #define MAC_RSS_HASH_KEY_9              0x00000694
00928 /* 0x698 --> 0x800 unused */
00929 
00930 #define MAC_TX_STATS_OCTETS             0x00000800
00931 #define MAC_TX_STATS_RESV1              0x00000804
00932 #define MAC_TX_STATS_COLLISIONS         0x00000808
00933 #define MAC_TX_STATS_XON_SENT           0x0000080c
00934 #define MAC_TX_STATS_XOFF_SENT          0x00000810
00935 #define MAC_TX_STATS_RESV2              0x00000814
00936 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
00937 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
00938 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
00939 #define MAC_TX_STATS_DEFERRED           0x00000824
00940 #define MAC_TX_STATS_RESV3              0x00000828
00941 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
00942 #define MAC_TX_STATS_LATE_COL           0x00000830
00943 #define MAC_TX_STATS_RESV4_1            0x00000834
00944 #define MAC_TX_STATS_RESV4_2            0x00000838
00945 #define MAC_TX_STATS_RESV4_3            0x0000083c
00946 #define MAC_TX_STATS_RESV4_4            0x00000840
00947 #define MAC_TX_STATS_RESV4_5            0x00000844
00948 #define MAC_TX_STATS_RESV4_6            0x00000848
00949 #define MAC_TX_STATS_RESV4_7            0x0000084c
00950 #define MAC_TX_STATS_RESV4_8            0x00000850
00951 #define MAC_TX_STATS_RESV4_9            0x00000854
00952 #define MAC_TX_STATS_RESV4_10           0x00000858
00953 #define MAC_TX_STATS_RESV4_11           0x0000085c
00954 #define MAC_TX_STATS_RESV4_12           0x00000860
00955 #define MAC_TX_STATS_RESV4_13           0x00000864
00956 #define MAC_TX_STATS_RESV4_14           0x00000868
00957 #define MAC_TX_STATS_UCAST              0x0000086c
00958 #define MAC_TX_STATS_MCAST              0x00000870
00959 #define MAC_TX_STATS_BCAST              0x00000874
00960 #define MAC_TX_STATS_RESV5_1            0x00000878
00961 #define MAC_TX_STATS_RESV5_2            0x0000087c
00962 #define MAC_RX_STATS_OCTETS             0x00000880
00963 #define MAC_RX_STATS_RESV1              0x00000884
00964 #define MAC_RX_STATS_FRAGMENTS          0x00000888
00965 #define MAC_RX_STATS_UCAST              0x0000088c
00966 #define MAC_RX_STATS_MCAST              0x00000890
00967 #define MAC_RX_STATS_BCAST              0x00000894
00968 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
00969 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
00970 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
00971 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
00972 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
00973 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
00974 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
00975 #define MAC_RX_STATS_JABBERS            0x000008b4
00976 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
00977 /* 0x8bc --> 0xc00 unused */
00978 
00979 /* Send data initiator control registers */
00980 #define SNDDATAI_MODE                   0x00000c00
00981 #define  SNDDATAI_MODE_RESET             0x00000001
00982 #define  SNDDATAI_MODE_ENABLE            0x00000002
00983 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
00984 #define SNDDATAI_STATUS                 0x00000c04
00985 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
00986 #define SNDDATAI_STATSCTRL              0x00000c08
00987 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
00988 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
00989 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
00990 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
00991 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
00992 #define SNDDATAI_STATSENAB              0x00000c0c
00993 #define SNDDATAI_STATSINCMASK           0x00000c10
00994 #define ISO_PKT_TX                      0x00000c20
00995 /* 0xc24 --> 0xc80 unused */
00996 #define SNDDATAI_COS_CNT_0              0x00000c80
00997 #define SNDDATAI_COS_CNT_1              0x00000c84
00998 #define SNDDATAI_COS_CNT_2              0x00000c88
00999 #define SNDDATAI_COS_CNT_3              0x00000c8c
01000 #define SNDDATAI_COS_CNT_4              0x00000c90
01001 #define SNDDATAI_COS_CNT_5              0x00000c94
01002 #define SNDDATAI_COS_CNT_6              0x00000c98
01003 #define SNDDATAI_COS_CNT_7              0x00000c9c
01004 #define SNDDATAI_COS_CNT_8              0x00000ca0
01005 #define SNDDATAI_COS_CNT_9              0x00000ca4
01006 #define SNDDATAI_COS_CNT_10             0x00000ca8
01007 #define SNDDATAI_COS_CNT_11             0x00000cac
01008 #define SNDDATAI_COS_CNT_12             0x00000cb0
01009 #define SNDDATAI_COS_CNT_13             0x00000cb4
01010 #define SNDDATAI_COS_CNT_14             0x00000cb8
01011 #define SNDDATAI_COS_CNT_15             0x00000cbc
01012 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
01013 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
01014 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
01015 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
01016 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
01017 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
01018 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
01019 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
01020 /* 0xce0 --> 0x1000 unused */
01021 
01022 /* Send data completion control registers */
01023 #define SNDDATAC_MODE                   0x00001000
01024 #define  SNDDATAC_MODE_RESET             0x00000001
01025 #define  SNDDATAC_MODE_ENABLE            0x00000002
01026 #define  SNDDATAC_MODE_CDELAY            0x00000010
01027 /* 0x1004 --> 0x1400 unused */
01028 
01029 /* Send BD ring selector */
01030 #define SNDBDS_MODE                     0x00001400
01031 #define  SNDBDS_MODE_RESET               0x00000001
01032 #define  SNDBDS_MODE_ENABLE              0x00000002
01033 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
01034 #define SNDBDS_STATUS                   0x00001404
01035 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
01036 #define SNDBDS_HWDIAG                   0x00001408
01037 /* 0x140c --> 0x1440 */
01038 #define SNDBDS_SEL_CON_IDX_0            0x00001440
01039 #define SNDBDS_SEL_CON_IDX_1            0x00001444
01040 #define SNDBDS_SEL_CON_IDX_2            0x00001448
01041 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
01042 #define SNDBDS_SEL_CON_IDX_4            0x00001450
01043 #define SNDBDS_SEL_CON_IDX_5            0x00001454
01044 #define SNDBDS_SEL_CON_IDX_6            0x00001458
01045 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
01046 #define SNDBDS_SEL_CON_IDX_8            0x00001460
01047 #define SNDBDS_SEL_CON_IDX_9            0x00001464
01048 #define SNDBDS_SEL_CON_IDX_10           0x00001468
01049 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
01050 #define SNDBDS_SEL_CON_IDX_12           0x00001470
01051 #define SNDBDS_SEL_CON_IDX_13           0x00001474
01052 #define SNDBDS_SEL_CON_IDX_14           0x00001478
01053 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
01054 /* 0x1480 --> 0x1800 unused */
01055 
01056 /* Send BD initiator control registers */
01057 #define SNDBDI_MODE                     0x00001800
01058 #define  SNDBDI_MODE_RESET               0x00000001
01059 #define  SNDBDI_MODE_ENABLE              0x00000002
01060 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
01061 #define  SNDBDI_MODE_MULTI_TXQ_EN        0x00000020
01062 #define SNDBDI_STATUS                   0x00001804
01063 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
01064 #define SNDBDI_IN_PROD_IDX_0            0x00001808
01065 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
01066 #define SNDBDI_IN_PROD_IDX_2            0x00001810
01067 #define SNDBDI_IN_PROD_IDX_3            0x00001814
01068 #define SNDBDI_IN_PROD_IDX_4            0x00001818
01069 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
01070 #define SNDBDI_IN_PROD_IDX_6            0x00001820
01071 #define SNDBDI_IN_PROD_IDX_7            0x00001824
01072 #define SNDBDI_IN_PROD_IDX_8            0x00001828
01073 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
01074 #define SNDBDI_IN_PROD_IDX_10           0x00001830
01075 #define SNDBDI_IN_PROD_IDX_11           0x00001834
01076 #define SNDBDI_IN_PROD_IDX_12           0x00001838
01077 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
01078 #define SNDBDI_IN_PROD_IDX_14           0x00001840
01079 #define SNDBDI_IN_PROD_IDX_15           0x00001844
01080 /* 0x1848 --> 0x1c00 unused */
01081 
01082 /* Send BD completion control registers */
01083 #define SNDBDC_MODE                     0x00001c00
01084 #define SNDBDC_MODE_RESET                0x00000001
01085 #define SNDBDC_MODE_ENABLE               0x00000002
01086 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
01087 /* 0x1c04 --> 0x2000 unused */
01088 
01089 /* Receive list placement control registers */
01090 #define RCVLPC_MODE                     0x00002000
01091 #define  RCVLPC_MODE_RESET               0x00000001
01092 #define  RCVLPC_MODE_ENABLE              0x00000002
01093 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
01094 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
01095 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
01096 #define RCVLPC_STATUS                   0x00002004
01097 #define  RCVLPC_STATUS_CLASS0            0x00000004
01098 #define  RCVLPC_STATUS_MAPOOR            0x00000008
01099 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
01100 #define RCVLPC_LOCK                     0x00002008
01101 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
01102 #define  RCVLPC_LOCK_REQ_SHIFT           0
01103 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
01104 #define  RCVLPC_LOCK_GRANT_SHIFT         16
01105 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
01106 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
01107 #define RCVLPC_CONFIG                   0x00002010
01108 #define RCVLPC_STATSCTRL                0x00002014
01109 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
01110 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
01111 #define RCVLPC_STATS_ENABLE             0x00002018
01112 #define  RCVLPC_STATSENAB_ASF_FIX        0x00000002
01113 #define  RCVLPC_STATSENAB_DACK_FIX       0x00040000
01114 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
01115 #define RCVLPC_STATS_INCMASK            0x0000201c
01116 /* 0x2020 --> 0x2100 unused */
01117 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
01118 #define  SELLST_TAIL                    0x00000004
01119 #define  SELLST_CONT                    0x00000008
01120 #define  SELLST_UNUSED                  0x0000000c
01121 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
01122 #define RCVLPC_DROP_FILTER_CNT          0x00002240
01123 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
01124 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
01125 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
01126 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
01127 #define RCVLPC_IN_ERRORS_CNT            0x00002254
01128 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
01129 /* 0x225c --> 0x2400 unused */
01130 
01131 /* Receive Data and Receive BD Initiator Control */
01132 #define RCVDBDI_MODE                    0x00002400
01133 #define  RCVDBDI_MODE_RESET              0x00000001
01134 #define  RCVDBDI_MODE_ENABLE             0x00000002
01135 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
01136 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
01137 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
01138 #define  RCVDBDI_MODE_LRG_RING_SZ        0x00010000
01139 #define RCVDBDI_STATUS                  0x00002404
01140 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
01141 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
01142 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
01143 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
01144 /* 0x240c --> 0x2440 unused */
01145 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
01146 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
01147 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
01148 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
01149 #define RCVDBDI_STD_CON_IDX             0x00002474
01150 #define RCVDBDI_MINI_CON_IDX            0x00002478
01151 /* 0x247c --> 0x2480 unused */
01152 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
01153 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
01154 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
01155 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
01156 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
01157 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
01158 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
01159 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
01160 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
01161 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
01162 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
01163 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
01164 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
01165 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
01166 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
01167 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
01168 #define RCVDBDI_HWDIAG                  0x000024c0
01169 /* 0x24c4 --> 0x2800 unused */
01170 
01171 /* Receive Data Completion Control */
01172 #define RCVDCC_MODE                     0x00002800
01173 #define  RCVDCC_MODE_RESET               0x00000001
01174 #define  RCVDCC_MODE_ENABLE              0x00000002
01175 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
01176 /* 0x2804 --> 0x2c00 unused */
01177 
01178 /* Receive BD Initiator Control Registers */
01179 #define RCVBDI_MODE                     0x00002c00
01180 #define  RCVBDI_MODE_RESET               0x00000001
01181 #define  RCVBDI_MODE_ENABLE              0x00000002
01182 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
01183 #define RCVBDI_STATUS                   0x00002c04
01184 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
01185 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
01186 #define RCVBDI_STD_PROD_IDX             0x00002c0c
01187 #define RCVBDI_MINI_PROD_IDX            0x00002c10
01188 #define RCVBDI_MINI_THRESH              0x00002c14
01189 #define RCVBDI_STD_THRESH               0x00002c18
01190 #define RCVBDI_JUMBO_THRESH             0x00002c1c
01191 /* 0x2c20 --> 0x2d00 unused */
01192 
01193 #define STD_REPLENISH_LWM               0x00002d00
01194 #define JMB_REPLENISH_LWM               0x00002d04
01195 /* 0x2d08 --> 0x3000 unused */
01196 
01197 /* Receive BD Completion Control Registers */
01198 #define RCVCC_MODE                      0x00003000
01199 #define  RCVCC_MODE_RESET                0x00000001
01200 #define  RCVCC_MODE_ENABLE               0x00000002
01201 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
01202 #define RCVCC_STATUS                    0x00003004
01203 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
01204 #define RCVCC_JUMP_PROD_IDX             0x00003008
01205 #define RCVCC_STD_PROD_IDX              0x0000300c
01206 #define RCVCC_MINI_PROD_IDX             0x00003010
01207 /* 0x3014 --> 0x3400 unused */
01208 
01209 /* Receive list selector control registers */
01210 #define RCVLSC_MODE                     0x00003400
01211 #define  RCVLSC_MODE_RESET               0x00000001
01212 #define  RCVLSC_MODE_ENABLE              0x00000002
01213 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
01214 #define RCVLSC_STATUS                   0x00003404
01215 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
01216 /* 0x3408 --> 0x3600 unused */
01217 
01218 /* CPMU registers */
01219 #define TG3_CPMU_CTRL                   0x00003600
01220 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
01221 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
01222 #define  CPMU_CTRL_LINK_SPEED_MODE       0x00004000
01223 #define  CPMU_CTRL_GPHY_10MB_RXONLY      0x00010000
01224 #define TG3_CPMU_LSPD_10MB_CLK          0x00003604
01225 #define  CPMU_LSPD_10MB_MACCLK_MASK      0x001f0000
01226 #define  CPMU_LSPD_10MB_MACCLK_6_25      0x00130000
01227 /* 0x3608 --> 0x360c unused */
01228 
01229 #define TG3_CPMU_LSPD_1000MB_CLK        0x0000360c
01230 #define  CPMU_LSPD_1000MB_MACCLK_62_5    0x00000000
01231 #define  CPMU_LSPD_1000MB_MACCLK_12_5    0x00110000
01232 #define  CPMU_LSPD_1000MB_MACCLK_MASK    0x001f0000
01233 #define TG3_CPMU_LNK_AWARE_PWRMD        0x00003610
01234 #define  CPMU_LNK_AWARE_MACCLK_MASK      0x001f0000
01235 #define  CPMU_LNK_AWARE_MACCLK_6_25      0x00130000
01236 
01237 #define TG3_CPMU_D0_CLCK_POLICY         0x00003614
01238 /* 0x3614 --> 0x361c unused */
01239 
01240 #define TG3_CPMU_HST_ACC                0x0000361c
01241 #define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
01242 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
01243 /* 0x3620 --> 0x3630 unused */
01244 
01245 #define TG3_CPMU_CLCK_ORIDE             0x00003624
01246 #define  CPMU_CLCK_ORIDE_MAC_ORIDE_EN    0x80000000
01247 
01248 #define TG3_CPMU_CLCK_ORIDE_EN          0x00003628
01249 #define  CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN       0x00002000
01250 
01251 #define TG3_CPMU_CLCK_STAT              0x00003630
01252 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
01253 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
01254 #define  CPMU_CLCK_STAT_MAC_CLCK_12_5    0x00110000
01255 #define  CPMU_CLCK_STAT_MAC_CLCK_6_25    0x00130000
01256 /* 0x3634 --> 0x365c unused */
01257 
01258 #define TG3_CPMU_MUTEX_REQ              0x0000365c
01259 #define  CPMU_MUTEX_REQ_DRIVER           0x00001000
01260 #define TG3_CPMU_MUTEX_GNT              0x00003660
01261 #define  CPMU_MUTEX_GNT_DRIVER           0x00001000
01262 #define TG3_CPMU_PHY_STRAP              0x00003664
01263 #define TG3_CPMU_PHY_STRAP_IS_SERDES     0x00000020
01264 /* 0x3664 --> 0x36b0 unused */
01265 
01266 #define TG3_CPMU_EEE_MODE               0x000036b0
01267 #define  TG3_CPMU_EEEMD_APE_TX_DET_EN    0x00000004
01268 #define  TG3_CPMU_EEEMD_ERLY_L1_XIT_DET  0x00000008
01269 #define  TG3_CPMU_EEEMD_SND_IDX_DET_EN   0x00000040
01270 #define  TG3_CPMU_EEEMD_LPI_ENABLE       0x00000080
01271 #define  TG3_CPMU_EEEMD_LPI_IN_TX        0x00000100
01272 #define  TG3_CPMU_EEEMD_LPI_IN_RX        0x00000200
01273 #define  TG3_CPMU_EEEMD_EEE_ENABLE       0x00100000
01274 #define TG3_CPMU_EEE_DBTMR1             0x000036b4
01275 #define  TG3_CPMU_DBTMR1_PCIEXIT_2047US  0x07ff0000
01276 #define  TG3_CPMU_DBTMR1_LNKIDLE_2047US  0x000070ff
01277 #define TG3_CPMU_EEE_DBTMR2             0x000036b8
01278 #define  TG3_CPMU_DBTMR2_APE_TX_2047US   0x07ff0000
01279 #define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US  0x000070ff
01280 #define TG3_CPMU_EEE_LNKIDL_CTRL        0x000036bc
01281 #define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0    0x01000000
01282 #define  TG3_CPMU_EEE_LNKIDL_UART_IDL    0x00000004
01283 /* 0x36c0 --> 0x36d0 unused */
01284 
01285 #define TG3_CPMU_EEE_CTRL               0x000036d0
01286 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US   0x0000019d
01287 #define TG3_CPMU_EEE_CTRL_EXIT_36_US     0x00000384
01288 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US   0x000001f8
01289 /* 0x36d4 --> 0x3800 unused */
01290 
01291 /* Mbuf cluster free registers */
01292 #define MBFREE_MODE                     0x00003800
01293 #define  MBFREE_MODE_RESET               0x00000001
01294 #define  MBFREE_MODE_ENABLE              0x00000002
01295 #define MBFREE_STATUS                   0x00003804
01296 /* 0x3808 --> 0x3c00 unused */
01297 
01298 /* Host coalescing control registers */
01299 #define HOSTCC_MODE                     0x00003c00
01300 #define  HOSTCC_MODE_RESET               0x00000001
01301 #define  HOSTCC_MODE_ENABLE              0x00000002
01302 #define  HOSTCC_MODE_ATTN                0x00000004
01303 #define  HOSTCC_MODE_NOW                 0x00000008
01304 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
01305 #define  HOSTCC_MODE_64BYTE              0x00000080
01306 #define  HOSTCC_MODE_32BYTE              0x00000100
01307 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
01308 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
01309 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
01310 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
01311 #define  HOSTCC_MODE_COAL_VEC1_NOW       0x00002000
01312 #define HOSTCC_STATUS                   0x00003c04
01313 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
01314 #define HOSTCC_RXCOL_TICKS              0x00003c08
01315 #define  LOW_RXCOL_TICKS                 0x00000032
01316 #define  LOW_RXCOL_TICKS_CLRTCKS         0x00000014
01317 #define  DEFAULT_RXCOL_TICKS             0x00000048
01318 #define  HIGH_RXCOL_TICKS                0x00000096
01319 #define  MAX_RXCOL_TICKS                 0x000003ff
01320 #define HOSTCC_TXCOL_TICKS              0x00003c0c
01321 #define  LOW_TXCOL_TICKS                 0x00000096
01322 #define  LOW_TXCOL_TICKS_CLRTCKS         0x00000048
01323 #define  DEFAULT_TXCOL_TICKS             0x0000012c
01324 #define  HIGH_TXCOL_TICKS                0x00000145
01325 #define  MAX_TXCOL_TICKS                 0x000003ff
01326 #define HOSTCC_RXMAX_FRAMES             0x00003c10
01327 #define  LOW_RXMAX_FRAMES                0x00000005
01328 #define  DEFAULT_RXMAX_FRAMES            0x00000008
01329 #define  HIGH_RXMAX_FRAMES               0x00000012
01330 #define  MAX_RXMAX_FRAMES                0x000000ff
01331 #define HOSTCC_TXMAX_FRAMES             0x00003c14
01332 #define  LOW_TXMAX_FRAMES                0x00000035
01333 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
01334 #define  HIGH_TXMAX_FRAMES               0x00000052
01335 #define  MAX_TXMAX_FRAMES                0x000000ff
01336 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
01337 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
01338 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
01339 #define  MAX_RXCOAL_TICK_INT             0x000003ff
01340 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
01341 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
01342 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
01343 #define  MAX_TXCOAL_TICK_INT             0x000003ff
01344 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
01345 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
01346 #define  MAX_RXCOAL_MAXF_INT             0x000000ff
01347 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
01348 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
01349 #define  MAX_TXCOAL_MAXF_INT             0x000000ff
01350 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
01351 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
01352 #define  MAX_STAT_COAL_TICKS             0xd693d400
01353 #define  MIN_STAT_COAL_TICKS             0x00000064
01354 /* 0x3c2c --> 0x3c30 unused */
01355 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
01356 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
01357 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
01358 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
01359 #define HOSTCC_FLOW_ATTN                0x00003c48
01360 #define HOSTCC_FLOW_ATTN_MBUF_LWM        0x00000040
01361 /* 0x3c4c --> 0x3c50 unused */
01362 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
01363 #define HOSTCC_STD_CON_IDX              0x00003c54
01364 #define HOSTCC_MINI_CON_IDX             0x00003c58
01365 /* 0x3c5c --> 0x3c80 unused */
01366 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
01367 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
01368 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
01369 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
01370 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
01371 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
01372 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
01373 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
01374 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
01375 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
01376 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
01377 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
01378 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
01379 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
01380 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
01381 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
01382 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
01383 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
01384 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
01385 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
01386 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
01387 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
01388 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
01389 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
01390 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
01391 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
01392 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
01393 #define HOSTCC_SND_CON_IDX_11           0x00003cec
01394 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
01395 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
01396 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
01397 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
01398 #define HOSTCC_STATBLCK_RING1           0x00003d00
01399 /* 0x3d00 --> 0x3d80 unused */
01400 
01401 #define HOSTCC_RXCOL_TICKS_VEC1         0x00003d80
01402 #define HOSTCC_TXCOL_TICKS_VEC1         0x00003d84
01403 #define HOSTCC_RXMAX_FRAMES_VEC1        0x00003d88
01404 #define HOSTCC_TXMAX_FRAMES_VEC1        0x00003d8c
01405 #define HOSTCC_RXCOAL_MAXF_INT_VEC1     0x00003d90
01406 #define HOSTCC_TXCOAL_MAXF_INT_VEC1     0x00003d94
01407 /* 0x3d98 --> 0x4000 unused */
01408 
01409 /* Memory arbiter control registers */
01410 #define MEMARB_MODE                     0x00004000
01411 #define  MEMARB_MODE_RESET               0x00000001
01412 #define  MEMARB_MODE_ENABLE              0x00000002
01413 #define MEMARB_STATUS                   0x00004004
01414 #define MEMARB_TRAP_ADDR_LOW            0x00004008
01415 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
01416 /* 0x4010 --> 0x4400 unused */
01417 
01418 /* Buffer manager control registers */
01419 #define BUFMGR_MODE                     0x00004400
01420 #define  BUFMGR_MODE_RESET               0x00000001
01421 #define  BUFMGR_MODE_ENABLE              0x00000002
01422 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
01423 #define  BUFMGR_MODE_BM_TEST             0x00000008
01424 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
01425 #define  BUFMGR_MODE_NO_TX_UNDERRUN      0x80000000
01426 #define BUFMGR_STATUS                   0x00004404
01427 #define  BUFMGR_STATUS_ERROR             0x00000004
01428 #define  BUFMGR_STATUS_MBLOW             0x00000010
01429 #define BUFMGR_MB_POOL_ADDR             0x00004408
01430 #define BUFMGR_MB_POOL_SIZE             0x0000440c
01431 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
01432 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
01433 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
01434 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
01435 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
01436 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
01437 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
01438 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
01439 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
01440 #define  DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
01441 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
01442 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
01443 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
01444 #define BUFMGR_MB_HIGH_WATER            0x00004418
01445 #define  DEFAULT_MB_HIGH_WATER           0x00000060
01446 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
01447 #define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
01448 #define  DEFAULT_MB_HIGH_WATER_57765     0x000000a0
01449 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
01450 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
01451 #define  DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
01452 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
01453 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
01454 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
01455 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
01456 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
01457 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
01458 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
01459 #define BUFMGR_DMA_LOW_WATER            0x00004434
01460 #define  DEFAULT_DMA_LOW_WATER           0x00000005
01461 #define BUFMGR_DMA_HIGH_WATER           0x00004438
01462 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
01463 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
01464 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
01465 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
01466 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
01467 #define BUFMGR_HWDIAG_0                 0x0000444c
01468 #define BUFMGR_HWDIAG_1                 0x00004450
01469 #define BUFMGR_HWDIAG_2                 0x00004454
01470 /* 0x4458 --> 0x4800 unused */
01471 
01472 /* Read DMA control registers */
01473 #define RDMAC_MODE                      0x00004800
01474 #define  RDMAC_MODE_RESET                0x00000001
01475 #define  RDMAC_MODE_ENABLE               0x00000002
01476 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
01477 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
01478 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
01479 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
01480 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
01481 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
01482 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
01483 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
01484 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
01485 #define  RDMAC_MODE_BD_SBD_CRPT_ENAB     0x00000800
01486 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
01487 #define  RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000
01488 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000
01489 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
01490 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
01491 #define  RDMAC_MODE_MULT_DMA_RD_DIS      0x01000000
01492 #define  RDMAC_MODE_IPV4_LSO_EN          0x08000000
01493 #define  RDMAC_MODE_IPV6_LSO_EN          0x10000000
01494 #define  RDMAC_MODE_H2BNC_VLAN_DET       0x20000000
01495 #define RDMAC_STATUS                    0x00004804
01496 #define  RDMAC_STATUS_TGTABORT           0x00000004
01497 #define  RDMAC_STATUS_MSTABORT           0x00000008
01498 #define  RDMAC_STATUS_PARITYERR          0x00000010
01499 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
01500 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
01501 #define  RDMAC_STATUS_FIFOURUN           0x00000080
01502 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
01503 #define  RDMAC_STATUS_LNGREAD            0x00000200
01504 /* 0x4808 --> 0x4900 unused */
01505 
01506 #define TG3_RDMA_RSRVCTRL_REG           0x00004900
01507 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX  0x00000004
01508 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K  0x00000c00
01509 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK  0x00000ff0
01510 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K  0x000c0000
01511 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK  0x000ff000
01512 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B    0x28000000
01513 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK    0xffe00000
01514 /* 0x4904 --> 0x4910 unused */
01515 
01516 #define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
01517 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
01518 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
01519 /* 0x4914 --> 0x4c00 unused */
01520 
01521 /* Write DMA control registers */
01522 #define WDMAC_MODE                      0x00004c00
01523 #define  WDMAC_MODE_RESET                0x00000001
01524 #define  WDMAC_MODE_ENABLE               0x00000002
01525 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
01526 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
01527 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
01528 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
01529 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
01530 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
01531 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
01532 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
01533 #define  WDMAC_MODE_RX_ACCEL             0x00000400
01534 #define  WDMAC_MODE_STATUS_TAG_FIX       0x20000000
01535 #define  WDMAC_MODE_BURST_ALL_DATA       0xc0000000
01536 #define WDMAC_STATUS                    0x00004c04
01537 #define  WDMAC_STATUS_TGTABORT           0x00000004
01538 #define  WDMAC_STATUS_MSTABORT           0x00000008
01539 #define  WDMAC_STATUS_PARITYERR          0x00000010
01540 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
01541 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
01542 #define  WDMAC_STATUS_FIFOURUN           0x00000080
01543 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
01544 #define  WDMAC_STATUS_LNGREAD            0x00000200
01545 /* 0x4c08 --> 0x5000 unused */
01546 
01547 /* Per-cpu register offsets (arm9) */
01548 #define CPU_MODE                        0x00000000
01549 #define  CPU_MODE_RESET                  0x00000001
01550 #define  CPU_MODE_HALT                   0x00000400
01551 #define CPU_STATE                       0x00000004
01552 #define CPU_EVTMASK                     0x00000008
01553 /* 0xc --> 0x1c reserved */
01554 #define CPU_PC                          0x0000001c
01555 #define CPU_INSN                        0x00000020
01556 #define CPU_SPAD_UFLOW                  0x00000024
01557 #define CPU_WDOG_CLEAR                  0x00000028
01558 #define CPU_WDOG_VECTOR                 0x0000002c
01559 #define CPU_WDOG_PC                     0x00000030
01560 #define CPU_HW_BP                       0x00000034
01561 /* 0x38 --> 0x44 unused */
01562 #define CPU_WDOG_SAVED_STATE            0x00000044
01563 #define CPU_LAST_BRANCH_ADDR            0x00000048
01564 #define CPU_SPAD_UFLOW_SET              0x0000004c
01565 /* 0x50 --> 0x200 unused */
01566 #define CPU_R0                          0x00000200
01567 #define CPU_R1                          0x00000204
01568 #define CPU_R2                          0x00000208
01569 #define CPU_R3                          0x0000020c
01570 #define CPU_R4                          0x00000210
01571 #define CPU_R5                          0x00000214
01572 #define CPU_R6                          0x00000218
01573 #define CPU_R7                          0x0000021c
01574 #define CPU_R8                          0x00000220
01575 #define CPU_R9                          0x00000224
01576 #define CPU_R10                         0x00000228
01577 #define CPU_R11                         0x0000022c
01578 #define CPU_R12                         0x00000230
01579 #define CPU_R13                         0x00000234
01580 #define CPU_R14                         0x00000238
01581 #define CPU_R15                         0x0000023c
01582 #define CPU_R16                         0x00000240
01583 #define CPU_R17                         0x00000244
01584 #define CPU_R18                         0x00000248
01585 #define CPU_R19                         0x0000024c
01586 #define CPU_R20                         0x00000250
01587 #define CPU_R21                         0x00000254
01588 #define CPU_R22                         0x00000258
01589 #define CPU_R23                         0x0000025c
01590 #define CPU_R24                         0x00000260
01591 #define CPU_R25                         0x00000264
01592 #define CPU_R26                         0x00000268
01593 #define CPU_R27                         0x0000026c
01594 #define CPU_R28                         0x00000270
01595 #define CPU_R29                         0x00000274
01596 #define CPU_R30                         0x00000278
01597 #define CPU_R31                         0x0000027c
01598 /* 0x280 --> 0x400 unused */
01599 
01600 #define RX_CPU_BASE                     0x00005000
01601 #define RX_CPU_MODE                     0x00005000
01602 #define RX_CPU_STATE                    0x00005004
01603 #define RX_CPU_PGMCTR                   0x0000501c
01604 #define RX_CPU_HWBKPT                   0x00005034
01605 #define TX_CPU_BASE                     0x00005400
01606 #define TX_CPU_MODE                     0x00005400
01607 #define TX_CPU_STATE                    0x00005404
01608 #define TX_CPU_PGMCTR                   0x0000541c
01609 
01610 #define VCPU_STATUS                     0x00005100
01611 #define  VCPU_STATUS_INIT_DONE           0x04000000
01612 #define  VCPU_STATUS_DRV_RESET           0x08000000
01613 
01614 #define VCPU_CFGSHDW                    0x00005104
01615 #define  VCPU_CFGSHDW_WOL_ENABLE         0x00000001
01616 #define  VCPU_CFGSHDW_WOL_MAGPKT         0x00000004
01617 #define  VCPU_CFGSHDW_ASPM_DBNC          0x00001000
01618 
01619 /* Mailboxes */
01620 #define GRCMBOX_BASE                    0x00005600
01621 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
01622 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
01623 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
01624 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
01625 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
01626 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
01627 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
01628 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
01629 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
01630 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
01631 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
01632 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
01633 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
01634 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
01635 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
01636 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
01637 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
01638 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
01639 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
01640 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
01641 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
01642 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
01643 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
01644 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
01645 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
01646 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
01647 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
01648 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
01649 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
01650 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
01651 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
01652 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
01653 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
01654 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
01655 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
01656 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
01657 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
01658 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
01659 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
01660 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
01661 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
01662 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
01663 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
01664 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
01665 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
01666 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
01667 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
01668 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
01669 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
01670 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
01671 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
01672 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
01673 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
01674 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
01675 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
01676 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
01677 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
01678 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
01679 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
01680 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
01681 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
01682 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
01683 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
01684 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
01685 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
01686 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
01687 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
01688 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
01689 /* 0x5a10 --> 0x5c00 */
01690 
01691 /* Flow Through queues */
01692 #define FTQ_RESET                       0x00005c00
01693 /* 0x5c04 --> 0x5c10 unused */
01694 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
01695 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
01696 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
01697 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
01698 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
01699 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
01700 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
01701 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
01702 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
01703 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
01704 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
01705 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
01706 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
01707 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
01708 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
01709 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
01710 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
01711 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
01712 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
01713 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
01714 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
01715 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
01716 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
01717 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
01718 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
01719 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
01720 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
01721 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
01722 #define FTQ_SWTYPE1_CTL                 0x00005c80
01723 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
01724 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
01725 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
01726 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
01727 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
01728 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
01729 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
01730 #define FTQ_HOST_COAL_CTL               0x00005ca0
01731 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
01732 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
01733 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
01734 #define FTQ_MAC_TX_CTL                  0x00005cb0
01735 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
01736 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
01737 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
01738 #define FTQ_MB_FREE_CTL                 0x00005cc0
01739 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
01740 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
01741 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
01742 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
01743 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
01744 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
01745 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
01746 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
01747 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
01748 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
01749 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
01750 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
01751 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
01752 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
01753 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
01754 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
01755 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
01756 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
01757 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
01758 #define FTQ_SWTYPE2_CTL                 0x00005d10
01759 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
01760 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
01761 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
01762 /* 0x5d20 --> 0x6000 unused */
01763 
01764 /* Message signaled interrupt registers */
01765 #define MSGINT_MODE                     0x00006000
01766 #define  MSGINT_MODE_RESET               0x00000001
01767 #define  MSGINT_MODE_ENABLE              0x00000002
01768 #define  MSGINT_MODE_ONE_SHOT_DISABLE    0x00000020
01769 #define  MSGINT_MODE_MULTIVEC_EN         0x00000080
01770 #define MSGINT_STATUS                   0x00006004
01771 #define  MSGINT_STATUS_MSI_REQ           0x00000001
01772 #define MSGINT_FIFO                     0x00006008
01773 /* 0x600c --> 0x6400 unused */
01774 
01775 /* DMA completion registers */
01776 #define DMAC_MODE                       0x00006400
01777 #define  DMAC_MODE_RESET                 0x00000001
01778 #define  DMAC_MODE_ENABLE                0x00000002
01779 /* 0x6404 --> 0x6800 unused */
01780 
01781 /* GRC registers */
01782 #define GRC_MODE                        0x00006800
01783 #define  GRC_MODE_UPD_ON_COAL           0x00000001
01784 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
01785 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
01786 #define  GRC_MODE_BSWAP_DATA            0x00000010
01787 #define  GRC_MODE_WSWAP_DATA            0x00000020
01788 #define  GRC_MODE_BYTE_SWAP_B2HRX_DATA  0x00000040
01789 #define  GRC_MODE_WORD_SWAP_B2HRX_DATA  0x00000080
01790 #define  GRC_MODE_SPLITHDR              0x00000100
01791 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
01792 #define  GRC_MODE_INCL_CRC              0x00000400
01793 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
01794 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
01795 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
01796 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
01797 #define  GRC_MODE_B2HRX_ENABLE          0x00008000
01798 #define  GRC_MODE_HOST_STACKUP          0x00010000
01799 #define  GRC_MODE_HOST_SENDBDS          0x00020000
01800 #define  GRC_MODE_HTX2B_ENABLE          0x00040000
01801 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
01802 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
01803 #define  GRC_MODE_PCIE_TL_SEL           0x00000000
01804 #define  GRC_MODE_PCIE_PL_SEL           0x00400000
01805 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
01806 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
01807 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
01808 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
01809 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
01810 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
01811 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
01812 #define  GRC_MODE_PCIE_DL_SEL           0x20000000
01813 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
01814 #define  GRC_MODE_PCIE_HI_1K_EN         0x80000000
01815 #define  GRC_MODE_PCIE_PORT_MASK        (GRC_MODE_PCIE_TL_SEL | \
01816                                          GRC_MODE_PCIE_PL_SEL | \
01817                                          GRC_MODE_PCIE_DL_SEL | \
01818                                          GRC_MODE_PCIE_HI_1K_EN)
01819 #define GRC_MISC_CFG                    0x00006804
01820 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
01821 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
01822 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
01823 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
01824 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
01825 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
01826 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
01827 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
01828 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
01829 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
01830 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
01831 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
01832 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
01833 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
01834 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
01835 #define  GRC_MISC_CFG_EPHY_IDDQ         0x00200000
01836 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
01837 #define GRC_LOCAL_CTRL                  0x00006808
01838 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
01839 #define  GRC_LCLCTRL_CLEARINT           0x00000002
01840 #define  GRC_LCLCTRL_SETINT             0x00000004
01841 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
01842 #define  GRC_LCLCTRL_GPIO_UART_SEL      0x00000010      /* 5755 only */
01843 #define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
01844 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
01845 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
01846 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
01847 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
01848 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
01849 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
01850 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
01851 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
01852 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
01853 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
01854 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
01855 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
01856 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
01857 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
01858 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
01859 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
01860 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
01861 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
01862 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
01863 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
01864 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
01865 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
01866 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
01867 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
01868 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
01869 #define GRC_TIMER                       0x0000680c
01870 #define GRC_RX_CPU_EVENT                0x00006810
01871 #define  GRC_RX_CPU_DRIVER_EVENT        0x00004000
01872 #define GRC_RX_TIMER_REF                0x00006814
01873 #define GRC_RX_CPU_SEM                  0x00006818
01874 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
01875 #define GRC_TX_CPU_EVENT                0x00006820
01876 #define GRC_TX_TIMER_REF                0x00006824
01877 #define GRC_TX_CPU_SEM                  0x00006828
01878 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
01879 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
01880 #define GRC_EEPROM_ADDR                 0x00006838
01881 #define  EEPROM_ADDR_WRITE              0x00000000
01882 #define  EEPROM_ADDR_READ               0x80000000
01883 #define  EEPROM_ADDR_COMPLETE           0x40000000
01884 #define  EEPROM_ADDR_FSM_RESET          0x20000000
01885 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
01886 #define  EEPROM_ADDR_DEVID_SHIFT        26
01887 #define  EEPROM_ADDR_START              0x02000000
01888 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
01889 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
01890 #define  EEPROM_ADDR_ADDR_SHIFT         0
01891 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
01892 #define  EEPROM_CHIP_SIZE               (64 * 1024)
01893 #define GRC_EEPROM_DATA                 0x0000683c
01894 #define GRC_EEPROM_CTRL                 0x00006840
01895 #define GRC_MDI_CTRL                    0x00006844
01896 #define GRC_SEEPROM_DELAY               0x00006848
01897 /* 0x684c --> 0x6890 unused */
01898 #define GRC_VCPU_EXT_CTRL               0x00006890
01899 #define GRC_VCPU_EXT_CTRL_HALT_CPU       0x00400000
01900 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL    0x20000000
01901 #define GRC_FASTBOOT_PC                 0x00006894      /* 5752, 5755, 5787 */
01902 
01903 /* 0x6c00 --> 0x7000 unused */
01904 
01905 /* NVRAM Control registers */
01906 #define NVRAM_CMD                       0x00007000
01907 #define  NVRAM_CMD_RESET                 0x00000001
01908 #define  NVRAM_CMD_DONE                  0x00000008
01909 #define  NVRAM_CMD_GO                    0x00000010
01910 #define  NVRAM_CMD_WR                    0x00000020
01911 #define  NVRAM_CMD_RD                    0x00000000
01912 #define  NVRAM_CMD_ERASE                 0x00000040
01913 #define  NVRAM_CMD_FIRST                 0x00000080
01914 #define  NVRAM_CMD_LAST                  0x00000100
01915 #define  NVRAM_CMD_WREN                  0x00010000
01916 #define  NVRAM_CMD_WRDI                  0x00020000
01917 #define NVRAM_STAT                      0x00007004
01918 #define NVRAM_WRDATA                    0x00007008
01919 #define NVRAM_ADDR                      0x0000700c
01920 #define  NVRAM_ADDR_MSK                 0x00ffffff
01921 #define NVRAM_RDDATA                    0x00007010
01922 #define NVRAM_CFG1                      0x00007014
01923 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
01924 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
01925 #define  NVRAM_CFG1_PASS_THRU            0x00000004
01926 #define  NVRAM_CFG1_STATUS_BITS          0x00000070
01927 #define  NVRAM_CFG1_BIT_BANG             0x00000008
01928 #define  NVRAM_CFG1_FLASH_SIZE           0x02000000
01929 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
01930 #define  NVRAM_CFG1_VENDOR_MASK          0x03000003
01931 #define  FLASH_VENDOR_ATMEL_EEPROM       0x02000000
01932 #define  FLASH_VENDOR_ATMEL_FLASH_BUFFERED       0x02000003
01933 #define  FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED     0x00000003
01934 #define  FLASH_VENDOR_ST                         0x03000001
01935 #define  FLASH_VENDOR_SAIFUN             0x01000003
01936 #define  FLASH_VENDOR_SST_SMALL          0x00000001
01937 #define  FLASH_VENDOR_SST_LARGE          0x02000001
01938 #define  NVRAM_CFG1_5752VENDOR_MASK      0x03c00003
01939 #define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ     0x00000000
01940 #define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ    0x02000000
01941 #define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
01942 #define  FLASH_5752VENDOR_ST_M45PE10     0x02400000
01943 #define  FLASH_5752VENDOR_ST_M45PE20     0x02400002
01944 #define  FLASH_5752VENDOR_ST_M45PE40     0x02400001
01945 #define  FLASH_5755VENDOR_ATMEL_FLASH_1  0x03400001
01946 #define  FLASH_5755VENDOR_ATMEL_FLASH_2  0x03400002
01947 #define  FLASH_5755VENDOR_ATMEL_FLASH_3  0x03400000
01948 #define  FLASH_5755VENDOR_ATMEL_FLASH_4  0x00000003
01949 #define  FLASH_5755VENDOR_ATMEL_FLASH_5  0x02000003
01950 #define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ     0x03c00003
01951 #define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ    0x03c00002
01952 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ     0x03000003
01953 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
01954 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
01955 #define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ    0x02000000
01956 #define  FLASH_5761VENDOR_ATMEL_MDB021D  0x00800003
01957 #define  FLASH_5761VENDOR_ATMEL_MDB041D  0x00800000
01958 #define  FLASH_5761VENDOR_ATMEL_MDB081D  0x00800002
01959 #define  FLASH_5761VENDOR_ATMEL_MDB161D  0x00800001
01960 #define  FLASH_5761VENDOR_ATMEL_ADB021D  0x00000003
01961 #define  FLASH_5761VENDOR_ATMEL_ADB041D  0x00000000
01962 #define  FLASH_5761VENDOR_ATMEL_ADB081D  0x00000002
01963 #define  FLASH_5761VENDOR_ATMEL_ADB161D  0x00000001
01964 #define  FLASH_5761VENDOR_ST_M_M45PE20   0x02800001
01965 #define  FLASH_5761VENDOR_ST_M_M45PE40   0x02800000
01966 #define  FLASH_5761VENDOR_ST_M_M45PE80   0x02800002
01967 #define  FLASH_5761VENDOR_ST_M_M45PE16   0x02800003
01968 #define  FLASH_5761VENDOR_ST_A_M45PE20   0x02000001
01969 #define  FLASH_5761VENDOR_ST_A_M45PE40   0x02000000
01970 #define  FLASH_5761VENDOR_ST_A_M45PE80   0x02000002
01971 #define  FLASH_5761VENDOR_ST_A_M45PE16   0x02000003
01972 #define  FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
01973 #define  FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
01974 #define  FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
01975 #define  FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
01976 #define  FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
01977 #define  FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
01978 #define  FLASH_5717VENDOR_ATMEL_EEPROM   0x02000001
01979 #define  FLASH_5717VENDOR_MICRO_EEPROM   0x02000003
01980 #define  FLASH_5717VENDOR_ATMEL_MDB011D  0x01000001
01981 #define  FLASH_5717VENDOR_ATMEL_MDB021D  0x01000003
01982 #define  FLASH_5717VENDOR_ST_M_M25PE10   0x02000000
01983 #define  FLASH_5717VENDOR_ST_M_M25PE20   0x02000002
01984 #define  FLASH_5717VENDOR_ST_M_M45PE10   0x00000001
01985 #define  FLASH_5717VENDOR_ST_M_M45PE20   0x00000003
01986 #define  FLASH_5717VENDOR_ATMEL_ADB011B  0x01400000
01987 #define  FLASH_5717VENDOR_ATMEL_ADB021B  0x01400002
01988 #define  FLASH_5717VENDOR_ATMEL_ADB011D  0x01400001
01989 #define  FLASH_5717VENDOR_ATMEL_ADB021D  0x01400003
01990 #define  FLASH_5717VENDOR_ST_A_M25PE10   0x02400000
01991 #define  FLASH_5717VENDOR_ST_A_M25PE20   0x02400002
01992 #define  FLASH_5717VENDOR_ST_A_M45PE10   0x02400001
01993 #define  FLASH_5717VENDOR_ST_A_M45PE20   0x02400003
01994 #define  FLASH_5717VENDOR_ATMEL_45USPT   0x03400000
01995 #define  FLASH_5717VENDOR_ST_25USPT      0x03400002
01996 #define  FLASH_5717VENDOR_ST_45USPT      0x03400001
01997 #define  FLASH_5720_EEPROM_HD            0x00000001
01998 #define  FLASH_5720_EEPROM_LD            0x00000003
01999 #define  FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
02000 #define  FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
02001 #define  FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
02002 #define  FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
02003 #define  FLASH_5720VENDOR_M_ST_M25PE10   0x02000000
02004 #define  FLASH_5720VENDOR_M_ST_M25PE20   0x02000002
02005 #define  FLASH_5720VENDOR_M_ST_M25PE40   0x02000001
02006 #define  FLASH_5720VENDOR_M_ST_M25PE80   0x02000003
02007 #define  FLASH_5720VENDOR_M_ST_M45PE10   0x03000000
02008 #define  FLASH_5720VENDOR_M_ST_M45PE20   0x03000002
02009 #define  FLASH_5720VENDOR_M_ST_M45PE40   0x03000001
02010 #define  FLASH_5720VENDOR_M_ST_M45PE80   0x03000003
02011 #define  FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
02012 #define  FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
02013 #define  FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
02014 #define  FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
02015 #define  FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
02016 #define  FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
02017 #define  FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
02018 #define  FLASH_5720VENDOR_A_ST_M25PE10   0x02800000
02019 #define  FLASH_5720VENDOR_A_ST_M25PE20   0x02800002
02020 #define  FLASH_5720VENDOR_A_ST_M25PE40   0x02800001
02021 #define  FLASH_5720VENDOR_A_ST_M25PE80   0x02800003
02022 #define  FLASH_5720VENDOR_A_ST_M45PE10   0x02c00000
02023 #define  FLASH_5720VENDOR_A_ST_M45PE20   0x02c00002
02024 #define  FLASH_5720VENDOR_A_ST_M45PE40   0x02c00001
02025 #define  FLASH_5720VENDOR_A_ST_M45PE80   0x02c00003
02026 #define  FLASH_5720VENDOR_ATMEL_45USPT   0x03c00000
02027 #define  FLASH_5720VENDOR_ST_25USPT      0x03c00002
02028 #define  FLASH_5720VENDOR_ST_45USPT      0x03c00001
02029 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
02030 #define  FLASH_5752PAGE_SIZE_256         0x00000000
02031 #define  FLASH_5752PAGE_SIZE_512         0x10000000
02032 #define  FLASH_5752PAGE_SIZE_1K          0x20000000
02033 #define  FLASH_5752PAGE_SIZE_2K          0x30000000
02034 #define  FLASH_5752PAGE_SIZE_4K          0x40000000
02035 #define  FLASH_5752PAGE_SIZE_264         0x50000000
02036 #define  FLASH_5752PAGE_SIZE_528         0x60000000
02037 #define NVRAM_CFG2                      0x00007018
02038 #define NVRAM_CFG3                      0x0000701c
02039 #define NVRAM_SWARB                     0x00007020
02040 #define  SWARB_REQ_SET0                  0x00000001
02041 #define  SWARB_REQ_SET1                  0x00000002
02042 #define  SWARB_REQ_SET2                  0x00000004
02043 #define  SWARB_REQ_SET3                  0x00000008
02044 #define  SWARB_REQ_CLR0                  0x00000010
02045 #define  SWARB_REQ_CLR1                  0x00000020
02046 #define  SWARB_REQ_CLR2                  0x00000040
02047 #define  SWARB_REQ_CLR3                  0x00000080
02048 #define  SWARB_GNT0                      0x00000100
02049 #define  SWARB_GNT1                      0x00000200
02050 #define  SWARB_GNT2                      0x00000400
02051 #define  SWARB_GNT3                      0x00000800
02052 #define  SWARB_REQ0                      0x00001000
02053 #define  SWARB_REQ1                      0x00002000
02054 #define  SWARB_REQ2                      0x00004000
02055 #define  SWARB_REQ3                      0x00008000
02056 #define NVRAM_ACCESS                    0x00007024
02057 #define  ACCESS_ENABLE                   0x00000001
02058 #define  ACCESS_WR_ENABLE                0x00000002
02059 #define NVRAM_WRITE1                    0x00007028
02060 /* 0x702c unused */
02061 
02062 #define NVRAM_ADDR_LOCKOUT              0x00007030
02063 /* 0x7034 --> 0x7500 unused */
02064 
02065 #define OTP_MODE                        0x00007500
02066 #define OTP_MODE_OTP_THRU_GRC            0x00000001
02067 #define OTP_CTRL                        0x00007504
02068 #define OTP_CTRL_OTP_PROG_ENABLE         0x00200000
02069 #define OTP_CTRL_OTP_CMD_READ            0x00000000
02070 #define OTP_CTRL_OTP_CMD_INIT            0x00000008
02071 #define OTP_CTRL_OTP_CMD_START           0x00000001
02072 #define OTP_STATUS                      0x00007508
02073 #define OTP_STATUS_CMD_DONE              0x00000001
02074 #define OTP_ADDRESS                     0x0000750c
02075 #define OTP_ADDRESS_MAGIC1               0x000000a0
02076 #define OTP_ADDRESS_MAGIC2               0x00000080
02077 /* 0x7510 unused */
02078 
02079 #define OTP_READ_DATA                   0x00007514
02080 /* 0x7518 --> 0x7c04 unused */
02081 
02082 #define PCIE_TRANSACTION_CFG            0x00007c04
02083 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
02084 #define PCIE_TRANS_CFG_LOM               0x00000020
02085 /* 0x7c08 --> 0x7d28 unused */
02086 
02087 #define PCIE_PWR_MGMT_THRESH            0x00007d28
02088 #define PCIE_PWR_MGMT_L1_THRESH_MSK      0x0000ff00
02089 #define PCIE_PWR_MGMT_L1_THRESH_4MS      0x0000ff00
02090 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN    0x01000000
02091 /* 0x7d2c --> 0x7d54 unused */
02092 
02093 #define TG3_PCIE_LNKCTL                 0x00007d54
02094 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_EN    0x00000008
02095 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_DIS   0x00000080
02096 /* 0x7d58 --> 0x7e70 unused */
02097 
02098 #define TG3_PCIE_PHY_TSTCTL             0x00007e2c
02099 #define  TG3_PCIE_PHY_TSTCTL_PCIE10      0x00000040
02100 #define  TG3_PCIE_PHY_TSTCTL_PSCRAM      0x00000020
02101 
02102 #define TG3_PCIE_EIDLE_DELAY            0x00007e70
02103 #define  TG3_PCIE_EIDLE_DELAY_MASK       0x0000001f
02104 #define  TG3_PCIE_EIDLE_DELAY_13_CLKS    0x0000000c
02105 /* 0x7e74 --> 0x8000 unused */
02106 
02107 
02108 /* Alternate PCIE definitions */
02109 #define TG3_PCIE_TLDLPL_PORT            0x00007c00
02110 #define TG3_PCIE_DL_LO_FTSMAX           0x0000000c
02111 #define TG3_PCIE_DL_LO_FTSMAX_MSK       0x000000ff
02112 #define TG3_PCIE_DL_LO_FTSMAX_VAL       0x0000002c
02113 #define TG3_PCIE_PL_LO_PHYCTL1           0x00000004
02114 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN         0x00001000
02115 #define TG3_PCIE_PL_LO_PHYCTL5           0x00000014
02116 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ       0x80000000
02117 
02118 #define TG3_REG_BLK_SIZE                0x00008000
02119 
02120 /* OTP bit definitions */
02121 #define TG3_OTP_AGCTGT_MASK             0x000000e0
02122 #define TG3_OTP_AGCTGT_SHIFT            1
02123 #define TG3_OTP_HPFFLTR_MASK            0x00000300
02124 #define TG3_OTP_HPFFLTR_SHIFT           1
02125 #define TG3_OTP_HPFOVER_MASK            0x00000400
02126 #define TG3_OTP_HPFOVER_SHIFT           1
02127 #define TG3_OTP_LPFDIS_MASK             0x00000800
02128 #define TG3_OTP_LPFDIS_SHIFT            11
02129 #define TG3_OTP_VDAC_MASK               0xff000000
02130 #define TG3_OTP_VDAC_SHIFT              24
02131 #define TG3_OTP_10BTAMP_MASK            0x0000f000
02132 #define TG3_OTP_10BTAMP_SHIFT           8
02133 #define TG3_OTP_ROFF_MASK               0x00e00000
02134 #define TG3_OTP_ROFF_SHIFT              11
02135 #define TG3_OTP_RCOFF_MASK              0x001c0000
02136 #define TG3_OTP_RCOFF_SHIFT             16
02137 
02138 #define TG3_OTP_DEFAULT                 0x286c1640
02139 
02140 
02141 /* Hardware Legacy NVRAM layout */
02142 #define TG3_NVM_VPD_OFF                 0x100
02143 #define TG3_NVM_VPD_LEN                 256
02144 
02145 /* Hardware Selfboot NVRAM layout */
02146 #define TG3_NVM_HWSB_CFG1               0x00000004
02147 #define  TG3_NVM_HWSB_CFG1_MAJMSK       0xf8000000
02148 #define  TG3_NVM_HWSB_CFG1_MAJSFT       27
02149 #define  TG3_NVM_HWSB_CFG1_MINMSK       0x07c00000
02150 #define  TG3_NVM_HWSB_CFG1_MINSFT       22
02151 
02152 #define TG3_EEPROM_MAGIC                0x669955aa
02153 #define TG3_EEPROM_MAGIC_FW             0xa5000000
02154 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
02155 #define TG3_EEPROM_SB_FORMAT_MASK       0x00e00000
02156 #define TG3_EEPROM_SB_FORMAT_1          0x00200000
02157 #define TG3_EEPROM_SB_REVISION_MASK     0x001f0000
02158 #define TG3_EEPROM_SB_REVISION_0        0x00000000
02159 #define TG3_EEPROM_SB_REVISION_2        0x00020000
02160 #define TG3_EEPROM_SB_REVISION_3        0x00030000
02161 #define TG3_EEPROM_SB_REVISION_4        0x00040000
02162 #define TG3_EEPROM_SB_REVISION_5        0x00050000
02163 #define TG3_EEPROM_SB_REVISION_6        0x00060000
02164 #define TG3_EEPROM_MAGIC_HW             0xabcd
02165 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
02166 
02167 #define TG3_NVM_DIR_START               0x18
02168 #define TG3_NVM_DIR_END                 0x78
02169 #define TG3_NVM_DIRENT_SIZE             0xc
02170 #define TG3_NVM_DIRTYPE_SHIFT           24
02171 #define TG3_NVM_DIRTYPE_LENMSK          0x003fffff
02172 #define TG3_NVM_DIRTYPE_ASFINI          1
02173 #define TG3_NVM_DIRTYPE_EXTVPD          20
02174 #define TG3_NVM_PTREV_BCVER             0x94
02175 #define TG3_NVM_BCVER_MAJMSK            0x0000ff00
02176 #define TG3_NVM_BCVER_MAJSFT            8
02177 #define TG3_NVM_BCVER_MINMSK            0x000000ff
02178 
02179 #define TG3_EEPROM_SB_F1R0_EDH_OFF      0x10
02180 #define TG3_EEPROM_SB_F1R2_EDH_OFF      0x14
02181 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
02182 #define TG3_EEPROM_SB_F1R3_EDH_OFF      0x18
02183 #define TG3_EEPROM_SB_F1R4_EDH_OFF      0x1c
02184 #define TG3_EEPROM_SB_F1R5_EDH_OFF      0x20
02185 #define TG3_EEPROM_SB_F1R6_EDH_OFF      0x4c
02186 #define TG3_EEPROM_SB_EDH_MAJ_MASK      0x00000700
02187 #define TG3_EEPROM_SB_EDH_MAJ_SHFT      8
02188 #define TG3_EEPROM_SB_EDH_MIN_MASK      0x000000ff
02189 #define TG3_EEPROM_SB_EDH_BLD_MASK      0x0000f800
02190 #define TG3_EEPROM_SB_EDH_BLD_SHFT      11
02191 
02192 
02193 /* 32K Window into NIC internal memory */
02194 #define NIC_SRAM_WIN_BASE               0x00008000
02195 
02196 /* Offsets into first 32k of NIC internal memory. */
02197 #define NIC_SRAM_PAGE_ZERO              0x00000000
02198 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
02199 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
02200 #define NIC_SRAM_STATS_BLK              0x00000300
02201 #define NIC_SRAM_STATUS_BLK             0x00000b00
02202 
02203 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
02204 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
02205 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
02206 
02207 #define NIC_SRAM_DATA_SIG               0x00000b54
02208 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
02209 
02210 #define NIC_SRAM_DATA_CFG                       0x00000b58
02211 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
02212 #define  NIC_SRAM_DATA_CFG_LED_MODE_MAC          0x00000000
02213 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_1        0x00000004
02214 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_2        0x00000008
02215 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
02216 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
02217 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
02218 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
02219 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
02220 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
02221 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
02222 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
02223 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
02224 #define  NIC_SRAM_DATA_CFG_NO_GPIO2              0x00100000
02225 #define  NIC_SRAM_DATA_CFG_APE_ENABLE            0x00200000
02226 
02227 #define NIC_SRAM_DATA_VER                       0x00000b5c
02228 #define  NIC_SRAM_DATA_VER_SHIFT                 16
02229 
02230 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
02231 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
02232 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
02233 
02234 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
02235 #define  FWCMD_NICDRV_ALIVE              0x00000001
02236 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
02237 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
02238 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
02239 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
02240 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
02241 #define  FWCMD_NICDRV_LINK_UPDATE        0x0000000c
02242 #define  FWCMD_NICDRV_ALIVE2             0x0000000d
02243 #define  FWCMD_NICDRV_ALIVE3             0x0000000e
02244 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
02245 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
02246 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
02247 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
02248 #define  DRV_STATE_START                 0x00000001
02249 #define  DRV_STATE_START_DONE            0x80000001
02250 #define  DRV_STATE_UNLOAD                0x00000002
02251 #define  DRV_STATE_UNLOAD_DONE           0x80000002
02252 #define  DRV_STATE_WOL                   0x00000003
02253 #define  DRV_STATE_SUSPEND               0x00000004
02254 
02255 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
02256 
02257 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
02258 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
02259 
02260 #define NIC_SRAM_WOL_MBOX               0x00000d30
02261 #define  WOL_SIGNATURE                   0x474c0000
02262 #define  WOL_DRV_STATE_SHUTDOWN          0x00000001
02263 #define  WOL_DRV_WOL                     0x00000002
02264 #define  WOL_SET_MAGIC_PKT               0x00000004
02265 
02266 #define NIC_SRAM_DATA_CFG_2             0x00000d38
02267 
02268 #define  NIC_SRAM_DATA_CFG_2_APD_EN      0x00000400
02269 #define  SHASTA_EXT_LED_MODE_MASK        0x00018000
02270 #define  SHASTA_EXT_LED_LEGACY           0x00000000
02271 #define  SHASTA_EXT_LED_SHARED           0x00008000
02272 #define  SHASTA_EXT_LED_MAC              0x00010000
02273 #define  SHASTA_EXT_LED_COMBO            0x00018000
02274 
02275 #define NIC_SRAM_DATA_CFG_3             0x00000d3c
02276 #define  NIC_SRAM_ASPM_DEBOUNCE          0x00000002
02277 
02278 #define NIC_SRAM_DATA_CFG_4             0x00000d60
02279 #define  NIC_SRAM_GMII_MODE              0x00000002
02280 #define  NIC_SRAM_RGMII_INBAND_DISABLE   0x00000004
02281 #define  NIC_SRAM_RGMII_EXT_IBND_RX_EN   0x00000008
02282 #define  NIC_SRAM_RGMII_EXT_IBND_TX_EN   0x00000010
02283 
02284 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
02285 
02286 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
02287 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
02288 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
02289 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
02290 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
02291 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
02292 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
02293 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
02294 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
02295 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
02296 
02297 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700       128
02298 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755       64
02299 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906       32
02300 
02301 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700       64
02302 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717       16
02303 
02304 
02305 /* Currently this is fixed. */
02306 #define TG3_PHY_MII_ADDR                0x01
02307 
02308 
02309 /*** Tigon3 specific PHY MII registers. ***/
02310 #define  TG3_BMCR_SPEED1000             0x0040
02311 
02312 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
02313 #define  MII_TG3_CTRL_ADV_1000_HALF     0x0100
02314 #define  MII_TG3_CTRL_ADV_1000_FULL     0x0200
02315 #define  MII_TG3_CTRL_AS_MASTER         0x0800
02316 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
02317 
02318 #define MII_TG3_MMD_CTRL                0x0d /* MMD Access Control register */
02319 #define MII_TG3_MMD_CTRL_DATA_NOINC     0x4000
02320 #define MII_TG3_MMD_ADDRESS             0x0e /* MMD Address Data register */
02321 
02322 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
02323 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
02324 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
02325 #define  MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
02326 #define  MII_TG3_EXT_CTRL_TBI           0x8000
02327 
02328 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
02329 #define  MII_TG3_EXT_STAT_LPASS         0x0100
02330 
02331 #define MII_TG3_RXR_COUNTERS            0x14 /* Local/Remote Receiver Counts */
02332 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
02333 #define MII_TG3_DSP_CONTROL             0x16 /* DSP control register */
02334 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
02335 
02336 #define MII_TG3_DSP_TAP1                0x0001
02337 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
02338 #define MII_TG3_DSP_TAP26               0x001a
02339 #define  MII_TG3_DSP_TAP26_ALNOKO       0x0001
02340 #define  MII_TG3_DSP_TAP26_RMRXSTO      0x0002
02341 #define  MII_TG3_DSP_TAP26_OPCSINPT     0x0004
02342 #define MII_TG3_DSP_AADJ1CH0            0x001f
02343 #define MII_TG3_DSP_CH34TP2             0x4022
02344 #define MII_TG3_DSP_CH34TP2_HIBW01      0x017b
02345 #define MII_TG3_DSP_AADJ1CH3            0x601f
02346 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
02347 #define MII_TG3_DSP_EXP1_INT_STAT       0x0f01
02348 #define MII_TG3_DSP_EXP8                0x0f08
02349 #define  MII_TG3_DSP_EXP8_REJ2MHz       0x0001
02350 #define  MII_TG3_DSP_EXP8_AEDW          0x0200
02351 #define MII_TG3_DSP_EXP75               0x0f75
02352 #define MII_TG3_DSP_EXP96               0x0f96
02353 #define MII_TG3_DSP_EXP97               0x0f97
02354 
02355 #define MII_TG3_AUX_CTRL                0x18 /* auxiliary control register */
02356 
02357 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
02358 #define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
02359 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
02360 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN   0x4000
02361 
02362 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
02363 #define MII_TG3_AUXCTL_PCTL_WOL_EN      0x0008
02364 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR  0x0010
02365 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
02366 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
02367 #define MII_TG3_AUXCTL_PCTL_VREG_11V    0x0180
02368 
02369 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
02370 
02371 #define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
02372 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN  0x0010
02373 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
02374 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
02375 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
02376 
02377 
02378 #define MII_TG3_AUX_STAT                0x19 /* auxiliary status register */
02379 #define MII_TG3_AUX_STAT_LPASS          0x0004
02380 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
02381 #define MII_TG3_AUX_STAT_10HALF         0x0100
02382 #define MII_TG3_AUX_STAT_10FULL         0x0200
02383 #define MII_TG3_AUX_STAT_100HALF        0x0300
02384 #define MII_TG3_AUX_STAT_100_4          0x0400
02385 #define MII_TG3_AUX_STAT_100FULL        0x0500
02386 #define MII_TG3_AUX_STAT_1000HALF       0x0600
02387 #define MII_TG3_AUX_STAT_1000FULL       0x0700
02388 #define MII_TG3_AUX_STAT_100            0x0008
02389 #define MII_TG3_AUX_STAT_FULL           0x0001
02390 
02391 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
02392 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
02393 
02394 /* ISTAT/IMASK event bits */
02395 #define MII_TG3_INT_LINKCHG             0x0002
02396 #define MII_TG3_INT_SPEEDCHG            0x0004
02397 #define MII_TG3_INT_DUPLEXCHG           0x0008
02398 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
02399 
02400 #define MII_TG3_MISC_SHDW               0x1c
02401 #define MII_TG3_MISC_SHDW_WREN          0x8000
02402 
02403 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
02404 #define MII_TG3_MISC_SHDW_APD_ENABLE    0x0020
02405 #define MII_TG3_MISC_SHDW_APD_SEL       0x2800
02406 
02407 #define MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001
02408 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002
02409 #define MII_TG3_MISC_SHDW_SCR5_SDTL     0x0004
02410 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008
02411 #define MII_TG3_MISC_SHDW_SCR5_LPED     0x0010
02412 #define MII_TG3_MISC_SHDW_SCR5_SEL      0x1400
02413 
02414 #define MII_TG3_TEST1                   0x1e
02415 #define MII_TG3_TEST1_TRIM_EN           0x0010
02416 #define MII_TG3_TEST1_CRC_EN            0x8000
02417 
02418 /* Clause 45 expansion registers */
02419 #define TG3_CL45_D7_EEERES_STAT         0x803e
02420 #define TG3_CL45_D7_EEERES_STAT_LP_100TX        0x0002
02421 #define TG3_CL45_D7_EEERES_STAT_LP_1000T        0x0004
02422 
02423 
02424 /* Fast Ethernet Tranceiver definitions */
02425 #define MII_TG3_FET_PTEST               0x17
02426 #define  MII_TG3_FET_PTEST_FRC_TX_LINK  0x1000
02427 #define  MII_TG3_FET_PTEST_FRC_TX_LOCK  0x0800
02428 
02429 #define MII_TG3_FET_TEST                0x1f
02430 #define  MII_TG3_FET_SHADOW_EN          0x0080
02431 
02432 #define MII_TG3_FET_SHDW_MISCCTRL       0x10
02433 #define  MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
02434 
02435 #define MII_TG3_FET_SHDW_AUXMODE4       0x1a
02436 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD  0x0008
02437 
02438 #define MII_TG3_FET_SHDW_AUXSTAT2       0x1b
02439 #define  MII_TG3_FET_SHDW_AUXSTAT2_APD  0x0020
02440 
02441 /* Serdes PHY Register Definitions */
02442 #define SERDES_TG3_1000X_STATUS         0x14
02443 #define SERDES_TG3_SGMII_MODE           0x0001
02444 #define SERDES_TG3_LINK_UP              0x0002
02445 #define SERDES_TG3_FULL_DUPLEX          0x0004
02446 #define SERDES_TG3_SPEED_100            0x0008
02447 #define SERDES_TG3_SPEED_1000           0x0010
02448 
02449 
02450 /* APE registers.  Accessible through BAR1 */
02451 #define TG3_APE_EVENT                   0x000c
02452 #define  APE_EVENT_1                     0x00000001
02453 #define TG3_APE_LOCK_REQ                0x002c
02454 #define  APE_LOCK_REQ_DRIVER             0x00001000
02455 #define TG3_APE_LOCK_GRANT              0x004c
02456 #define  APE_LOCK_GRANT_DRIVER           0x00001000
02457 #define TG3_APE_SEG_SIG                 0x4000
02458 #define  APE_SEG_SIG_MAGIC               0x41504521
02459 
02460 /* APE shared memory.  Accessible through BAR1 */
02461 #define TG3_APE_FW_STATUS               0x400c
02462 #define  APE_FW_STATUS_READY             0x00000100
02463 #define TG3_APE_FW_FEATURES             0x4010
02464 #define  TG3_APE_FW_FEATURE_NCSI         0x00000002
02465 #define TG3_APE_FW_VERSION              0x4018
02466 #define  APE_FW_VERSION_MAJMSK           0xff000000
02467 #define  APE_FW_VERSION_MAJSFT           24
02468 #define  APE_FW_VERSION_MINMSK           0x00ff0000
02469 #define  APE_FW_VERSION_MINSFT           16
02470 #define  APE_FW_VERSION_REVMSK           0x0000ff00
02471 #define  APE_FW_VERSION_REVSFT           8
02472 #define  APE_FW_VERSION_BLDMSK           0x000000ff
02473 #define TG3_APE_HOST_SEG_SIG            0x4200
02474 #define  APE_HOST_SEG_SIG_MAGIC          0x484f5354
02475 #define TG3_APE_HOST_SEG_LEN            0x4204
02476 #define  APE_HOST_SEG_LEN_MAGIC          0x00000020
02477 #define TG3_APE_HOST_INIT_COUNT         0x4208
02478 #define TG3_APE_HOST_DRIVER_ID          0x420c
02479 #define  APE_HOST_DRIVER_ID_LINUX        0xf0000000
02480 #define  APE_HOST_DRIVER_ID_MAGIC(maj, min)     \
02481         (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
02482 #define TG3_APE_HOST_BEHAVIOR           0x4210
02483 #define  APE_HOST_BEHAV_NO_PHYLOCK       0x00000001
02484 #define TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214
02485 #define  APE_HOST_HEARTBEAT_INT_DISABLE  0
02486 #define  APE_HOST_HEARTBEAT_INT_5SEC     5000
02487 #define TG3_APE_HOST_HEARTBEAT_COUNT    0x4218
02488 #define TG3_APE_HOST_DRVR_STATE         0x421c
02489 #define TG3_APE_HOST_DRVR_STATE_START    0x00000001
02490 #define TG3_APE_HOST_DRVR_STATE_UNLOAD   0x00000002
02491 #define TG3_APE_HOST_DRVR_STATE_WOL      0x00000003
02492 #define TG3_APE_HOST_WOL_SPEED          0x4224
02493 #define TG3_APE_HOST_WOL_SPEED_AUTO      0x00008000
02494 
02495 #define TG3_APE_EVENT_STATUS            0x4300
02496 
02497 #define  APE_EVENT_STATUS_DRIVER_EVNT    0x00000010
02498 #define  APE_EVENT_STATUS_STATE_CHNGE    0x00000500
02499 #define  APE_EVENT_STATUS_STATE_START    0x00010000
02500 #define  APE_EVENT_STATUS_STATE_UNLOAD   0x00020000
02501 #define  APE_EVENT_STATUS_STATE_WOL      0x00030000
02502 #define  APE_EVENT_STATUS_STATE_SUSPEND  0x00040000
02503 #define  APE_EVENT_STATUS_EVENT_PENDING  0x80000000
02504 
02505 #define TG3_APE_PER_LOCK_REQ            0x8400
02506 #define  APE_LOCK_PER_REQ_DRIVER         0x00001000
02507 #define TG3_APE_PER_LOCK_GRANT          0x8420
02508 #define  APE_PER_LOCK_GRANT_DRIVER       0x00001000
02509 
02510 /* APE convenience enumerations. */
02511 #define TG3_APE_LOCK_GRC                1
02512 #define TG3_APE_LOCK_MEM                4
02513 
02514 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
02515 
02516 
02517 /* There are two ways to manage the TX descriptors on the tigon3.
02518  * Either the descriptors are in host DMA'able memory, or they
02519  * exist only in the cards on-chip SRAM.  All 16 send bds are under
02520  * the same mode, they may not be configured individually.
02521  *
02522  * This driver always uses host memory TX descriptors.
02523  *
02524  * To use host memory TX descriptors:
02525  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
02526  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
02527  *      2) Allocate DMA'able memory.
02528  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
02529  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
02530  *            obtained in step 2
02531  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
02532  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
02533  *            of TX descriptors.  Leave flags field clear.
02534  *      4) Access TX descriptors via host memory.  The chip
02535  *         will refetch into local SRAM as needed when producer
02536  *         index mailboxes are updated.
02537  *
02538  * To use on-chip TX descriptors:
02539  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
02540  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
02541  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
02542  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
02543  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
02544  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
02545  *      3) Access TX descriptors directly in on-chip SRAM
02546  *         using normal {read,write}l().  (and not using
02547  *         pointer dereferencing of ioremap()'d memory like
02548  *         the broken Broadcom driver does)
02549  *
02550  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
02551  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
02552  */
02553 struct tg3_tx_buffer_desc {
02554         u32                             addr_hi;
02555         u32                             addr_lo;
02556 
02557         u32                             len_flags;
02558 #define TXD_FLAG_TCPUDP_CSUM            0x0001
02559 #define TXD_FLAG_IP_CSUM                0x0002
02560 #define TXD_FLAG_END                    0x0004
02561 #define TXD_FLAG_IP_FRAG                0x0008
02562 #define TXD_FLAG_JMB_PKT                0x0008
02563 #define TXD_FLAG_IP_FRAG_END            0x0010
02564 #define TXD_FLAG_VLAN                   0x0040
02565 #define TXD_FLAG_COAL_NOW               0x0080
02566 #define TXD_FLAG_CPU_PRE_DMA            0x0100
02567 #define TXD_FLAG_CPU_POST_DMA           0x0200
02568 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
02569 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
02570 #define TXD_FLAG_NO_CRC                 0x8000
02571 #define TXD_LEN_SHIFT                   16
02572 
02573         u32                             vlan_tag;
02574 #define TXD_VLAN_TAG_SHIFT              0
02575 #define TXD_MSS_SHIFT                   16
02576 };
02577 
02578 #define TXD_ADDR                        0x00UL /* 64-bit */
02579 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
02580 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
02581 #define TXD_SIZE                        0x10UL
02582 
02583 struct tg3_rx_buffer_desc {
02584         u32                             addr_hi;
02585         u32                             addr_lo;
02586 
02587         u32                             idx_len;
02588 #define RXD_IDX_MASK    0xffff0000
02589 #define RXD_IDX_SHIFT   16
02590 #define RXD_LEN_MASK    0x0000ffff
02591 #define RXD_LEN_SHIFT   0
02592 
02593         u32                             type_flags;
02594 #define RXD_TYPE_SHIFT  16
02595 #define RXD_FLAGS_SHIFT 0
02596 
02597 #define RXD_FLAG_END                    0x0004
02598 #define RXD_FLAG_MINI                   0x0800
02599 #define RXD_FLAG_JUMBO                  0x0020
02600 #define RXD_FLAG_VLAN                   0x0040
02601 #define RXD_FLAG_ERROR                  0x0400
02602 #define RXD_FLAG_IP_CSUM                0x1000
02603 #define RXD_FLAG_TCPUDP_CSUM            0x2000
02604 #define RXD_FLAG_IS_TCP                 0x4000
02605 
02606         u32                             ip_tcp_csum;
02607 #define RXD_IPCSUM_MASK         0xffff0000
02608 #define RXD_IPCSUM_SHIFT        16
02609 #define RXD_TCPCSUM_MASK        0x0000ffff
02610 #define RXD_TCPCSUM_SHIFT       0
02611 
02612         u32                             err_vlan;
02613 
02614 #define RXD_VLAN_MASK                   0x0000ffff
02615 
02616 #define RXD_ERR_BAD_CRC                 0x00010000
02617 #define RXD_ERR_COLLISION               0x00020000
02618 #define RXD_ERR_LINK_LOST               0x00040000
02619 #define RXD_ERR_PHY_DECODE              0x00080000
02620 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
02621 #define RXD_ERR_MAC_ABRT                0x00200000
02622 #define RXD_ERR_TOO_SMALL               0x00400000
02623 #define RXD_ERR_NO_RESOURCES            0x00800000
02624 #define RXD_ERR_HUGE_FRAME              0x01000000
02625 #define RXD_ERR_MASK                    0xffff0000
02626 
02627         u32                             reserved;
02628         u32                             opaque;
02629 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
02630 #define RXD_OPAQUE_INDEX_SHIFT          0
02631 #define RXD_OPAQUE_RING_STD             0x00010000
02632 #define RXD_OPAQUE_RING_JUMBO           0x00020000
02633 #define RXD_OPAQUE_RING_MINI            0x00040000
02634 #define RXD_OPAQUE_RING_MASK            0x00070000
02635 };
02636 
02637 struct tg3_ext_rx_buffer_desc {
02638         struct {
02639                 u32                     addr_hi;
02640                 u32                     addr_lo;
02641         }                               addrlist[3];
02642         u32                             len2_len1;
02643         u32                             resv_len3;
02644         struct tg3_rx_buffer_desc       std;
02645 };
02646 
02647 /* We only use this when testing out the DMA engine
02648  * at probe time.  This is the internal format of buffer
02649  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
02650  */
02651 struct tg3_internal_buffer_desc {
02652         u32                             addr_hi;
02653         u32                             addr_lo;
02654         u32                             nic_mbuf;
02655         /* XXX FIX THIS */
02656 #if __BYTE_ORDER == __BIG_ENDIAN
02657         u16                             cqid_sqid;
02658         u16                             len;
02659 #else
02660         u16                             len;
02661         u16                             cqid_sqid;
02662 #endif
02663         u32                             flags;
02664         u32                             __cookie1;
02665         u32                             __cookie2;
02666         u32                             __cookie3;
02667 };
02668 
02669 #define TG3_HW_STATUS_SIZE              0x50
02670 struct tg3_hw_status {
02671         u32                             status;
02672 #define SD_STATUS_UPDATED               0x00000001
02673 #define SD_STATUS_LINK_CHG              0x00000002
02674 #define SD_STATUS_ERROR                 0x00000004
02675 
02676         u32                             status_tag;
02677 
02678 #if __BYTE_ORDER == __BIG_ENDIAN
02679         u16                             rx_consumer;
02680         u16                             rx_jumbo_consumer;
02681 #else
02682         u16                             rx_jumbo_consumer;
02683         u16                             rx_consumer;
02684 #endif
02685 
02686 #if __BYTE_ORDER == __BIG_ENDIAN
02687         u16                             reserved;
02688         u16                             rx_mini_consumer;
02689 #else
02690         u16                             rx_mini_consumer;
02691         u16                             reserved;
02692 #endif
02693         struct {
02694 #if __BYTE_ORDER == __BIG_ENDIAN
02695                 u16                     tx_consumer;
02696                 u16                     rx_producer;
02697 #else
02698                 u16                     rx_producer;
02699                 u16                     tx_consumer;
02700 #endif
02701         }                               idx[16];
02702 };
02703 
02704 typedef struct {
02705         u32 high, low;
02706 } tg3_stat64_t;
02707 
02708 struct tg3_hw_stats {
02709         u8                              __reserved0[0x400-0x300];
02710 
02711         /* Statistics maintained by Receive MAC. */
02712         tg3_stat64_t                    rx_octets;
02713         u64                             __reserved1;
02714         tg3_stat64_t                    rx_fragments;
02715         tg3_stat64_t                    rx_ucast_packets;
02716         tg3_stat64_t                    rx_mcast_packets;
02717         tg3_stat64_t                    rx_bcast_packets;
02718         tg3_stat64_t                    rx_fcs_errors;
02719         tg3_stat64_t                    rx_align_errors;
02720         tg3_stat64_t                    rx_xon_pause_rcvd;
02721         tg3_stat64_t                    rx_xoff_pause_rcvd;
02722         tg3_stat64_t                    rx_mac_ctrl_rcvd;
02723         tg3_stat64_t                    rx_xoff_entered;
02724         tg3_stat64_t                    rx_frame_too_long_errors;
02725         tg3_stat64_t                    rx_jabbers;
02726         tg3_stat64_t                    rx_undersize_packets;
02727         tg3_stat64_t                    rx_in_length_errors;
02728         tg3_stat64_t                    rx_out_length_errors;
02729         tg3_stat64_t                    rx_64_or_less_octet_packets;
02730         tg3_stat64_t                    rx_65_to_127_octet_packets;
02731         tg3_stat64_t                    rx_128_to_255_octet_packets;
02732         tg3_stat64_t                    rx_256_to_511_octet_packets;
02733         tg3_stat64_t                    rx_512_to_1023_octet_packets;
02734         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
02735         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
02736         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
02737         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
02738         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
02739 
02740         u64                             __unused0[37];
02741 
02742         /* Statistics maintained by Transmit MAC. */
02743         tg3_stat64_t                    tx_octets;
02744         u64                             __reserved2;
02745         tg3_stat64_t                    tx_collisions;
02746         tg3_stat64_t                    tx_xon_sent;
02747         tg3_stat64_t                    tx_xoff_sent;
02748         tg3_stat64_t                    tx_flow_control;
02749         tg3_stat64_t                    tx_mac_errors;
02750         tg3_stat64_t                    tx_single_collisions;
02751         tg3_stat64_t                    tx_mult_collisions;
02752         tg3_stat64_t                    tx_deferred;
02753         u64                             __reserved3;
02754         tg3_stat64_t                    tx_excessive_collisions;
02755         tg3_stat64_t                    tx_late_collisions;
02756         tg3_stat64_t                    tx_collide_2times;
02757         tg3_stat64_t                    tx_collide_3times;
02758         tg3_stat64_t                    tx_collide_4times;
02759         tg3_stat64_t                    tx_collide_5times;
02760         tg3_stat64_t                    tx_collide_6times;
02761         tg3_stat64_t                    tx_collide_7times;
02762         tg3_stat64_t                    tx_collide_8times;
02763         tg3_stat64_t                    tx_collide_9times;
02764         tg3_stat64_t                    tx_collide_10times;
02765         tg3_stat64_t                    tx_collide_11times;
02766         tg3_stat64_t                    tx_collide_12times;
02767         tg3_stat64_t                    tx_collide_13times;
02768         tg3_stat64_t                    tx_collide_14times;
02769         tg3_stat64_t                    tx_collide_15times;
02770         tg3_stat64_t                    tx_ucast_packets;
02771         tg3_stat64_t                    tx_mcast_packets;
02772         tg3_stat64_t                    tx_bcast_packets;
02773         tg3_stat64_t                    tx_carrier_sense_errors;
02774         tg3_stat64_t                    tx_discards;
02775         tg3_stat64_t                    tx_errors;
02776 
02777         u64                             __unused1[31];
02778 
02779         /* Statistics maintained by Receive List Placement. */
02780         tg3_stat64_t                    COS_rx_packets[16];
02781         tg3_stat64_t                    COS_rx_filter_dropped;
02782         tg3_stat64_t                    dma_writeq_full;
02783         tg3_stat64_t                    dma_write_prioq_full;
02784         tg3_stat64_t                    rxbds_empty;
02785         tg3_stat64_t                    rx_discards;
02786         tg3_stat64_t                    rx_errors;
02787         tg3_stat64_t                    rx_threshold_hit;
02788 
02789         u64                             __unused2[9];
02790 
02791         /* Statistics maintained by Send Data Initiator. */
02792         tg3_stat64_t                    COS_out_packets[16];
02793         tg3_stat64_t                    dma_readq_full;
02794         tg3_stat64_t                    dma_read_prioq_full;
02795         tg3_stat64_t                    tx_comp_queue_full;
02796 
02797         /* Statistics maintained by Host Coalescing. */
02798         tg3_stat64_t                    ring_set_send_prod_index;
02799         tg3_stat64_t                    ring_status_update;
02800         tg3_stat64_t                    nic_irqs;
02801         tg3_stat64_t                    nic_avoided_irqs;
02802         tg3_stat64_t                    nic_tx_threshold_hit;
02803 
02804         /* NOT a part of the hardware statistics block format.
02805          * These stats are here as storage for tg3_periodic_fetch_stats().
02806          */
02807         tg3_stat64_t                    mbuf_lwm_thresh_hit;
02808 
02809         u8                              __reserved4[0xb00-0x9c8];
02810 };
02811 
02812 typedef unsigned long dma_addr_t;
02813 
02814 /* 'mapping' is superfluous as the chip does not write into
02815  * the tx/rx post rings so we could just fetch it from there.
02816  * But the cache behavior is better how we are doing it now.
02817  */
02818 struct ring_info {
02819         struct io_buffer                        *iob;
02820 ///     dma_addr_t mapping;
02821 };
02822 
02823 struct tg3_link_config {
02824         /* Describes what we're trying to get. */
02825         u32                             advertising;
02826         u16                             speed;
02827         u8                              duplex;
02828         u8                              autoneg;
02829         u8                              flowctrl;
02830 
02831         /* Describes what we actually have. */
02832         u8                              active_flowctrl;
02833 
02834         u8                              active_duplex;
02835 #define SPEED_INVALID           0xffff
02836 #define DUPLEX_INVALID          0xff
02837 #define AUTONEG_INVALID         0xff
02838         u16                             active_speed;
02839         u32                             rmt_adv;
02840 
02841         /* When we go in and out of low power mode we need
02842          * to swap with this state.
02843          */
02844         u16                             orig_speed;
02845         u8                              orig_duplex;
02846         u8                              orig_autoneg;
02847         u32                             orig_advertising;
02848 };
02849 
02850 struct tg3_bufmgr_config {
02851         u32             mbuf_read_dma_low_water;
02852         u32             mbuf_mac_rx_low_water;
02853         u32             mbuf_high_water;
02854 
02855         u32             mbuf_read_dma_low_water_jumbo;
02856         u32             mbuf_mac_rx_low_water_jumbo;
02857         u32             mbuf_high_water_jumbo;
02858 
02859         u32             dma_low_water;
02860         u32             dma_high_water;
02861 };
02862 
02863 struct tg3_ethtool_stats {
02864         /* Statistics maintained by Receive MAC. */
02865         u64             rx_octets;
02866         u64             rx_fragments;
02867         u64             rx_ucast_packets;
02868         u64             rx_mcast_packets;
02869         u64             rx_bcast_packets;
02870         u64             rx_fcs_errors;
02871         u64             rx_align_errors;
02872         u64             rx_xon_pause_rcvd;
02873         u64             rx_xoff_pause_rcvd;
02874         u64             rx_mac_ctrl_rcvd;
02875         u64             rx_xoff_entered;
02876         u64             rx_frame_too_long_errors;
02877         u64             rx_jabbers;
02878         u64             rx_undersize_packets;
02879         u64             rx_in_length_errors;
02880         u64             rx_out_length_errors;
02881         u64             rx_64_or_less_octet_packets;
02882         u64             rx_65_to_127_octet_packets;
02883         u64             rx_128_to_255_octet_packets;
02884         u64             rx_256_to_511_octet_packets;
02885         u64             rx_512_to_1023_octet_packets;
02886         u64             rx_1024_to_1522_octet_packets;
02887         u64             rx_1523_to_2047_octet_packets;
02888         u64             rx_2048_to_4095_octet_packets;
02889         u64             rx_4096_to_8191_octet_packets;
02890         u64             rx_8192_to_9022_octet_packets;
02891 
02892         /* Statistics maintained by Transmit MAC. */
02893         u64             tx_octets;
02894         u64             tx_collisions;
02895         u64             tx_xon_sent;
02896         u64             tx_xoff_sent;
02897         u64             tx_flow_control;
02898         u64             tx_mac_errors;
02899         u64             tx_single_collisions;
02900         u64             tx_mult_collisions;
02901         u64             tx_deferred;
02902         u64             tx_excessive_collisions;
02903         u64             tx_late_collisions;
02904         u64             tx_collide_2times;
02905         u64             tx_collide_3times;
02906         u64             tx_collide_4times;
02907         u64             tx_collide_5times;
02908         u64             tx_collide_6times;
02909         u64             tx_collide_7times;
02910         u64             tx_collide_8times;
02911         u64             tx_collide_9times;
02912         u64             tx_collide_10times;
02913         u64             tx_collide_11times;
02914         u64             tx_collide_12times;
02915         u64             tx_collide_13times;
02916         u64             tx_collide_14times;
02917         u64             tx_collide_15times;
02918         u64             tx_ucast_packets;
02919         u64             tx_mcast_packets;
02920         u64             tx_bcast_packets;
02921         u64             tx_carrier_sense_errors;
02922         u64             tx_discards;
02923         u64             tx_errors;
02924 
02925         /* Statistics maintained by Receive List Placement. */
02926         u64             dma_writeq_full;
02927         u64             dma_write_prioq_full;
02928         u64             rxbds_empty;
02929         u64             rx_discards;
02930         u64             rx_errors;
02931         u64             rx_threshold_hit;
02932 
02933         /* Statistics maintained by Send Data Initiator. */
02934         u64             dma_readq_full;
02935         u64             dma_read_prioq_full;
02936         u64             tx_comp_queue_full;
02937 
02938         /* Statistics maintained by Host Coalescing. */
02939         u64             ring_set_send_prod_index;
02940         u64             ring_status_update;
02941         u64             nic_irqs;
02942         u64             nic_avoided_irqs;
02943         u64             nic_tx_threshold_hit;
02944 
02945         u64             mbuf_lwm_thresh_hit;
02946 };
02947 
02948 /* number of io_buffers to allocate */
02949 #define TG3_DEF_RX_RING_PENDING         8
02950 
02951 struct tg3_rx_prodring_set {
02952         u32                             rx_std_prod_idx;
02953         u32                             rx_std_cons_idx;
02954         u32                             rx_std_iob_cnt;
02955         struct tg3_rx_buffer_desc       *rx_std;
02956         struct io_buffer                *rx_iobufs[TG3_DEF_RX_RING_PENDING];
02957         dma_addr_t                      rx_std_mapping;
02958 };
02959 
02960 #define TG3_IRQ_MAX_VECS_RSS            5
02961 #define TG3_IRQ_MAX_VECS                TG3_IRQ_MAX_VECS_RSS
02962 
02963 enum TG3_FLAGS {
02964         TG3_FLAG_TAGGED_STATUS = 0,
02965         TG3_FLAG_TXD_MBOX_HWBUG,
02966         TG3_FLAG_USE_LINKCHG_REG,
02967         TG3_FLAG_ERROR_PROCESSED,
02968         TG3_FLAG_ENABLE_ASF,
02969         TG3_FLAG_ASPM_WORKAROUND,
02970         TG3_FLAG_POLL_SERDES,
02971         TG3_FLAG_MBOX_WRITE_REORDER,
02972         TG3_FLAG_PCIX_TARGET_HWBUG,
02973         TG3_FLAG_WOL_SPEED_100MB,
02974         TG3_FLAG_WOL_ENABLE,
02975         TG3_FLAG_EEPROM_WRITE_PROT,
02976         TG3_FLAG_NVRAM,
02977         TG3_FLAG_NVRAM_BUFFERED,
02978         TG3_FLAG_SUPPORT_MSI,
02979         TG3_FLAG_SUPPORT_MSIX,
02980         TG3_FLAG_PCIX_MODE,
02981         TG3_FLAG_PCI_HIGH_SPEED,
02982         TG3_FLAG_PCI_32BIT,
02983         TG3_FLAG_SRAM_USE_CONFIG,
02984         TG3_FLAG_TX_RECOVERY_PENDING,
02985         TG3_FLAG_WOL_CAP,
02986         TG3_FLAG_JUMBO_RING_ENABLE,
02987         TG3_FLAG_PAUSE_AUTONEG,
02988         TG3_FLAG_CPMU_PRESENT,
02989         TG3_FLAG_BROKEN_CHECKSUMS,
02990         TG3_FLAG_JUMBO_CAPABLE,
02991         TG3_FLAG_CHIP_RESETTING,
02992         TG3_FLAG_INIT_COMPLETE,
02993         TG3_FLAG_RESTART_TIMER,
02994         TG3_FLAG_TSO_BUG,
02995         TG3_FLAG_IS_5788,
02996         TG3_FLAG_MAX_RXPEND_64,
02997         TG3_FLAG_TSO_CAPABLE,
02998         TG3_FLAG_PCI_EXPRESS,
02999         TG3_FLAG_ASF_NEW_HANDSHAKE,
03000         TG3_FLAG_HW_AUTONEG,
03001         TG3_FLAG_IS_NIC,
03002         TG3_FLAG_FLASH,
03003         TG3_FLAG_HW_TSO_1,
03004         TG3_FLAG_5705_PLUS,
03005         TG3_FLAG_5750_PLUS,
03006         TG3_FLAG_HW_TSO_3,
03007         TG3_FLAG_USING_MSI,
03008         TG3_FLAG_USING_MSIX,
03009         TG3_FLAG_ICH_WORKAROUND,
03010         TG3_FLAG_5780_CLASS,
03011         TG3_FLAG_HW_TSO_2,
03012         TG3_FLAG_1SHOT_MSI,
03013         TG3_FLAG_NO_FWARE_REPORTED,
03014         TG3_FLAG_NO_NVRAM_ADDR_TRANS,
03015         TG3_FLAG_ENABLE_APE,
03016         TG3_FLAG_PROTECTED_NVRAM,
03017         TG3_FLAG_MDIOBUS_INITED,
03018         TG3_FLAG_LRG_PROD_RING_CAP,
03019         TG3_FLAG_RGMII_INBAND_DISABLE,
03020         TG3_FLAG_RGMII_EXT_IBND_RX_EN,
03021         TG3_FLAG_RGMII_EXT_IBND_TX_EN,
03022         TG3_FLAG_CLKREQ_BUG,
03023         TG3_FLAG_5755_PLUS,
03024         TG3_FLAG_NO_NVRAM,
03025         TG3_FLAG_ENABLE_RSS,
03026         TG3_FLAG_ENABLE_TSS,
03027         TG3_FLAG_4G_DMA_BNDRY_BUG,
03028         TG3_FLAG_USE_JUMBO_BDFLAG,
03029         TG3_FLAG_L1PLLPD_EN,
03030         TG3_FLAG_57765_PLUS,
03031         TG3_FLAG_APE_HAS_NCSI,
03032         TG3_FLAG_5717_PLUS,
03033 
03034         /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
03035         TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
03036 };
03037 
03038 /* Following definition is copied from linux-3.0rc1/include/linux/kernel.h */
03039 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
03040 /* bitops.h */
03041 #define BITS_PER_BYTE           8
03042 #define BITS_TO_LONGS(nr)       DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
03043 /* types.h: */
03044 #define DECLARE_BITMAP(name,bits) \
03045         unsigned long name[BITS_TO_LONGS(bits)]
03046 
03047 struct tg3 {
03048         /* begin "general, frequently-used members" cacheline section */
03049 
03050         /* If the IRQ handler (which runs lockless) needs to be
03051          * quiesced, the following bitmask state is used.  The
03052          * SYNC flag is set by non-IRQ context code to initiate
03053          * the quiescence.
03054          *
03055          * When the IRQ handler notices that SYNC is set, it
03056          * disables interrupts and returns.
03057          *
03058          * When all outstanding IRQ handlers have returned after
03059          * the SYNC flag has been set, the setter can be assured
03060          * that interrupts will no longer get run.
03061          *
03062          * In this way all SMP driver locks are never acquired
03063          * in hw IRQ context, only sw IRQ context or lower.
03064          */
03065         unsigned int                    irq_sync;
03066 
03067         /* SMP locking strategy:
03068          *
03069          * lock: Held during reset, PHY access, timer, and when
03070          *       updating tg3_flags.
03071          *
03072          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
03073          *                netif_tx_lock when it needs to call
03074          *                netif_wake_queue.
03075          *
03076          * Both of these locks are to be held with BH safety.
03077          *
03078          * Because the IRQ handler, tg3_poll, and tg3_start_xmit
03079          * are running lockless, it is necessary to completely
03080          * quiesce the chip with tg3_netif_stop and tg3_full_lock
03081          * before reconfiguring the device.
03082          *
03083          * indirect_lock: Held when accessing registers indirectly
03084          *                with IRQ disabling.
03085          */
03086 
03087         u32                             (*read32_mbox) (struct tg3 *, u32);
03088         void                            (*write32_mbox) (struct tg3 *, u32,
03089                                                          u32);
03090         void                            *regs;
03091         struct net_device               *dev;
03092         struct pci_device               *pdev;
03093 
03094         u32                             msg_enable;
03095 
03096         /* begin "tx thread" cacheline section */
03097         void                            (*write32_tx_mbox) (struct tg3 *, u32,
03098                                                             u32);
03099 
03100         /* begin "rx thread" cacheline section */
03101         void                            (*write32_rx_mbox) (struct tg3 *, u32,
03102                                                             u32);
03103         u32                             rx_std_max_post;
03104         u32                             rx_pkt_map_sz;
03105 
03106         /* was struct tg3_napi: */
03107         struct tg3_hw_status            *hw_status;
03108 
03109         u32                             last_tag;
03110         u32                             last_irq_tag;
03111         u32                             int_mbox;
03112         /* NOTE: there was a coal_now in struct tg3_napi and struct tg3. We
03113          * didn't use coal_now in struct tg3, so it was removed */
03114         u32                             coal_now;
03115 
03116         u32                             consmbox;
03117         u32                             rx_rcb_ptr;
03118         u16                             *rx_rcb_prod_idx;
03119         struct tg3_rx_prodring_set      prodring;
03120         struct tg3_rx_buffer_desc       *rx_rcb;
03121 
03122         u32                             tx_prod;
03123         u32                             tx_cons;
03124         u32                             prodmbox;
03125         struct tg3_tx_buffer_desc       *tx_ring;
03126         struct ring_info                *tx_buffers;
03127 
03128         dma_addr_t                      status_mapping;
03129         dma_addr_t                      rx_rcb_mapping;
03130         dma_addr_t                      tx_desc_mapping;
03131         /* end tg3_napi */
03132 
03133         /* begin "everything else" cacheline(s) section */
03134         unsigned long                   rx_dropped;
03135 
03136         DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
03137 
03138         union {
03139         unsigned long                   phy_crc_errors;
03140         };
03141 
03142         u16                             timer_counter;
03143         u16                             timer_multiplier;
03144         u32                             timer_offset;
03145         u16                             asf_counter;
03146         u16                             asf_multiplier;
03147 
03148         /* 1 second counter for transient serdes link events */
03149         u32                             serdes_counter;
03150 #define SERDES_AN_TIMEOUT_5704S         2
03151 #define SERDES_PARALLEL_DET_TIMEOUT     1
03152 #define SERDES_AN_TIMEOUT_5714S         1
03153 
03154         struct tg3_link_config          link_config;
03155         struct tg3_bufmgr_config        bufmgr_config;
03156 
03157         /* cache h/w values, often passed straight to h/w */
03158         u32                             rx_mode;
03159         u32                             tx_mode;
03160         u32                             mac_mode;
03161         u32                             mi_mode;
03162         u32                             misc_host_ctrl;
03163         u32                             grc_mode;
03164         u32                             grc_local_ctrl;
03165         u32                             dma_rwctrl;
03166         u32                             coalesce_mode;
03167 
03168         /* PCI block */
03169         u32                             pci_chip_rev_id;
03170         u16                             pci_cmd;
03171         u8                              pci_cacheline_sz;
03172         u8                              pci_lat_timer;
03173 
03174         int                             pm_cap;
03175         union {
03176         int                             pcix_cap;
03177         int                             pcie_cap;
03178         };
03179         int                             pcie_readrq;
03180 
03181         u8                              phy_addr;
03182 
03183         /* PHY info */
03184         u32                             phy_id;
03185 #define TG3_PHY_ID_MASK                 0xfffffff0
03186 #define TG3_PHY_ID_BCM5400              0x60008040
03187 #define TG3_PHY_ID_BCM5401              0x60008050
03188 #define TG3_PHY_ID_BCM5411              0x60008070
03189 #define TG3_PHY_ID_BCM5701              0x60008110
03190 #define TG3_PHY_ID_BCM5703              0x60008160
03191 #define TG3_PHY_ID_BCM5704              0x60008190
03192 #define TG3_PHY_ID_BCM5705              0x600081a0
03193 #define TG3_PHY_ID_BCM5750              0x60008180
03194 #define TG3_PHY_ID_BCM5752              0x60008100
03195 #define TG3_PHY_ID_BCM5714              0x60008340
03196 #define TG3_PHY_ID_BCM5780              0x60008350
03197 #define TG3_PHY_ID_BCM5755              0xbc050cc0
03198 #define TG3_PHY_ID_BCM5787              0xbc050ce0
03199 #define TG3_PHY_ID_BCM5756              0xbc050ed0
03200 #define TG3_PHY_ID_BCM5784              0xbc050fa0
03201 #define TG3_PHY_ID_BCM5761              0xbc050fd0
03202 #define TG3_PHY_ID_BCM5718C             0x5c0d8a00
03203 #define TG3_PHY_ID_BCM5718S             0xbc050ff0
03204 #define TG3_PHY_ID_BCM57765             0x5c0d8a40
03205 #define TG3_PHY_ID_BCM5719C             0x5c0d8a20
03206 #define TG3_PHY_ID_BCM5720C             0x5c0d8b60
03207 #define TG3_PHY_ID_BCM5906              0xdc00ac40
03208 #define TG3_PHY_ID_BCM8002              0x60010140
03209 #define TG3_PHY_ID_INVALID              0xffffffff
03210 
03211 #define PHY_ID_RTL8211C                 0x001cc910
03212 #define PHY_ID_RTL8201E                 0x00008200
03213 
03214 #define TG3_PHY_ID_REV_MASK             0x0000000f
03215 #define TG3_PHY_REV_BCM5401_B0          0x1
03216 
03217         /* This macro assumes the passed PHY ID is
03218          * already masked with TG3_PHY_ID_MASK.
03219          */
03220 #define TG3_KNOWN_PHY_ID(X)             \
03221         ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
03222          (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
03223          (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
03224          (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
03225          (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
03226          (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
03227          (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
03228          (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
03229          (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
03230          (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
03231          (X) == TG3_PHY_ID_BCM8002)
03232 
03233         u32                             phy_flags;
03234 #define TG3_PHYFLG_IS_LOW_POWER         0x00000001
03235 #define TG3_PHYFLG_IS_CONNECTED         0x00000002
03236 #define TG3_PHYFLG_USE_MI_INTERRUPT     0x00000004
03237 #define TG3_PHYFLG_PHY_SERDES           0x00000010
03238 #define TG3_PHYFLG_MII_SERDES           0x00000020
03239 #define TG3_PHYFLG_ANY_SERDES           (TG3_PHYFLG_PHY_SERDES |        \
03240                                         TG3_PHYFLG_MII_SERDES)
03241 #define TG3_PHYFLG_IS_FET               0x00000040
03242 #define TG3_PHYFLG_10_100_ONLY          0x00000080
03243 #define TG3_PHYFLG_ENABLE_APD           0x00000100
03244 #define TG3_PHYFLG_CAPACITIVE_COUPLING  0x00000200
03245 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED    0x00000400
03246 #define TG3_PHYFLG_JITTER_BUG           0x00000800
03247 #define TG3_PHYFLG_ADJUST_TRIM          0x00001000
03248 #define TG3_PHYFLG_ADC_BUG              0x00002000
03249 #define TG3_PHYFLG_5704_A0_BUG          0x00004000
03250 #define TG3_PHYFLG_BER_BUG              0x00008000
03251 #define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
03252 #define TG3_PHYFLG_PARALLEL_DETECT      0x00020000
03253 #define TG3_PHYFLG_EEE_CAP              0x00040000
03254 
03255         u32                             led_ctrl;
03256         u32                             phy_otp;
03257         u32                             setlpicnt;
03258 
03259 #define TG3_BPN_SIZE                    24
03260         char                            board_part_number[TG3_BPN_SIZE];
03261 #define TG3_VER_SIZE                    32
03262         char                            fw_ver[TG3_VER_SIZE];
03263         u32                             nic_sram_data_cfg;
03264         u32                             pci_clock_ctrl;
03265         struct pci_device                       *pdev_peer;
03266 
03267         int                             nvram_lock_cnt;
03268         u32                             nvram_size;
03269 #define TG3_NVRAM_SIZE_2KB              0x00000800
03270 #define TG3_NVRAM_SIZE_64KB             0x00010000
03271 #define TG3_NVRAM_SIZE_128KB            0x00020000
03272 #define TG3_NVRAM_SIZE_256KB            0x00040000
03273 #define TG3_NVRAM_SIZE_512KB            0x00080000
03274 #define TG3_NVRAM_SIZE_1MB              0x00100000
03275 #define TG3_NVRAM_SIZE_2MB              0x00200000
03276 
03277         u32                             nvram_pagesize;
03278         u32                             nvram_jedecnum;
03279 
03280 #define JEDEC_ATMEL                     0x1f
03281 #define JEDEC_ST                        0x20
03282 #define JEDEC_SAIFUN                    0x4f
03283 #define JEDEC_SST                       0xbf
03284 
03285 #define ATMEL_AT24C02_CHIP_SIZE         TG3_NVRAM_SIZE_2KB
03286 #define ATMEL_AT24C02_PAGE_SIZE         (8)
03287 
03288 #define ATMEL_AT24C64_CHIP_SIZE         TG3_NVRAM_SIZE_64KB
03289 #define ATMEL_AT24C64_PAGE_SIZE         (32)
03290 
03291 #define ATMEL_AT24C512_CHIP_SIZE        TG3_NVRAM_SIZE_512KB
03292 #define ATMEL_AT24C512_PAGE_SIZE        (128)
03293 
03294 #define ATMEL_AT45DB0X1B_PAGE_POS       9
03295 #define ATMEL_AT45DB0X1B_PAGE_SIZE      264
03296 
03297 #define ATMEL_AT25F512_PAGE_SIZE        256
03298 
03299 #define ST_M45PEX0_PAGE_SIZE            256
03300 
03301 #define SAIFUN_SA25F0XX_PAGE_SIZE       256
03302 
03303 #define SST_25VF0X0_PAGE_SIZE           4098
03304 
03305         u16                             subsystem_vendor;
03306         u16                             subsystem_device;
03307         int                             link_up;
03308 };
03309 
03310 #define TG3_TX_RING_SIZE                512
03311 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
03312 
03313 #define TG3_DMA_ALIGNMENT       16
03314 
03315 #define TG3_RX_STD_DMA_SZ               (1536 + 64 + 2)
03316 
03317 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
03318 {
03319         tp->write32_mbox(tp, off, val);
03320 ///     if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
03321 ///             tp->read32_mbox(tp, off);
03322 }
03323 
03324 u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off);
03325 void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val);
03326 u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off);
03327 void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val);
03328 
03329 #define tw32(reg, val)                  tg3_write_indirect_reg32(tp, reg, val)
03330 ///#define tw32_mailbox(reg, val)               tg3_write_indirect_mbox(((val) & 0xffffffff), tp->regs + (reg))
03331 #define tw32_mailbox(reg, val)          tg3_write_indirect_mbox(tp, (reg), (val))
03332 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
03333 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
03334 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
03335 
03336 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
03337 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
03338 
03339 #define tr32(reg)                       tg3_read_indirect_reg32(tp, reg)
03340 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
03341 
03342 /* Functions & macros to verify TG3_FLAGS types */
03343 
03344 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
03345 {
03346         unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
03347         unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
03348         return ( !! ( bits[index] & ( 1UL << bit ) ) );
03349 }
03350 
03351 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
03352 {
03353         unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
03354         unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
03355         bits[index] |= ( 1UL << bit );
03356 }
03357 
03358 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
03359 {
03360         unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
03361         unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
03362         bits[index] &= ~( 1UL << bit );
03363 }
03364 
03365 #define tg3_flag(tp, flag)                              \
03366         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
03367 #define tg3_flag_set(tp, flag)                          \
03368         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
03369 #define tg3_flag_clear(tp, flag)                        \
03370         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
03371 
03372 /* tg3_main.c forward declarations */
03373 int tg3_init_rings(struct tg3 *tp);
03374 void tg3_rx_prodring_fini(struct tg3_rx_prodring_set *tpr);
03375 ///int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
03376 
03377 /* tg3_phy.c forward declarations */
03378 u32 tg3_read_otp_phycfg(struct tg3 *tp);
03379 void tg3_mdio_init(struct tg3 *tp);
03380 int tg3_phy_probe(struct tg3 *tp);
03381 int tg3_phy_reset(struct tg3 *tp);
03382 int tg3_setup_phy(struct tg3 *tp, int force_reset);
03383 int tg3_readphy(struct tg3 *tp, int reg, u32 *val);
03384 int tg3_writephy(struct tg3 *tp, int reg, u32 val);
03385 
03386 /* tg3_hw.c forward declarations */
03387 void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait);
03388 void tg3_write_mem(struct tg3 *tp, u32 off, u32 val);
03389 int tg3_get_invariants(struct tg3 *tp);
03390 void tg3_init_bufmgr_config(struct tg3 *tp);
03391 int tg3_get_device_address(struct tg3 *tp);
03392 int tg3_halt(struct tg3 *tp);
03393 void tg3_set_txd(struct tg3 *tp, int entry, dma_addr_t mapping, int len, u32 flags);
03394 void tg3_set_power_state_0(struct tg3 *tp);
03395 int tg3_alloc_consistent(struct tg3 *tp);
03396 int tg3_init_hw(struct tg3 *tp, int reset_phy);
03397 void tg3_poll_link(struct tg3 *tp);
03398 void tg3_wait_for_event_ack(struct tg3 *tp);
03399 void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1);
03400 void tg3_disable_ints(struct tg3 *tp);
03401 void tg3_enable_ints(struct tg3 *tp);
03402 
03403 static inline void tg3_generate_fw_event(struct tg3 *tp)
03404 {
03405         u32 val;
03406 
03407         val = tr32(GRC_RX_CPU_EVENT);
03408         val |= GRC_RX_CPU_DRIVER_EVENT;
03409         tw32_f(GRC_RX_CPU_EVENT, val);
03410 }
03411 
03412 /* linux-2.6.39, include/linux/mii.h: */
03413 /**
03414  * mii_resolve_flowctrl_fdx
03415  * @lcladv: value of MII ADVERTISE register
03416  * @rmtadv: value of MII LPA register
03417  *
03418  * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
03419  */
03420 static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
03421 {
03422         u8 cap = 0;
03423 
03424         if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
03425                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
03426         } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
03427                 if (lcladv & ADVERTISE_PAUSE_CAP)
03428                         cap = FLOW_CTRL_RX;
03429                 else if (rmtadv & ADVERTISE_PAUSE_CAP)
03430                         cap = FLOW_CTRL_TX;
03431         }
03432 
03433         return cap;
03434 }
03435 
03436 static inline u32 mii_adv_to_ethtool_adv_x(u32 adv)
03437 {
03438         u32 result = 0;
03439 
03440         if (adv & ADVERTISE_1000XHALF)
03441                 result |= ADVERTISED_1000baseT_Half;
03442         if (adv & ADVERTISE_1000XFULL)
03443                 result |= ADVERTISED_1000baseT_Full;
03444         if (adv & ADVERTISE_1000XPAUSE)
03445                 result |= ADVERTISED_Pause;
03446         if (adv & ADVERTISE_1000XPSE_ASYM)
03447                 result |= ADVERTISED_Asym_Pause;
03448 
03449         return result;
03450 }
03451 
03452 static inline u32 ethtool_adv_to_mii_adv_x(u32 ethadv)
03453 {
03454         u32 result = 0;
03455 
03456         if (ethadv & ADVERTISED_1000baseT_Half)
03457                 result |= ADVERTISE_1000XHALF;
03458         if (ethadv & ADVERTISED_1000baseT_Full)
03459                 result |= ADVERTISE_1000XFULL;
03460         if (ethadv & ADVERTISED_Pause)
03461                 result |= ADVERTISE_1000XPAUSE;
03462         if (ethadv & ADVERTISED_Asym_Pause)
03463                 result |= ADVERTISE_1000XPSE_ASYM;
03464 
03465         return result;
03466 }
03467 
03468 
03469 #define ETH_FCS_LEN 4
03470 
03471 #endif /* !(_T3_H) */