iPXE
vxge_main.h
Go to the documentation of this file.
00001 /*
00002  * vxge-main.h: iPXE driver for Neterion Inc's X3100 Series 10GbE
00003  *              PCIe I/O Virtualized Server Adapter.
00004  *
00005  * Copyright(c) 2002-2010 Neterion Inc.
00006  *
00007  * This software may be used and distributed according to the terms of
00008  * the GNU General Public License (GPL), incorporated herein by
00009  * reference.  Drivers based on or derived from this code fall under
00010  * the GPL and must retain the authorship, copyright and license
00011  * notice.
00012  *
00013  */
00014 
00015 FILE_LICENCE(GPL2_ONLY);
00016 
00017 #ifndef VXGE_MAIN_H
00018 #define VXGE_MAIN_H
00019 
00020 #include <unistd.h>
00021 #include "vxge_traffic.h"
00022 #include "vxge_config.h"
00023 
00024 #define VXGE_DRIVER_NAME                "vxge"
00025 #define VXGE_DRIVER_VENDOR              "Neterion, Inc"
00026 
00027 #ifndef PCI_VENDOR_ID_S2IO
00028 #define PCI_VENDOR_ID_S2IO              0x17D5
00029 #endif
00030 
00031 #ifndef PCI_DEVICE_ID_TITAN_WIN
00032 #define PCI_DEVICE_ID_TITAN_WIN         0x5733
00033 #endif
00034 
00035 #ifndef PCI_DEVICE_ID_TITAN_UNI
00036 #define PCI_DEVICE_ID_TITAN_UNI         0x5833
00037 #endif
00038 
00039 #define VXGE_HW_TITAN1_PCI_REVISION     1
00040 #define VXGE_HW_TITAN1A_PCI_REVISION    2
00041 
00042 #define VXGE_HP_ISS_SUBSYS_VENDORID     0x103C
00043 #define VXGE_HP_ISS_SUBSYS_DEVICEID_1   0x323B
00044 #define VXGE_HP_ISS_SUBSYS_DEVICEID_2   0x323C
00045 
00046 #define VXGE_USE_DEFAULT                0xffffffff
00047 #define VXGE_HW_VPATH_MSIX_ACTIVE       4
00048 #define VXGE_ALARM_MSIX_ID              2
00049 #define VXGE_HW_RXSYNC_FREQ_CNT         4
00050 #define VXGE_LL_RX_COPY_THRESHOLD       256
00051 #define VXGE_DEF_FIFO_LENGTH            84
00052 
00053 #define NO_STEERING             0
00054 #define PORT_STEERING           0x1
00055 #define RTH_TCP_UDP_STEERING    0x2
00056 #define RTH_IPV4_STEERING       0x3
00057 #define RTH_IPV6_EX_STEERING    0x4
00058 #define RTH_BUCKET_SIZE         8
00059 
00060 #define TX_PRIORITY_STEERING            1
00061 #define TX_VLAN_STEERING                2
00062 #define TX_PORT_STEERING                3
00063 #define TX_MULTIQ_STEERING              4
00064 
00065 #define VXGE_HW_PROM_MODE_ENABLE        1
00066 #define VXGE_HW_PROM_MODE_DISABLE       0
00067 
00068 #define VXGE_HW_FW_UPGRADE_DISABLE      0
00069 #define VXGE_HW_FW_UPGRADE_ALL          1
00070 #define VXGE_HW_FW_UPGRADE_FORCE        2
00071 #define VXGE_HW_FUNC_MODE_DISABLE       0
00072 
00073 #define VXGE_TTI_BTIMER_VAL 250000
00074 #define VXGE_T1A_TTI_LTIMER_VAL 80
00075 #define VXGE_T1A_TTI_RTIMER_VAL 400
00076 
00077 #define VXGE_TTI_LTIMER_VAL 1000
00078 #define VXGE_TTI_RTIMER_VAL 0
00079 #define VXGE_RTI_BTIMER_VAL 250
00080 #define VXGE_RTI_LTIMER_VAL 100
00081 #define VXGE_RTI_RTIMER_VAL 0
00082 #define VXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH
00083 #define VXGE_ISR_POLLING_CNT    8
00084 #define VXGE_MAX_CONFIG_DEV     0xFF
00085 #define VXGE_EXEC_MODE_DISABLE  0
00086 #define VXGE_EXEC_MODE_ENABLE   1
00087 #define VXGE_MAX_CONFIG_PORT    1
00088 #define VXGE_ALL_VID_DISABLE    0
00089 #define VXGE_ALL_VID_ENABLE     1
00090 #define VXGE_PAUSE_CTRL_DISABLE 0
00091 #define VXGE_PAUSE_CTRL_ENABLE  1
00092 
00093 #define TTI_TX_URANGE_A 5
00094 #define TTI_TX_URANGE_B 15
00095 #define TTI_TX_URANGE_C 40
00096 #define TTI_TX_UFC_A    5
00097 #define TTI_TX_UFC_B    40
00098 #define TTI_TX_UFC_C    60
00099 #define TTI_TX_UFC_D    100
00100 #define TTI_T1A_TX_UFC_A        30
00101 #define TTI_T1A_TX_UFC_B        80
00102 
00103 /* Slope - (max_mtu - min_mtu)/(max_mtu_ufc - min_mtu_ufc) */
00104 /* Slope - 93 */
00105 /* 60 - 9k Mtu, 140 - 1.5k mtu */
00106 #define TTI_T1A_TX_UFC_C(mtu)   (60 + ((VXGE_HW_MAX_MTU - mtu)/93))
00107 
00108 /* Slope - 37 */
00109 /* 100 - 9k Mtu, 300 - 1.5k mtu */
00110 #define TTI_T1A_TX_UFC_D(mtu)   (100 + ((VXGE_HW_MAX_MTU - mtu)/37))
00111 
00112 #define RTI_RX_URANGE_A         5
00113 #define RTI_RX_URANGE_B         15
00114 #define RTI_RX_URANGE_C         40
00115 #define RTI_T1A_RX_URANGE_A     1
00116 #define RTI_T1A_RX_URANGE_B     20
00117 #define RTI_T1A_RX_URANGE_C     50
00118 #define RTI_RX_UFC_A            1
00119 #define RTI_RX_UFC_B            5
00120 #define RTI_RX_UFC_C            10
00121 #define RTI_RX_UFC_D            15
00122 #define RTI_T1A_RX_UFC_B        20
00123 #define RTI_T1A_RX_UFC_C        50
00124 #define RTI_T1A_RX_UFC_D        60
00125 
00126 /*
00127  * The interrupt rate is maintained at 3k per second with the moderation
00128  * parameters for most traffics but not all. This is the maximum interrupt
00129  * count per allowed per function with INTA or per vector in the case of in a
00130  * MSI-X 10 millisecond time period. Enabled only for Titan 1A.
00131  */
00132 #define VXGE_T1A_MAX_INTERRUPT_COUNT 100
00133 
00134 #define VXGE_ENABLE_NAPI        1
00135 #define VXGE_DISABLE_NAPI       0
00136 #define VXGE_LRO_MAX_BYTES 0x4000
00137 #define VXGE_T1A_LRO_MAX_BYTES 0xC000
00138 
00139 #define VXGE_HW_MIN_VPATH_TX_BW_SUPPORT 0
00140 #define VXGE_HW_MAX_VPATH_TX_BW_SUPPORT 7
00141 
00142 /* Milli secs timer period */
00143 #define VXGE_TIMER_DELAY                10000
00144 
00145 #define VXGE_TIMER_COUNT        (2 * 60)
00146 
00147 #define VXGE_LL_MAX_FRAME_SIZE(dev) ((dev)->mtu + VXGE_HW_MAC_HEADER_MAX_SIZE)
00148 
00149 #define VXGE_REG_DUMP_BUFSIZE           65000
00150 
00151 #define is_mf(function_mode) \
00152         ((function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION) ||   \
00153         (function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_17) || \
00154         (function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_2) ||  \
00155         (function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_4))
00156 
00157 #define is_titan1(dev_id, rev) (((dev_id == PCI_DEVICE_ID_TITAN_UNI) || \
00158                                 (dev_id == PCI_DEVICE_ID_TITAN_WIN)) && \
00159                                 (rev == VXGE_HW_TITAN1_PCI_REVISION))
00160 
00161 /* These flags represent the devices temporary state */
00162 #define __VXGE_STATE_RESET_CARD         0x01
00163 #define __VXGE_STATE_CARD_UP            0x02
00164 
00165 #define test_bit(bit, loc)      ((bit) & (loc))
00166 #define set_bit(bit, loc)       do { (loc) |= (bit); } while (0);
00167 #define clear_bit(bit, loc)     do { (loc) &= ~(bit); } while (0);
00168 
00169 #define msleep(n)       mdelay(n)
00170 
00171 struct vxge_fifo {
00172         struct net_device       *ndev;
00173         struct pci_device       *pdev;
00174         struct __vxge_hw_fifo   *fifoh;
00175 };
00176 
00177 struct vxge_ring {
00178         struct net_device       *ndev;
00179         struct pci_device       *pdev;
00180         struct __vxge_hw_ring   *ringh;
00181 };
00182 
00183 struct vxge_vpath {
00184 
00185         struct vxge_fifo fifo;
00186         struct vxge_ring ring;
00187 
00188         /* Actual vpath id for this vpath in the device - 0 to 16 */
00189         int device_id;
00190         int is_open;
00191         int vp_open;
00192         u8 (macaddr)[ETH_ALEN];
00193         u8 (macmask)[ETH_ALEN];
00194         struct vxgedev *vdev;
00195         struct __vxge_hw_virtualpath *vpathh;
00196 };
00197 
00198 struct vxgedev {
00199         struct net_device       *ndev;
00200         struct pci_device       *pdev;
00201         struct __vxge_hw_device *devh;
00202         u8                      titan1;
00203 
00204         unsigned long           state;
00205 
00206         struct vxge_vpath       vpath;
00207 
00208         void __iomem            *bar0;
00209         int                     mtu;
00210 
00211         char                    fw_version[VXGE_HW_FW_STRLEN];
00212 };
00213 
00214 void vxge_vpath_intr_enable(struct vxgedev *vdev, int vp_id);
00215 
00216 void vxge_vpath_intr_disable(struct vxgedev *vdev, int vp_id);
00217 
00218 int vxge_reset(struct vxgedev *vdev);
00219 
00220 enum vxge_hw_status
00221 vxge_xmit_compl(struct __vxge_hw_fifo *fifo_hw,
00222         struct vxge_hw_fifo_txd *txdp, enum vxge_hw_fifo_tcode tcode);
00223 
00224 void vxge_close_vpaths(struct vxgedev *vdev);
00225 
00226 int vxge_open_vpaths(struct vxgedev *vdev);
00227 
00228 enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev);
00229 
00230 #endif