iPXE
vxge_reg.h
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00001 /*
00002  * vxge-reg.h: iPXE driver for Neterion Inc's X3100 Series 10GbE
00003  *              PCIe I/O Virtualized Server Adapter.
00004  *
00005  * Copyright(c) 2002-2010 Neterion Inc.
00006  *
00007  * This software may be used and distributed according to the terms of
00008  * the GNU General Public License (GPL), incorporated herein by
00009  * reference.  Drivers based on or derived from this code fall under
00010  * the GPL and must retain the authorship, copyright and license
00011  * notice.
00012  *
00013  */
00014 
00015 FILE_LICENCE(GPL2_ONLY);
00016 
00017 #ifndef VXGE_REG_H
00018 #define VXGE_REG_H
00019 
00020 #include <stdint.h>
00021 /*
00022  * vxge_mBIT(loc) - set bit at offset
00023  */
00024 #define vxge_mBIT(loc)          (0x8000000000000000ULL >> (loc))
00025 
00026 /*
00027  * vxge_vBIT(val, loc, sz) - set bits at offset
00028  */
00029 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
00030 #define vxge_vBIT32(val, loc, sz)       (((u32)(val)) << (32-(loc)-(sz)))
00031 
00032 /*
00033  * vxge_bVALn(bits, loc, n) - Get the value of n bits at location
00034  */
00035 #define vxge_bVALn(bits, loc, n) \
00036         ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1))
00037 
00038 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \
00039                                                         vxge_bVALn(bits, 0, 16)
00040 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \
00041                                                         vxge_bVALn(bits, 48, 8)
00042 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \
00043                                                         vxge_bVALn(bits, 56, 8)
00044 
00045 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \
00046                                                         vxge_bVALn(bits, 3, 5)
00047 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits) \
00048                                                         vxge_bVALn(bits, 5, 3)
00049 #define VXGE_HW_PF_SW_RESET_COMMAND                             0xA5
00050 
00051 #define VXGE_HW_TITAN_PCICFGMGMT_REG_SPACES             17
00052 #define VXGE_HW_TITAN_SRPCIM_REG_SPACES                 17
00053 #define VXGE_HW_TITAN_VPMGMT_REG_SPACES                 17
00054 #define VXGE_HW_TITAN_VPATH_REG_SPACES                  17
00055 
00056 
00057 #define VXGE_HW_PRIV_FN_ACTION                  8
00058 #define VXGE_HW_PRIV_VP_ACTION                  5
00059 #define VXGE_HW_PRIV_FN_MEMO                    13
00060 #define VXGE_HW_EN_DIS_UDP_RTH                  10
00061 #define VXGE_HW_BW_CONTROL                      12
00062 #define VXGE_HW_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF     17
00063 
00064 #define VXGE_HW_FW_API_FUNC_MODE                11
00065 #define VXGE_HW_FW_API_GET_FUNC_MODE            29
00066 #define VXGE_HW_FW_API_FUNC_MODE_COMMIT         21
00067 #define VXGE_HW_GET_FUNC_MODE_VAL(val)          (val & 0xFF)
00068 
00069 #define VXGE_HW_BYTES_PER_U64                   8
00070 #define VXGE_HW_FW_UPGRADE_MEMO                 13
00071 #define VXGE_HW_FW_UPGRADE_ACTION               16
00072 #define VXGE_HW_FW_UPGRADE_OFFSET_START         2 /* Start upgrade */
00073 #define VXGE_HW_FW_UPGRADE_OFFSET_SEND          3 /* Send upgrade data */
00074 #define VXGE_HW_FW_UPGRADE_OFFSET_COMMIT        4 /* Commit upgrade */
00075 #define VXGE_HW_FW_UPGRADE_OFFSET_READ          5 /* Read upgrade version */
00076 
00077 #define VXGE_HW_FW_UPGRADE_BLK_SIZE             16 /* Bytes to write */
00078 #define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val)   (val & 0xff)
00079 #define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val)   ((val >> 8) & 0xff)
00080 
00081 #define VXGE_HW_ASIC_MODE_RESERVED                              0
00082 #define VXGE_HW_ASIC_MODE_NO_IOV                                1
00083 #define VXGE_HW_ASIC_MODE_SR_IOV                                2
00084 #define VXGE_HW_ASIC_MODE_MR_IOV                                3
00085 
00086 #define VXGE_HW_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN               vxge_mBIT(3)
00087 #define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE              vxge_mBIT(19)
00088 #define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH    vxge_mBIT(23)
00089 #define VXGE_HW_TXMAC_GEN_CFG1_HOST_APPEND_FCS                  vxge_mBIT(31)
00090 
00091 #define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) vxge_bVALn(bits, 3, 1)
00092 
00093 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) \
00094                                                 vxge_bVALn(bits, 0, 32)
00095 
00096 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits) \
00097                                                         vxge_bVALn(bits, 50, 14)
00098 
00099 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) \
00100                                                         vxge_bVALn(bits, 0, 17)
00101 
00102 #define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits) \
00103                                                         vxge_bVALn(bits, 3, 5)
00104 
00105 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits) \
00106                                                         vxge_bVALn(bits, 17, 15)
00107 
00108 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE                  0
00109 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY             1
00110 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE                2
00111 
00112 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY                0
00113 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE                1
00114 
00115 #define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val) \
00116                                 (val&~VXGE_HW_TOC_KDFC_INITIAL_BIR(7))
00117 #define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val) \
00118                                 vxge_bVALn(val, 61, 3)
00119 #define VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET(val) \
00120                                 (val&~VXGE_HW_TOC_USDC_INITIAL_BIR(7))
00121 #define VXGE_HW_TOC_GET_USDC_INITIAL_BIR(val) \
00122                                 vxge_bVALn(val, 61, 3)
00123 
00124 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits)   bits
00125 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits)     bits
00126 
00127 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) \
00128                                                 vxge_bVALn(bits, 1, 15)
00129 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) \
00130                                                 vxge_bVALn(bits, 17, 15)
00131 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) \
00132                                                 vxge_bVALn(bits, 33, 15)
00133 
00134 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vxge_vBIT(val, 42, 5)
00135 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vxge_vBIT(val, 47, 2)
00136 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) \
00137                                         vxge_vBIT(val, 49, 15)
00138 
00139 #define VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER                   0
00140 #define VXGE_HW_PRC_CFG4_RING_MODE_THREE_BUFFER                 1
00141 #define VXGE_HW_PRC_CFG4_RING_MODE_FIVE_BUFFER                  2
00142 
00143 #define VXGE_HW_PRC_CFG7_SCATTER_MODE_A                         0
00144 #define VXGE_HW_PRC_CFG7_SCATTER_MODE_B                         2
00145 #define VXGE_HW_PRC_CFG7_SCATTER_MODE_C                         1
00146 
00147 #define VXGE_HW_RTS_MGR_STEER_CTRL_WE_READ                             0
00148 #define VXGE_HW_RTS_MGR_STEER_CTRL_WE_WRITE                            1
00149 
00150 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA                  0
00151 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID                 1
00152 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE               2
00153 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN                  3
00154 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN            4
00155 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG         5
00156 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT         6
00157 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG       7
00158 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK            8
00159 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY             9
00160 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS                 10
00161 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS                  11
00162 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT        12
00163 #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_VERSION          13
00164 
00165 #define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) \
00166                                                         vxge_bVALn(bits, 0, 48)
00167 #define VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48)
00168 
00169 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \
00170                                                         vxge_bVALn(bits, 0, 48)
00171 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vxge_vBIT(val, 0, 48)
00172 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE \
00173                                                                 vxge_mBIT(54)
00174 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits) \
00175                                                         vxge_bVALn(bits, 55, 5)
00176 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) \
00177                                                         vxge_vBIT(val, 55, 5)
00178 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits) \
00179                                                         vxge_bVALn(bits, 62, 2)
00180 #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vxge_vBIT(val, 62, 2)
00181 
00182 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY                  0
00183 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY               1
00184 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY           2
00185 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY            3
00186 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY                 0
00187 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY                1
00188 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY            3
00189 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL                4
00190 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR                  172
00191 
00192 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA                0
00193 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID               1
00194 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE             2
00195 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN                3
00196 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG       5
00197 #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT  6
00198 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG     7
00199 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK          8
00200 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY           9
00201 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS               10
00202 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS                11
00203 #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12
00204 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO           13
00205 
00206 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \
00207                                                         vxge_bVALn(bits, 0, 48)
00208 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48)
00209 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_SEND_TO_NW       vxge_mBIT(51)
00210 
00211 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) vxge_bVALn(bits, 0, 12)
00212 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vxge_vBIT(val, 0, 12)
00213 
00214 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits)  vxge_bVALn(bits, 0, 11)
00215 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE(val) vxge_vBIT(val, 0, 16)
00216 
00217 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) \
00218                                                         vxge_bVALn(bits, 3, 1)
00219 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL          vxge_mBIT(3)
00220 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) \
00221                                                         vxge_bVALn(bits, 7, 1)
00222 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL           vxge_mBIT(7)
00223 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) \
00224                                                         vxge_bVALn(bits, 8, 16)
00225 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vxge_vBIT(val, 8, 16)
00226 
00227 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) \
00228                                                         vxge_bVALn(bits, 3, 1)
00229 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN           vxge_mBIT(3)
00230 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits) \
00231                                                         vxge_bVALn(bits, 4, 4)
00232 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) \
00233                                                         vxge_vBIT(val, 4, 4)
00234 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits) \
00235                                                         vxge_bVALn(bits, 10, 2)
00236 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) \
00237                                                         vxge_vBIT(val, 10, 2)
00238 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS  0
00239 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS   1
00240 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C   2
00241 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits) \
00242                                                         vxge_bVALn(bits, 15, 1)
00243 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN  vxge_mBIT(15)
00244 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits) \
00245                                                         vxge_bVALn(bits, 19, 1)
00246 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN      vxge_mBIT(19)
00247 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits) \
00248                                                         vxge_bVALn(bits, 23, 1)
00249 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN  vxge_mBIT(23)
00250 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits) \
00251                                                         vxge_bVALn(bits, 27, 1)
00252 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN      vxge_mBIT(27)
00253 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits) \
00254                                                         vxge_bVALn(bits, 31, 1)
00255 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN vxge_mBIT(31)
00256 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits) \
00257                                                         vxge_bVALn(bits, 35, 1)
00258 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN   vxge_mBIT(35)
00259 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits) \
00260                                                         vxge_bVALn(bits, 39, 1)
00261 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE     vxge_mBIT(39)
00262 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits) \
00263                                                         vxge_bVALn(bits, 43, 1)
00264 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN    vxge_mBIT(43)
00265 
00266 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits) \
00267                                                         vxge_bVALn(bits, 3, 1)
00268 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN     vxge_mBIT(3)
00269 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits) \
00270                                                         vxge_bVALn(bits, 9, 7)
00271 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val) \
00272                                                         vxge_vBIT(val, 9, 7)
00273 
00274 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits) \
00275                                                         vxge_bVALn(bits, 0, 8)
00276 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val) \
00277                                                         vxge_vBIT(val, 0, 8)
00278 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits) \
00279                                                         vxge_bVALn(bits, 8, 1)
00280 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN       vxge_mBIT(8)
00281 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits) \
00282                                                         vxge_bVALn(bits, 9, 7)
00283 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val) \
00284                                                         vxge_vBIT(val, 9, 7)
00285 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits) \
00286                                                         vxge_bVALn(bits, 16, 8)
00287 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val) \
00288                                                         vxge_vBIT(val, 16, 8)
00289 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits) \
00290                                                         vxge_bVALn(bits, 24, 1)
00291 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN       vxge_mBIT(24)
00292 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits) \
00293                                                         vxge_bVALn(bits, 25, 7)
00294 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val) \
00295                                                         vxge_vBIT(val, 25, 7)
00296 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits) \
00297                                                         vxge_bVALn(bits, 0, 8)
00298 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val) \
00299                                                         vxge_vBIT(val, 0, 8)
00300 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits) \
00301                                                         vxge_bVALn(bits, 8, 1)
00302 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN       vxge_mBIT(8)
00303 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits) \
00304                                                         vxge_bVALn(bits, 9, 7)
00305 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val) \
00306                                                         vxge_vBIT(val, 9, 7)
00307 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits) \
00308                                                         vxge_bVALn(bits, 16, 8)
00309 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val) \
00310                                                         vxge_vBIT(val, 16, 8)
00311 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits) \
00312                                                         vxge_bVALn(bits, 24, 1)
00313 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN       vxge_mBIT(24)
00314 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits) \
00315                                                         vxge_bVALn(bits, 25, 7)
00316 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val) \
00317                                                         vxge_vBIT(val, 25, 7)
00318 
00319 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits) \
00320                                                         vxge_bVALn(bits, 0, 32)
00321 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val) \
00322                                                         vxge_vBIT(val, 0, 32)
00323 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits) \
00324                                                         vxge_bVALn(bits, 32, 32)
00325 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val) \
00326                                                         vxge_vBIT(val, 32, 32)
00327 
00328 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits) \
00329                                                         vxge_bVALn(bits, 0, 16)
00330 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val) \
00331                                                         vxge_vBIT(val, 0, 16)
00332 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits) \
00333                                                         vxge_bVALn(bits, 16, 16)
00334 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val) \
00335                                                         vxge_vBIT(val, 16, 16)
00336 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits) \
00337                                                         vxge_bVALn(bits, 32, 4)
00338 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val) \
00339                                                         vxge_vBIT(val, 32, 4)
00340 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits) \
00341                                                         vxge_bVALn(bits, 36, 4)
00342 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val) \
00343                                                         vxge_vBIT(val, 36, 4)
00344 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits) \
00345                                                         vxge_bVALn(bits, 40, 2)
00346 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) \
00347                                                         vxge_vBIT(val, 40, 2)
00348 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits) \
00349                                                         vxge_bVALn(bits, 42, 2)
00350 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) \
00351                                                         vxge_vBIT(val, 42, 2)
00352 
00353 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) \
00354                                                         vxge_bVALn(bits, 0, 64)
00355 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vxge_vBIT(val, 0, 64)
00356 
00357 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) \
00358                                                         vxge_bVALn(bits, 3, 1)
00359 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN             vxge_mBIT(3)
00360 
00361 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) \
00362                                                         vxge_bVALn(bits, 3, 1)
00363 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN              vxge_mBIT(3)
00364 
00365 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \
00366                                                         vxge_bVALn(bits, 0, 48)
00367 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) \
00368                                                         vxge_vBIT(val, 0, 48)
00369 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) \
00370                                                         vxge_vBIT(val, 62, 2)
00371 
00372 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits) \
00373                                                         vxge_bVALn(bits, 0, 8)
00374 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val) \
00375                                                         vxge_vBIT(val, 0, 8)
00376 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits) \
00377                                                         vxge_bVALn(bits, 8, 1)
00378 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN       vxge_mBIT(8)
00379 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits) \
00380                                                         vxge_bVALn(bits, 9, 7)
00381 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val) \
00382                                                         vxge_vBIT(val, 9, 7)
00383 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits) \
00384                                                         vxge_bVALn(bits, 16, 8)
00385 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val) \
00386                                                         vxge_vBIT(val, 16, 8)
00387 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits) \
00388                                                         vxge_bVALn(bits, 24, 1)
00389 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN       vxge_mBIT(24)
00390 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits) \
00391                                                         vxge_bVALn(bits, 25, 7)
00392 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val) \
00393                                                         vxge_vBIT(val, 25, 7)
00394 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits) \
00395                                                         vxge_bVALn(bits, 32, 8)
00396 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val) \
00397                                                         vxge_vBIT(val, 32, 8)
00398 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits) \
00399                                                         vxge_bVALn(bits, 40, 1)
00400 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN       vxge_mBIT(40)
00401 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits) \
00402                                                         vxge_bVALn(bits, 41, 7)
00403 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val) \
00404                                                         vxge_vBIT(val, 41, 7)
00405 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits) \
00406                                                         vxge_bVALn(bits, 48, 8)
00407 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val) \
00408                                                         vxge_vBIT(val, 48, 8)
00409 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits) \
00410                                                         vxge_bVALn(bits, 56, 1)
00411 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN       vxge_mBIT(56)
00412 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits) \
00413                                                         vxge_bVALn(bits, 57, 7)
00414 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val) \
00415                                                         vxge_vBIT(val, 57, 7)
00416 
00417 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER           0
00418 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER         1
00419 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_VERSION               2
00420 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE              3
00421 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0                4
00422 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1                5
00423 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2                6
00424 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3                7
00425 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORTS                  8
00426 
00427 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_TYPE         10
00428 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_VENDOR       11
00429 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_PARTNO       13
00430 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_SERNO        14
00431 
00432 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_TYPE         20
00433 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_VENDOR       21
00434 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_PARTNO       23
00435 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_SERNO        24
00436 
00437 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON                   1
00438 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF                  0
00439 
00440 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits) \
00441                                                         vxge_bVALn(bits, 0, 8)
00442 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vxge_vBIT(val, 0, 8)
00443 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits) \
00444                                                         vxge_bVALn(bits, 8, 8)
00445 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vxge_vBIT(val, 8, 8)
00446 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) \
00447                                                 vxge_bVALn(bits, 16, 16)
00448 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) \
00449                                                         vxge_vBIT(val, 16, 16)
00450 
00451 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits) \
00452                                                 vxge_bVALn(bits, 32, 8)
00453 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vxge_vBIT(val, 32, 8)
00454 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits) \
00455                                                 vxge_bVALn(bits, 40, 8)
00456 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vxge_vBIT(val, 40, 8)
00457 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits) \
00458                                                 vxge_bVALn(bits, 48, 16)
00459 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits) \
00460                                                 vxge_bVALn(bits, 0, 8)
00461 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vxge_vBIT(val, 48, 16)
00462 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits) \
00463                                                 vxge_bVALn(bits, 0, 8)
00464 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY(val) vxge_vBIT(val, 0, 8)
00465 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits) \
00466                                                         vxge_bVALn(bits, 8, 8)
00467 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH(val) vxge_vBIT(val, 8, 8)
00468 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits) \
00469                                                         vxge_bVALn(bits, 16, 16)
00470 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR(val) \
00471                                                         vxge_vBIT(val, 16, 16)
00472 
00473 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits) \
00474                                                         vxge_bVALn(bits, 32, 8)
00475 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR vxge_vBIT(val, 32, 8)
00476 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits) \
00477                                                         vxge_bVALn(bits, 40, 8)
00478 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR vxge_vBIT(val, 40, 8)
00479 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \
00480                                                         vxge_bVALn(bits, 48, 16)
00481 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16)
00482 
00483 /* Netork port control API related */
00484 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(val) \
00485                                                 vxge_vBIT(val, 0, 8)
00486 
00487 /* Bandwidth & priority related MACROS */
00488 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_API_VER(bits) \
00489                                                 vxge_bVALn(bits, 0, 8)
00490 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_TX_PRIORITY(bits) \
00491                                                         vxge_bVALn(bits, 21, 3)
00492 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_TX_MIN_BW(bits) \
00493                                                         vxge_bVALn(bits, 24, 8)
00494 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_TX_MAX_BW(bits) \
00495                                                         vxge_bVALn(bits, 32, 8)
00496 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(bits) \
00497                                                         vxge_bVALn(bits, 45, 3)
00498 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RX_MIN_BW(bits) \
00499                                                         vxge_bVALn(bits, 48, 8)
00500 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(bits) \
00501                                                         vxge_bVALn(bits, 56, 8)
00502 
00503 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(val) \
00504                                                         vxge_vBIT(val, 0, 8)
00505 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(val) \
00506                                                         vxge_vBIT(val, 21, 3)
00507 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_TX_MIN_BW(val) \
00508                                                         vxge_vBIT(val, 24, 8)
00509 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(val) \
00510                                                         vxge_vBIT(val, 32, 8)
00511 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(val) \
00512                                                         vxge_vBIT(val, 45, 3)
00513 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_RX_MIN_BW(val) \
00514                                                         vxge_vBIT(val, 48, 8)
00515 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(val) \
00516                                                         vxge_vBIT(val, 56, 8)
00517 
00518 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\
00519                                                         vxge_bVALn(bits, 0, 18)
00520 
00521 #define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) \
00522                                                         vxge_bVALn(bits, 48, 16)
00523 #define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits) \
00524                                                         vxge_bVALn(bits, 32, 32)
00525 #define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits)     vxge_bVALn(bits, 48, 16)
00526 #define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) \
00527                                                         vxge_bVALn(bits, 0, 32)
00528 #define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) \
00529                                                         vxge_bVALn(bits, 0, 32)
00530 #define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) \
00531                                                         vxge_bVALn(bits, 0, 32)
00532 #define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits)      (bits)
00533 #define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits)      (bits)
00534 #define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) \
00535                                                         vxge_bVALn(bits, 32, 32)
00536 #define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) \
00537                                                         vxge_bVALn(bits, 32, 32)
00538 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits) \
00539                                                         vxge_bVALn(bits, 0, 32)
00540 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits) \
00541                                                         vxge_bVALn(bits, 32, 32)
00542 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits) \
00543                                                         vxge_bVALn(bits, 0, 32)
00544 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits) \
00545                                                         vxge_bVALn(bits, 32, 32)
00546 #define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits) \
00547                                                         vxge_bVALn(bits, 0, 32)
00548 #define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits) \
00549                                                         vxge_bVALn(bits, 32, 32)
00550 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits\
00551 ) vxge_bVALn(bits, 48, 16)
00552 #define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) vxge_bVALn(bits, 0, 16)
00553 #define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) \
00554                                                         vxge_bVALn(bits, 16, 16)
00555 #define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) \
00556                                                         vxge_bVALn(bits, 32, 16)
00557 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits)  vxge_bVALn(bits, 0, 16)
00558 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits) \
00559                                                         vxge_bVALn(bits, 16, 16)
00560 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) \
00561                                                         vxge_bVALn(bits, 32, 16)
00562 
00563 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) \
00564                                                         vxge_bVALn(bits, 0, 32)
00565 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) \
00566                                                         vxge_bVALn(bits, 32, 32)
00567 #define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits\
00568 ) vxge_bVALn(bits, 32, 32)
00569 #define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits\
00570 ) vxge_bVALn(bits, 32, 32)
00571 #define \
00572 VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \
00573         vxge_bVALn(bits, 32, 32)
00574 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) \
00575                                                         vxge_bVALn(bits, 0, 32)
00576 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) \
00577                                                         vxge_bVALn(bits, 32, 32)
00578 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) \
00579                                                         vxge_bVALn(bits, 0, 32)
00580 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) \
00581                                                         vxge_bVALn(bits, 32, 32)
00582 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) \
00583                                                         vxge_bVALn(bits, 0, 32)
00584 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) \
00585                                                         vxge_bVALn(bits, 32, 32)
00586 #define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) \
00587                                                         vxge_bVALn(bits, 32, 32)
00588 #define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) \
00589                                                         vxge_bVALn(bits, 32, 32)
00590 
00591 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits)      vxge_bVALn(bits, 0, 32)
00592 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits)      vxge_bVALn(bits, 32, 32)
00593 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits)  vxge_bVALn(bits, 0, 32)
00594 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits)  vxge_bVALn(bits, 32, 32)
00595 #define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits)  vxge_bVALn(bits, 0, 32)
00596 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits)   vxge_bVALn(bits, 0, 16)
00597 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits)  vxge_bVALn(bits, 16, 16)
00598 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) vxge_bVALn(bits, 32, 16)
00599 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits)   vxge_bVALn(bits, 0, 16)
00600 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits)  vxge_bVALn(bits, 16, 16)
00601 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) vxge_bVALn(bits, 32, 16)
00602 
00603 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits) \
00604                                                         vxge_bVALn(bits, 32, 32)
00605 
00606 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits) \
00607                                                         vxge_bVALn(bits, 0, 8)
00608 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits) \
00609                                                         vxge_bVALn(bits, 8, 8)
00610 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits) \
00611                                                         vxge_bVALn(bits, 16, 8)
00612 
00613 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits) \
00614                                                         vxge_bVALn(bits, 0, 8)
00615 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits) \
00616                                                         vxge_bVALn(bits, 8, 8)
00617 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits) \
00618                                                         vxge_bVALn(bits, 16, 8)
00619 
00620 #define VXGE_HW_CONFIG_PRIV_H
00621 
00622 #define VXGE_HW_SWAPPER_INITIAL_VALUE                   0x0123456789abcdefULL
00623 #define VXGE_HW_SWAPPER_BYTE_SWAPPED                    0xefcdab8967452301ULL
00624 #define VXGE_HW_SWAPPER_BIT_FLIPPED                     0x80c4a2e691d5b3f7ULL
00625 #define VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED        0xf7b3d591e6a2c480ULL
00626 
00627 #define VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE           0xFFFFFFFFFFFFFFFFULL
00628 #define VXGE_HW_SWAPPER_READ_BYTE_SWAP_DISABLE          0x0000000000000000ULL
00629 
00630 #define VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE            0xFFFFFFFFFFFFFFFFULL
00631 #define VXGE_HW_SWAPPER_READ_BIT_FLAP_DISABLE           0x0000000000000000ULL
00632 
00633 #define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE          0xFFFFFFFFFFFFFFFFULL
00634 #define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_DISABLE         0x0000000000000000ULL
00635 
00636 #define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE           0xFFFFFFFFFFFFFFFFULL
00637 #define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_DISABLE          0x0000000000000000ULL
00638 
00639 /*
00640  * The registers are memory mapped and are native big-endian byte order. The
00641  * little-endian hosts are handled by enabling hardware byte-swapping for
00642  * register and dma operations.
00643  */
00644 struct vxge_hw_legacy_reg {
00645 
00646         u8      unused00010[0x00010];
00647 
00648 /*0x00010*/     u64     toc_swapper_fb;
00649 #define VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00650 /*0x00018*/     u64     pifm_rd_swap_en;
00651 #define VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vxge_vBIT(val, 0, 64)
00652 /*0x00020*/     u64     pifm_rd_flip_en;
00653 #define VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vxge_vBIT(val, 0, 64)
00654 /*0x00028*/     u64     pifm_wr_swap_en;
00655 #define VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vxge_vBIT(val, 0, 64)
00656 /*0x00030*/     u64     pifm_wr_flip_en;
00657 #define VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vxge_vBIT(val, 0, 64)
00658 /*0x00038*/     u64     toc_first_pointer;
00659 #define VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00660 /*0x00040*/     u64     host_access_en;
00661 #define VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vxge_vBIT(val, 0, 64)
00662 
00663 } __attribute((packed));
00664 
00665 struct vxge_hw_toc_reg {
00666 
00667         u8      unused00050[0x00050];
00668 
00669 /*0x00050*/     u64     toc_common_pointer;
00670 #define VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00671 /*0x00058*/     u64     toc_memrepair_pointer;
00672 #define VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00673 /*0x00060*/     u64     toc_pcicfgmgmt_pointer[17];
00674 #define VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00675         u8      unused001e0[0x001e0-0x000e8];
00676 
00677 /*0x001e0*/     u64     toc_mrpcim_pointer;
00678 #define VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00679 /*0x001e8*/     u64     toc_srpcim_pointer[17];
00680 #define VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00681         u8      unused00278[0x00278-0x00270];
00682 
00683 /*0x00278*/     u64     toc_vpmgmt_pointer[17];
00684 #define VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00685         u8      unused00390[0x00390-0x00300];
00686 
00687 /*0x00390*/     u64     toc_vpath_pointer[17];
00688 #define VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64)
00689         u8      unused004a0[0x004a0-0x00418];
00690 
00691 /*0x004a0*/     u64     toc_kdfc;
00692 #define VXGE_HW_TOC_KDFC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61)
00693 #define VXGE_HW_TOC_KDFC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3)
00694 /*0x004a8*/     u64     toc_usdc;
00695 #define VXGE_HW_TOC_USDC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61)
00696 #define VXGE_HW_TOC_USDC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3)
00697 /*0x004b0*/     u64     toc_kdfc_vpath_stride;
00698 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val) \
00699                                                         vxge_vBIT(val, 0, 64)
00700 /*0x004b8*/     u64     toc_kdfc_fifo_stride;
00701 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val) \
00702                                                         vxge_vBIT(val, 0, 64)
00703 
00704 } __attribute((packed));
00705 
00706 struct vxge_hw_common_reg {
00707 
00708         u8      unused00a00[0x00a00];
00709 
00710 /*0x00a00*/     u64     prc_status1;
00711 #define VXGE_HW_PRC_STATUS1_PRC_VP_QUIESCENT(n) vxge_mBIT(n)
00712 /*0x00a08*/     u64     rxdcm_reset_in_progress;
00713 #define VXGE_HW_RXDCM_RESET_IN_PROGRESS_PRC_VP(n)       vxge_mBIT(n)
00714 /*0x00a10*/     u64     replicq_flush_in_progress;
00715 #define VXGE_HW_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n)     vxge_mBIT(n)
00716 /*0x00a18*/     u64     rxpe_cmds_reset_in_progress;
00717 #define VXGE_HW_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n)   vxge_mBIT(n)
00718 /*0x00a20*/     u64     mxp_cmds_reset_in_progress;
00719 #define VXGE_HW_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n)    vxge_mBIT(n)
00720 /*0x00a28*/     u64     noffload_reset_in_progress;
00721 #define VXGE_HW_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n)    vxge_mBIT(n)
00722 /*0x00a30*/     u64     rd_req_in_progress;
00723 #define VXGE_HW_RD_REQ_IN_PROGRESS_VP(n)        vxge_mBIT(n)
00724 /*0x00a38*/     u64     rd_req_outstanding;
00725 #define VXGE_HW_RD_REQ_OUTSTANDING_VP(n)        vxge_mBIT(n)
00726 /*0x00a40*/     u64     kdfc_reset_in_progress;
00727 #define VXGE_HW_KDFC_RESET_IN_PROGRESS_NOA_VP(n)        vxge_mBIT(n)
00728         u8      unused00b00[0x00b00-0x00a48];
00729 
00730 /*0x00b00*/     u64     one_cfg_vp;
00731 #define VXGE_HW_ONE_CFG_VP_RDY(n)       vxge_mBIT(n)
00732 /*0x00b08*/     u64     one_common;
00733 #define VXGE_HW_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n)       vxge_mBIT(n)
00734         u8      unused00b80[0x00b80-0x00b10];
00735 
00736 /*0x00b80*/     u64     tim_int_en;
00737 #define VXGE_HW_TIM_INT_EN_TIM_VP(n)    vxge_mBIT(n)
00738 /*0x00b88*/     u64     tim_set_int_en;
00739 #define VXGE_HW_TIM_SET_INT_EN_VP(n)    vxge_mBIT(n)
00740 /*0x00b90*/     u64     tim_clr_int_en;
00741 #define VXGE_HW_TIM_CLR_INT_EN_VP(n)    vxge_mBIT(n)
00742 /*0x00b98*/     u64     tim_mask_int_during_reset;
00743 #define VXGE_HW_TIM_MASK_INT_DURING_RESET_VPATH(n)      vxge_mBIT(n)
00744 /*0x00ba0*/     u64     tim_reset_in_progress;
00745 #define VXGE_HW_TIM_RESET_IN_PROGRESS_TIM_VPATH(n)      vxge_mBIT(n)
00746 /*0x00ba8*/     u64     tim_outstanding_bmap;
00747 #define VXGE_HW_TIM_OUTSTANDING_BMAP_TIM_VPATH(n)       vxge_mBIT(n)
00748         u8      unused00c00[0x00c00-0x00bb0];
00749 
00750 /*0x00c00*/     u64     msg_reset_in_progress;
00751 #define VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vxge_vBIT(val, 0, 17)
00752 /*0x00c08*/     u64     msg_mxp_mr_ready;
00753 #define VXGE_HW_MSG_MXP_MR_READY_MP_BOOTED(n)   vxge_mBIT(n)
00754 /*0x00c10*/     u64     msg_uxp_mr_ready;
00755 #define VXGE_HW_MSG_UXP_MR_READY_UP_BOOTED(n)   vxge_mBIT(n)
00756 /*0x00c18*/     u64     msg_dmq_noni_rtl_prefetch;
00757 #define VXGE_HW_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n)      vxge_mBIT(n)
00758 /*0x00c20*/     u64     msg_umq_rtl_bwr;
00759 #define VXGE_HW_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n)     vxge_mBIT(n)
00760         u8      unused00d00[0x00d00-0x00c28];
00761 
00762 /*0x00d00*/     u64     cmn_rsthdlr_cfg0;
00763 #define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vxge_vBIT(val, 0, 17)
00764 /*0x00d08*/     u64     cmn_rsthdlr_cfg1;
00765 #define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vxge_vBIT(val, 0, 17)
00766 /*0x00d10*/     u64     cmn_rsthdlr_cfg2;
00767 #define VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vxge_vBIT(val, 0, 17)
00768 /*0x00d18*/     u64     cmn_rsthdlr_cfg3;
00769 #define VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vxge_vBIT(val, 0, 17)
00770 /*0x00d20*/     u64     cmn_rsthdlr_cfg4;
00771 #define VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vxge_vBIT(val, 0, 17)
00772         u8      unused00d40[0x00d40-0x00d28];
00773 
00774 /*0x00d40*/     u64     cmn_rsthdlr_cfg8;
00775 #define VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vxge_vBIT(val, 0, 17)
00776 /*0x00d48*/     u64     stats_cfg0;
00777 #define VXGE_HW_STATS_CFG0_STATS_ENABLE(val) vxge_vBIT(val, 0, 17)
00778         u8      unused00da8[0x00da8-0x00d50];
00779 
00780 /*0x00da8*/     u64     clear_msix_mask_vect[4];
00781 #define VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) \
00782                                                 vxge_vBIT(val, 0, 17)
00783 /*0x00dc8*/     u64     set_msix_mask_vect[4];
00784 #define VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vxge_vBIT(val, 0, 17)
00785 /*0x00de8*/     u64     clear_msix_mask_all_vect;
00786 #define VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val) \
00787                                                         vxge_vBIT(val, 0, 17)
00788 /*0x00df0*/     u64     set_msix_mask_all_vect;
00789 #define VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val) \
00790                                                         vxge_vBIT(val, 0, 17)
00791 /*0x00df8*/     u64     mask_vector[4];
00792 #define VXGE_HW_MASK_VECTOR_MASK_VECTOR(val) vxge_vBIT(val, 0, 17)
00793 /*0x00e18*/     u64     msix_pending_vector[4];
00794 #define VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) \
00795                                                         vxge_vBIT(val, 0, 17)
00796 /*0x00e38*/     u64     clr_msix_one_shot_vec[4];
00797 #define VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val) \
00798                                                         vxge_vBIT(val, 0, 17)
00799 /*0x00e58*/     u64     titan_asic_id;
00800 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vxge_vBIT(val, 0, 16)
00801 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vxge_vBIT(val, 48, 8)
00802 #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vxge_vBIT(val, 56, 8)
00803 /*0x00e60*/     u64     titan_general_int_status;
00804 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT       vxge_mBIT(0)
00805 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT       vxge_mBIT(1)
00806 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT        vxge_mBIT(2)
00807 #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val) \
00808                                                         vxge_vBIT(val, 3, 17)
00809         u8      unused00e70[0x00e70-0x00e68];
00810 
00811 /*0x00e70*/     u64     titan_mask_all_int;
00812 #define VXGE_HW_TITAN_MASK_ALL_INT_ALARM        vxge_mBIT(7)
00813 #define VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC      vxge_mBIT(15)
00814         u8      unused00e80[0x00e80-0x00e78];
00815 
00816 /*0x00e80*/     u64     tim_int_status0;
00817 #define VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0(val) vxge_vBIT(val, 0, 64)
00818 /*0x00e88*/     u64     tim_int_mask0;
00819 #define VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0(val) vxge_vBIT(val, 0, 64)
00820 /*0x00e90*/     u64     tim_int_status1;
00821 #define VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1(val) vxge_vBIT(val, 0, 4)
00822 /*0x00e98*/     u64     tim_int_mask1;
00823 #define VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1(val) vxge_vBIT(val, 0, 4)
00824 /*0x00ea0*/     u64     rti_int_status;
00825 #define VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS(val) vxge_vBIT(val, 0, 17)
00826 /*0x00ea8*/     u64     rti_int_mask;
00827 #define VXGE_HW_RTI_INT_MASK_RTI_INT_MASK(val) vxge_vBIT(val, 0, 17)
00828 /*0x00eb0*/     u64     adapter_status;
00829 #define VXGE_HW_ADAPTER_STATUS_RTDMA_RTDMA_READY        vxge_mBIT(0)
00830 #define VXGE_HW_ADAPTER_STATUS_WRDMA_WRDMA_READY        vxge_mBIT(1)
00831 #define VXGE_HW_ADAPTER_STATUS_KDFC_KDFC_READY  vxge_mBIT(2)
00832 #define VXGE_HW_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY       vxge_mBIT(3)
00833 #define VXGE_HW_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT      vxge_mBIT(4)
00834 #define VXGE_HW_ADAPTER_STATUS_XGMAC_NETWORK_FAULT      vxge_mBIT(5)
00835 #define VXGE_HW_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT  vxge_mBIT(6)
00836 #define VXGE_HW_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY      vxge_mBIT(7)
00837 #define VXGE_HW_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY      vxge_mBIT(8)
00838 #define VXGE_HW_ADAPTER_STATUS_RIC_RIC_RUNNING  vxge_mBIT(9)
00839 #define VXGE_HW_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK        vxge_mBIT(10)
00840 #define VXGE_HW_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK      vxge_mBIT(11)
00841 #define VXGE_HW_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK       vxge_mBIT(12)
00842 #define VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE(val) vxge_vBIT(val, 24, 8)
00843 #define VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val) vxge_vBIT(val, 44, 8)
00844 /*0x00eb8*/     u64     gen_ctrl;
00845 #define VXGE_HW_GEN_CTRL_SPI_MRPCIM_WR_DIS      vxge_mBIT(0)
00846 #define VXGE_HW_GEN_CTRL_SPI_MRPCIM_RD_DIS      vxge_mBIT(1)
00847 #define VXGE_HW_GEN_CTRL_SPI_SRPCIM_WR_DIS      vxge_mBIT(2)
00848 #define VXGE_HW_GEN_CTRL_SPI_SRPCIM_RD_DIS      vxge_mBIT(3)
00849 #define VXGE_HW_GEN_CTRL_SPI_DEBUG_DIS  vxge_mBIT(4)
00850 #define VXGE_HW_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS        vxge_mBIT(5)
00851 #define VXGE_HW_GEN_CTRL_SPI_NOT_USED(val) vxge_vBIT(val, 6, 4)
00852         u8      unused00ed0[0x00ed0-0x00ec0];
00853 
00854 /*0x00ed0*/     u64     adapter_ready;
00855 #define VXGE_HW_ADAPTER_READY_ADAPTER_READY     vxge_mBIT(63)
00856 /*0x00ed8*/     u64     outstanding_read;
00857 #define VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ(val) vxge_vBIT(val, 0, 17)
00858 /*0x00ee0*/     u64     vpath_rst_in_prog;
00859 #define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val) vxge_vBIT(val, 0, 17)
00860 /*0x00ee8*/     u64     vpath_reg_modified;
00861 #define VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vxge_vBIT(val, 0, 17)
00862         u8      unused00fc0[0x00fc0-0x00ef0];
00863 
00864 /*0x00fc0*/     u64     cp_reset_in_progress;
00865 #define VXGE_HW_CP_RESET_IN_PROGRESS_CP_VPATH(n)        vxge_mBIT(n)
00866         u8      unused01080[0x01080-0x00fc8];
00867 
00868 /*0x01080*/     u64     xgmac_ready;
00869 #define VXGE_HW_XGMAC_READY_XMACJ_READY(val) vxge_vBIT(val, 0, 17)
00870         u8      unused010c0[0x010c0-0x01088];
00871 
00872 /*0x010c0*/     u64     fbif_ready;
00873 #define VXGE_HW_FBIF_READY_FAU_READY(val) vxge_vBIT(val, 0, 17)
00874         u8      unused01100[0x01100-0x010c8];
00875 
00876 /*0x01100*/     u64     vplane_assignments;
00877 #define VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vxge_vBIT(val, 3, 5)
00878 /*0x01108*/     u64     vpath_assignments;
00879 #define VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vxge_vBIT(val, 0, 17)
00880 /*0x01110*/     u64     resource_assignments;
00881 #define VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) \
00882                                                 vxge_vBIT(val, 0, 17)
00883 /*0x01118*/     u64     host_type_assignments;
00884 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val) \
00885                                                         vxge_vBIT(val, 5, 3)
00886         u8      unused01128[0x01128-0x01120];
00887 
00888 /*0x01128*/     u64     max_resource_assignments;
00889 #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) \
00890                                                         vxge_vBIT(val, 3, 5)
00891 #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) \
00892                                                 vxge_vBIT(val, 11, 5)
00893 /*0x01130*/     u64     pf_vpath_assignments;
00894 #define VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) \
00895                                                 vxge_vBIT(val, 0, 17)
00896         u8      unused01200[0x01200-0x01138];
00897 
00898 /*0x01200*/     u64     rts_access_icmp;
00899 #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17)
00900 /*0x01208*/     u64     rts_access_tcpsyn;
00901 #define VXGE_HW_RTS_ACCESS_TCPSYN_EN(val) vxge_vBIT(val, 0, 17)
00902 /*0x01210*/     u64     rts_access_zl4pyld;
00903 #define VXGE_HW_RTS_ACCESS_ZL4PYLD_EN(val) vxge_vBIT(val, 0, 17)
00904 /*0x01218*/     u64     rts_access_l4prtcl_tcp;
00905 #define VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN(val) vxge_vBIT(val, 0, 17)
00906 /*0x01220*/     u64     rts_access_l4prtcl_udp;
00907 #define VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN(val) vxge_vBIT(val, 0, 17)
00908 /*0x01228*/     u64     rts_access_l4prtcl_flex;
00909 #define VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN(val) vxge_vBIT(val, 0, 17)
00910 /*0x01230*/     u64     rts_access_ipfrag;
00911 #define VXGE_HW_RTS_ACCESS_IPFRAG_EN(val) vxge_vBIT(val, 0, 17)
00912 
00913 } __attribute((packed));
00914 
00915 struct vxge_hw_memrepair_reg {
00916         u64     unused1;
00917         u64     unused2;
00918 } __attribute((packed));
00919 
00920 struct vxge_hw_pcicfgmgmt_reg {
00921 
00922 /*0x00000*/     u64     resource_no;
00923 #define VXGE_HW_RESOURCE_NO_PFN_OR_VF   BIT(3)
00924 /*0x00008*/     u64     bargrp_pf_or_vf_bar0_mask;
00925 #define VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val) \
00926                                                         vxge_vBIT(val, 2, 6)
00927 /*0x00010*/     u64     bargrp_pf_or_vf_bar1_mask;
00928 #define VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val) \
00929                                                         vxge_vBIT(val, 2, 6)
00930 /*0x00018*/     u64     bargrp_pf_or_vf_bar2_mask;
00931 #define VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val) \
00932                                                         vxge_vBIT(val, 2, 6)
00933 /*0x00020*/     u64     msixgrp_no;
00934 #define VXGE_HW_MSIXGRP_NO_TABLE_SIZE(val) vxge_vBIT(val, 5, 11)
00935 
00936 } __attribute((packed));
00937 
00938 struct vxge_hw_mrpcim_reg {
00939 /*0x00000*/     u64     g3fbct_int_status;
00940 #define VXGE_HW_G3FBCT_INT_STATUS_ERR_G3IF_INT  vxge_mBIT(0)
00941 /*0x00008*/     u64     g3fbct_int_mask;
00942 /*0x00010*/     u64     g3fbct_err_reg;
00943 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_SM_ERR      vxge_mBIT(4)
00944 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_DECC  vxge_mBIT(5)
00945 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC        vxge_mBIT(6)
00946 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC      vxge_mBIT(7)
00947 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_SECC  vxge_mBIT(29)
00948 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC        vxge_mBIT(30)
00949 #define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC      vxge_mBIT(31)
00950 /*0x00018*/     u64     g3fbct_err_mask;
00951 /*0x00020*/     u64     g3fbct_err_alarm;
00952 
00953         u8      unused00a00[0x00a00-0x00028];
00954 
00955 /*0x00a00*/     u64     wrdma_int_status;
00956 #define VXGE_HW_WRDMA_INT_STATUS_RC_ALARM_RC_INT        vxge_mBIT(0)
00957 #define VXGE_HW_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT vxge_mBIT(1)
00958 #define VXGE_HW_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT      vxge_mBIT(2)
00959 #define VXGE_HW_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT vxge_mBIT(3)
00960 #define VXGE_HW_WRDMA_INT_STATUS_RDA_ERR_RDA_INT        vxge_mBIT(6)
00961 #define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT      vxge_mBIT(8)
00962 #define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT      vxge_mBIT(9)
00963 #define VXGE_HW_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT      vxge_mBIT(12)
00964 #define VXGE_HW_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT  vxge_mBIT(13)
00965 #define VXGE_HW_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT    vxge_mBIT(14)
00966 #define VXGE_HW_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT    vxge_mBIT(15)
00967 #define VXGE_HW_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT    vxge_mBIT(16)
00968 #define VXGE_HW_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT    vxge_mBIT(17)
00969 /*0x00a08*/     u64     wrdma_int_mask;
00970 /*0x00a10*/     u64     rc_alarm_reg;
00971 #define VXGE_HW_RC_ALARM_REG_FTC_SM_ERR vxge_mBIT(0)
00972 #define VXGE_HW_RC_ALARM_REG_FTC_SM_PHASE_ERR   vxge_mBIT(1)
00973 #define VXGE_HW_RC_ALARM_REG_BTDWM_SM_ERR       vxge_mBIT(2)
00974 #define VXGE_HW_RC_ALARM_REG_BTC_SM_ERR vxge_mBIT(3)
00975 #define VXGE_HW_RC_ALARM_REG_BTDCM_SM_ERR       vxge_mBIT(4)
00976 #define VXGE_HW_RC_ALARM_REG_BTDRM_SM_ERR       vxge_mBIT(5)
00977 #define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR      vxge_mBIT(6)
00978 #define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR      vxge_mBIT(7)
00979 #define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR     vxge_mBIT(8)
00980 #define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR     vxge_mBIT(9)
00981 #define VXGE_HW_RC_ALARM_REG_RMM_SM_ERR vxge_mBIT(10)
00982 #define VXGE_HW_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR     vxge_mBIT(12)
00983 /*0x00a18*/     u64     rc_alarm_mask;
00984 /*0x00a20*/     u64     rc_alarm_alarm;
00985 /*0x00a28*/     u64     rxdrm_sm_err_reg;
00986 #define VXGE_HW_RXDRM_SM_ERR_REG_PRC_VP(n)      vxge_mBIT(n)
00987 /*0x00a30*/     u64     rxdrm_sm_err_mask;
00988 /*0x00a38*/     u64     rxdrm_sm_err_alarm;
00989 /*0x00a40*/     u64     rxdcm_sm_err_reg;
00990 #define VXGE_HW_RXDCM_SM_ERR_REG_PRC_VP(n)      vxge_mBIT(n)
00991 /*0x00a48*/     u64     rxdcm_sm_err_mask;
00992 /*0x00a50*/     u64     rxdcm_sm_err_alarm;
00993 /*0x00a58*/     u64     rxdwm_sm_err_reg;
00994 #define VXGE_HW_RXDWM_SM_ERR_REG_PRC_VP(n)      vxge_mBIT(n)
00995 /*0x00a60*/     u64     rxdwm_sm_err_mask;
00996 /*0x00a68*/     u64     rxdwm_sm_err_alarm;
00997 /*0x00a70*/     u64     rda_err_reg;
00998 #define VXGE_HW_RDA_ERR_REG_RDA_SM0_ERR_ALARM   vxge_mBIT(0)
00999 #define VXGE_HW_RDA_ERR_REG_RDA_MISC_ERR        vxge_mBIT(1)
01000 #define VXGE_HW_RDA_ERR_REG_RDA_PCIX_ERR        vxge_mBIT(2)
01001 #define VXGE_HW_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR  vxge_mBIT(3)
01002 #define VXGE_HW_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR  vxge_mBIT(4)
01003 #define VXGE_HW_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR  vxge_mBIT(5)
01004 #define VXGE_HW_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR  vxge_mBIT(6)
01005 #define VXGE_HW_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR  vxge_mBIT(7)
01006 /*0x00a78*/     u64     rda_err_mask;
01007 /*0x00a80*/     u64     rda_err_alarm;
01008 /*0x00a88*/     u64     rda_ecc_db_reg;
01009 #define VXGE_HW_RDA_ECC_DB_REG_RDA_RXD_ERR(n)   vxge_mBIT(n)
01010 /*0x00a90*/     u64     rda_ecc_db_mask;
01011 /*0x00a98*/     u64     rda_ecc_db_alarm;
01012 /*0x00aa0*/     u64     rda_ecc_sg_reg;
01013 #define VXGE_HW_RDA_ECC_SG_REG_RDA_RXD_ERR(n)   vxge_mBIT(n)
01014 /*0x00aa8*/     u64     rda_ecc_sg_mask;
01015 /*0x00ab0*/     u64     rda_ecc_sg_alarm;
01016 /*0x00ab8*/     u64     rqa_err_reg;
01017 #define VXGE_HW_RQA_ERR_REG_RQA_SM_ERR_ALARM    vxge_mBIT(0)
01018 /*0x00ac0*/     u64     rqa_err_mask;
01019 /*0x00ac8*/     u64     rqa_err_alarm;
01020 /*0x00ad0*/     u64     frf_alarm_reg;
01021 #define VXGE_HW_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n)      vxge_mBIT(n)
01022 /*0x00ad8*/     u64     frf_alarm_mask;
01023 /*0x00ae0*/     u64     frf_alarm_alarm;
01024 /*0x00ae8*/     u64     rocrc_alarm_reg;
01025 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB      vxge_mBIT(0)
01026 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG      vxge_mBIT(1)
01027 #define VXGE_HW_ROCRC_ALARM_REG_NOA_NMA_SM_ERR  vxge_mBIT(2)
01028 #define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB vxge_mBIT(3)
01029 #define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG vxge_mBIT(4)
01030 #define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB vxge_mBIT(5)
01031 #define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG vxge_mBIT(6)
01032 #define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB vxge_mBIT(11)
01033 #define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG vxge_mBIT(12)
01034 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR  vxge_mBIT(13)
01035 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR   vxge_mBIT(14)
01036 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR   vxge_mBIT(15)
01037 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR        vxge_mBIT(16)
01038 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR   vxge_mBIT(17)
01039 #define VXGE_HW_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR        vxge_mBIT(18)
01040 #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW      vxge_mBIT(19)
01041 #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW      vxge_mBIT(20)
01042 #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW      vxge_mBIT(21)
01043 #define VXGE_HW_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR    vxge_mBIT(22)
01044 /*0x00af0*/     u64     rocrc_alarm_mask;
01045 /*0x00af8*/     u64     rocrc_alarm_alarm;
01046 /*0x00b00*/     u64     wde0_alarm_reg;
01047 #define VXGE_HW_WDE0_ALARM_REG_WDE0_DCC_SM_ERR  vxge_mBIT(0)
01048 #define VXGE_HW_WDE0_ALARM_REG_WDE0_PRM_SM_ERR  vxge_mBIT(1)
01049 #define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_SM_ERR   vxge_mBIT(2)
01050 #define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_CMD_ERR  vxge_mBIT(3)
01051 #define VXGE_HW_WDE0_ALARM_REG_WDE0_PCR_SM_ERR  vxge_mBIT(4)
01052 /*0x00b08*/     u64     wde0_alarm_mask;
01053 /*0x00b10*/     u64     wde0_alarm_alarm;
01054 /*0x00b18*/     u64     wde1_alarm_reg;
01055 #define VXGE_HW_WDE1_ALARM_REG_WDE1_DCC_SM_ERR  vxge_mBIT(0)
01056 #define VXGE_HW_WDE1_ALARM_REG_WDE1_PRM_SM_ERR  vxge_mBIT(1)
01057 #define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_SM_ERR   vxge_mBIT(2)
01058 #define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_CMD_ERR  vxge_mBIT(3)
01059 #define VXGE_HW_WDE1_ALARM_REG_WDE1_PCR_SM_ERR  vxge_mBIT(4)
01060 /*0x00b20*/     u64     wde1_alarm_mask;
01061 /*0x00b28*/     u64     wde1_alarm_alarm;
01062 /*0x00b30*/     u64     wde2_alarm_reg;
01063 #define VXGE_HW_WDE2_ALARM_REG_WDE2_DCC_SM_ERR  vxge_mBIT(0)
01064 #define VXGE_HW_WDE2_ALARM_REG_WDE2_PRM_SM_ERR  vxge_mBIT(1)
01065 #define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_SM_ERR   vxge_mBIT(2)
01066 #define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_CMD_ERR  vxge_mBIT(3)
01067 #define VXGE_HW_WDE2_ALARM_REG_WDE2_PCR_SM_ERR  vxge_mBIT(4)
01068 /*0x00b38*/     u64     wde2_alarm_mask;
01069 /*0x00b40*/     u64     wde2_alarm_alarm;
01070 /*0x00b48*/     u64     wde3_alarm_reg;
01071 #define VXGE_HW_WDE3_ALARM_REG_WDE3_DCC_SM_ERR  vxge_mBIT(0)
01072 #define VXGE_HW_WDE3_ALARM_REG_WDE3_PRM_SM_ERR  vxge_mBIT(1)
01073 #define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_SM_ERR   vxge_mBIT(2)
01074 #define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_CMD_ERR  vxge_mBIT(3)
01075 #define VXGE_HW_WDE3_ALARM_REG_WDE3_PCR_SM_ERR  vxge_mBIT(4)
01076 /*0x00b50*/     u64     wde3_alarm_mask;
01077 /*0x00b58*/     u64     wde3_alarm_alarm;
01078 
01079         u8      unused00be8[0x00be8-0x00b60];
01080 
01081 /*0x00be8*/     u64     rx_w_round_robin_0;
01082 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vxge_vBIT(val, 3, 5)
01083 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vxge_vBIT(val, 11, 5)
01084 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vxge_vBIT(val, 19, 5)
01085 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vxge_vBIT(val, 27, 5)
01086 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vxge_vBIT(val, 35, 5)
01087 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vxge_vBIT(val, 43, 5)
01088 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vxge_vBIT(val, 51, 5)
01089 #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vxge_vBIT(val, 59, 5)
01090 /*0x00bf0*/     u64     rx_w_round_robin_1;
01091 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vxge_vBIT(val, 3, 5)
01092 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vxge_vBIT(val, 11, 5)
01093 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) \
01094                                                 vxge_vBIT(val, 19, 5)
01095 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) \
01096                                                 vxge_vBIT(val, 27, 5)
01097 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) \
01098                                                 vxge_vBIT(val, 35, 5)
01099 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) \
01100                                                 vxge_vBIT(val, 43, 5)
01101 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) \
01102                                                 vxge_vBIT(val, 51, 5)
01103 #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) \
01104                                                 vxge_vBIT(val, 59, 5)
01105 /*0x00bf8*/     u64     rx_w_round_robin_2;
01106 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vxge_vBIT(val, 3, 5)
01107 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) \
01108                                                         vxge_vBIT(val, 11, 5)
01109 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) \
01110                                                         vxge_vBIT(val, 19, 5)
01111 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) \
01112                                                         vxge_vBIT(val, 27, 5)
01113 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) \
01114                                                         vxge_vBIT(val, 35, 5)
01115 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) \
01116                                                         vxge_vBIT(val, 43, 5)
01117 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) \
01118                                                         vxge_vBIT(val, 51, 5)
01119 #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) \
01120                                                         vxge_vBIT(val, 59, 5)
01121 /*0x00c00*/     u64     rx_w_round_robin_3;
01122 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vxge_vBIT(val, 3, 5)
01123 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) \
01124                                                         vxge_vBIT(val, 11, 5)
01125 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) \
01126                                                         vxge_vBIT(val, 19, 5)
01127 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) \
01128                                                         vxge_vBIT(val, 27, 5)
01129 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) \
01130                                                         vxge_vBIT(val, 35, 5)
01131 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) \
01132                                                         vxge_vBIT(val, 43, 5)
01133 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) \
01134                                                         vxge_vBIT(val, 51, 5)
01135 #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) \
01136                                                         vxge_vBIT(val, 59, 5)
01137 /*0x00c08*/     u64     rx_w_round_robin_4;
01138 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vxge_vBIT(val, 3, 5)
01139 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) \
01140                                                         vxge_vBIT(val, 11, 5)
01141 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) \
01142                                                         vxge_vBIT(val, 19, 5)
01143 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) \
01144                                                         vxge_vBIT(val, 27, 5)
01145 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) \
01146                                                         vxge_vBIT(val, 35, 5)
01147 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) \
01148                                                         vxge_vBIT(val, 43, 5)
01149 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) \
01150                                                         vxge_vBIT(val, 51, 5)
01151 #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) \
01152                                                         vxge_vBIT(val, 59, 5)
01153 /*0x00c10*/     u64     rx_w_round_robin_5;
01154 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vxge_vBIT(val, 3, 5)
01155 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) \
01156                                                         vxge_vBIT(val, 11, 5)
01157 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) \
01158                                                         vxge_vBIT(val, 19, 5)
01159 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) \
01160                                                         vxge_vBIT(val, 27, 5)
01161 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) \
01162                                                         vxge_vBIT(val, 35, 5)
01163 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) \
01164                                                         vxge_vBIT(val, 43, 5)
01165 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) \
01166                                                         vxge_vBIT(val, 51, 5)
01167 #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) \
01168                                                         vxge_vBIT(val, 59, 5)
01169 /*0x00c18*/     u64     rx_w_round_robin_6;
01170 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vxge_vBIT(val, 3, 5)
01171 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) \
01172                                                         vxge_vBIT(val, 11, 5)
01173 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) \
01174                                                         vxge_vBIT(val, 19, 5)
01175 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) \
01176                                                         vxge_vBIT(val, 27, 5)
01177 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) \
01178                                                         vxge_vBIT(val, 35, 5)
01179 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) \
01180                                                         vxge_vBIT(val, 43, 5)
01181 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) \
01182                                                         vxge_vBIT(val, 51, 5)
01183 #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) \
01184                                                         vxge_vBIT(val, 59, 5)
01185 /*0x00c20*/     u64     rx_w_round_robin_7;
01186 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vxge_vBIT(val, 3, 5)
01187 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) \
01188                                                         vxge_vBIT(val, 11, 5)
01189 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) \
01190                                                         vxge_vBIT(val, 19, 5)
01191 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) \
01192                                                         vxge_vBIT(val, 27, 5)
01193 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) \
01194                                                         vxge_vBIT(val, 35, 5)
01195 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) \
01196                                                         vxge_vBIT(val, 43, 5)
01197 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) \
01198                                                         vxge_vBIT(val, 51, 5)
01199 #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) \
01200                                                         vxge_vBIT(val, 59, 5)
01201 /*0x00c28*/     u64     rx_w_round_robin_8;
01202 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vxge_vBIT(val, 3, 5)
01203 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) \
01204                                                         vxge_vBIT(val, 11, 5)
01205 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) \
01206                                                         vxge_vBIT(val, 19, 5)
01207 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) \
01208                                                         vxge_vBIT(val, 27, 5)
01209 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) \
01210                                                         vxge_vBIT(val, 35, 5)
01211 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) \
01212                                                 vxge_vBIT(val, 43, 5)
01213 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) \
01214                                                         vxge_vBIT(val, 51, 5)
01215 #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) \
01216                                                 vxge_vBIT(val, 59, 5)
01217 /*0x00c30*/     u64     rx_w_round_robin_9;
01218 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vxge_vBIT(val, 3, 5)
01219 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) \
01220                                                         vxge_vBIT(val, 11, 5)
01221 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) \
01222                                                         vxge_vBIT(val, 19, 5)
01223 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) \
01224                                                         vxge_vBIT(val, 27, 5)
01225 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) \
01226                                                         vxge_vBIT(val, 35, 5)
01227 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) \
01228                                                         vxge_vBIT(val, 43, 5)
01229 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) \
01230                                                         vxge_vBIT(val, 51, 5)
01231 #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) \
01232                                                         vxge_vBIT(val, 59, 5)
01233 /*0x00c38*/     u64     rx_w_round_robin_10;
01234 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) \
01235                                                         vxge_vBIT(val, 3, 5)
01236 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) \
01237                                                         vxge_vBIT(val, 11, 5)
01238 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) \
01239                                                         vxge_vBIT(val, 19, 5)
01240 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) \
01241                                                         vxge_vBIT(val, 27, 5)
01242 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) \
01243                                                         vxge_vBIT(val, 35, 5)
01244 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) \
01245                                                         vxge_vBIT(val, 43, 5)
01246 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) \
01247                                                         vxge_vBIT(val, 51, 5)
01248 #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) \
01249                                                         vxge_vBIT(val, 59, 5)
01250 /*0x00c40*/     u64     rx_w_round_robin_11;
01251 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) \
01252                                                         vxge_vBIT(val, 3, 5)
01253 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) \
01254                                                         vxge_vBIT(val, 11, 5)
01255 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) \
01256                                                         vxge_vBIT(val, 19, 5)
01257 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) \
01258                                                         vxge_vBIT(val, 27, 5)
01259 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) \
01260                                                         vxge_vBIT(val, 35, 5)
01261 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) \
01262                                                         vxge_vBIT(val, 43, 5)
01263 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) \
01264                                                         vxge_vBIT(val, 51, 5)
01265 #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) \
01266                                                         vxge_vBIT(val, 59, 5)
01267 /*0x00c48*/     u64     rx_w_round_robin_12;
01268 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) \
01269                                                         vxge_vBIT(val, 3, 5)
01270 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) \
01271                                                         vxge_vBIT(val, 11, 5)
01272 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) \
01273                                                         vxge_vBIT(val, 19, 5)
01274 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) \
01275                                                         vxge_vBIT(val, 27, 5)
01276 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) \
01277                                                         vxge_vBIT(val, 35, 5)
01278 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) \
01279                                                         vxge_vBIT(val, 43, 5)
01280 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) \
01281                                                         vxge_vBIT(val, 51, 5)
01282 #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) \
01283                                                         vxge_vBIT(val, 59, 5)
01284 /*0x00c50*/     u64     rx_w_round_robin_13;
01285 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) \
01286                                                         vxge_vBIT(val, 3, 5)
01287 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) \
01288                                                         vxge_vBIT(val, 11, 5)
01289 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) \
01290                                                         vxge_vBIT(val, 19, 5)
01291 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) \
01292                                                         vxge_vBIT(val, 27, 5)
01293 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) \
01294                                                         vxge_vBIT(val, 35, 5)
01295 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) \
01296                                                         vxge_vBIT(val, 43, 5)
01297 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) \
01298                                                         vxge_vBIT(val, 51, 5)
01299 #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) \
01300                                                         vxge_vBIT(val, 59, 5)
01301 /*0x00c58*/     u64     rx_w_round_robin_14;
01302 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) \
01303                                                         vxge_vBIT(val, 3, 5)
01304 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) \
01305                                                         vxge_vBIT(val, 11, 5)
01306 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) \
01307                                                         vxge_vBIT(val, 19, 5)
01308 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) \
01309                                                         vxge_vBIT(val, 27, 5)
01310 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) \
01311                                                         vxge_vBIT(val, 35, 5)
01312 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) \
01313                                                         vxge_vBIT(val, 43, 5)
01314 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) \
01315                                                         vxge_vBIT(val, 51, 5)
01316 #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) \
01317                                                         vxge_vBIT(val, 59, 5)
01318 /*0x00c60*/     u64     rx_w_round_robin_15;
01319 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) \
01320                                                         vxge_vBIT(val, 3, 5)
01321 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) \
01322                                                         vxge_vBIT(val, 11, 5)
01323 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) \
01324                                                         vxge_vBIT(val, 19, 5)
01325 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) \
01326                                                         vxge_vBIT(val, 27, 5)
01327 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) \
01328                                                         vxge_vBIT(val, 35, 5)
01329 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) \
01330                                                         vxge_vBIT(val, 43, 5)
01331 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) \
01332                                                         vxge_vBIT(val, 51, 5)
01333 #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) \
01334                                                         vxge_vBIT(val, 59, 5)
01335 /*0x00c68*/     u64     rx_w_round_robin_16;
01336 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) \
01337                                                         vxge_vBIT(val, 3, 5)
01338 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) \
01339                                                         vxge_vBIT(val, 11, 5)
01340 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) \
01341                                                         vxge_vBIT(val, 19, 5)
01342 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) \
01343                                                         vxge_vBIT(val, 27, 5)
01344 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) \
01345                                                         vxge_vBIT(val, 35, 5)
01346 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) \
01347                                                         vxge_vBIT(val, 43, 5)
01348 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) \
01349                                                         vxge_vBIT(val, 51, 5)
01350 #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) \
01351                                                         vxge_vBIT(val, 59, 5)
01352 /*0x00c70*/     u64     rx_w_round_robin_17;
01353 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) \
01354                                                         vxge_vBIT(val, 3, 5)
01355 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) \
01356                                                         vxge_vBIT(val, 11, 5)
01357 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) \
01358                                                         vxge_vBIT(val, 19, 5)
01359 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) \
01360                                                         vxge_vBIT(val, 27, 5)
01361 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) \
01362                                                         vxge_vBIT(val, 35, 5)
01363 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) \
01364                                                         vxge_vBIT(val, 43, 5)
01365 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) \
01366                                                         vxge_vBIT(val, 51, 5)
01367 #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) \
01368                                                         vxge_vBIT(val, 59, 5)
01369 /*0x00c78*/     u64     rx_w_round_robin_18;
01370 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) \
01371                                                         vxge_vBIT(val, 3, 5)
01372 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) \
01373                                                         vxge_vBIT(val, 11, 5)
01374 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) \
01375                                                         vxge_vBIT(val, 19, 5)
01376 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) \
01377                                                         vxge_vBIT(val, 27, 5)
01378 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) \
01379                                                         vxge_vBIT(val, 35, 5)
01380 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) \
01381                                                         vxge_vBIT(val, 43, 5)
01382 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) \
01383                                                         vxge_vBIT(val, 51, 5)
01384 #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) \
01385                                                         vxge_vBIT(val, 59, 5)
01386 /*0x00c80*/     u64     rx_w_round_robin_19;
01387 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) \
01388                                                         vxge_vBIT(val, 3, 5)
01389 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) \
01390                                                         vxge_vBIT(val, 11, 5)
01391 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) \
01392                                                         vxge_vBIT(val, 19, 5)
01393 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) \
01394                                                         vxge_vBIT(val, 27, 5)
01395 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) \
01396                                                         vxge_vBIT(val, 35, 5)
01397 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) \
01398                                                         vxge_vBIT(val, 43, 5)
01399 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) \
01400                                                         vxge_vBIT(val, 51, 5)
01401 #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) \
01402                                                         vxge_vBIT(val, 59, 5)
01403 /*0x00c88*/     u64     rx_w_round_robin_20;
01404 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) \
01405                                                         vxge_vBIT(val, 3, 5)
01406 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) \
01407                                                         vxge_vBIT(val, 11, 5)
01408 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) \
01409                                                         vxge_vBIT(val, 19, 5)
01410 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) \
01411                                                         vxge_vBIT(val, 27, 5)
01412 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) \
01413                                                         vxge_vBIT(val, 35, 5)
01414 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) \
01415                                                         vxge_vBIT(val, 43, 5)
01416 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) \
01417                                                         vxge_vBIT(val, 51, 5)
01418 #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) \
01419                                                         vxge_vBIT(val, 59, 5)
01420 /*0x00c90*/     u64     rx_w_round_robin_21;
01421 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) \
01422                                                         vxge_vBIT(val, 3, 5)
01423 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) \
01424                                                         vxge_vBIT(val, 11, 5)
01425 #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) \
01426                                                         vxge_vBIT(val, 19, 5)
01427 
01428 #define VXGE_HW_WRR_RING_SERVICE_STATES                 171
01429 #define VXGE_HW_WRR_RING_COUNT                          22
01430 
01431 /*0x00c98*/     u64     rx_queue_priority_0;
01432 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vxge_vBIT(val, 3, 5)
01433 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vxge_vBIT(val, 11, 5)
01434 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vxge_vBIT(val, 19, 5)
01435 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vxge_vBIT(val, 27, 5)
01436 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vxge_vBIT(val, 35, 5)
01437 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vxge_vBIT(val, 43, 5)
01438 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vxge_vBIT(val, 51, 5)
01439 #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vxge_vBIT(val, 59, 5)
01440 /*0x00ca0*/     u64     rx_queue_priority_1;
01441 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vxge_vBIT(val, 3, 5)
01442 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vxge_vBIT(val, 11, 5)
01443 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vxge_vBIT(val, 19, 5)
01444 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vxge_vBIT(val, 27, 5)
01445 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vxge_vBIT(val, 35, 5)
01446 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vxge_vBIT(val, 43, 5)
01447 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vxge_vBIT(val, 51, 5)
01448 #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vxge_vBIT(val, 59, 5)
01449 /*0x00ca8*/     u64     rx_queue_priority_2;
01450 #define VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vxge_vBIT(val, 3, 5)
01451         u8      unused00cc8[0x00cc8-0x00cb0];
01452 
01453 /*0x00cc8*/     u64     replication_queue_priority;
01454 #define VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val) \
01455                                                         vxge_vBIT(val, 59, 5)
01456 /*0x00cd0*/     u64     rx_queue_select;
01457 #define VXGE_HW_RX_QUEUE_SELECT_NUMBER(n)       vxge_mBIT(n)
01458 #define VXGE_HW_RX_QUEUE_SELECT_ENABLE_CODE     vxge_mBIT(15)
01459 #define VXGE_HW_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY        vxge_mBIT(23)
01460 /*0x00cd8*/     u64     rqa_vpbp_ctrl;
01461 #define VXGE_HW_RQA_VPBP_CTRL_WR_XON_DIS        vxge_mBIT(15)
01462 #define VXGE_HW_RQA_VPBP_CTRL_ROCRC_DIS vxge_mBIT(23)
01463 #define VXGE_HW_RQA_VPBP_CTRL_TXPE_DIS  vxge_mBIT(31)
01464 /*0x00ce0*/     u64     rx_multi_cast_ctrl;
01465 #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_DIS vxge_mBIT(0)
01466 #define VXGE_HW_RX_MULTI_CAST_CTRL_FRM_DROP_DIS vxge_mBIT(1)
01467 #define VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) \
01468                                                         vxge_vBIT(val, 2, 30)
01469 #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32)
01470 /*0x00ce8*/     u64     wde_prm_ctrl;
01471 #define VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vxge_vBIT(val, 2, 10)
01472 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vxge_vBIT(val, 18, 14)
01473 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW   vxge_mBIT(32)
01474 #define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY vxge_mBIT(33)
01475 #define VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE(val) vxge_vBIT(val, 46, 2)
01476 /*0x00cf0*/     u64     noa_ctrl;
01477 #define VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 3, 5)
01478 #define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 11, 5)
01479 #define VXGE_HW_NOA_CTRL_IGNORE_KDFC_IF_STATUS  vxge_mBIT(16)
01480 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vxge_vBIT(val, 37, 4)
01481 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vxge_vBIT(val, 45, 4)
01482 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vxge_vBIT(val, 53, 4)
01483 #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vxge_vBIT(val, 60, 4)
01484 /*0x00cf8*/     u64     phase_cfg;
01485 #define VXGE_HW_PHASE_CFG_QCC_WR_PHASE_EN       vxge_mBIT(0)
01486 #define VXGE_HW_PHASE_CFG_QCC_RD_PHASE_EN       vxge_mBIT(3)
01487 #define VXGE_HW_PHASE_CFG_IMMM_WR_PHASE_EN      vxge_mBIT(7)
01488 #define VXGE_HW_PHASE_CFG_IMMM_RD_PHASE_EN      vxge_mBIT(11)
01489 #define VXGE_HW_PHASE_CFG_UMQM_WR_PHASE_EN      vxge_mBIT(15)
01490 #define VXGE_HW_PHASE_CFG_UMQM_RD_PHASE_EN      vxge_mBIT(19)
01491 #define VXGE_HW_PHASE_CFG_RCBM_WR_PHASE_EN      vxge_mBIT(23)
01492 #define VXGE_HW_PHASE_CFG_RCBM_RD_PHASE_EN      vxge_mBIT(27)
01493 #define VXGE_HW_PHASE_CFG_RXD_RC_WR_PHASE_EN    vxge_mBIT(31)
01494 #define VXGE_HW_PHASE_CFG_RXD_RC_RD_PHASE_EN    vxge_mBIT(35)
01495 #define VXGE_HW_PHASE_CFG_RXD_RHS_WR_PHASE_EN   vxge_mBIT(39)
01496 #define VXGE_HW_PHASE_CFG_RXD_RHS_RD_PHASE_EN   vxge_mBIT(43)
01497 /*0x00d00*/     u64     rcq_bypq_cfg;
01498 #define VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vxge_vBIT(val, 10, 22)
01499 #define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vxge_vBIT(val, 39, 9)
01500 #define VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vxge_vBIT(val, 55, 9)
01501         u8      unused00e00[0x00e00-0x00d08];
01502 
01503 /*0x00e00*/     u64     doorbell_int_status;
01504 #define VXGE_HW_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT vxge_mBIT(7)
01505 #define VXGE_HW_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT vxge_mBIT(15)
01506 /*0x00e08*/     u64     doorbell_int_mask;
01507 /*0x00e10*/     u64     kdfc_err_reg;
01508 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR       vxge_mBIT(7)
01509 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR       vxge_mBIT(15)
01510 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM     vxge_mBIT(23)
01511 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1       vxge_mBIT(32)
01512 #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR vxge_mBIT(39)
01513 /*0x00e18*/     u64     kdfc_err_mask;
01514 /*0x00e20*/     u64     kdfc_err_reg_alarm;
01515 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR vxge_mBIT(7)
01516 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR vxge_mBIT(15)
01517 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM       vxge_mBIT(23)
01518 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32)
01519 #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR   vxge_mBIT(39)
01520         u8      unused00e40[0x00e40-0x00e28];
01521 /*0x00e40*/     u64     kdfc_vp_partition_0;
01522 #define VXGE_HW_KDFC_VP_PARTITION_0_ENABLE      vxge_mBIT(0)
01523 #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0(val) vxge_vBIT(val, 5, 3)
01524 #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val) vxge_vBIT(val, 17, 15)
01525 #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1(val) vxge_vBIT(val, 37, 3)
01526 #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1(val) vxge_vBIT(val, 49, 15)
01527 /*0x00e48*/     u64     kdfc_vp_partition_1;
01528 #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2(val) vxge_vBIT(val, 5, 3)
01529 #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val) vxge_vBIT(val, 17, 15)
01530 #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3(val) vxge_vBIT(val, 37, 3)
01531 #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3(val) vxge_vBIT(val, 49, 15)
01532 /*0x00e50*/     u64     kdfc_vp_partition_2;
01533 #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4(val) vxge_vBIT(val, 5, 3)
01534 #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val) vxge_vBIT(val, 17, 15)
01535 #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5(val) vxge_vBIT(val, 37, 3)
01536 #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5(val) vxge_vBIT(val, 49, 15)
01537 /*0x00e58*/     u64     kdfc_vp_partition_3;
01538 #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6(val) vxge_vBIT(val, 5, 3)
01539 #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val) vxge_vBIT(val, 17, 15)
01540 #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7(val) vxge_vBIT(val, 37, 3)
01541 #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7(val) vxge_vBIT(val, 49, 15)
01542 /*0x00e60*/     u64     kdfc_vp_partition_4;
01543 #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8(val) vxge_vBIT(val, 17, 15)
01544 #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val) vxge_vBIT(val, 49, 15)
01545 /*0x00e68*/     u64     kdfc_vp_partition_5;
01546 #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10(val) vxge_vBIT(val, 17, 15)
01547 #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val) vxge_vBIT(val, 49, 15)
01548 /*0x00e70*/     u64     kdfc_vp_partition_6;
01549 #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12(val) vxge_vBIT(val, 17, 15)
01550 #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val) vxge_vBIT(val, 49, 15)
01551 /*0x00e78*/     u64     kdfc_vp_partition_7;
01552 #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14(val) vxge_vBIT(val, 17, 15)
01553 #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val) vxge_vBIT(val, 49, 15)
01554 /*0x00e80*/     u64     kdfc_vp_partition_8;
01555 #define VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16(val) vxge_vBIT(val, 17, 15)
01556 /*0x00e88*/     u64     kdfc_w_round_robin_0;
01557 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vxge_vBIT(val, 3, 5)
01558 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vxge_vBIT(val, 11, 5)
01559 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vxge_vBIT(val, 19, 5)
01560 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vxge_vBIT(val, 27, 5)
01561 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vxge_vBIT(val, 35, 5)
01562 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vxge_vBIT(val, 43, 5)
01563 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vxge_vBIT(val, 51, 5)
01564 #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vxge_vBIT(val, 59, 5)
01565 
01566         u8      unused0f28[0x0f28-0x0e90];
01567 
01568 /*0x00f28*/     u64     kdfc_w_round_robin_20;
01569 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vxge_vBIT(val, 3, 5)
01570 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vxge_vBIT(val, 11, 5)
01571 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vxge_vBIT(val, 19, 5)
01572 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vxge_vBIT(val, 27, 5)
01573 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vxge_vBIT(val, 35, 5)
01574 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vxge_vBIT(val, 43, 5)
01575 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vxge_vBIT(val, 51, 5)
01576 #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vxge_vBIT(val, 59, 5)
01577 
01578 #define VXGE_HW_WRR_FIFO_COUNT                          20
01579 
01580         u8      unused0fc8[0x0fc8-0x0f30];
01581 
01582 /*0x00fc8*/     u64     kdfc_w_round_robin_40;
01583 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vxge_vBIT(val, 3, 5)
01584 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vxge_vBIT(val, 11, 5)
01585 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vxge_vBIT(val, 19, 5)
01586 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vxge_vBIT(val, 27, 5)
01587 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vxge_vBIT(val, 35, 5)
01588 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vxge_vBIT(val, 43, 5)
01589 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vxge_vBIT(val, 51, 5)
01590 #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vxge_vBIT(val, 59, 5)
01591 
01592         u8      unused1068[0x01068-0x0fd0];
01593 
01594 /*0x01068*/     u64     kdfc_entry_type_sel_0;
01595 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vxge_vBIT(val, 6, 2)
01596 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vxge_vBIT(val, 14, 2)
01597 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vxge_vBIT(val, 22, 2)
01598 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vxge_vBIT(val, 30, 2)
01599 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vxge_vBIT(val, 38, 2)
01600 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vxge_vBIT(val, 46, 2)
01601 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vxge_vBIT(val, 54, 2)
01602 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vxge_vBIT(val, 62, 2)
01603 /*0x01070*/     u64     kdfc_entry_type_sel_1;
01604 #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vxge_vBIT(val, 6, 2)
01605 /*0x01078*/     u64     kdfc_fifo_0_ctrl;
01606 #define VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5)
01607 #define VXGE_HW_WEIGHTED_RR_SERVICE_STATES              176
01608 #define VXGE_HW_WRR_FIFO_SERVICE_STATES                 153
01609 
01610         u8      unused1100[0x01100-0x1080];
01611 
01612 /*0x01100*/     u64     kdfc_fifo_17_ctrl;
01613 #define VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5)
01614 
01615         u8      unused1600[0x01600-0x1108];
01616 
01617 /*0x01600*/     u64     rxmac_int_status;
01618 #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT    vxge_mBIT(3)
01619 #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT    vxge_mBIT(7)
01620 #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT \
01621                                                                 vxge_mBIT(11)
01622 /*0x01608*/     u64     rxmac_int_mask;
01623         u8      unused01618[0x01618-0x01610];
01624 
01625 /*0x01618*/     u64     rxmac_gen_err_reg;
01626 /*0x01620*/     u64     rxmac_gen_err_mask;
01627 /*0x01628*/     u64     rxmac_gen_err_alarm;
01628 /*0x01630*/     u64     rxmac_ecc_err_reg;
01629 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val) \
01630                                                         vxge_vBIT(val, 0, 4)
01631 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val) \
01632                                                         vxge_vBIT(val, 4, 4)
01633 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val) \
01634                                                         vxge_vBIT(val, 8, 4)
01635 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val) \
01636                                                         vxge_vBIT(val, 12, 4)
01637 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val) \
01638                                                         vxge_vBIT(val, 16, 4)
01639 #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val) \
01640                                                         vxge_vBIT(val, 20, 4)
01641 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val) \
01642                                                         vxge_vBIT(val, 24, 2)
01643 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val) \
01644                                                         vxge_vBIT(val, 26, 2)
01645 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val) \
01646                                                         vxge_vBIT(val, 28, 2)
01647 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val) \
01648                                                         vxge_vBIT(val, 30, 2)
01649 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR      vxge_mBIT(32)
01650 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR      vxge_mBIT(33)
01651 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR  vxge_mBIT(34)
01652 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR  vxge_mBIT(35)
01653 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR  vxge_mBIT(36)
01654 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR  vxge_mBIT(37)
01655 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR  vxge_mBIT(38)
01656 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR  vxge_mBIT(39)
01657 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val) \
01658                                                         vxge_vBIT(val, 40, 7)
01659 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val) \
01660                                                         vxge_vBIT(val, 47, 7)
01661 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val) \
01662                                                         vxge_vBIT(val, 54, 3)
01663 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val) \
01664                                                         vxge_vBIT(val, 57, 3)
01665 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR \
01666                                                         vxge_mBIT(60)
01667 #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR \
01668                                                         vxge_mBIT(61)
01669 /*0x01638*/     u64     rxmac_ecc_err_mask;
01670 /*0x01640*/     u64     rxmac_ecc_err_alarm;
01671 /*0x01648*/     u64     rxmac_various_err_reg;
01672 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR   vxge_mBIT(0)
01673 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR   vxge_mBIT(1)
01674 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR   vxge_mBIT(2)
01675 #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR       vxge_mBIT(3)
01676 /*0x01650*/     u64     rxmac_various_err_mask;
01677 /*0x01658*/     u64     rxmac_various_err_alarm;
01678 /*0x01660*/     u64     rxmac_gen_cfg;
01679 #define VXGE_HW_RXMAC_GEN_CFG_SCALE_RMAC_UTIL   vxge_mBIT(11)
01680 /*0x01668*/     u64     rxmac_authorize_all_addr;
01681 #define VXGE_HW_RXMAC_AUTHORIZE_ALL_ADDR_VP(n)  vxge_mBIT(n)
01682 /*0x01670*/     u64     rxmac_authorize_all_vid;
01683 #define VXGE_HW_RXMAC_AUTHORIZE_ALL_VID_VP(n)   vxge_mBIT(n)
01684         u8      unused016c0[0x016c0-0x01678];
01685 
01686 /*0x016c0*/     u64     rxmac_red_rate_repl_queue;
01687 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vxge_vBIT(val, 0, 4)
01688 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vxge_vBIT(val, 4, 4)
01689 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vxge_vBIT(val, 8, 4)
01690 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vxge_vBIT(val, 12, 4)
01691 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vxge_vBIT(val, 16, 4)
01692 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vxge_vBIT(val, 20, 4)
01693 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vxge_vBIT(val, 24, 4)
01694 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vxge_vBIT(val, 28, 4)
01695 #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN    vxge_mBIT(35)
01696         u8      unused016e0[0x016e0-0x016c8];
01697 
01698 /*0x016e0*/     u64     rxmac_cfg0_port[3];
01699 #define VXGE_HW_RXMAC_CFG0_PORT_RMAC_EN vxge_mBIT(3)
01700 #define VXGE_HW_RXMAC_CFG0_PORT_STRIP_FCS       vxge_mBIT(7)
01701 #define VXGE_HW_RXMAC_CFG0_PORT_DISCARD_PFRM    vxge_mBIT(11)
01702 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_FCS_ERR  vxge_mBIT(15)
01703 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LONG_ERR vxge_mBIT(19)
01704 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR       vxge_mBIT(23)
01705 #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH     vxge_mBIT(27)
01706 #define VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vxge_vBIT(val, 50, 14)
01707         u8      unused01710[0x01710-0x016f8];
01708 
01709 /*0x01710*/     u64     rxmac_cfg2_port[3];
01710 #define VXGE_HW_RXMAC_CFG2_PORT_PROM_EN vxge_mBIT(3)
01711 /*0x01728*/     u64     rxmac_pause_cfg_port[3];
01712 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN     vxge_mBIT(3)
01713 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN     vxge_mBIT(7)
01714 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vxge_vBIT(val, 9, 3)
01715 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_DUAL_THR   vxge_mBIT(15)
01716 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vxge_vBIT(val, 20, 16)
01717 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR  vxge_mBIT(39)
01718 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR  vxge_mBIT(43)
01719 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_LIMITER_EN vxge_mBIT(47)
01720 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vxge_vBIT(val, 48, 8)
01721 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL       vxge_mBIT(59)
01722         u8      unused01758[0x01758-0x01740];
01723 
01724 /*0x01758*/     u64     rxmac_red_cfg0_port[3];
01725 #define VXGE_HW_RXMAC_RED_CFG0_PORT_RED_EN_VP(n)        vxge_mBIT(n)
01726 /*0x01770*/     u64     rxmac_red_cfg1_port[3];
01727 #define VXGE_HW_RXMAC_RED_CFG1_PORT_FINE_EN     vxge_mBIT(3)
01728 #define VXGE_HW_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE   vxge_mBIT(11)
01729 /*0x01788*/     u64     rxmac_red_cfg2_port[3];
01730 #define VXGE_HW_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n)    vxge_mBIT(n)
01731 /*0x017a0*/     u64     rxmac_link_util_port[3];
01732 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) \
01733                                                         vxge_vBIT(val, 1, 7)
01734 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4)
01735 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) \
01736                                                         vxge_vBIT(val, 12, 4)
01737 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4)
01738 #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR     vxge_mBIT(23)
01739         u8      unused017d0[0x017d0-0x017b8];
01740 
01741 /*0x017d0*/     u64     rxmac_status_port[3];
01742 #define VXGE_HW_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD      vxge_mBIT(3)
01743         u8      unused01800[0x01800-0x017e8];
01744 
01745 /*0x01800*/     u64     rxmac_rx_pa_cfg0;
01746 #define VXGE_HW_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR       vxge_mBIT(3)
01747 #define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N      vxge_mBIT(7)
01748 #define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO vxge_mBIT(18)
01749 #define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS       vxge_mBIT(19)
01750 #define VXGE_HW_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING    vxge_mBIT(23)
01751 #define VXGE_HW_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN       vxge_mBIT(27)
01752 #define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE       vxge_mBIT(35)
01753 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR    vxge_mBIT(39)
01754 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR  vxge_mBIT(43)
01755 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR    vxge_mBIT(47)
01756 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR  vxge_mBIT(51)
01757 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR        vxge_mBIT(55)
01758 #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR      vxge_mBIT(59)
01759 #define VXGE_HW_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN  vxge_mBIT(63)
01760 /*0x01808*/     u64     rxmac_rx_pa_cfg1;
01761 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH  vxge_mBIT(3)
01762 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH  vxge_mBIT(7)
01763 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH  vxge_mBIT(11)
01764 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH  vxge_mBIT(15)
01765 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF        vxge_mBIT(19)
01766 #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG    vxge_mBIT(23)
01767         u8      unused01828[0x01828-0x01810];
01768 
01769 /*0x01828*/     u64     rts_mgr_cfg0;
01770 #define VXGE_HW_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY vxge_mBIT(3)
01771 #define VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vxge_vBIT(val, 24, 8)
01772 #define VXGE_HW_RTS_MGR_CFG0_ICMP_TRASH vxge_mBIT(35)
01773 #define VXGE_HW_RTS_MGR_CFG0_TCPSYN_TRASH       vxge_mBIT(39)
01774 #define VXGE_HW_RTS_MGR_CFG0_ZL4PYLD_TRASH      vxge_mBIT(43)
01775 #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH  vxge_mBIT(47)
01776 #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH  vxge_mBIT(51)
01777 #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH vxge_mBIT(55)
01778 #define VXGE_HW_RTS_MGR_CFG0_IPFRAG_TRASH       vxge_mBIT(59)
01779 /*0x01830*/     u64     rts_mgr_cfg1;
01780 #define VXGE_HW_RTS_MGR_CFG1_DA_ACTIVE_TABLE    vxge_mBIT(3)
01781 #define VXGE_HW_RTS_MGR_CFG1_PN_ACTIVE_TABLE    vxge_mBIT(7)
01782 /*0x01838*/     u64     rts_mgr_criteria_priority;
01783 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vxge_vBIT(val, 5, 3)
01784 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vxge_vBIT(val, 9, 3)
01785 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vxge_vBIT(val, 13, 3)
01786 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vxge_vBIT(val, 17, 3)
01787 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vxge_vBIT(val, 21, 3)
01788 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS(val) vxge_vBIT(val, 25, 3)
01789 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vxge_vBIT(val, 29, 3)
01790 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vxge_vBIT(val, 33, 3)
01791 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vxge_vBIT(val, 37, 3)
01792 /*0x01840*/     u64     rts_mgr_da_pause_cfg;
01793 #define VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vxge_vBIT(val, 0, 17)
01794 /*0x01848*/     u64     rts_mgr_da_slow_proto_cfg;
01795 #define VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) \
01796                                                         vxge_vBIT(val, 0, 17)
01797         u8      unused01890[0x01890-0x01850];
01798 /*0x01890*/     u64     rts_mgr_cbasin_cfg;
01799         u8      unused01968[0x01968-0x01898];
01800 
01801 /*0x01968*/     u64     dbg_stat_rx_any_frms;
01802 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vxge_vBIT(val, 0, 8)
01803 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vxge_vBIT(val, 8, 8)
01804 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) \
01805                                                         vxge_vBIT(val, 16, 8)
01806         u8      unused01a00[0x01a00-0x01970];
01807 
01808 /*0x01a00*/     u64     rxmac_red_rate_vp[17];
01809 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0(val) vxge_vBIT(val, 0, 4)
01810 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val) vxge_vBIT(val, 4, 4)
01811 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2(val) vxge_vBIT(val, 8, 4)
01812 #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3(val) vxge_vBIT(val, 12, 4)
01813 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0(val) vxge_vBIT(val, 16, 4)
01814 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1(val) vxge_vBIT(val, 20, 4)
01815 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2(val) vxge_vBIT(val, 24, 4)
01816 #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3(val) vxge_vBIT(val, 28, 4)
01817         u8      unused01e00[0x01e00-0x01a88];
01818 
01819 /*0x01e00*/     u64     xgmac_int_status;
01820 #define VXGE_HW_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT      vxge_mBIT(3)
01821 #define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0 \
01822                                                                 vxge_mBIT(7)
01823 #define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1 \
01824                                                                 vxge_mBIT(11)
01825 #define VXGE_HW_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT      vxge_mBIT(15)
01826 #define VXGE_HW_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT    vxge_mBIT(19)
01827 #define VXGE_HW_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT    vxge_mBIT(23)
01828 /*0x01e08*/     u64     xgmac_int_mask;
01829 /*0x01e10*/     u64     xmac_gen_err_reg;
01830 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED \
01831                                                                 vxge_mBIT(7)
01832 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED \
01833                                                                 vxge_mBIT(11)
01834 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU vxge_mBIT(15)
01835 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED \
01836                                                                 vxge_mBIT(19)
01837 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED \
01838                                                                 vxge_mBIT(23)
01839 #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU vxge_mBIT(27)
01840 #define VXGE_HW_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED     vxge_mBIT(31)
01841 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val) \
01842                                                         vxge_vBIT(val, 40, 2)
01843 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val) \
01844                                                         vxge_vBIT(val, 42, 2)
01845 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val) \
01846                                                         vxge_vBIT(val, 44, 2)
01847 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val) \
01848                                                         vxge_vBIT(val, 46, 2)
01849 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val) \
01850                                                         vxge_vBIT(val, 48, 2)
01851 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val) \
01852                                                         vxge_vBIT(val, 50, 2)
01853 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val) \
01854                                                         vxge_vBIT(val, 52, 2)
01855 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val) \
01856                                                         vxge_vBIT(val, 54, 2)
01857 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val) \
01858                                                         vxge_vBIT(val, 56, 2)
01859 #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val) \
01860                                                         vxge_vBIT(val, 58, 2)
01861 #define VXGE_HW_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR     vxge_mBIT(63)
01862 /*0x01e18*/     u64     xmac_gen_err_mask;
01863 /*0x01e20*/     u64     xmac_gen_err_alarm;
01864 /*0x01e28*/     u64     xmac_link_err_port0_reg;
01865 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN  vxge_mBIT(3)
01866 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP    vxge_mBIT(7)
01867 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN     vxge_mBIT(11)
01868 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP       vxge_mBIT(15)
01869 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT \
01870                                                                 vxge_mBIT(19)
01871 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK vxge_mBIT(23)
01872 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN  vxge_mBIT(27)
01873 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP    vxge_mBIT(31)
01874 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE     vxge_mBIT(35)
01875 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV        vxge_mBIT(39)
01876 #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE \
01877                                                                 vxge_mBIT(47)
01878 /*0x01e30*/     u64     xmac_link_err_port0_mask;
01879 /*0x01e38*/     u64     xmac_link_err_port0_alarm;
01880 /*0x01e40*/     u64     xmac_link_err_port1_reg;
01881 /*0x01e48*/     u64     xmac_link_err_port1_mask;
01882 /*0x01e50*/     u64     xmac_link_err_port1_alarm;
01883 /*0x01e58*/     u64     xgxs_gen_err_reg;
01884 #define VXGE_HW_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR      vxge_mBIT(63)
01885 /*0x01e60*/     u64     xgxs_gen_err_mask;
01886 /*0x01e68*/     u64     xgxs_gen_err_alarm;
01887 /*0x01e70*/     u64     asic_ntwk_err_reg;
01888 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN       vxge_mBIT(3)
01889 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP vxge_mBIT(7)
01890 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN  vxge_mBIT(11)
01891 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP    vxge_mBIT(15)
01892 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT   vxge_mBIT(19)
01893 #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK      vxge_mBIT(23)
01894 /*0x01e78*/     u64     asic_ntwk_err_mask;
01895 /*0x01e80*/     u64     asic_ntwk_err_alarm;
01896 /*0x01e88*/     u64     asic_gpio_err_reg;
01897 #define VXGE_HW_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n)     vxge_mBIT(n)
01898 /*0x01e90*/     u64     asic_gpio_err_mask;
01899 /*0x01e98*/     u64     asic_gpio_err_alarm;
01900 /*0x01ea0*/     u64     xgmac_gen_status;
01901 #define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_OK  vxge_mBIT(3)
01902 #define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE   vxge_mBIT(11)
01903 /*0x01ea8*/     u64     xgmac_gen_fw_memo_status;
01904 #define VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val) \
01905                                                         vxge_vBIT(val, 0, 17)
01906 /*0x01eb0*/     u64     xgmac_gen_fw_memo_mask;
01907 #define VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vxge_vBIT(val, 0, 64)
01908 /*0x01eb8*/     u64     xgmac_gen_fw_vpath_to_vsport_status;
01909 #define VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val) \
01910                                                 vxge_vBIT(val, 0, 17)
01911 /*0x01ec0*/     u64     xgmac_main_cfg_port[2];
01912 #define VXGE_HW_XGMAC_MAIN_CFG_PORT_PORT_EN     vxge_mBIT(3)
01913         u8      unused01f40[0x01f40-0x01ed0];
01914 
01915 /*0x01f40*/     u64     xmac_gen_cfg;
01916 #define VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vxge_vBIT(val, 2, 2)
01917 #define VXGE_HW_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT    vxge_mBIT(7)
01918 #define VXGE_HW_XMAC_GEN_CFG_FAULT_BEHAVIOUR    vxge_mBIT(27)
01919 #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vxge_vBIT(val, 28, 4)
01920 #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vxge_vBIT(val, 32, 4)
01921 /*0x01f48*/     u64     xmac_timestamp;
01922 #define VXGE_HW_XMAC_TIMESTAMP_EN       vxge_mBIT(3)
01923 #define VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(val) vxge_vBIT(val, 6, 2)
01924 #define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val) vxge_vBIT(val, 12, 4)
01925 #define VXGE_HW_XMAC_TIMESTAMP_TIMER_RESTART    vxge_mBIT(19)
01926 #define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vxge_vBIT(val, 32, 16)
01927 /*0x01f50*/     u64     xmac_stats_gen_cfg;
01928 #define VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vxge_vBIT(val, 4, 4)
01929 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vxge_vBIT(val, 8, 4)
01930 #define VXGE_HW_XMAC_STATS_GEN_CFG_VLAN_HANDLING        vxge_mBIT(15)
01931 /*0x01f58*/     u64     xmac_stats_sys_cmd;
01932 #define VXGE_HW_XMAC_STATS_SYS_CMD_OP(val) vxge_vBIT(val, 5, 3)
01933 #define VXGE_HW_XMAC_STATS_SYS_CMD_STROBE       vxge_mBIT(15)
01934 #define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val) vxge_vBIT(val, 27, 5)
01935 #define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8)
01936 /*0x01f60*/     u64     xmac_stats_sys_data;
01937 #define VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64)
01938         u8      unused01f80[0x01f80-0x01f68];
01939 
01940 /*0x01f80*/     u64     asic_ntwk_ctrl;
01941 #define VXGE_HW_ASIC_NTWK_CTRL_REQ_TEST_NTWK    vxge_mBIT(3)
01942 #define VXGE_HW_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT      vxge_mBIT(11)
01943 #define VXGE_HW_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT      vxge_mBIT(15)
01944 /*0x01f88*/     u64     asic_ntwk_cfg_show_port_info;
01945 #define VXGE_HW_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n)      vxge_mBIT(n)
01946 /*0x01f90*/     u64     asic_ntwk_cfg_port_num;
01947 #define VXGE_HW_ASIC_NTWK_CFG_PORT_NUM_VP(n)    vxge_mBIT(n)
01948 /*0x01f98*/     u64     xmac_cfg_port[3];
01949 #define VXGE_HW_XMAC_CFG_PORT_XGMII_LOOPBACK    vxge_mBIT(3)
01950 #define VXGE_HW_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK    vxge_mBIT(7)
01951 #define VXGE_HW_XMAC_CFG_PORT_XGMII_TX_BEHAV    vxge_mBIT(11)
01952 #define VXGE_HW_XMAC_CFG_PORT_XGMII_RX_BEHAV    vxge_mBIT(15)
01953 /*0x01fb0*/     u64     xmac_station_addr_port[2];
01954 #define VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vxge_vBIT(val, 0, 48)
01955         u8      unused02020[0x02020-0x01fc0];
01956 
01957 /*0x02020*/     u64     lag_cfg;
01958 #define VXGE_HW_LAG_CFG_EN      vxge_mBIT(3)
01959 #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2)
01960 #define VXGE_HW_LAG_CFG_TX_DISCARD_BEHAV        vxge_mBIT(11)
01961 #define VXGE_HW_LAG_CFG_RX_DISCARD_BEHAV        vxge_mBIT(15)
01962 #define VXGE_HW_LAG_CFG_PREF_INDIV_PORT_NUM     vxge_mBIT(19)
01963 /*0x02028*/     u64     lag_status;
01964 #define VXGE_HW_LAG_STATUS_XLCM_WAITING_TO_FAILBACK     vxge_mBIT(3)
01965 #define VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) \
01966                                                         vxge_vBIT(val, 8, 8)
01967 /*0x02030*/     u64     lag_active_passive_cfg;
01968 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY      vxge_mBIT(3)
01969 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES     vxge_mBIT(7)
01970 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM     vxge_mBIT(11)
01971 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK    vxge_mBIT(15)
01972 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN      vxge_mBIT(19)
01973 #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val) \
01974                                                         vxge_vBIT(val, 32, 16)
01975         u8      unused02040[0x02040-0x02038];
01976 
01977 /*0x02040*/     u64     lag_lacp_cfg;
01978 #define VXGE_HW_LAG_LACP_CFG_EN vxge_mBIT(3)
01979 #define VXGE_HW_LAG_LACP_CFG_LACP_BEGIN vxge_mBIT(7)
01980 #define VXGE_HW_LAG_LACP_CFG_DISCARD_LACP       vxge_mBIT(11)
01981 #define VXGE_HW_LAG_LACP_CFG_LIBERAL_LEN_CHK    vxge_mBIT(15)
01982 /*0x02048*/     u64     lag_timer_cfg_1;
01983 #define VXGE_HW_LAG_TIMER_CFG_1_FAST_PER(val) vxge_vBIT(val, 0, 16)
01984 #define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val) vxge_vBIT(val, 16, 16)
01985 #define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vxge_vBIT(val, 32, 16)
01986 #define VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vxge_vBIT(val, 48, 16)
01987 /*0x02050*/     u64     lag_timer_cfg_2;
01988 #define VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET(val) vxge_vBIT(val, 0, 16)
01989 #define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val) vxge_vBIT(val, 16, 16)
01990 #define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vxge_vBIT(val, 32, 16)
01991 #define VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val)  vxge_vBIT(val, 48, 16)
01992 /*0x02058*/     u64     lag_sys_id;
01993 #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48)
01994 #define VXGE_HW_LAG_SYS_ID_USE_PORT_ADDR        vxge_mBIT(51)
01995 #define VXGE_HW_LAG_SYS_ID_ADDR_SEL     vxge_mBIT(55)
01996 /*0x02060*/     u64     lag_sys_cfg;
01997 #define VXGE_HW_LAG_SYS_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16)
01998         u8      unused02070[0x02070-0x02068];
01999 
02000 /*0x02070*/     u64     lag_aggr_addr_cfg[2];
02001 #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR(val) vxge_vBIT(val, 0, 48)
02002 #define VXGE_HW_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR vxge_mBIT(51)
02003 #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR_SEL      vxge_mBIT(55)
02004 /*0x02080*/     u64     lag_aggr_id_cfg[2];
02005 #define VXGE_HW_LAG_AGGR_ID_CFG_ID(val) vxge_vBIT(val, 0, 16)
02006 /*0x02090*/     u64     lag_aggr_admin_key[2];
02007 #define VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16)
02008 /*0x020a0*/     u64     lag_aggr_alt_admin_key;
02009 #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16)
02010 #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR vxge_mBIT(19)
02011 /*0x020a8*/     u64     lag_aggr_oper_key[2];
02012 #define VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16)
02013 /*0x020b8*/     u64     lag_aggr_partner_sys_id[2];
02014 #define VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vxge_vBIT(val, 0, 48)
02015 /*0x020c8*/     u64     lag_aggr_partner_info[2];
02016 #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vxge_vBIT(val, 0, 16)
02017 #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) \
02018                                                 vxge_vBIT(val, 16, 16)
02019 /*0x020d8*/     u64     lag_aggr_state[2];
02020 #define VXGE_HW_LAG_AGGR_STATE_LAGC_TX  vxge_mBIT(3)
02021 #define VXGE_HW_LAG_AGGR_STATE_LAGC_RX  vxge_mBIT(7)
02022 #define VXGE_HW_LAG_AGGR_STATE_LAGC_READY       vxge_mBIT(11)
02023 #define VXGE_HW_LAG_AGGR_STATE_LAGC_INDIVIDUAL  vxge_mBIT(15)
02024         u8      unused020f0[0x020f0-0x020e8];
02025 
02026 /*0x020f0*/     u64     lag_port_cfg[2];
02027 #define VXGE_HW_LAG_PORT_CFG_EN vxge_mBIT(3)
02028 #define VXGE_HW_LAG_PORT_CFG_DISCARD_SLOW_PROTO vxge_mBIT(7)
02029 #define VXGE_HW_LAG_PORT_CFG_HOST_CHOSEN_AGGR   vxge_mBIT(11)
02030 #define VXGE_HW_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO vxge_mBIT(15)
02031 /*0x02100*/     u64     lag_port_actor_admin_cfg[2];
02032 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vxge_vBIT(val, 0, 16)
02033 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vxge_vBIT(val, 16, 16)
02034 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vxge_vBIT(val, 32, 16)
02035 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vxge_vBIT(val, 48, 16)
02036 /*0x02110*/     u64     lag_port_actor_admin_state[2];
02037 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY        vxge_mBIT(3)
02038 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT vxge_mBIT(7)
02039 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION  vxge_mBIT(11)
02040 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION      vxge_mBIT(15)
02041 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING   vxge_mBIT(19)
02042 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING vxge_mBIT(23)
02043 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED    vxge_mBIT(27)
02044 #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED      vxge_mBIT(31)
02045 /*0x02120*/     u64     lag_port_partner_admin_sys_id[2];
02046 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48)
02047 /*0x02130*/     u64     lag_port_partner_admin_cfg[2];
02048 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16)
02049 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vxge_vBIT(val, 16, 16)
02050 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) \
02051                                                         vxge_vBIT(val, 32, 16)
02052 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) \
02053                                                         vxge_vBIT(val, 48, 16)
02054 /*0x02140*/     u64     lag_port_partner_admin_state[2];
02055 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY      vxge_mBIT(3)
02056 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT       vxge_mBIT(7)
02057 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION        vxge_mBIT(11)
02058 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION    vxge_mBIT(15)
02059 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING vxge_mBIT(19)
02060 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING       vxge_mBIT(23)
02061 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED  vxge_mBIT(27)
02062 #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED    vxge_mBIT(31)
02063 /*0x02150*/     u64     lag_port_to_aggr[2];
02064 #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vxge_vBIT(val, 0, 16)
02065 #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID       vxge_mBIT(19)
02066 /*0x02160*/     u64     lag_port_actor_oper_key[2];
02067 #define VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16)
02068 /*0x02170*/     u64     lag_port_actor_oper_state[2];
02069 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY    vxge_mBIT(3)
02070 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT     vxge_mBIT(7)
02071 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION      vxge_mBIT(11)
02072 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION  vxge_mBIT(15)
02073 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING       vxge_mBIT(19)
02074 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING     vxge_mBIT(23)
02075 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED        vxge_mBIT(27)
02076 #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED  vxge_mBIT(31)
02077 /*0x02180*/     u64     lag_port_partner_oper_sys_id[2];
02078 #define VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) \
02079                                                 vxge_vBIT(val, 0, 48)
02080 /*0x02190*/     u64     lag_port_partner_oper_info[2];
02081 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) \
02082                                                 vxge_vBIT(val, 0, 16)
02083 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) \
02084                                                 vxge_vBIT(val, 16, 16)
02085 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) \
02086                                                 vxge_vBIT(val, 32, 16)
02087 #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) \
02088                                                 vxge_vBIT(val, 48, 16)
02089 /*0x021a0*/     u64     lag_port_partner_oper_state[2];
02090 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY  vxge_mBIT(3)
02091 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT   vxge_mBIT(7)
02092 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION    vxge_mBIT(11)
02093 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION \
02094                                                                 vxge_mBIT(15)
02095 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING     vxge_mBIT(19)
02096 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING   vxge_mBIT(23)
02097 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED      vxge_mBIT(27)
02098 #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED        vxge_mBIT(31)
02099 /*0x021b0*/     u64     lag_port_state_vars[2];
02100 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_READY  vxge_mBIT(3)
02101 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vxge_vBIT(val, 6, 2)
02102 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM       vxge_mBIT(11)
02103 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED     vxge_mBIT(15)
02104 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED   vxge_mBIT(18)
02105 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED  vxge_mBIT(19)
02106 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_NTT    vxge_mBIT(23)
02107 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN    vxge_mBIT(27)
02108 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN  vxge_mBIT(31)
02109 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH \
02110                                                                 vxge_mBIT(32)
02111 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH \
02112                                                                 vxge_mBIT(33)
02113 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH vxge_mBIT(34)
02114 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH vxge_mBIT(35)
02115 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vxge_vBIT(val, 37, 3)
02116 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) \
02117                                                         vxge_vBIT(val, 41, 3)
02118 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vxge_vBIT(val, 44, 4)
02119 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE      vxge_mBIT(54)
02120 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE    vxge_mBIT(55)
02121 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val) \
02122                                                         vxge_vBIT(val, 56, 4)
02123 #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val) \
02124                                                         vxge_vBIT(val, 60, 4)
02125 /*0x021c0*/     u64     lag_port_timer_cntr[2];
02126 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE(val) vxge_vBIT(val, 0, 8)
02127 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val) \
02128                                                         vxge_vBIT(val, 8, 8)
02129 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE(val) vxge_vBIT(val, 16, 8)
02130 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vxge_vBIT(val, 24, 8)
02131 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val) \
02132                                                         vxge_vBIT(val, 32, 8)
02133 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val) \
02134                                                         vxge_vBIT(val, 40, 8)
02135 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val) \
02136                                                         vxge_vBIT(val, 48, 8)
02137 #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val) \
02138                                                         vxge_vBIT(val, 56, 8)
02139         u8      unused02208[0x02700-0x021d0];
02140 
02141 /*0x02700*/     u64     rtdma_int_status;
02142 #define VXGE_HW_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT      vxge_mBIT(1)
02143 #define VXGE_HW_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT      vxge_mBIT(2)
02144 #define VXGE_HW_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT      vxge_mBIT(4)
02145 #define VXGE_HW_RTDMA_INT_STATUS_SM_ERROR_SM_INT        vxge_mBIT(5)
02146 /*0x02708*/     u64     rtdma_int_mask;
02147 /*0x02710*/     u64     pda_alarm_reg;
02148 #define VXGE_HW_PDA_ALARM_REG_PDA_HSC_FIFO_ERR  vxge_mBIT(0)
02149 #define VXGE_HW_PDA_ALARM_REG_PDA_SM_ERR        vxge_mBIT(1)
02150 /*0x02718*/     u64     pda_alarm_mask;
02151 /*0x02720*/     u64     pda_alarm_alarm;
02152 /*0x02728*/     u64     pcc_error_reg;
02153 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n)    vxge_mBIT(n)
02154 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n)       vxge_mBIT(n)
02155 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n)    vxge_mBIT(n)
02156 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n)       vxge_mBIT(n)
02157 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n)  vxge_mBIT(n)
02158 #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_SERR(n)   vxge_mBIT(n)
02159 /*0x02730*/     u64     pcc_error_mask;
02160 /*0x02738*/     u64     pcc_error_alarm;
02161 /*0x02740*/     u64     lso_error_reg;
02162 #define VXGE_HW_LSO_ERROR_REG_PCC_LSO_ABORT(n)  vxge_mBIT(n)
02163 #define VXGE_HW_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n)  vxge_mBIT(n)
02164 /*0x02748*/     u64     lso_error_mask;
02165 /*0x02750*/     u64     lso_error_alarm;
02166 /*0x02758*/     u64     sm_error_reg;
02167 #define VXGE_HW_SM_ERROR_REG_SM_FSM_ERR_ALARM   vxge_mBIT(15)
02168 /*0x02760*/     u64     sm_error_mask;
02169 /*0x02768*/     u64     sm_error_alarm;
02170 
02171         u8      unused027a8[0x027a8-0x02770];
02172 
02173 /*0x027a8*/     u64     txd_ownership_ctrl;
02174 #define VXGE_HW_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP       vxge_mBIT(7)
02175 /*0x027b0*/     u64     pcc_cfg;
02176 #define VXGE_HW_PCC_CFG_PCC_ENABLE(n)   vxge_mBIT(n)
02177 #define VXGE_HW_PCC_CFG_PCC_ECC_ENABLE_N(n)     vxge_mBIT(n)
02178 /*0x027b8*/     u64     pcc_control;
02179 #define VXGE_HW_PCC_CONTROL_FE_ENABLE(val) vxge_vBIT(val, 6, 2)
02180 #define VXGE_HW_PCC_CONTROL_EARLY_ASSIGN_EN     vxge_mBIT(15)
02181 #define VXGE_HW_PCC_CONTROL_UNBLOCK_DB_ERR      vxge_mBIT(31)
02182 /*0x027c0*/     u64     pda_status1;
02183 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR(val) vxge_vBIT(val, 4, 4)
02184 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val) vxge_vBIT(val, 12, 4)
02185 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR(val) vxge_vBIT(val, 20, 4)
02186 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR(val) vxge_vBIT(val, 28, 4)
02187 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR(val) vxge_vBIT(val, 36, 4)
02188 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR(val) vxge_vBIT(val, 44, 4)
02189 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR(val) vxge_vBIT(val, 52, 4)
02190 #define VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR(val) vxge_vBIT(val, 60, 4)
02191 /*0x027c8*/     u64     rtdma_bw_timer;
02192 #define VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL(val) vxge_vBIT(val, 12, 4)
02193 
02194         u8      unused02900[0x02900-0x027d0];
02195 /*0x02900*/     u64     g3cmct_int_status;
02196 #define VXGE_HW_G3CMCT_INT_STATUS_ERR_G3IF_INT  vxge_mBIT(0)
02197 /*0x02908*/     u64     g3cmct_int_mask;
02198 /*0x02910*/     u64     g3cmct_err_reg;
02199 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_SM_ERR      vxge_mBIT(4)
02200 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_DECC  vxge_mBIT(5)
02201 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC        vxge_mBIT(6)
02202 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC      vxge_mBIT(7)
02203 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_SECC  vxge_mBIT(29)
02204 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC        vxge_mBIT(30)
02205 #define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC      vxge_mBIT(31)
02206 /*0x02918*/     u64     g3cmct_err_mask;
02207 /*0x02920*/     u64     g3cmct_err_alarm;
02208         u8      unused03000[0x03000-0x02928];
02209 
02210 /*0x03000*/     u64     mc_int_status;
02211 #define VXGE_HW_MC_INT_STATUS_MC_ERR_MC_INT     vxge_mBIT(3)
02212 #define VXGE_HW_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT    vxge_mBIT(7)
02213 #define VXGE_HW_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT   vxge_mBIT(11)
02214 #define VXGE_HW_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT   vxge_mBIT(15)
02215 /*0x03008*/     u64     mc_int_mask;
02216 /*0x03010*/     u64     mc_err_reg;
02217 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A     vxge_mBIT(3)
02218 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B     vxge_mBIT(4)
02219 #define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR   vxge_mBIT(5)
02220 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0 vxge_mBIT(6)
02221 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1 vxge_mBIT(7)
02222 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A     vxge_mBIT(10)
02223 #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B     vxge_mBIT(11)
02224 #define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR   vxge_mBIT(12)
02225 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 vxge_mBIT(13)
02226 #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 vxge_mBIT(14)
02227 #define VXGE_HW_MC_ERR_REG_MC_SM_ERR    vxge_mBIT(15)
02228 /*0x03018*/     u64     mc_err_mask;
02229 /*0x03020*/     u64     mc_err_alarm;
02230 /*0x03028*/     u64     grocrc_alarm_reg;
02231 #define VXGE_HW_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR       vxge_mBIT(3)
02232 #define VXGE_HW_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR    vxge_mBIT(7)
02233 /*0x03030*/     u64     grocrc_alarm_mask;
02234 /*0x03038*/     u64     grocrc_alarm_alarm;
02235         u8      unused03100[0x03100-0x03040];
02236 
02237 /*0x03100*/     u64     rx_thresh_cfg_repl;
02238 #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8)
02239 #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8)
02240 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0(val) vxge_vBIT(val, 16, 8)
02241 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1(val) vxge_vBIT(val, 24, 8)
02242 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val) vxge_vBIT(val, 32, 8)
02243 #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3(val) vxge_vBIT(val, 40, 8)
02244 #define VXGE_HW_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN        vxge_mBIT(62)
02245 #define VXGE_HW_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ   vxge_mBIT(63)
02246         u8      unused033b8[0x033b8-0x03108];
02247 
02248 /*0x033b8*/     u64     fbmc_ecc_cfg;
02249 #define VXGE_HW_FBMC_ECC_CFG_ENABLE(val) vxge_vBIT(val, 3, 5)
02250         u8      unused03400[0x03400-0x033c0];
02251 
02252 /*0x03400*/     u64     pcipif_int_status;
02253 #define VXGE_HW_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT       vxge_mBIT(3)
02254 #define VXGE_HW_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT       vxge_mBIT(7)
02255 #define VXGE_HW_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT   vxge_mBIT(11)
02256 #define VXGE_HW_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT     vxge_mBIT(15)
02257 #define VXGE_HW_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT \
02258                                                                 vxge_mBIT(19)
02259 /*0x03408*/     u64     pcipif_int_mask;
02260 /*0x03410*/     u64     dbecc_err_reg;
02261 #define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR      vxge_mBIT(3)
02262 #define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR      vxge_mBIT(7)
02263 #define VXGE_HW_DBECC_ERR_REG_PCI_P_HDR_DB_ERR  vxge_mBIT(11)
02264 #define VXGE_HW_DBECC_ERR_REG_PCI_P_DATA_DB_ERR vxge_mBIT(15)
02265 #define VXGE_HW_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR vxge_mBIT(19)
02266 #define VXGE_HW_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR        vxge_mBIT(23)
02267 /*0x03418*/     u64     dbecc_err_mask;
02268 /*0x03420*/     u64     dbecc_err_alarm;
02269 /*0x03428*/     u64     sbecc_err_reg;
02270 #define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR      vxge_mBIT(3)
02271 #define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR      vxge_mBIT(7)
02272 #define VXGE_HW_SBECC_ERR_REG_PCI_P_HDR_SG_ERR  vxge_mBIT(11)
02273 #define VXGE_HW_SBECC_ERR_REG_PCI_P_DATA_SG_ERR vxge_mBIT(15)
02274 #define VXGE_HW_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR vxge_mBIT(19)
02275 #define VXGE_HW_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR        vxge_mBIT(23)
02276 /*0x03430*/     u64     sbecc_err_mask;
02277 /*0x03438*/     u64     sbecc_err_alarm;
02278 /*0x03440*/     u64     general_err_reg;
02279 #define VXGE_HW_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG vxge_mBIT(3)
02280 #define VXGE_HW_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG        vxge_mBIT(7)
02281 #define VXGE_HW_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR    vxge_mBIT(11)
02282 #define VXGE_HW_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE       vxge_mBIT(15)
02283 #define VXGE_HW_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET  vxge_mBIT(19)
02284 #define VXGE_HW_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET   vxge_mBIT(23)
02285 #define VXGE_HW_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP      vxge_mBIT(27)
02286 /*0x03448*/     u64     general_err_mask;
02287 /*0x03450*/     u64     general_err_alarm;
02288 /*0x03458*/     u64     srpcim_msg_reg;
02289 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT \
02290                                                                 vxge_mBIT(0)
02291 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT \
02292                                                                 vxge_mBIT(1)
02293 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT \
02294                                                                 vxge_mBIT(2)
02295 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT \
02296                                                                 vxge_mBIT(3)
02297 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT \
02298                                                                 vxge_mBIT(4)
02299 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT \
02300                                                                 vxge_mBIT(5)
02301 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT \
02302                                                                 vxge_mBIT(6)
02303 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT \
02304                                                                 vxge_mBIT(7)
02305 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT \
02306                                                                 vxge_mBIT(8)
02307 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT \
02308                                                                 vxge_mBIT(9)
02309 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT \
02310                                                                 vxge_mBIT(10)
02311 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT \
02312                                                                 vxge_mBIT(11)
02313 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT \
02314                                                                 vxge_mBIT(12)
02315 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT \
02316                                                                 vxge_mBIT(13)
02317 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT \
02318                                                                 vxge_mBIT(14)
02319 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT \
02320                                                                 vxge_mBIT(15)
02321 #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT \
02322                                                                 vxge_mBIT(16)
02323 /*0x03460*/     u64     srpcim_msg_mask;
02324 /*0x03468*/     u64     srpcim_msg_alarm;
02325         u8      unused03600[0x03600-0x03470];
02326 
02327 /*0x03600*/     u64     gcmg1_int_status;
02328 #define VXGE_HW_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT    vxge_mBIT(0)
02329 #define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT vxge_mBIT(1)
02330 #define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT vxge_mBIT(2)
02331 #define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT vxge_mBIT(3)
02332 #define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT vxge_mBIT(4)
02333 #define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT vxge_mBIT(5)
02334 #define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT vxge_mBIT(6)
02335 #define VXGE_HW_GCMG1_INT_STATUS_UQM_ERR_UQM_INT        vxge_mBIT(7)
02336 #define VXGE_HW_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT      vxge_mBIT(8)
02337 /*0x03608*/     u64     gcmg1_int_mask;
02338         u8      unused03a00[0x03a00-0x03610];
02339 
02340 /*0x03a00*/     u64     pcmg1_int_status;
02341 #define VXGE_HW_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT    vxge_mBIT(0)
02342 #define VXGE_HW_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT      vxge_mBIT(1)
02343 #define VXGE_HW_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT      vxge_mBIT(2)
02344 #define VXGE_HW_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT      vxge_mBIT(3)
02345 /*0x03a08*/     u64     pcmg1_int_mask;
02346         u8      unused04000[0x04000-0x03a10];
02347 
02348 /*0x04000*/     u64     one_int_status;
02349 #define VXGE_HW_ONE_INT_STATUS_RXPE_ERR_RXPE_INT        vxge_mBIT(7)
02350 #define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT \
02351                                                         vxge_mBIT(13)
02352 #define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT \
02353                                                         vxge_mBIT(14)
02354 #define VXGE_HW_ONE_INT_STATUS_TXPE_ERR_TXPE_INT        vxge_mBIT(15)
02355 #define VXGE_HW_ONE_INT_STATUS_DLM_ERR_DLM_INT  vxge_mBIT(23)
02356 #define VXGE_HW_ONE_INT_STATUS_PE_ERR_PE_INT    vxge_mBIT(31)
02357 #define VXGE_HW_ONE_INT_STATUS_RPE_ERR_RPE_INT  vxge_mBIT(39)
02358 #define VXGE_HW_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT  vxge_mBIT(47)
02359 #define VXGE_HW_ONE_INT_STATUS_OES_ERR_OES_INT  vxge_mBIT(55)
02360 /*0x04008*/     u64     one_int_mask;
02361         u8      unused04818[0x04818-0x04010];
02362 
02363 /*0x04818*/     u64     noa_wct_ctrl;
02364 #define VXGE_HW_NOA_WCT_CTRL_VP_INT_NUM vxge_mBIT(0)
02365 /*0x04820*/     u64     rc_cfg2;
02366 #define VXGE_HW_RC_CFG2_BUFF1_SIZE(val) vxge_vBIT(val, 0, 16)
02367 #define VXGE_HW_RC_CFG2_BUFF2_SIZE(val) vxge_vBIT(val, 16, 16)
02368 #define VXGE_HW_RC_CFG2_BUFF3_SIZE(val) vxge_vBIT(val, 32, 16)
02369 #define VXGE_HW_RC_CFG2_BUFF4_SIZE(val) vxge_vBIT(val, 48, 16)
02370 /*0x04828*/     u64     rc_cfg3;
02371 #define VXGE_HW_RC_CFG3_BUFF5_SIZE(val) vxge_vBIT(val, 0, 16)
02372 /*0x04830*/     u64     rx_multi_cast_ctrl1;
02373 #define VXGE_HW_RX_MULTI_CAST_CTRL1_ENABLE      vxge_mBIT(7)
02374 #define VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vxge_vBIT(val, 11, 5)
02375 /*0x04838*/     u64     rxdm_dbg_rd;
02376 #define VXGE_HW_RXDM_DBG_RD_ADDR(val) vxge_vBIT(val, 0, 12)
02377 #define VXGE_HW_RXDM_DBG_RD_ENABLE      vxge_mBIT(31)
02378 /*0x04840*/     u64     rxdm_dbg_rd_data;
02379 #define VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vxge_vBIT(val, 0, 64)
02380 /*0x04848*/     u64     rqa_top_prty_for_vh[17];
02381 #define VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \
02382                                                         vxge_vBIT(val, 59, 5)
02383         u8      unused04900[0x04900-0x048d0];
02384 
02385 /*0x04900*/     u64     tim_status;
02386 #define VXGE_HW_TIM_STATUS_TIM_RESET_IN_PROGRESS        vxge_mBIT(0)
02387 /*0x04908*/     u64     tim_ecc_enable;
02388 #define VXGE_HW_TIM_ECC_ENABLE_VBLS_N   vxge_mBIT(7)
02389 #define VXGE_HW_TIM_ECC_ENABLE_BMAP_N   vxge_mBIT(15)
02390 #define VXGE_HW_TIM_ECC_ENABLE_BMAP_MSG_N       vxge_mBIT(23)
02391 /*0x04910*/     u64     tim_bp_ctrl;
02392 #define VXGE_HW_TIM_BP_CTRL_RD_XON      vxge_mBIT(7)
02393 #define VXGE_HW_TIM_BP_CTRL_WR_XON      vxge_mBIT(15)
02394 #define VXGE_HW_TIM_BP_CTRL_ROCRC_BYP   vxge_mBIT(23)
02395 /*0x04918*/     u64     tim_resource_assignment_vh[17];
02396 #define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
02397 /*0x049a0*/     u64     tim_bmap_mapping_vp_err[17];
02398 #define VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vxge_vBIT(val, 3, 5)
02399         u8      unused04b00[0x04b00-0x04a28];
02400 
02401 /*0x04b00*/     u64     gcmg2_int_status;
02402 #define VXGE_HW_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT    vxge_mBIT(7)
02403 #define VXGE_HW_GCMG2_INT_STATUS_GCP_ERR_GCP_INT        vxge_mBIT(15)
02404 #define VXGE_HW_GCMG2_INT_STATUS_CMC_ERR_CMC_INT        vxge_mBIT(23)
02405 /*0x04b08*/     u64     gcmg2_int_mask;
02406 /*0x04b10*/     u64     gxtmc_err_reg;
02407 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vxge_vBIT(val, 0, 4)
02408 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vxge_vBIT(val, 4, 4)
02409 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR   vxge_mBIT(8)
02410 #define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(9)
02411 #define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR    vxge_mBIT(10)
02412 #define VXGE_HW_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR      vxge_mBIT(11)
02413 #define VXGE_HW_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR      vxge_mBIT(12)
02414 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR     vxge_mBIT(13)
02415 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR  vxge_mBIT(14)
02416 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR     vxge_mBIT(15)
02417 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR  vxge_mBIT(16)
02418 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR      vxge_mBIT(17)
02419 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR      vxge_mBIT(18)
02420 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR   vxge_mBIT(19)
02421 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR   vxge_mBIT(20)
02422 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW \
02423                                                         vxge_mBIT(21)
02424 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW \
02425                                                         vxge_mBIT(22)
02426 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR        vxge_mBIT(23)
02427 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW \
02428                                                         vxge_mBIT(24)
02429 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW \
02430                                                         vxge_mBIT(25)
02431 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR vxge_mBIT(26)
02432 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR        vxge_mBIT(27)
02433 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR       vxge_mBIT(28)
02434 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR  vxge_mBIT(29)
02435 #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR        vxge_mBIT(30)
02436 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR vxge_mBIT(31)
02437 #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR  vxge_mBIT(32)
02438 #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR       vxge_mBIT(33)
02439 #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR   vxge_mBIT(34)
02440 #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR       vxge_mBIT(35)
02441 /*0x04b18*/     u64     gxtmc_err_mask;
02442 /*0x04b20*/     u64     gxtmc_err_alarm;
02443 /*0x04b28*/     u64     cmc_err_reg;
02444 #define VXGE_HW_CMC_ERR_REG_CMC_CMC_SM_ERR      vxge_mBIT(0)
02445 /*0x04b30*/     u64     cmc_err_mask;
02446 /*0x04b38*/     u64     cmc_err_alarm;
02447 /*0x04b40*/     u64     gcp_err_reg;
02448 #define VXGE_HW_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR  vxge_mBIT(0)
02449 #define VXGE_HW_GCP_ERR_REG_CP_STC2CP_FIFO_ERR  vxge_mBIT(1)
02450 #define VXGE_HW_GCP_ERR_REG_CP_STE2CP_FIFO_ERR  vxge_mBIT(2)
02451 #define VXGE_HW_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR  vxge_mBIT(3)
02452 /*0x04b48*/     u64     gcp_err_mask;
02453 /*0x04b50*/     u64     gcp_err_alarm;
02454         u8      unused04f00[0x04f00-0x04b58];
02455 
02456 /*0x04f00*/     u64     pcmg2_int_status;
02457 #define VXGE_HW_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT    vxge_mBIT(7)
02458 #define VXGE_HW_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT   vxge_mBIT(15)
02459 #define VXGE_HW_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT      vxge_mBIT(23)
02460 /*0x04f08*/     u64     pcmg2_int_mask;
02461 /*0x04f10*/     u64     pxtmc_err_reg;
02462 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vxge_vBIT(val, 0, 2)
02463 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR     vxge_mBIT(2)
02464 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR    vxge_mBIT(3)
02465 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR    vxge_mBIT(4)
02466 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR     vxge_mBIT(5)
02467 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR    vxge_mBIT(6)
02468 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR    vxge_mBIT(7)
02469 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR     vxge_mBIT(8)
02470 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR    vxge_mBIT(9)
02471 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR    vxge_mBIT(10)
02472 #define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(11)
02473 #define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR    vxge_mBIT(12)
02474 #define VXGE_HW_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR      vxge_mBIT(13)
02475 #define VXGE_HW_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR      vxge_mBIT(14)
02476 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR   vxge_mBIT(15)
02477 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR   vxge_mBIT(16)
02478 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR   vxge_mBIT(17)
02479 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR   vxge_mBIT(18)
02480 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR   vxge_mBIT(19)
02481 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR   vxge_mBIT(20)
02482 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR       vxge_mBIT(21)
02483 #define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR       vxge_mBIT(22)
02484 #define VXGE_HW_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR       vxge_mBIT(23)
02485 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR       vxge_mBIT(24)
02486 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR       vxge_mBIT(25)
02487 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR      vxge_mBIT(26)
02488 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR      vxge_mBIT(27)
02489 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR      vxge_mBIT(28)
02490 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR      vxge_mBIT(29)
02491 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR      vxge_mBIT(30)
02492 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR      vxge_mBIT(31)
02493 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR  vxge_mBIT(32)
02494 #define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR  vxge_mBIT(33)
02495 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR  vxge_mBIT(34)
02496 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR  vxge_mBIT(35)
02497 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR      vxge_mBIT(36)
02498 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR      vxge_mBIT(37)
02499 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR      vxge_mBIT(38)
02500 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR      vxge_mBIT(39)
02501 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR      vxge_mBIT(40)
02502 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR      vxge_mBIT(41)
02503 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR     vxge_mBIT(42)
02504 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR     vxge_mBIT(43)
02505 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR     vxge_mBIT(44)
02506 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR vxge_mBIT(45)
02507 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR vxge_mBIT(46)
02508 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR vxge_mBIT(47)
02509 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR vxge_mBIT(48)
02510 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR vxge_mBIT(49)
02511 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR vxge_mBIT(50)
02512 #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR        vxge_mBIT(51)
02513 #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR        vxge_mBIT(52)
02514 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR        vxge_mBIT(53)
02515 #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vxge_vBIT(val, 54, 2)
02516 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR        vxge_mBIT(56)
02517 #define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR        vxge_mBIT(57)
02518 /*0x04f18*/     u64     pxtmc_err_mask;
02519 /*0x04f20*/     u64     pxtmc_err_alarm;
02520 /*0x04f28*/     u64     cp_err_reg;
02521 #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vxge_vBIT(val, 0, 8)
02522 #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vxge_vBIT(val, 8, 2)
02523 #define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_SG_ERR    vxge_mBIT(10)
02524 #define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_SG_ERR    vxge_mBIT(11)
02525 #define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_SG_ERR   vxge_mBIT(12)
02526 #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_SG_ERR     vxge_mBIT(13)
02527 #define VXGE_HW_CP_ERR_REG_CP_MP2CP_SG_ERR      vxge_mBIT(14)
02528 #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_SG_ERR     vxge_mBIT(15)
02529 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vxge_vBIT(val, 16, 2)
02530 #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vxge_vBIT(val, 24, 8)
02531 #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vxge_vBIT(val, 32, 2)
02532 #define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_DB_ERR    vxge_mBIT(34)
02533 #define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_DB_ERR    vxge_mBIT(35)
02534 #define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_DB_ERR   vxge_mBIT(36)
02535 #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_DB_ERR     vxge_mBIT(37)
02536 #define VXGE_HW_CP_ERR_REG_CP_MP2CP_DB_ERR      vxge_mBIT(38)
02537 #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_DB_ERR     vxge_mBIT(39)
02538 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vxge_vBIT(val, 40, 2)
02539 #define VXGE_HW_CP_ERR_REG_CP_H2L2CP_FIFO_ERR   vxge_mBIT(48)
02540 #define VXGE_HW_CP_ERR_REG_CP_STC2CP_FIFO_ERR   vxge_mBIT(49)
02541 #define VXGE_HW_CP_ERR_REG_CP_STE2CP_FIFO_ERR   vxge_mBIT(50)
02542 #define VXGE_HW_CP_ERR_REG_CP_TTE2CP_FIFO_ERR   vxge_mBIT(51)
02543 #define VXGE_HW_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR  vxge_mBIT(52)
02544 #define VXGE_HW_CP_ERR_REG_CP_CP2DMA_FIFO_ERR   vxge_mBIT(53)
02545 #define VXGE_HW_CP_ERR_REG_CP_DAM2CP_FIFO_ERR   vxge_mBIT(54)
02546 #define VXGE_HW_CP_ERR_REG_CP_MP2CP_FIFO_ERR    vxge_mBIT(55)
02547 #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_FIFO_ERR   vxge_mBIT(56)
02548 #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_FIFO_ERR   vxge_mBIT(57)
02549 #define VXGE_HW_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(60)
02550 #define VXGE_HW_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(61)
02551 #define VXGE_HW_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR vxge_mBIT(62)
02552 #define VXGE_HW_CP_ERR_REG_CP_PIFT_CREDIT_ERR   vxge_mBIT(63)
02553 /*0x04f30*/     u64     cp_err_mask;
02554 /*0x04f38*/     u64     cp_err_alarm;
02555         u8      unused04fe8[0x04f50-0x04f40];
02556 
02557 /*0x04f50*/     u64     cp_exc_reg;
02558 #define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_INFO_INT vxge_mBIT(47)
02559 #define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT vxge_mBIT(55)
02560 #define VXGE_HW_CP_EXC_REG_CP_CP_SERR   vxge_mBIT(63)
02561 /*0x04f58*/     u64     cp_exc_mask;
02562 /*0x04f60*/     u64     cp_exc_alarm;
02563 /*0x04f68*/     u64     cp_exc_cause;
02564 #define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val) vxge_vBIT(val, 32, 32)
02565         u8      unused05200[0x05200-0x04f70];
02566 
02567 /*0x05200*/     u64     msg_int_status;
02568 #define VXGE_HW_MSG_INT_STATUS_TIM_ERR_TIM_INT  vxge_mBIT(7)
02569 #define VXGE_HW_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT   vxge_mBIT(60)
02570 #define VXGE_HW_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT    vxge_mBIT(61)
02571 #define VXGE_HW_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT    vxge_mBIT(62)
02572 #define VXGE_HW_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT      vxge_mBIT(63)
02573 /*0x05208*/     u64     msg_int_mask;
02574 /*0x05210*/     u64     tim_err_reg;
02575 #define VXGE_HW_TIM_ERR_REG_TIM_VBLS_SG_ERR     vxge_mBIT(4)
02576 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR  vxge_mBIT(5)
02577 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR  vxge_mBIT(6)
02578 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR vxge_mBIT(7)
02579 #define VXGE_HW_TIM_ERR_REG_TIM_VBLS_DB_ERR     vxge_mBIT(12)
02580 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR  vxge_mBIT(13)
02581 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR  vxge_mBIT(14)
02582 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR vxge_mBIT(15)
02583 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR   vxge_mBIT(18)
02584 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR       vxge_mBIT(19)
02585 #define VXGE_HW_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR  vxge_mBIT(20)
02586 #define VXGE_HW_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR        vxge_mBIT(22)
02587 #define VXGE_HW_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR vxge_mBIT(23)
02588 #define VXGE_HW_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH        vxge_mBIT(46)
02589 #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n)  vxge_mBIT(n)
02590 /*0x05218*/     u64     tim_err_mask;
02591 /*0x05220*/     u64     tim_err_alarm;
02592 /*0x05228*/     u64     msg_err_reg;
02593 #define VXGE_HW_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR       vxge_mBIT(0)
02594 #define VXGE_HW_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR       vxge_mBIT(1)
02595 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR \
02596                                                                 vxge_mBIT(2)
02597 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR \
02598                                                                 vxge_mBIT(3)
02599 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR   vxge_mBIT(4)
02600 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR   vxge_mBIT(5)
02601 #define VXGE_HW_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR       vxge_mBIT(6)
02602 #define VXGE_HW_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR       vxge_mBIT(7)
02603 #define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR  vxge_mBIT(8)
02604 #define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR  vxge_mBIT(10)
02605 #define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR  vxge_mBIT(12)
02606 #define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR  vxge_mBIT(14)
02607 #define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR vxge_mBIT(16)
02608 #define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR vxge_mBIT(17)
02609 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR      vxge_mBIT(18)
02610 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR     vxge_mBIT(19)
02611 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR     vxge_mBIT(20)
02612 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR      vxge_mBIT(21)
02613 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR  vxge_mBIT(26)
02614 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR       vxge_mBIT(27)
02615 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR      vxge_mBIT(29)
02616 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR vxge_mBIT(31)
02617 #define VXGE_HW_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR       vxge_mBIT(33)
02618 #define VXGE_HW_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR        vxge_mBIT(34)
02619 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR vxge_mBIT(35)
02620 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR \
02621                                                                 vxge_mBIT(36)
02622 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR   vxge_mBIT(38)
02623 #define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR  vxge_mBIT(39)
02624 #define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR  vxge_mBIT(41)
02625 #define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR  vxge_mBIT(43)
02626 #define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR  vxge_mBIT(45)
02627 #define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR vxge_mBIT(47)
02628 #define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR vxge_mBIT(48)
02629 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR      vxge_mBIT(49)
02630 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR     vxge_mBIT(50)
02631 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR     vxge_mBIT(51)
02632 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR      vxge_mBIT(52)
02633 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR   vxge_mBIT(53)
02634 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR    vxge_mBIT(54)
02635 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR   vxge_mBIT(55)
02636 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR   vxge_mBIT(56)
02637 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR  vxge_mBIT(57)
02638 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR       vxge_mBIT(58)
02639 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR    vxge_mBIT(59)
02640 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR      vxge_mBIT(60)
02641 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR   vxge_mBIT(61)
02642 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR vxge_mBIT(62)
02643 #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR    vxge_mBIT(63)
02644 /*0x05230*/     u64     msg_err_mask;
02645 /*0x05238*/     u64     msg_err_alarm;
02646         u8      unused05340[0x05340-0x05240];
02647 
02648 /*0x05340*/     u64     msg_exc_reg;
02649 #define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT       vxge_mBIT(50)
02650 #define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT       vxge_mBIT(51)
02651 #define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT       vxge_mBIT(54)
02652 #define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT       vxge_mBIT(55)
02653 #define VXGE_HW_MSG_EXC_REG_MP_MXP_SERR vxge_mBIT(62)
02654 #define VXGE_HW_MSG_EXC_REG_UP_UXP_SERR vxge_mBIT(63)
02655 /*0x05348*/     u64     msg_exc_mask;
02656 /*0x05350*/     u64     msg_exc_alarm;
02657 /*0x05358*/     u64     msg_exc_cause;
02658 #define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val) vxge_vBIT(val, 0, 32)
02659 #define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val) vxge_vBIT(val, 32, 32)
02660         u8      unused05368[0x05380-0x05360];
02661 
02662 /*0x05380*/     u64     msg_err2_reg;
02663 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR \
02664                                                         vxge_mBIT(0)
02665 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR \
02666                                                                 vxge_mBIT(1)
02667 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR \
02668                                                                 vxge_mBIT(2)
02669 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR \
02670                                                                 vxge_mBIT(3)
02671 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR  vxge_mBIT(4)
02672 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR \
02673                                                                 vxge_mBIT(5)
02674 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR   vxge_mBIT(6)
02675 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR  vxge_mBIT(7)
02676 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR  vxge_mBIT(8)
02677 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR  vxge_mBIT(9)
02678 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR   vxge_mBIT(10)
02679 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR    vxge_mBIT(11)
02680 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR \
02681                                                         vxge_mBIT(12)
02682 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR \
02683                                                         vxge_mBIT(13)
02684 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR \
02685                                                         vxge_mBIT(14)
02686 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR \
02687                                                         vxge_mBIT(15)
02688 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR \
02689                                                         vxge_mBIT(16)
02690 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR \
02691                                                         vxge_mBIT(17)
02692 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR \
02693                                                         vxge_mBIT(18)
02694 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR \
02695                                                         vxge_mBIT(19)
02696 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR \
02697                                                         vxge_mBIT(20)
02698 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR \
02699                                                         vxge_mBIT(21)
02700 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR \
02701                                                         vxge_mBIT(22)
02702 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR \
02703                                                         vxge_mBIT(23)
02704 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR \
02705                                                         vxge_mBIT(24)
02706 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR \
02707                                                         vxge_mBIT(25)
02708 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR \
02709                                                         vxge_mBIT(26)
02710 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR \
02711                                                         vxge_mBIT(27)
02712 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR \
02713                                                         vxge_mBIT(28)
02714 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR vxge_mBIT(29)
02715 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \
02716                                                         vxge_mBIT(30)
02717 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \
02718                                                         vxge_mBIT(31)
02719 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \
02720                                                         vxge_mBIT(32)
02721 #define VXGE_HW_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR       vxge_mBIT(33)
02722 #define VXGE_HW_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR       vxge_mBIT(34)
02723 #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR       vxge_mBIT(62)
02724 #define VXGE_HW_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR   vxge_mBIT(63)
02725 /*0x05388*/     u64     msg_err2_mask;
02726 /*0x05390*/     u64     msg_err2_alarm;
02727 /*0x05398*/     u64     msg_err3_reg;
02728 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0      vxge_mBIT(0)
02729 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1      vxge_mBIT(1)
02730 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2      vxge_mBIT(2)
02731 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3      vxge_mBIT(3)
02732 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4      vxge_mBIT(4)
02733 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5      vxge_mBIT(5)
02734 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6      vxge_mBIT(6)
02735 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7      vxge_mBIT(7)
02736 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0      vxge_mBIT(8)
02737 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1      vxge_mBIT(9)
02738 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0      vxge_mBIT(16)
02739 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1      vxge_mBIT(17)
02740 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2      vxge_mBIT(18)
02741 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3      vxge_mBIT(19)
02742 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4      vxge_mBIT(20)
02743 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5      vxge_mBIT(21)
02744 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6      vxge_mBIT(22)
02745 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7      vxge_mBIT(23)
02746 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0      vxge_mBIT(24)
02747 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1      vxge_mBIT(25)
02748 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0      vxge_mBIT(32)
02749 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1      vxge_mBIT(33)
02750 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2      vxge_mBIT(34)
02751 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3      vxge_mBIT(35)
02752 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4      vxge_mBIT(36)
02753 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5      vxge_mBIT(37)
02754 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6      vxge_mBIT(38)
02755 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7      vxge_mBIT(39)
02756 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0      vxge_mBIT(40)
02757 #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1      vxge_mBIT(41)
02758 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0      vxge_mBIT(48)
02759 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1      vxge_mBIT(49)
02760 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2      vxge_mBIT(50)
02761 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3      vxge_mBIT(51)
02762 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4      vxge_mBIT(52)
02763 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5      vxge_mBIT(53)
02764 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6      vxge_mBIT(54)
02765 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7      vxge_mBIT(55)
02766 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0      vxge_mBIT(56)
02767 #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1      vxge_mBIT(57)
02768 /*0x053a0*/     u64     msg_err3_mask;
02769 /*0x053a8*/     u64     msg_err3_alarm;
02770         u8      unused05600[0x05600-0x053b0];
02771 
02772 /*0x05600*/     u64     fau_gen_err_reg;
02773 #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP       vxge_mBIT(3)
02774 #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP       vxge_mBIT(7)
02775 #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP       vxge_mBIT(11)
02776 #define VXGE_HW_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIFICATION      vxge_mBIT(15)
02777 /*0x05608*/     u64     fau_gen_err_mask;
02778 /*0x05610*/     u64     fau_gen_err_alarm;
02779 /*0x05618*/     u64     fau_ecc_err_reg;
02780 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR    vxge_mBIT(0)
02781 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR    vxge_mBIT(1)
02782 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val) \
02783                                                         vxge_vBIT(val, 2, 2)
02784 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val) \
02785                                                         vxge_vBIT(val, 4, 2)
02786 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR    vxge_mBIT(6)
02787 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR    vxge_mBIT(7)
02788 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val) \
02789                                                         vxge_vBIT(val, 8, 2)
02790 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val) \
02791                                                         vxge_vBIT(val, 10, 2)
02792 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR    vxge_mBIT(12)
02793 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR    vxge_mBIT(13)
02794 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val) \
02795                                                         vxge_vBIT(val, 14, 2)
02796 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val) \
02797                                                         vxge_vBIT(val, 16, 2)
02798 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) \
02799                                                         vxge_vBIT(val, 18, 2)
02800 #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) \
02801                                                         vxge_vBIT(val, 20, 2)
02802 #define VXGE_HW_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR        vxge_mBIT(31)
02803 /*0x05620*/     u64     fau_ecc_err_mask;
02804 /*0x05628*/     u64     fau_ecc_err_alarm;
02805         u8      unused05658[0x05658-0x05630];
02806 /*0x05658*/     u64     fau_pa_cfg;
02807 #define VXGE_HW_FAU_PA_CFG_REPL_L4_COMP_CSUM    vxge_mBIT(3)
02808 #define VXGE_HW_FAU_PA_CFG_REPL_L3_INCL_CF      vxge_mBIT(7)
02809 #define VXGE_HW_FAU_PA_CFG_REPL_L3_COMP_CSUM    vxge_mBIT(11)
02810         u8      unused05668[0x05668-0x05660];
02811 
02812 /*0x05668*/     u64     dbg_stats_fau_rx_path;
02813 #define VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) \
02814                                                 vxge_vBIT(val, 32, 32)
02815         u8      unused056c0[0x056c0-0x05670];
02816 
02817 /*0x056c0*/     u64     fau_lag_cfg;
02818 #define VXGE_HW_FAU_LAG_CFG_COLL_ALG(val) vxge_vBIT(val, 2, 2)
02819 #define VXGE_HW_FAU_LAG_CFG_INCR_RX_AGGR_STATS  vxge_mBIT(7)
02820         u8      unused05800[0x05800-0x056c8];
02821 
02822 /*0x05800*/     u64     tpa_int_status;
02823 #define VXGE_HW_TPA_INT_STATUS_ORP_ERR_ORP_INT  vxge_mBIT(15)
02824 #define VXGE_HW_TPA_INT_STATUS_PTM_ALARM_PTM_INT        vxge_mBIT(23)
02825 #define VXGE_HW_TPA_INT_STATUS_TPA_ERROR_TPA_INT        vxge_mBIT(31)
02826 /*0x05808*/     u64     tpa_int_mask;
02827 /*0x05810*/     u64     orp_err_reg;
02828 #define VXGE_HW_ORP_ERR_REG_ORP_FIFO_SG_ERR     vxge_mBIT(3)
02829 #define VXGE_HW_ORP_ERR_REG_ORP_FIFO_DB_ERR     vxge_mBIT(7)
02830 #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR     vxge_mBIT(11)
02831 #define VXGE_HW_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR      vxge_mBIT(15)
02832 #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR        vxge_mBIT(19)
02833 #define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR vxge_mBIT(23)
02834 #define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR  vxge_mBIT(27)
02835 #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR     vxge_mBIT(31)
02836 #define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR      vxge_mBIT(35)
02837 #define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR       vxge_mBIT(39)
02838 #define VXGE_HW_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR       vxge_mBIT(43)
02839 #define VXGE_HW_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR       vxge_mBIT(47)
02840 /*0x05818*/     u64     orp_err_mask;
02841 /*0x05820*/     u64     orp_err_alarm;
02842 /*0x05828*/     u64     ptm_alarm_reg;
02843 #define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR       vxge_mBIT(3)
02844 #define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR       vxge_mBIT(7)
02845 #define VXGE_HW_PTM_ALARM_REG_XFMD_RD_FIFO_ERR  vxge_mBIT(11)
02846 #define VXGE_HW_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR       vxge_mBIT(15)
02847 #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vxge_vBIT(val, 18, 2)
02848 #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vxge_vBIT(val, 22, 2)
02849 /*0x05830*/     u64     ptm_alarm_mask;
02850 /*0x05838*/     u64     ptm_alarm_alarm;
02851 /*0x05840*/     u64     tpa_error_reg;
02852 #define VXGE_HW_TPA_ERROR_REG_TPA_FSM_ERR_ALARM vxge_mBIT(3)
02853 #define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR       vxge_mBIT(7)
02854 #define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR       vxge_mBIT(11)
02855 /*0x05848*/     u64     tpa_error_mask;
02856 /*0x05850*/     u64     tpa_error_alarm;
02857 /*0x05858*/     u64     tpa_global_cfg;
02858 #define VXGE_HW_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N        vxge_mBIT(7)
02859 #define VXGE_HW_TPA_GLOBAL_CFG_ECC_ENABLE_N     vxge_mBIT(35)
02860         u8      unused05868[0x05870-0x05860];
02861 
02862 /*0x05870*/     u64     ptm_ecc_cfg;
02863 #define VXGE_HW_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N   vxge_mBIT(3)
02864 /*0x05878*/     u64     ptm_phase_cfg;
02865 #define VXGE_HW_PTM_PHASE_CFG_FRMM_WR_PHASE_EN  vxge_mBIT(3)
02866 #define VXGE_HW_PTM_PHASE_CFG_FRMM_RD_PHASE_EN  vxge_mBIT(7)
02867         u8      unused05898[0x05898-0x05880];
02868 
02869 /*0x05898*/     u64     dbg_stats_tpa_tx_path;
02870 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) \
02871                                                         vxge_vBIT(val, 32, 32)
02872         u8      unused05900[0x05900-0x058a0];
02873 
02874 /*0x05900*/     u64     tmac_int_status;
02875 #define VXGE_HW_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT     vxge_mBIT(3)
02876 #define VXGE_HW_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT     vxge_mBIT(7)
02877 /*0x05908*/     u64     tmac_int_mask;
02878 /*0x05910*/     u64     txmac_gen_err_reg;
02879 #define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP  vxge_mBIT(3)
02880 #define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT vxge_mBIT(7)
02881 /*0x05918*/     u64     txmac_gen_err_mask;
02882 /*0x05920*/     u64     txmac_gen_err_alarm;
02883 /*0x05928*/     u64     txmac_ecc_err_reg;
02884 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR     vxge_mBIT(3)
02885 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR     vxge_mBIT(7)
02886 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR    vxge_mBIT(11)
02887 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR    vxge_mBIT(15)
02888 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR    vxge_mBIT(19)
02889 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR    vxge_mBIT(23)
02890 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR       vxge_mBIT(27)
02891 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR       vxge_mBIT(31)
02892 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR       vxge_mBIT(35)
02893 #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR   vxge_mBIT(39)
02894 /*0x05930*/     u64     txmac_ecc_err_mask;
02895 /*0x05938*/     u64     txmac_ecc_err_alarm;
02896         u8      unused05978[0x05978-0x05940];
02897 
02898 /*0x05978*/     u64     dbg_stat_tx_any_frms;
02899 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vxge_vBIT(val, 0, 8)
02900 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vxge_vBIT(val, 8, 8)
02901 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) \
02902                                                         vxge_vBIT(val, 16, 8)
02903         u8      unused059a0[0x059a0-0x05980];
02904 
02905 /*0x059a0*/     u64     txmac_link_util_port[3];
02906 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) \
02907                                                         vxge_vBIT(val, 1, 7)
02908 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4)
02909 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) \
02910                                                         vxge_vBIT(val, 12, 4)
02911 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4)
02912 #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR     vxge_mBIT(23)
02913 /*0x059b8*/     u64     txmac_cfg0_port[3];
02914 #define VXGE_HW_TXMAC_CFG0_PORT_TMAC_EN vxge_mBIT(3)
02915 #define VXGE_HW_TXMAC_CFG0_PORT_APPEND_PAD      vxge_mBIT(7)
02916 #define VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE(val) vxge_vBIT(val, 8, 8)
02917 /*0x059d0*/     u64     txmac_cfg1_port[3];
02918 #define VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG(val) vxge_vBIT(val, 40, 8)
02919 /*0x059e8*/     u64     txmac_status_port[3];
02920 #define VXGE_HW_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT      vxge_mBIT(3)
02921         u8      unused05a20[0x05a20-0x05a00];
02922 
02923 /*0x05a20*/     u64     lag_distrib_dest;
02924 #define VXGE_HW_LAG_DISTRIB_DEST_MAP_VPATH(n)   vxge_mBIT(n)
02925 /*0x05a28*/     u64     lag_marker_cfg;
02926 #define VXGE_HW_LAG_MARKER_CFG_GEN_RCVR_EN      vxge_mBIT(3)
02927 #define VXGE_HW_LAG_MARKER_CFG_RESP_EN  vxge_mBIT(7)
02928 #define VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT(val) vxge_vBIT(val, 16, 16)
02929 #define VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val) \
02930                                                         vxge_vBIT(val, 32, 16)
02931 #define VXGE_HW_LAG_MARKER_CFG_THROTTLE_MRKR_RESP       vxge_mBIT(51)
02932 /*0x05a30*/     u64     lag_tx_cfg;
02933 #define VXGE_HW_LAG_TX_CFG_INCR_TX_AGGR_STATS   vxge_mBIT(3)
02934 #define VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vxge_vBIT(val, 6, 2)
02935 #define VXGE_HW_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL        vxge_mBIT(11)
02936 #define VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY(val) vxge_vBIT(val, 16, 16)
02937 /*0x05a38*/     u64     lag_tx_status;
02938 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) \
02939                                                         vxge_vBIT(val, 0, 8)
02940 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val) \
02941                                                         vxge_vBIT(val, 8, 8)
02942 #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val) \
02943                                                         vxge_vBIT(val, 16, 8)
02944         u8      unused05d48[0x05d48-0x05a40];
02945 
02946 /*0x05d48*/     u64     srpcim_to_mrpcim_vplane_rmsg[17];
02947 #define \
02948 VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG(val)\
02949  vxge_vBIT(val, 0, 64)
02950                 u8      unused06420[0x06420-0x05dd0];
02951 
02952 /*0x06420*/     u64     mrpcim_to_srpcim_vplane_wmsg[17];
02953 #define VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG(val) \
02954                                                         vxge_vBIT(val, 0, 64)
02955 /*0x064a8*/     u64     mrpcim_to_srpcim_vplane_wmsg_trig[17];
02956 
02957 /*0x06530*/     u64     debug_stats0;
02958 #define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val) vxge_vBIT(val, 0, 32)
02959 #define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val) vxge_vBIT(val, 32, 32)
02960 /*0x06538*/     u64     debug_stats1;
02961 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val) vxge_vBIT(val, 0, 32)
02962 #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val) vxge_vBIT(val, 32, 32)
02963 /*0x06540*/     u64     debug_stats2;
02964 #define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val) vxge_vBIT(val, 0, 32)
02965 /*0x06548*/     u64     debug_stats3_vplane[17];
02966 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH(val) vxge_vBIT(val, 0, 16)
02967 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vxge_vBIT(val, 16, 16)
02968 #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vxge_vBIT(val, 32, 16)
02969 /*0x065d0*/     u64     debug_stats4_vplane[17];
02970 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD(val) vxge_vBIT(val, 0, 16)
02971 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vxge_vBIT(val, 16, 16)
02972 #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vxge_vBIT(val, 32, 16)
02973 
02974         u8      unused07000[0x07000-0x06658];
02975 
02976 /*0x07000*/     u64     mrpcim_general_int_status;
02977 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PIC_INT       vxge_mBIT(0)
02978 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCI_INT       vxge_mBIT(1)
02979 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT     vxge_mBIT(2)
02980 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT     vxge_mBIT(3)
02981 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT    vxge_mBIT(4)
02982 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT     vxge_mBIT(5)
02983 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT     vxge_mBIT(6)
02984 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT     vxge_mBIT(7)
02985 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT   vxge_mBIT(8)
02986 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT   vxge_mBIT(9)
02987 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT     vxge_mBIT(10)
02988 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT     vxge_mBIT(11)
02989 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT     vxge_mBIT(12)
02990 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_XMAC_INT      vxge_mBIT(13)
02991 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT     vxge_mBIT(14)
02992 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TMAC_INT      vxge_mBIT(15)
02993 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT    vxge_mBIT(16)
02994 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_FBMC_INT      vxge_mBIT(17)
02995 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT    vxge_mBIT(18)
02996 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TPA_INT       vxge_mBIT(19)
02997 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT    vxge_mBIT(20)
02998 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_ONE_INT       vxge_mBIT(21)
02999 #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_MSG_INT       vxge_mBIT(22)
03000 /*0x07008*/     u64     mrpcim_general_int_mask;
03001 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PIC_INT vxge_mBIT(0)
03002 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCI_INT vxge_mBIT(1)
03003 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RTDMA_INT       vxge_mBIT(2)
03004 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_WRDMA_INT       vxge_mBIT(3)
03005 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT      vxge_mBIT(4)
03006 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG1_INT       vxge_mBIT(5)
03007 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG2_INT       vxge_mBIT(6)
03008 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG3_INT       vxge_mBIT(7)
03009 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT     vxge_mBIT(8)
03010 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT     vxge_mBIT(9)
03011 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG1_INT       vxge_mBIT(10)
03012 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG2_INT       vxge_mBIT(11)
03013 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG3_INT       vxge_mBIT(12)
03014 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_XMAC_INT        vxge_mBIT(13)
03015 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RXMAC_INT       vxge_mBIT(14)
03016 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TMAC_INT        vxge_mBIT(15)
03017 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT      vxge_mBIT(16)
03018 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_FBMC_INT        vxge_mBIT(17)
03019 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT      vxge_mBIT(18)
03020 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TPA_INT vxge_mBIT(19)
03021 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_DRBELL_INT      vxge_mBIT(20)
03022 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_ONE_INT vxge_mBIT(21)
03023 #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_MSG_INT vxge_mBIT(22)
03024 /*0x07010*/     u64     mrpcim_ppif_int_status;
03025 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT       vxge_mBIT(3)
03026 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT       vxge_mBIT(7)
03027 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT       vxge_mBIT(11)
03028 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT vxge_mBIT(15)
03029 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT     vxge_mBIT(19)
03030 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT       vxge_mBIT(27)
03031 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE0_CRD_INT_VPLANE0_INT\
03032                                                         vxge_mBIT(31)
03033 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE1_CRD_INT_VPLANE1_INT\
03034                                                         vxge_mBIT(32)
03035 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE2_CRD_INT_VPLANE2_INT\
03036                                                         vxge_mBIT(33)
03037 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE3_CRD_INT_VPLANE3_INT\
03038                                                         vxge_mBIT(34)
03039 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE4_CRD_INT_VPLANE4_INT\
03040                                                         vxge_mBIT(35)
03041 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE5_CRD_INT_VPLANE5_INT\
03042                                                         vxge_mBIT(36)
03043 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE6_CRD_INT_VPLANE6_INT\
03044                                                         vxge_mBIT(37)
03045 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE7_CRD_INT_VPLANE7_INT\
03046                                                         vxge_mBIT(38)
03047 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE8_CRD_INT_VPLANE8_INT\
03048                                                         vxge_mBIT(39)
03049 #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE9_CRD_INT_VPLANE9_INT\
03050                                                         vxge_mBIT(40)
03051 #define \
03052 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE10_CRD_INT_VPLANE10_INT \
03053                                                         vxge_mBIT(41)
03054 #define \
03055 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE11_CRD_INT_VPLANE11_INT \
03056                                                         vxge_mBIT(42)
03057 #define \
03058 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE12_CRD_INT_VPLANE12_INT \
03059                                                         vxge_mBIT(43)
03060 #define \
03061 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE13_CRD_INT_VPLANE13_INT \
03062                                                         vxge_mBIT(44)
03063 #define \
03064 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE14_CRD_INT_VPLANE14_INT \
03065                                                         vxge_mBIT(45)
03066 #define \
03067 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE15_CRD_INT_VPLANE15_INT \
03068                                                         vxge_mBIT(46)
03069 #define \
03070 VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE16_CRD_INT_VPLANE16_INT \
03071                                                         vxge_mBIT(47)
03072 #define \
03073 VXGE_HW_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_VPATH_TO_MRPCIM_ALARM_INT \
03074                                                         vxge_mBIT(55)
03075 /*0x07018*/     u64     mrpcim_ppif_int_mask;
03076         u8      unused07028[0x07028-0x07020];
03077 
03078 /*0x07028*/     u64     ini_errors_reg;
03079 #define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG      vxge_mBIT(3)
03080 #define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT vxge_mBIT(7)
03081 #define VXGE_HW_INI_ERRORS_REG_DCPL_FSM_ERR     vxge_mBIT(11)
03082 #define VXGE_HW_INI_ERRORS_REG_DCPL_POISON      vxge_mBIT(12)
03083 #define VXGE_HW_INI_ERRORS_REG_DCPL_UNSUPPORTED vxge_mBIT(15)
03084 #define VXGE_HW_INI_ERRORS_REG_DCPL_ABORT       vxge_mBIT(19)
03085 #define VXGE_HW_INI_ERRORS_REG_INI_TLP_ABORT    vxge_mBIT(23)
03086 #define VXGE_HW_INI_ERRORS_REG_INI_DLLP_ABORT   vxge_mBIT(27)
03087 #define VXGE_HW_INI_ERRORS_REG_INI_ECRC_ERR     vxge_mBIT(31)
03088 #define VXGE_HW_INI_ERRORS_REG_INI_BUF_DB_ERR   vxge_mBIT(35)
03089 #define VXGE_HW_INI_ERRORS_REG_INI_BUF_SG_ERR   vxge_mBIT(39)
03090 #define VXGE_HW_INI_ERRORS_REG_INI_DATA_OVERFLOW        vxge_mBIT(43)
03091 #define VXGE_HW_INI_ERRORS_REG_INI_HDR_OVERFLOW vxge_mBIT(47)
03092 #define VXGE_HW_INI_ERRORS_REG_INI_MRD_SYS_DROP vxge_mBIT(51)
03093 #define VXGE_HW_INI_ERRORS_REG_INI_MWR_SYS_DROP vxge_mBIT(55)
03094 #define VXGE_HW_INI_ERRORS_REG_INI_MRD_CLIENT_DROP      vxge_mBIT(59)
03095 #define VXGE_HW_INI_ERRORS_REG_INI_MWR_CLIENT_DROP      vxge_mBIT(63)
03096 /*0x07030*/     u64     ini_errors_mask;
03097 /*0x07038*/     u64     ini_errors_alarm;
03098 /*0x07040*/     u64     dma_errors_reg;
03099 #define VXGE_HW_DMA_ERRORS_REG_RDARB_FSM_ERR    vxge_mBIT(3)
03100 #define VXGE_HW_DMA_ERRORS_REG_WRARB_FSM_ERR    vxge_mBIT(7)
03101 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW        vxge_mBIT(8)
03102 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW       vxge_mBIT(9)
03103 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW       vxge_mBIT(10)
03104 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW      vxge_mBIT(11)
03105 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW  vxge_mBIT(12)
03106 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW vxge_mBIT(13)
03107 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW vxge_mBIT(14)
03108 #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW        vxge_mBIT(15)
03109 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW        vxge_mBIT(16)
03110 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW       vxge_mBIT(17)
03111 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW       vxge_mBIT(18)
03112 #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW      vxge_mBIT(19)
03113 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW        vxge_mBIT(20)
03114 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW       vxge_mBIT(21)
03115 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW       vxge_mBIT(22)
03116 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW      vxge_mBIT(23)
03117 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW        vxge_mBIT(24)
03118 #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW       vxge_mBIT(25)
03119 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW        vxge_mBIT(28)
03120 #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW       vxge_mBIT(29)
03121 #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_FSM_ERR   vxge_mBIT(32)
03122 #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR    vxge_mBIT(33)
03123 #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR    vxge_mBIT(34)
03124 /*0x07048*/     u64     dma_errors_mask;
03125 /*0x07050*/     u64     dma_errors_alarm;
03126 /*0x07058*/     u64     tgt_errors_reg;
03127 #define VXGE_HW_TGT_ERRORS_REG_TGT_VENDOR_MSG   vxge_mBIT(0)
03128 #define VXGE_HW_TGT_ERRORS_REG_TGT_MSG_UNLOCK   vxge_mBIT(1)
03129 #define VXGE_HW_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE       vxge_mBIT(2)
03130 #define VXGE_HW_TGT_ERRORS_REG_TGT_BOOT_WRITE   vxge_mBIT(3)
03131 #define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE vxge_mBIT(4)
03132 #define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE       vxge_mBIT(5)
03133 #define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_READ    vxge_mBIT(6)
03134 #define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_READ    vxge_mBIT(7)
03135 #define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE        vxge_mBIT(8)
03136 #define VXGE_HW_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE    vxge_mBIT(9)
03137 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON    vxge_mBIT(10)
03138 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON    vxge_mBIT(11)
03139 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON     vxge_mBIT(12)
03140 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON    vxge_mBIT(13)
03141 #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON   vxge_mBIT(14)
03142 #define VXGE_HW_TGT_ERRORS_REG_TGT_NOT_MEM_TLP  vxge_mBIT(15)
03143 #define VXGE_HW_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP      vxge_mBIT(16)
03144 #define VXGE_HW_TGT_ERRORS_REG_TGT_REQ_FSM_ERR  vxge_mBIT(17)
03145 #define VXGE_HW_TGT_ERRORS_REG_TGT_CPL_FSM_ERR  vxge_mBIT(18)
03146 #define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR        vxge_mBIT(19)
03147 #define VXGE_HW_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR        vxge_mBIT(20)
03148 #define VXGE_HW_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR        vxge_mBIT(21)
03149 /*0x07060*/     u64     tgt_errors_mask;
03150 /*0x07068*/     u64     tgt_errors_alarm;
03151 /*0x07070*/     u64     config_errors_reg;
03152 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND vxge_mBIT(3)
03153 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND        vxge_mBIT(7)
03154 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT        vxge_mBIT(11)
03155 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE       vxge_mBIT(15)
03156 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR      vxge_mBIT(19)
03157 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_REQ_COLLISION     vxge_mBIT(23)
03158 #define VXGE_HW_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR       vxge_mBIT(27)
03159 #define VXGE_HW_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT      vxge_mBIT(31)
03160 #define VXGE_HW_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT       vxge_mBIT(35)
03161 #define VXGE_HW_CONFIG_ERRORS_REG_CFGM_FSM_ERR  vxge_mBIT(39)
03162 #define VXGE_HW_CONFIG_ERRORS_REG_RIC_FSM_ERR   vxge_mBIT(43)
03163 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS   vxge_mBIT(47)
03164 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TIMEOUT  vxge_mBIT(51)
03165 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_FSM_ERR  vxge_mBIT(55)
03166 #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR       vxge_mBIT(59)
03167 #define VXGE_HW_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT    vxge_mBIT(63)
03168 /*0x07078*/     u64     config_errors_mask;
03169 /*0x07080*/     u64     config_errors_alarm;
03170         u8      unused07090[0x07090-0x07088];
03171 
03172 /*0x07090*/     u64     crdt_errors_reg;
03173 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR       vxge_mBIT(11)
03174 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL \
03175                                                         vxge_mBIT(15)
03176 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL  vxge_mBIT(19)
03177 #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL \
03178                                                         vxge_mBIT(23)
03179 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR       vxge_mBIT(35)
03180 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL  vxge_mBIT(39)
03181 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL  vxge_mBIT(43)
03182 #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL \
03183                                                         vxge_mBIT(47)
03184 /*0x07098*/     u64     crdt_errors_mask;
03185 /*0x070a0*/     u64     crdt_errors_alarm;
03186         u8      unused070b0[0x070b0-0x070a8];
03187 
03188 /*0x070b0*/     u64     mrpcim_general_errors_reg;
03189 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR        vxge_mBIT(3)
03190 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR  vxge_mBIT(7)
03191 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR  vxge_mBIT(11)
03192 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR       vxge_mBIT(15)
03193 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR      vxge_mBIT(19)
03194 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR  vxge_mBIT(23)
03195 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR       vxge_mBIT(27)
03196 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR    vxge_mBIT(31)
03197 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET  vxge_mBIT(35)
03198 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR   vxge_mBIT(39)
03199 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW   vxge_mBIT(43)
03200 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_DURING_SW_RESET \
03201                                                         vxge_mBIT(47)
03202 #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR vxge_mBIT(51)
03203 /*0x070b8*/     u64     mrpcim_general_errors_mask;
03204 /*0x070c0*/     u64     mrpcim_general_errors_alarm;
03205         u8      unused070d0[0x070d0-0x070c8];
03206 
03207 /*0x070d0*/     u64     pll_errors_reg;
03208 #define VXGE_HW_PLL_ERRORS_REG_CORE_CMG_PLL_OOL vxge_mBIT(3)
03209 #define VXGE_HW_PLL_ERRORS_REG_CORE_FB_PLL_OOL  vxge_mBIT(7)
03210 #define VXGE_HW_PLL_ERRORS_REG_CORE_X_PLL_OOL   vxge_mBIT(11)
03211 /*0x070d8*/     u64     pll_errors_mask;
03212 /*0x070e0*/     u64     pll_errors_alarm;
03213 /*0x070e8*/     u64     srpcim_to_mrpcim_alarm_reg;
03214 #define VXGE_HW_SRPCIM_TO_MRPCIM_ALARM_REG_PPIF_SRPCIM_TO_MRPCIM_ALARM(val) \
03215                                                         vxge_vBIT(val, 0, 17)
03216 /*0x070f0*/     u64     srpcim_to_mrpcim_alarm_mask;
03217 /*0x070f8*/     u64     srpcim_to_mrpcim_alarm_alarm;
03218 /*0x07100*/     u64     vpath_to_mrpcim_alarm_reg;
03219 #define VXGE_HW_VPATH_TO_MRPCIM_ALARM_REG_PPIF_VPATH_TO_MRPCIM_ALARM(val) \
03220                                                         vxge_vBIT(val, 0, 17)
03221 /*0x07108*/     u64     vpath_to_mrpcim_alarm_mask;
03222 /*0x07110*/     u64     vpath_to_mrpcim_alarm_alarm;
03223         u8      unused07128[0x07128-0x07118];
03224 
03225 /*0x07128*/     u64     crdt_errors_vplane_reg[17];
03226 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR \
03227                                                         vxge_mBIT(3)
03228 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR \
03229                                                         vxge_mBIT(7)
03230 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR \
03231                                                         vxge_mBIT(11)
03232 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR \
03233                                                         vxge_mBIT(15)
03234 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR \
03235                                                         vxge_mBIT(19)
03236 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR \
03237                                                         vxge_mBIT(23)
03238 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR \
03239                                                         vxge_mBIT(27)
03240 #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR \
03241                                                         vxge_mBIT(31)
03242 /*0x07130*/     u64     crdt_errors_vplane_mask[17];
03243 /*0x07138*/     u64     crdt_errors_vplane_alarm[17];
03244         u8      unused072f0[0x072f0-0x072c0];
03245 
03246 /*0x072f0*/     u64     mrpcim_rst_in_prog;
03247 #define VXGE_HW_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG   vxge_mBIT(7)
03248 /*0x072f8*/     u64     mrpcim_reg_modified;
03249 #define VXGE_HW_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED vxge_mBIT(7)
03250 
03251         u8      unused07378[0x07378-0x07300];
03252 
03253 /*0x07378*/     u64     write_arb_pending;
03254 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_WRDMA   vxge_mBIT(3)
03255 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_RTDMA   vxge_mBIT(7)
03256 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_MSG     vxge_mBIT(11)
03257 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_STATSB  vxge_mBIT(15)
03258 #define VXGE_HW_WRITE_ARB_PENDING_WRARB_INTCTL  vxge_mBIT(19)
03259 /*0x07380*/     u64     read_arb_pending;
03260 #define VXGE_HW_READ_ARB_PENDING_RDARB_WRDMA    vxge_mBIT(3)
03261 #define VXGE_HW_READ_ARB_PENDING_RDARB_RTDMA    vxge_mBIT(7)
03262 #define VXGE_HW_READ_ARB_PENDING_RDARB_DBLGEN   vxge_mBIT(11)
03263 /*0x07388*/     u64     dmaif_dmadbl_pending;
03264 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR     vxge_mBIT(0)
03265 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD     vxge_mBIT(1)
03266 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR     vxge_mBIT(2)
03267 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD     vxge_mBIT(3)
03268 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR       vxge_mBIT(4)
03269 #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR     vxge_mBIT(5)
03270 #define VXGE_HW_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) \
03271                                                         vxge_vBIT(val, 13, 51)
03272 /*0x07390*/     u64     wrcrdtarb_status0_vplane[17];
03273 #define VXGE_HW_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val) \
03274                                                         vxge_vBIT(val, 0, 8)
03275 /*0x07418*/     u64     wrcrdtarb_status1_vplane[17];
03276 #define VXGE_HW_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val) \
03277                                                         vxge_vBIT(val, 4, 12)
03278         u8      unused07500[0x07500-0x074a0];
03279 
03280 /*0x07500*/     u64     mrpcim_general_cfg1;
03281 #define VXGE_HW_MRPCIM_GENERAL_CFG1_CLEAR_SERR  vxge_mBIT(7)
03282 /*0x07508*/     u64     mrpcim_general_cfg2;
03283 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD        vxge_mBIT(3)
03284 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD        vxge_mBIT(7)
03285 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD       vxge_mBIT(11)
03286 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR  vxge_mBIT(15)
03287 #define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD  vxge_mBIT(19)
03288 #define VXGE_HW_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX   vxge_mBIT(23)
03289 #define VXGE_HW_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB      vxge_mBIT(27)
03290 #define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR        vxge_mBIT(31)
03291 #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE vxge_mBIT(43)
03292 #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val) \
03293                                                         vxge_vBIT(val, 47, 5)
03294 #define VXGE_HW_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR   vxge_mBIT(55)
03295 #define VXGE_HW_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA  vxge_mBIT(59)
03296 #define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS        vxge_mBIT(63)
03297 /*0x07510*/     u64     mrpcim_general_cfg3;
03298 #define VXGE_HW_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN     vxge_mBIT(0)
03299 #define VXGE_HW_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN     vxge_mBIT(3)
03300 #define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN      vxge_mBIT(7)
03301 #define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN       vxge_mBIT(11)
03302 #define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN      vxge_mBIT(15)
03303 #define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN       vxge_mBIT(19)
03304 #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vxge_vBIT(val, 20, 16)
03305 #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) \
03306                                                         vxge_vBIT(val, 36, 16)
03307 #define VXGE_HW_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN     vxge_mBIT(55)
03308 #define VXGE_HW_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vxge_vBIT(val, 56, 2)
03309 #define VXGE_HW_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N    vxge_mBIT(59)
03310 #define VXGE_HW_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN  vxge_mBIT(63)
03311 /*0x07518*/     u64     mrpcim_stats_start_host_addr;
03312 #define VXGE_HW_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\
03313                                                         vxge_vBIT(val, 0, 57)
03314 
03315         u8      unused07950[0x07950-0x07520];
03316 
03317 /*0x07950*/     u64     rdcrdtarb_cfg0;
03318 #define VXGE_HW_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) \
03319                                                 vxge_vBIT(val, 18, 6)
03320 #define VXGE_HW_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) \
03321                                                 vxge_vBIT(val, 26, 6)
03322 #define VXGE_HW_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) \
03323                                                 vxge_vBIT(val, 34, 6)
03324 #define VXGE_HW_RDCRDTARB_CFG0_WAIT_CNT(val) vxge_vBIT(val, 48, 4)
03325 #define VXGE_HW_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vxge_vBIT(val, 54, 6)
03326 #define VXGE_HW_RDCRDTARB_CFG0_EN_XON   vxge_mBIT(63)
03327         u8      unused07be8[0x07be8-0x07958];
03328 
03329 /*0x07be8*/     u64     bf_sw_reset;
03330 #define VXGE_HW_BF_SW_RESET_BF_SW_RESET(val) vxge_vBIT(val, 0, 8)
03331 /*0x07bf0*/     u64     sw_reset_status;
03332 #define VXGE_HW_SW_RESET_STATUS_RESET_CMPLT     vxge_mBIT(7)
03333 #define VXGE_HW_SW_RESET_STATUS_INIT_CMPLT      vxge_mBIT(15)
03334         u8      unused07c20[0x07c20-0x07bf8];
03335 
03336 /* 0x07c20 */   u64     sw_reset_cfg1;
03337 #define VXGE_HW_SW_RESET_CFG1_TYPE      vxge_mBIT(0)
03338 #define VXGE_HW_SW_RESET_CFG1_WAIT_TIME_FOR_FLUSH_PCI(val) \
03339                                                 vxge_vBIT(val, 7, 25)
03340 #define VXGE_HW_SW_RESET_CFG1_SOPR_ASSERT_TIME(val)     vxge_vBIT(val, 32, 4)
03341 #define VXGE_HW_SW_RESET_CFG1_WAIT_TIME_AFTER_RESET(val) \
03342                                                 vxge_vBIT(val, 38, 25)
03343         u8      unused07d30[0x07d30-0x07c28];
03344 
03345 /*0x07d30*/     u64     mrpcim_debug_stats0;
03346 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vxge_vBIT(val, 0, 32)
03347 #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vxge_vBIT(val, 32, 32)
03348 /*0x07d38*/     u64     mrpcim_debug_stats1_vplane[17];
03349 #define VXGE_HW_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val) \
03350                                                         vxge_vBIT(val, 32, 32)
03351 /*0x07dc0*/     u64     mrpcim_debug_stats2_vplane[17];
03352 #define VXGE_HW_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val) \
03353                                                         vxge_vBIT(val, 32, 32)
03354 /*0x07e48*/     u64     mrpcim_debug_stats3_vplane[17];
03355 #define VXGE_HW_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val) \
03356                                                         vxge_vBIT(val, 32, 32)
03357 /*0x07ed0*/     u64     mrpcim_debug_stats4;
03358 #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vxge_vBIT(val, 0, 32)
03359 #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) \
03360                                                         vxge_vBIT(val, 32, 32)
03361 /*0x07ed8*/     u64     genstats_count01;
03362 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vxge_vBIT(val, 0, 32)
03363 #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vxge_vBIT(val, 32, 32)
03364 /*0x07ee0*/     u64     genstats_count23;
03365 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vxge_vBIT(val, 0, 32)
03366 #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vxge_vBIT(val, 32, 32)
03367 /*0x07ee8*/     u64     genstats_count4;
03368 #define VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vxge_vBIT(val, 32, 32)
03369 /*0x07ef0*/     u64     genstats_count5;
03370 #define VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vxge_vBIT(val, 32, 32)
03371 
03372         u8      unused07f08[0x07f08-0x07ef8];
03373 
03374 /*0x07f08*/     u64     genstats_cfg[6];
03375 #define VXGE_HW_GENSTATS_CFG_DTYPE_SEL(val) vxge_vBIT(val, 3, 5)
03376 #define VXGE_HW_GENSTATS_CFG_CLIENT_NO_SEL(val) vxge_vBIT(val, 9, 3)
03377 #define VXGE_HW_GENSTATS_CFG_WR_RD_CPL_SEL(val) vxge_vBIT(val, 14, 2)
03378 #define VXGE_HW_GENSTATS_CFG_VPATH_SEL(val) vxge_vBIT(val, 31, 17)
03379 /*0x07f38*/     u64     genstat_64bit_cfg;
03380 #define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0      vxge_mBIT(3)
03381 #define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2      vxge_mBIT(7)
03382         u8      unused08000[0x08000-0x07f40];
03383 /*0x08000*/     u64     gcmg3_int_status;
03384 #define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT    vxge_mBIT(0)
03385 #define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT    vxge_mBIT(1)
03386 #define VXGE_HW_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT    vxge_mBIT(2)
03387 #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT     vxge_mBIT(3)
03388 #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT    vxge_mBIT(4)
03389 #define VXGE_HW_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT  vxge_mBIT(5)
03390 #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT    vxge_mBIT(6)
03391 /*0x08008*/     u64     gcmg3_int_mask;
03392         u8      unused09000[0x09000-0x8010];
03393 
03394 /*0x09000*/     u64     g3ifcmd_fb_int_status;
03395 #define VXGE_HW_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT      vxge_mBIT(0)
03396 /*0x09008*/     u64     g3ifcmd_fb_int_mask;
03397 /*0x09010*/     u64     g3ifcmd_fb_err_reg;
03398 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK     vxge_mBIT(6)
03399 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR  vxge_mBIT(7)
03400 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \
03401                                                 vxge_vBIT(val, 24, 8)
03402 #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT     vxge_mBIT(55)
03403 /*0x09018*/     u64     g3ifcmd_fb_err_mask;
03404 /*0x09020*/     u64     g3ifcmd_fb_err_alarm;
03405 
03406         u8      unused09400[0x09400-0x09028];
03407 
03408 /*0x09400*/     u64     g3ifcmd_cmu_int_status;
03409 #define VXGE_HW_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT     vxge_mBIT(0)
03410 /*0x09408*/     u64     g3ifcmd_cmu_int_mask;
03411 /*0x09410*/     u64     g3ifcmd_cmu_err_reg;
03412 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK    vxge_mBIT(6)
03413 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR vxge_mBIT(7)
03414 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \
03415                                                         vxge_vBIT(val, 24, 8)
03416 #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT    vxge_mBIT(55)
03417 /*0x09418*/     u64     g3ifcmd_cmu_err_mask;
03418 /*0x09420*/     u64     g3ifcmd_cmu_err_alarm;
03419 
03420         u8      unused09800[0x09800-0x09428];
03421 
03422 /*0x09800*/     u64     g3ifcmd_cml_int_status;
03423 #define VXGE_HW_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT     vxge_mBIT(0)
03424 /*0x09808*/     u64     g3ifcmd_cml_int_mask;
03425 /*0x09810*/     u64     g3ifcmd_cml_err_reg;
03426 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK    vxge_mBIT(6)
03427 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR vxge_mBIT(7)
03428 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \
03429                                                 vxge_vBIT(val, 24, 8)
03430 #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT    vxge_mBIT(55)
03431 /*0x09818*/     u64     g3ifcmd_cml_err_mask;
03432 /*0x09820*/     u64     g3ifcmd_cml_err_alarm;
03433         u8      unused09b00[0x09b00-0x09828];
03434 
03435 /*0x09b00*/     u64     vpath_to_vplane_map[17];
03436 #define VXGE_HW_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) \
03437                                                         vxge_vBIT(val, 3, 5)
03438         u8      unused09c30[0x09c30-0x09b88];
03439 
03440 /*0x09c30*/     u64     xgxs_cfg_port[2];
03441 #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vxge_vBIT(val, 16, 4)
03442 #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vxge_vBIT(val, 20, 4)
03443 #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_0        vxge_mBIT(27)
03444 #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_1(val) vxge_vBIT(val, 29, 3)
03445 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vxge_vBIT(val, 32, 4)
03446 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vxge_vBIT(val, 36, 4)
03447 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vxge_vBIT(val, 40, 4)
03448 #define VXGE_HW_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vxge_vBIT(val, 44, 4)
03449 /*0x09c40*/     u64     xgxs_rxber_cfg_port[2];
03450 #define VXGE_HW_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vxge_vBIT(val, 0, 4)
03451 #define VXGE_HW_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) \
03452                                                         vxge_vBIT(val, 16, 48)
03453 /*0x09c50*/     u64     xgxs_rxber_status_port[2];
03454 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val)  \
03455                                                         vxge_vBIT(val, 0, 16)
03456 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val)  \
03457                                                         vxge_vBIT(val, 16, 16)
03458 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val)  \
03459                                                         vxge_vBIT(val, 32, 16)
03460 #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val)  \
03461                                                         vxge_vBIT(val, 48, 16)
03462 /*0x09c60*/     u64     xgxs_status_port[2];
03463 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vxge_vBIT(val, 0, 4)
03464 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vxge_vBIT(val, 4, 4)
03465 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11)
03466 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) \
03467                                                         vxge_vBIT(val, 12, 4)
03468 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vxge_vBIT(val, 16, 4)
03469 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR        vxge_mBIT(23)
03470 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vxge_vBIT(val, 24, 8)
03471 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) \
03472                                                         vxge_vBIT(val, 32, 4)
03473 #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) \
03474                                                         vxge_vBIT(val, 36, 4)
03475 /*0x09c70*/     u64     xgxs_pma_reset_port[2];
03476 #define VXGE_HW_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vxge_vBIT(val, 0, 8)
03477         u8      unused09c90[0x09c90-0x09c80];
03478 
03479 /*0x09c90*/     u64     xgxs_static_cfg_port[2];
03480 #define VXGE_HW_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES     vxge_mBIT(3)
03481         u8      unused09d40[0x09d40-0x09ca0];
03482 
03483 /*0x09d40*/     u64     xgxs_info_port[2];
03484 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0(val) vxge_vBIT(val, 0, 32)
03485 #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1(val) vxge_vBIT(val, 32, 32)
03486 /*0x09d50*/     u64     ratemgmt_cfg_port[2];
03487 #define VXGE_HW_RATEMGMT_CFG_PORT_MODE(val) vxge_vBIT(val, 2, 2)
03488 #define VXGE_HW_RATEMGMT_CFG_PORT_RATE  vxge_mBIT(7)
03489 #define VXGE_HW_RATEMGMT_CFG_PORT_FIXED_USE_FSM vxge_mBIT(11)
03490 #define VXGE_HW_RATEMGMT_CFG_PORT_ANTP_USE_FSM  vxge_mBIT(15)
03491 #define VXGE_HW_RATEMGMT_CFG_PORT_ANBE_USE_FSM  vxge_mBIT(19)
03492 /*0x09d60*/     u64     ratemgmt_status_port[2];
03493 #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE  vxge_mBIT(3)
03494 #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_RATE      vxge_mBIT(7)
03495 #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY   vxge_mBIT(11)
03496         u8      unused09d80[0x09d80-0x09d70];
03497 
03498 /*0x09d80*/     u64     ratemgmt_fixed_cfg_port[2];
03499 #define VXGE_HW_RATEMGMT_FIXED_CFG_PORT_RESTART vxge_mBIT(7)
03500 /*0x09d90*/     u64     ratemgmt_antp_cfg_port[2];
03501 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_RESTART  vxge_mBIT(7)
03502 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY     vxge_mBIT(11)
03503 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL      vxge_mBIT(15)
03504 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val) \
03505                                                         vxge_vBIT(val, 16, 4)
03506 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESPONSE(val) \
03507                                                         vxge_vBIT(val, 20, 4)
03508 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESPONSE(val) \
03509                                                         vxge_vBIT(val, 24, 4)
03510 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G    vxge_mBIT(31)
03511 #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G     vxge_mBIT(35)
03512 /*0x09da0*/     u64     ratemgmt_anbe_cfg_port[2];
03513 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_RESTART  vxge_mBIT(7)
03514 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE \
03515                                                                 vxge_mBIT(11)
03516 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE \
03517                                                                 vxge_mBIT(15)
03518 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vxge_vBIT(val, 16, 4)
03519 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vxge_vBIT(val, 20, 4)
03520 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vxge_vBIT(val, 24, 4)
03521 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4        vxge_mBIT(31)
03522 #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX  vxge_mBIT(35)
03523 /*0x09db0*/     u64     anbe_cfg_port[2];
03524 #define VXGE_HW_ANBE_CFG_PORT_RESET_CFG_REGS(val) vxge_vBIT(val, 0, 8)
03525 #define VXGE_HW_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vxge_vBIT(val, 10, 2)
03526 #define VXGE_HW_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vxge_vBIT(val, 14, 2)
03527 /*0x09dc0*/     u64     anbe_mgr_ctrl_port[2];
03528 #define VXGE_HW_ANBE_MGR_CTRL_PORT_WE   vxge_mBIT(3)
03529 #define VXGE_HW_ANBE_MGR_CTRL_PORT_STROBE       vxge_mBIT(7)
03530 #define VXGE_HW_ANBE_MGR_CTRL_PORT_ADDR(val) vxge_vBIT(val, 15, 9)
03531 #define VXGE_HW_ANBE_MGR_CTRL_PORT_DATA(val) vxge_vBIT(val, 32, 32)
03532         u8      unused09de0[0x09de0-0x09dd0];
03533 
03534 /*0x09de0*/     u64     anbe_fw_mstr_port[2];
03535 #define VXGE_HW_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES        vxge_mBIT(3)
03536 #define VXGE_HW_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES   vxge_mBIT(7)
03537 /*0x09df0*/     u64     anbe_hwfsm_gen_status_port[2];
03538 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_PD \
03539                                                         vxge_mBIT(3)
03540 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_DME \
03541                                                         vxge_mBIT(7)
03542 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_PD \
03543                                                         vxge_mBIT(11)
03544 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_DME \
03545                                                         vxge_mBIT(15)
03546 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val)  \
03547                                                         vxge_vBIT(val, 18, 6)
03548 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_NEXT_PAGE_RECEIVED \
03549                                                         vxge_mBIT(27)
03550 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_BASE_PAGE_RECEIVED \
03551                                                         vxge_mBIT(35)
03552 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_AUTONEG_COMPLETE \
03553                                                         vxge_mBIT(39)
03554 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NP_BEFORE_BP \
03555                                                         vxge_mBIT(43)
03556 #define \
03557 VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_BP \
03558                                                         vxge_mBIT(47)
03559 #define \
03560 VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_NP \
03561 vxge_mBIT(51)
03562 #define \
03563 VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MODE_WHEN_AN_COMPLETE \
03564                                                         vxge_mBIT(55)
03565 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val) \
03566                                                         vxge_vBIT(val, 56, 4)
03567 #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val) \
03568                                                         vxge_vBIT(val, 60, 4)
03569 /*0x09e00*/     u64     anbe_hwfsm_bp_status_port[2];
03570 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE \
03571                                                         vxge_mBIT(32)
03572 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY \
03573                                                         vxge_mBIT(33)
03574 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE \
03575                                                         vxge_mBIT(40)
03576 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE \
03577                                                         vxge_mBIT(41)
03578 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE \
03579                                                         vxge_mBIT(42)
03580 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val)     \
03581                                                         vxge_vBIT(val, 43, 5)
03582 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP        vxge_mBIT(48)
03583 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK       vxge_mBIT(49)
03584 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT \
03585                                                         vxge_mBIT(50)
03586 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR   vxge_mBIT(51)
03587 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE     vxge_mBIT(53)
03588 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val) \
03589                                                         vxge_vBIT(val, 54, 5)
03590 #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \
03591                                                         vxge_vBIT(val, 59, 5)
03592 /*0x09e10*/     u64     anbe_hwfsm_np_status_port[2];
03593 #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val) \
03594                                                         vxge_vBIT(val, 16, 16)
03595 #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val) \
03596                                                         vxge_vBIT(val, 32, 32)
03597         u8      unused09e30[0x09e30-0x09e20];
03598 
03599 /*0x09e30*/     u64     antp_gen_cfg_port[2];
03600 /*0x09e40*/     u64     antp_hwfsm_gen_status_port[2];
03601 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G   vxge_mBIT(3)
03602 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G    vxge_mBIT(7)
03603 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val)  \
03604                                                         vxge_vBIT(val, 10, 6)
03605 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE \
03606                                                                 vxge_mBIT(23)
03607 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_LP_XNP \
03608                                                         vxge_mBIT(27)
03609 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP  vxge_mBIT(31)
03610 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MESSAGE_CODE \
03611                                                         vxge_mBIT(35)
03612 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD \
03613                                                         vxge_mBIT(43)
03614 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD   vxge_mBIT(47)
03615 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_INVALID_RATE \
03616                                                         vxge_mBIT(51)
03617 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE  vxge_mBIT(55)
03618 #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN \
03619                                                         vxge_mBIT(59)
03620 /*0x09e50*/     u64     antp_hwfsm_bp_status_port[2];
03621 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP        vxge_mBIT(0)
03622 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK       vxge_mBIT(1)
03623 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF        vxge_mBIT(2)
03624 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP       vxge_mBIT(3)
03625 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val) \
03626                                                         vxge_vBIT(val, 4, 7)
03627 #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \
03628                                                         vxge_vBIT(val, 11, 5)
03629 /*0x09e60*/     u64     antp_hwfsm_xnp_status_port[2];
03630 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP      vxge_mBIT(0)
03631 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK     vxge_mBIT(1)
03632 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP      vxge_mBIT(2)
03633 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2    vxge_mBIT(3)
03634 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE  vxge_mBIT(4)
03635 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val) \
03636                                                         vxge_vBIT(val, 5, 11)
03637 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val) \
03638                                                         vxge_vBIT(val, 16, 16)
03639 #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val) \
03640                                                         vxge_vBIT(val, 32, 16)
03641 /*0x09e70*/     u64     mdio_mgr_access_port[2];
03642 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE BIT(3)
03643 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vxge_vBIT(val, 5, 3)
03644 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DEVAD(val) vxge_vBIT(val, 11, 5)
03645 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ADDR(val) vxge_vBIT(val, 16, 16)
03646 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA(val) vxge_vBIT(val, 32, 16)
03647 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vxge_vBIT(val, 49, 2)
03648 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PREAMBLE   vxge_mBIT(51)
03649 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PRTAD(val) vxge_vBIT(val, 55, 5)
03650 #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_TWO vxge_mBIT(63)
03651         u8      unused0a200[0x0a200-0x09e80];
03652 /*0x0a200*/     u64     xmac_vsport_choices_vh[17];
03653 #define VXGE_HW_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17)
03654         u8      unused0a400[0x0a400-0x0a288];
03655 
03656 /*0x0a400*/     u64     rx_thresh_cfg_vp[17];
03657 #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8)
03658 #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8)
03659 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_0(val) vxge_vBIT(val, 16, 8)
03660 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_1(val) vxge_vBIT(val, 24, 8)
03661 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2(val) vxge_vBIT(val, 32, 8)
03662 #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_3(val) vxge_vBIT(val, 40, 8)
03663         u8      unused0ac90[0x0ac90-0x0a488];
03664 } __attribute((packed));
03665 
03666 /*VXGE_HW_SRPCIM_REGS_H*/
03667 struct vxge_hw_srpcim_reg {
03668 
03669 /*0x00000*/     u64     tim_mr2sr_resource_assignment_vh;
03670 #define VXGE_HW_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) \
03671                                                         vxge_vBIT(val, 0, 32)
03672         u8      unused00100[0x00100-0x00008];
03673 
03674 /*0x00100*/     u64     srpcim_pcipif_int_status;
03675 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT      BIT(3)
03676 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT        BIT(7)
03677 #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT \
03678                                                                         BIT(11)
03679 /*0x00108*/     u64     srpcim_pcipif_int_mask;
03680 /*0x00110*/     u64     mrpcim_msg_reg;
03681 #define VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT   BIT(3)
03682 /*0x00118*/     u64     mrpcim_msg_mask;
03683 /*0x00120*/     u64     mrpcim_msg_alarm;
03684 /*0x00128*/     u64     vpath_msg_reg;
03685 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT    BIT(0)
03686 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT    BIT(1)
03687 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT    BIT(2)
03688 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT    BIT(3)
03689 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT    BIT(4)
03690 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT    BIT(5)
03691 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT    BIT(6)
03692 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT    BIT(7)
03693 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT    BIT(8)
03694 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT    BIT(9)
03695 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT   BIT(10)
03696 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT   BIT(11)
03697 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT   BIT(12)
03698 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT   BIT(13)
03699 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT   BIT(14)
03700 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT   BIT(15)
03701 #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT   BIT(16)
03702 /*0x00130*/     u64     vpath_msg_mask;
03703 /*0x00138*/     u64     vpath_msg_alarm;
03704         u8      unused00160[0x00160-0x00140];
03705 
03706 /*0x00160*/     u64     srpcim_to_mrpcim_wmsg;
03707 #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val) \
03708                                                         vxge_vBIT(val, 0, 64)
03709 /*0x00168*/     u64     srpcim_to_mrpcim_wmsg_trig;
03710 #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG   BIT(0)
03711 /*0x00170*/     u64     mrpcim_to_srpcim_rmsg;
03712 #define VXGE_HW_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val) \
03713                                                         vxge_vBIT(val, 0, 64)
03714 /*0x00178*/     u64     vpath_to_srpcim_rmsg_sel;
03715 #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SEL_VPATH_TO_SRPCIM_RMSG_SEL(val) \
03716                                                         vxge_vBIT(val, 0, 5)
03717 /*0x00180*/     u64     vpath_to_srpcim_rmsg;
03718 #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val) \
03719                                                         vxge_vBIT(val, 0, 64)
03720         u8      unused00200[0x00200-0x00188];
03721 
03722 /*0x00200*/     u64     srpcim_general_int_status;
03723 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PIC_INT       BIT(0)
03724 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PCI_INT       BIT(3)
03725 #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_XMAC_INT      BIT(7)
03726         u8      unused00210[0x00210-0x00208];
03727 
03728 /*0x00210*/     u64     srpcim_general_int_mask;
03729 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PIC_INT BIT(0)
03730 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PCI_INT BIT(3)
03731 #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_XMAC_INT        BIT(7)
03732         u8      unused00220[0x00220-0x00218];
03733 
03734 /*0x00220*/     u64     srpcim_ppif_int_status;
03735 
03736 /*0x00228*/     u64     srpcim_ppif_int_mask;
03737 /*0x00230*/     u64     srpcim_gen_errors_reg;
03738 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR   BIT(3)
03739 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR    BIT(7)
03740 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR      BIT(11)
03741 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT BIT(15)
03742 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET      BIT(19)
03743 #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS     BIT(23)
03744 /*0x00238*/     u64     srpcim_gen_errors_mask;
03745 /*0x00240*/     u64     srpcim_gen_errors_alarm;
03746 /*0x00248*/     u64     mrpcim_to_srpcim_alarm_reg;
03747 #define VXGE_HW_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM  BIT(3)
03748 /*0x00250*/     u64     mrpcim_to_srpcim_alarm_mask;
03749 /*0x00258*/     u64     mrpcim_to_srpcim_alarm_alarm;
03750 /*0x00260*/     u64     vpath_to_srpcim_alarm_reg;
03751 
03752 /*0x00268*/     u64     vpath_to_srpcim_alarm_mask;
03753 /*0x00270*/     u64     vpath_to_srpcim_alarm_alarm;
03754         u8      unused00280[0x00280-0x00278];
03755 
03756 /*0x00280*/     u64     pf_sw_reset;
03757 #define VXGE_HW_PF_SW_RESET_PF_SW_RESET(val) vxge_vBIT(val, 0, 8)
03758 /*0x00288*/     u64     srpcim_general_cfg1;
03759 #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN    BIT(19)
03760 #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN     BIT(23)
03761 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN    BIT(27)
03762 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN    BIT(31)
03763 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN    BIT(35)
03764 #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN    BIT(39)
03765 /*0x00290*/     u64     srpcim_interrupt_cfg1;
03766 #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7)
03767 #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vxge_vBIT(val, 9, 3)
03768         u8      unused002a8[0x002a8-0x00298];
03769 
03770 /*0x002a8*/     u64     srpcim_clear_msix_mask;
03771 #define VXGE_HW_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK   BIT(0)
03772 /*0x002b0*/     u64     srpcim_set_msix_mask;
03773 #define VXGE_HW_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK       BIT(0)
03774 /*0x002b8*/     u64     srpcim_clr_msix_one_shot;
03775 #define VXGE_HW_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT       BIT(0)
03776 /*0x002c0*/     u64     srpcim_rst_in_prog;
03777 #define VXGE_HW_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG   BIT(7)
03778 /*0x002c8*/     u64     srpcim_reg_modified;
03779 #define VXGE_HW_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED BIT(7)
03780 /*0x002d0*/     u64     tgt_pf_illegal_access;
03781 #define VXGE_HW_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7)
03782 /*0x002d8*/     u64     srpcim_msix_status;
03783 #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK      BIT(3)
03784 #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR    BIT(7)
03785         u8      unused00880[0x00880-0x002e0];
03786 
03787 /*0x00880*/     u64     xgmac_sr_int_status;
03788 #define VXGE_HW_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_ASIC_NTWK_SR_INT   BIT(3)
03789 /*0x00888*/     u64     xgmac_sr_int_mask;
03790 /*0x00890*/     u64     asic_ntwk_sr_err_reg;
03791 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT BIT(3)
03792 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK    BIT(7)
03793 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED \
03794                                                                         BIT(11)
03795 #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED   BIT(15)
03796 /*0x00898*/     u64     asic_ntwk_sr_err_mask;
03797 /*0x008a0*/     u64     asic_ntwk_sr_err_alarm;
03798         u8      unused008c0[0x008c0-0x008a8];
03799 
03800 /*0x008c0*/     u64     xmac_vsport_choices_sr_clone;
03801 #define VXGE_HW_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val) \
03802                                                         vxge_vBIT(val, 0, 17)
03803         u8      unused00900[0x00900-0x008c8];
03804 
03805 /*0x00900*/     u64     mr_rqa_top_prty_for_vh;
03806 #define VXGE_HW_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \
03807                                                         vxge_vBIT(val, 59, 5)
03808 /*0x00908*/     u64     umq_vh_data_list_empty;
03809 #define VXGE_HW_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY \
03810                                                         BIT(0)
03811 /*0x00910*/     u64     wde_cfg;
03812 #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_START     BIT(0)
03813 #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_END       BIT(1)
03814 #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_START      BIT(2)
03815 #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_END        BIT(3)
03816 #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_START    BIT(4)
03817 #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_END      BIT(5)
03818 #define VXGE_HW_WDE_CFG_NS0_MWB_OPT_EN  BIT(6)
03819 #define VXGE_HW_WDE_CFG_NS0_QB_OPT_EN   BIT(7)
03820 #define VXGE_HW_WDE_CFG_NS0_MPSB_OPT_EN BIT(8)
03821 #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_START     BIT(9)
03822 #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_END       BIT(10)
03823 #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_START      BIT(11)
03824 #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_END        BIT(12)
03825 #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_START    BIT(13)
03826 #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_END      BIT(14)
03827 #define VXGE_HW_WDE_CFG_NS1_MWB_OPT_EN  BIT(15)
03828 #define VXGE_HW_WDE_CFG_NS1_QB_OPT_EN   BIT(16)
03829 #define VXGE_HW_WDE_CFG_NS1_MPSB_OPT_EN BIT(17)
03830 #define VXGE_HW_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR BIT(19)
03831 #define VXGE_HW_WDE_CFG_ALIGNMENT_PREFERENCE(val) vxge_vBIT(val, 30, 2)
03832 #define VXGE_HW_WDE_CFG_MEM_WORD_SIZE(val) vxge_vBIT(val, 46, 2)
03833 
03834 } __attribute((packed));
03835 
03836 /*VXGE_HW_VPMGMT_REGS_H*/
03837 struct vxge_hw_vpmgmt_reg {
03838 
03839         u8      unused00040[0x00040-0x00000];
03840 
03841 /*0x00040*/     u64     vpath_to_func_map_cfg1;
03842 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val) \
03843                                                         vxge_vBIT(val, 3, 5)
03844 /*0x00048*/     u64     vpath_is_first;
03845 #define VXGE_HW_VPATH_IS_FIRST_VPATH_IS_FIRST   vxge_mBIT(3)
03846 /*0x00050*/     u64     srpcim_to_vpath_wmsg;
03847 #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val) \
03848                                                         vxge_vBIT(val, 0, 64)
03849 /*0x00058*/     u64     srpcim_to_vpath_wmsg_trig;
03850 #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_TRIG_SRPCIM_TO_VPATH_WMSG_TRIG \
03851                                                                 vxge_mBIT(0)
03852         u8      unused00100[0x00100-0x00060];
03853 
03854 /*0x00100*/     u64     tim_vpath_assignment;
03855 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
03856         u8      unused00140[0x00140-0x00108];
03857 
03858 /*0x00140*/     u64     rqa_top_prty_for_vp;
03859 #define VXGE_HW_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) \
03860                                                         vxge_vBIT(val, 59, 5)
03861         u8      unused001c0[0x001c0-0x00148];
03862 
03863 /*0x001c0*/     u64     rxmac_rx_pa_cfg0_vpmgmt_clone;
03864 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR  vxge_mBIT(3)
03865 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N vxge_mBIT(7)
03866 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO    vxge_mBIT(18)
03867 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_MOBILE_IPV6_HDRS \
03868                                                                 vxge_mBIT(19)
03869 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING \
03870                                                                 vxge_mBIT(23)
03871 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN  vxge_mBIT(27)
03872 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE  vxge_mBIT(35)
03873 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L3_CSUM_ERR \
03874                                                                 vxge_mBIT(39)
03875 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR \
03876                                                                 vxge_mBIT(43)
03877 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L4_CSUM_ERR \
03878                                                                 vxge_mBIT(47)
03879 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR \
03880                                                                 vxge_mBIT(51)
03881 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_RPA_ERR \
03882                                                                 vxge_mBIT(55)
03883 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_RPA_ERR \
03884                                                                 vxge_mBIT(59)
03885 #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_JUMBO_SNAP_EN     vxge_mBIT(63)
03886 /*0x001c8*/     u64     rts_mgr_cfg0_vpmgmt_clone;
03887 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_RTS_DP_SP_PRIORITY    vxge_mBIT(3)
03888 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val) \
03889                                                         vxge_vBIT(val, 24, 8)
03890 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ICMP_TRASH    vxge_mBIT(35)
03891 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_TCPSYN_TRASH  vxge_mBIT(39)
03892 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ZL4PYLD_TRASH vxge_mBIT(43)
03893 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_TCP_TRASH     vxge_mBIT(47)
03894 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_UDP_TRASH     vxge_mBIT(51)
03895 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_FLEX_TRASH    vxge_mBIT(55)
03896 #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_IPFRAG_TRASH  vxge_mBIT(59)
03897 /*0x001d0*/     u64     rts_mgr_criteria_priority_vpmgmt_clone;
03898 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val) \
03899                                                         vxge_vBIT(val, 5, 3)
03900 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val) \
03901                                                         vxge_vBIT(val, 9, 3)
03902 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val) \
03903                                                         vxge_vBIT(val, 13, 3)
03904 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val) \
03905                                                         vxge_vBIT(val, 17, 3)
03906 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val) \
03907                                                         vxge_vBIT(val, 21, 3)
03908 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val) \
03909                                                         vxge_vBIT(val, 25, 3)
03910 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val) \
03911                                                         vxge_vBIT(val, 29, 3)
03912 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val) \
03913                                                         vxge_vBIT(val, 33, 3)
03914 #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val) \
03915                                                         vxge_vBIT(val, 37, 3)
03916 /*0x001d8*/     u64     rxmac_cfg0_port_vpmgmt_clone[3];
03917 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_RMAC_EN    vxge_mBIT(3)
03918 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS  vxge_mBIT(7)
03919 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_DISCARD_PFRM       vxge_mBIT(11)
03920 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_FCS_ERR     vxge_mBIT(15)
03921 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LONG_ERR    vxge_mBIT(19)
03922 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_USIZED_ERR  vxge_mBIT(23)
03923 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LEN_MISMATCH \
03924                                                                 vxge_mBIT(27)
03925 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val) \
03926                                                         vxge_vBIT(val, 50, 14)
03927 /*0x001f0*/     u64     rxmac_pause_cfg_port_vpmgmt_clone[3];
03928 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN        vxge_mBIT(3)
03929 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN        vxge_mBIT(7)
03930 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val) \
03931                                                         vxge_vBIT(val, 9, 3)
03932 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_DUAL_THR      vxge_mBIT(15)
03933 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val) \
03934                                                         vxge_vBIT(val, 20, 16)
03935 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_FCS_ERR \
03936                                                                 vxge_mBIT(39)
03937 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_LEN_ERR \
03938                                                                 vxge_mBIT(43)
03939 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_LIMITER_EN    vxge_mBIT(47)
03940 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val) \
03941                                                         vxge_vBIT(val, 48, 8)
03942 #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_PERMIT_RATEMGMT_CTRL \
03943                                                         vxge_mBIT(59)
03944         u8      unused00240[0x00240-0x00208];
03945 
03946 /*0x00240*/     u64     xmac_vsport_choices_vp;
03947 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17)
03948         u8      unused00260[0x00260-0x00248];
03949 
03950 /*0x00260*/     u64     xgmac_gen_status_vpmgmt_clone;
03951 #define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK     vxge_mBIT(3)
03952 #define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE \
03953                                                                 vxge_mBIT(11)
03954 /*0x00268*/     u64     xgmac_status_port_vpmgmt_clone[2];
03955 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_REMOTE_FAULT \
03956                                                                 vxge_mBIT(3)
03957 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_LOCAL_FAULT vxge_mBIT(7)
03958 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_MAC_PHY_LAYER_AVAIL \
03959                                                                 vxge_mBIT(11)
03960 #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_PORT_OK    vxge_mBIT(15)
03961 /*0x00278*/     u64     xmac_gen_cfg_vpmgmt_clone;
03962 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val) \
03963                                                         vxge_vBIT(val, 2, 2)
03964 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_TX_HEAD_DROP_WHEN_FAULT \
03965                                                         vxge_mBIT(7)
03966 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_FAULT_BEHAVIOUR       vxge_mBIT(27)
03967 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val) \
03968                                                         vxge_vBIT(val, 28, 4)
03969 #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val) \
03970                                                         vxge_vBIT(val, 32, 4)
03971 /*0x00280*/     u64     xmac_timestamp_vpmgmt_clone;
03972 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_EN  vxge_mBIT(3)
03973 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val) \
03974                                                         vxge_vBIT(val, 6, 2)
03975 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val) vxge_vBIT(val, 12, 4)
03976 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_TIMER_RESTART       vxge_mBIT(19)
03977 #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val) \
03978                                                         vxge_vBIT(val, 32, 16)
03979 /*0x00288*/     u64     xmac_stats_gen_cfg_vpmgmt_clone;
03980 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val) \
03981                                                         vxge_vBIT(val, 4, 4)
03982 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val) \
03983                                                         vxge_vBIT(val, 8, 4)
03984 #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VLAN_HANDLING   vxge_mBIT(15)
03985 /*0x00290*/     u64     xmac_cfg_port_vpmgmt_clone[3];
03986 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_LOOPBACK       vxge_mBIT(3)
03987 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_REVERSE_LOOPBACK \
03988                                                                 vxge_mBIT(7)
03989 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_TX_BEHAV       vxge_mBIT(11)
03990 #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_RX_BEHAV       vxge_mBIT(15)
03991         u8      unused002c0[0x002c0-0x002a8];
03992 
03993 /*0x002c0*/     u64     txmac_gen_cfg0_vpmgmt_clone;
03994 #define VXGE_HW_TXMAC_GEN_CFG0_VPMGMT_CLONE_CHOSEN_TX_PORT      vxge_mBIT(7)
03995 /*0x002c8*/     u64     txmac_cfg0_port_vpmgmt_clone[3];
03996 #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_TMAC_EN    vxge_mBIT(3)
03997 #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_APPEND_PAD vxge_mBIT(7)
03998 #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vxge_vBIT(val, 8, 8)
03999         u8      unused00300[0x00300-0x002e0];
04000 
04001 /*0x00300*/     u64     wol_mp_crc;
04002 #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32)
04003 #define VXGE_HW_WOL_MP_CRC_RC_EN        vxge_mBIT(63)
04004 /*0x00308*/     u64     wol_mp_mask_a;
04005 #define VXGE_HW_WOL_MP_MASK_A_MASK(val) vxge_vBIT(val, 0, 64)
04006 /*0x00310*/     u64     wol_mp_mask_b;
04007 #define VXGE_HW_WOL_MP_MASK_B_MASK(val) vxge_vBIT(val, 0, 64)
04008         u8      unused00360[0x00360-0x00318];
04009 
04010 /*0x00360*/     u64     fau_pa_cfg_vpmgmt_clone;
04011 #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L4_COMP_CSUM       vxge_mBIT(3)
04012 #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_INCL_CF vxge_mBIT(7)
04013 #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_COMP_CSUM       vxge_mBIT(11)
04014 /*0x00368*/     u64     rx_datapath_util_vp_clone;
04015 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val) \
04016                                                         vxge_vBIT(val, 7, 9)
04017 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) \
04018                                                         vxge_vBIT(val, 16, 4)
04019 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val) \
04020                                                         vxge_vBIT(val, 20, 4)
04021 #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val) \
04022                                                         vxge_vBIT(val, 24, 4)
04023         u8      unused00380[0x00380-0x00370];
04024 
04025 /*0x00380*/     u64     tx_datapath_util_vp_clone;
04026 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val) \
04027                                                         vxge_vBIT(val, 7, 9)
04028 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) \
04029                                                         vxge_vBIT(val, 16, 4)
04030 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val) \
04031                                                         vxge_vBIT(val, 20, 4)
04032 #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) \
04033                                                         vxge_vBIT(val, 24, 4)
04034 
04035 } __attribute((packed));
04036 
04037 struct vxge_hw_vpath_reg {
04038 
04039         u8      unused00300[0x00300];
04040 
04041 /*0x00300*/     u64     usdc_vpath;
04042 #define VXGE_HW_USDC_VPATH_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 32)
04043         u8      unused00a00[0x00a00-0x00308];
04044 
04045 /*0x00a00*/     u64     wrdma_alarm_status;
04046 #define VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT    vxge_mBIT(1)
04047 /*0x00a08*/     u64     wrdma_alarm_mask;
04048         u8      unused00a30[0x00a30-0x00a10];
04049 
04050 /*0x00a30*/     u64     prc_alarm_reg;
04051 #define VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP     vxge_mBIT(0)
04052 #define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR  vxge_mBIT(1)
04053 #define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT        vxge_mBIT(2)
04054 #define VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR       vxge_mBIT(3)
04055 /*0x00a38*/     u64     prc_alarm_mask;
04056 /*0x00a40*/     u64     prc_alarm_alarm;
04057 /*0x00a48*/     u64     prc_cfg1;
04058 #define VXGE_HW_PRC_CFG1_RX_TIMER_VAL(val) vxge_vBIT(val, 3, 29)
04059 #define VXGE_HW_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE       vxge_mBIT(34)
04060 #define VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE       vxge_mBIT(35)
04061 #define VXGE_HW_PRC_CFG1_GREEDY_RETURN  vxge_mBIT(36)
04062 #define VXGE_HW_PRC_CFG1_QUICK_SHOT     vxge_mBIT(37)
04063 #define VXGE_HW_PRC_CFG1_RX_TIMER_CI    vxge_mBIT(39)
04064 #define VXGE_HW_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vxge_vBIT(val, 40, 2)
04065         u8      unused00a60[0x00a60-0x00a50];
04066 
04067 /*0x00a60*/     u64     prc_cfg4;
04068 #define VXGE_HW_PRC_CFG4_IN_SVC vxge_mBIT(7)
04069 #define VXGE_HW_PRC_CFG4_RING_MODE(val) vxge_vBIT(val, 14, 2)
04070 #define VXGE_HW_PRC_CFG4_RXD_NO_SNOOP   vxge_mBIT(22)
04071 #define VXGE_HW_PRC_CFG4_FRM_NO_SNOOP   vxge_mBIT(23)
04072 #define VXGE_HW_PRC_CFG4_RTH_DISABLE    vxge_mBIT(31)
04073 #define VXGE_HW_PRC_CFG4_IGNORE_OWNERSHIP       vxge_mBIT(32)
04074 #define VXGE_HW_PRC_CFG4_SIGNAL_BENIGN_OVFLW    vxge_mBIT(36)
04075 #define VXGE_HW_PRC_CFG4_BIMODAL_INTERRUPT      vxge_mBIT(37)
04076 #define VXGE_HW_PRC_CFG4_BACKOFF_INTERVAL(val) vxge_vBIT(val, 40, 24)
04077 /*0x00a68*/     u64     prc_cfg5;
04078 #define VXGE_HW_PRC_CFG5_RXD0_ADD(val) vxge_vBIT(val, 0, 61)
04079 /*0x00a70*/     u64     prc_cfg6;
04080 #define VXGE_HW_PRC_CFG6_FRM_PAD_EN     vxge_mBIT(0)
04081 #define VXGE_HW_PRC_CFG6_QSIZE_ALIGNED_RXD      vxge_mBIT(2)
04082 #define VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN       vxge_mBIT(5)
04083 #define VXGE_HW_PRC_CFG6_L3_CPC_TRSFR_CODE_EN   vxge_mBIT(8)
04084 #define VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN   vxge_mBIT(9)
04085 #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9)
04086 #define VXGE_HW_PRC_CFG6_GET_RXD_CRXDT(val) vxge_bVALn(val, 23, 9)
04087 #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9)
04088 #define VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val) vxge_bVALn(val, 36, 9)
04089 /*0x00a78*/     u64     prc_cfg7;
04090 #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2)
04091 #define VXGE_HW_PRC_CFG7_SMART_SCAT_EN  vxge_mBIT(11)
04092 #define VXGE_HW_PRC_CFG7_RXD_NS_CHG_EN  vxge_mBIT(12)
04093 #define VXGE_HW_PRC_CFG7_NO_HDR_SEPARATION      vxge_mBIT(14)
04094 #define VXGE_HW_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vxge_vBIT(val, 20, 4)
04095 #define VXGE_HW_PRC_CFG7_BUFF_SIZE0_MASK(val) vxge_vBIT(val, 27, 5)
04096 /*0x00a80*/     u64     tim_dest_addr;
04097 #define VXGE_HW_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vxge_vBIT(val, 0, 64)
04098 /*0x00a88*/     u64     prc_rxd_doorbell;
04099 #define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vxge_vBIT(val, 48, 16)
04100 /*0x00a90*/     u64     rqa_prty_for_vp;
04101 #define VXGE_HW_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vxge_vBIT(val, 59, 5)
04102 /*0x00a98*/     u64     rxdmem_size;
04103 #define VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vxge_vBIT(val, 51, 13)
04104 /*0x00aa0*/     u64     frm_in_progress_cnt;
04105 #define VXGE_HW_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val) \
04106                                                         vxge_vBIT(val, 59, 5)
04107 /*0x00aa8*/     u64     rx_multi_cast_stats;
04108 #define VXGE_HW_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vxge_vBIT(val, 48, 16)
04109 /*0x00ab0*/     u64     rx_frm_transferred;
04110 #define VXGE_HW_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) \
04111                                                         vxge_vBIT(val, 32, 32)
04112 /*0x00ab8*/     u64     rxd_returned;
04113 #define VXGE_HW_RXD_RETURNED_RXD_RETURNED(val) vxge_vBIT(val, 48, 16)
04114         u8      unused00c00[0x00c00-0x00ac0];
04115 
04116 /*0x00c00*/     u64     kdfc_fifo_trpl_partition;
04117 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vxge_vBIT(val, 17, 15)
04118 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vxge_vBIT(val, 33, 15)
04119 #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vxge_vBIT(val, 49, 15)
04120 /*0x00c08*/     u64     kdfc_fifo_trpl_ctrl;
04121 #define VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE      vxge_mBIT(7)
04122 /*0x00c10*/     u64     kdfc_trpl_fifo_0_ctrl;
04123 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vxge_vBIT(val, 14, 2)
04124 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN   vxge_mBIT(22)
04125 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN   vxge_mBIT(23)
04126 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2)
04127 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC        vxge_mBIT(28)
04128 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD   vxge_mBIT(29)
04129 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP  vxge_mBIT(30)
04130 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD   vxge_mBIT(31)
04131 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
04132 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7)
04133 #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16)
04134 /*0x00c18*/     u64     kdfc_trpl_fifo_1_ctrl;
04135 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vxge_vBIT(val, 14, 2)
04136 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN   vxge_mBIT(22)
04137 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN   vxge_mBIT(23)
04138 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2)
04139 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC        vxge_mBIT(28)
04140 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD   vxge_mBIT(29)
04141 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP  vxge_mBIT(30)
04142 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD   vxge_mBIT(31)
04143 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
04144 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7)
04145 #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16)
04146 /*0x00c20*/     u64     kdfc_trpl_fifo_2_ctrl;
04147 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN   vxge_mBIT(22)
04148 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN   vxge_mBIT(23)
04149 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2)
04150 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC        vxge_mBIT(28)
04151 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD   vxge_mBIT(29)
04152 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP  vxge_mBIT(30)
04153 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD   vxge_mBIT(31)
04154 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vxge_vBIT(val, 32, 8)
04155 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7)
04156 #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16)
04157 /*0x00c28*/     u64     kdfc_trpl_fifo_0_wb_address;
04158 #define VXGE_HW_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64)
04159 /*0x00c30*/     u64     kdfc_trpl_fifo_1_wb_address;
04160 #define VXGE_HW_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64)
04161 /*0x00c38*/     u64     kdfc_trpl_fifo_2_wb_address;
04162 #define VXGE_HW_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64)
04163 /*0x00c40*/     u64     kdfc_trpl_fifo_offset;
04164 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vxge_vBIT(val, 1, 15)
04165 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vxge_vBIT(val, 17, 15)
04166 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vxge_vBIT(val, 33, 15)
04167 /*0x00c48*/     u64     kdfc_drbl_triplet_total;
04168 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) \
04169                                                         vxge_vBIT(val, 17, 15)
04170         u8      unused00c60[0x00c60-0x00c50];
04171 
04172 /*0x00c60*/     u64     usdc_drbl_ctrl;
04173 #define VXGE_HW_USDC_DRBL_CTRL_FLIP_EN  vxge_mBIT(22)
04174 #define VXGE_HW_USDC_DRBL_CTRL_SWAP_EN  vxge_mBIT(23)
04175 /*0x00c68*/     u64     usdc_vp_ready;
04176 #define VXGE_HW_USDC_VP_READY_USDC_HTN_READY    vxge_mBIT(7)
04177 #define VXGE_HW_USDC_VP_READY_USDC_SRQ_READY    vxge_mBIT(15)
04178 #define VXGE_HW_USDC_VP_READY_USDC_CQRQ_READY   vxge_mBIT(23)
04179 /*0x00c70*/     u64     kdfc_status;
04180 #define VXGE_HW_KDFC_STATUS_KDFC_WRR_0_READY    vxge_mBIT(0)
04181 #define VXGE_HW_KDFC_STATUS_KDFC_WRR_1_READY    vxge_mBIT(1)
04182 #define VXGE_HW_KDFC_STATUS_KDFC_WRR_2_READY    vxge_mBIT(2)
04183         u8      unused00c80[0x00c80-0x00c78];
04184 
04185 /*0x00c80*/     u64     xmac_rpa_vcfg;
04186 #define VXGE_HW_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH  vxge_mBIT(3)
04187 #define VXGE_HW_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH  vxge_mBIT(7)
04188 #define VXGE_HW_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH  vxge_mBIT(11)
04189 #define VXGE_HW_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH  vxge_mBIT(15)
04190 #define VXGE_HW_XMAC_RPA_VCFG_L4_INCL_CF        vxge_mBIT(19)
04191 #define VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG    vxge_mBIT(23)
04192 /*0x00c88*/     u64     rxmac_vcfg0;
04193 #define VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vxge_vBIT(val, 2, 14)
04194 #define VXGE_HW_RXMAC_VCFG0_RTS_USE_MIN_LEN     vxge_mBIT(19)
04195 #define VXGE_HW_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vxge_vBIT(val, 26, 14)
04196 #define VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN   vxge_mBIT(43)
04197 #define VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN   vxge_mBIT(47)
04198 #define VXGE_HW_RXMAC_VCFG0_BCAST_EN    vxge_mBIT(51)
04199 #define VXGE_HW_RXMAC_VCFG0_ALL_VID_EN  vxge_mBIT(55)
04200 /*0x00c90*/     u64     rxmac_vcfg1;
04201 #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vxge_vBIT(val, 42, 2)
04202 #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE    vxge_mBIT(47)
04203 #define VXGE_HW_RXMAC_VCFG1_CONTRIB_L2_FLOW     vxge_mBIT(51)
04204 /*0x00c98*/     u64     rts_access_steer_ctrl;
04205 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(val) vxge_vBIT(val, 1, 7)
04206 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vxge_vBIT(val, 8, 4)
04207 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE    vxge_mBIT(15)
04208 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL     vxge_mBIT(23)
04209 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL vxge_mBIT(27)
04210 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS      vxge_mBIT(0)
04211 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(val) vxge_vBIT(val, 40, 8)
04212 /* To be used by the privileged driver */
04213 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_VHN(val) vxge_vBIT(val, 48, 8)
04214 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_VFID(val) vxge_vBIT(val, 56, 8)
04215 /*0x00ca0*/     u64     rts_access_steer_data0;
04216 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DATA(val) vxge_vBIT(val, 0, 64)
04217 /*0x00ca8*/     u64     rts_access_steer_data1;
04218 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DATA(val) vxge_vBIT(val, 0, 64)
04219 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_EN vxge_mBIT(54)
04220 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_VPN(val) vxge_vBIT(val, 55, 5)
04221         u8      unused00d00[0x00d00-0x00cb0];
04222 
04223 /*0x00d00*/     u64     xmac_vsport_choice;
04224 #define VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vxge_vBIT(val, 3, 5)
04225 /*0x00d08*/     u64     xmac_stats_cfg;
04226 /*0x00d10*/     u64     xmac_stats_access_cmd;
04227 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(val) vxge_vBIT(val, 6, 2)
04228 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE    vxge_mBIT(15)
04229 #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8)
04230 /*0x00d18*/     u64     xmac_stats_access_data;
04231 #define VXGE_HW_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64)
04232 /*0x00d20*/     u64     asic_ntwk_vp_ctrl;
04233 #define VXGE_HW_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK vxge_mBIT(3)
04234 #define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO  vxge_mBIT(55)
04235 #define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM        vxge_mBIT(63)
04236         u8      unused00d30[0x00d30-0x00d28];
04237 
04238 /*0x00d30*/     u64     xgmac_vp_int_status;
04239 #define VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT \
04240                                                                 vxge_mBIT(3)
04241 /*0x00d38*/     u64     xgmac_vp_int_mask;
04242 /*0x00d40*/     u64     asic_ntwk_vp_err_reg;
04243 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT        vxge_mBIT(3)
04244 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK vxge_mBIT(7)
04245 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR \
04246                                                                 vxge_mBIT(11)
04247 #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR \
04248                                                         vxge_mBIT(15)
04249 #define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT \
04250                                                         vxge_mBIT(19)
04251 #define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK   vxge_mBIT(23)
04252 /*0x00d48*/     u64     asic_ntwk_vp_err_mask;
04253 /*0x00d50*/     u64     asic_ntwk_vp_err_alarm;
04254         u8      unused00d80[0x00d80-0x00d58];
04255 
04256 /*0x00d80*/     u64     rtdma_bw_ctrl;
04257 #define VXGE_HW_RTDMA_BW_CTRL_BW_CTRL_EN        vxge_mBIT(39)
04258 #define VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW(val) vxge_vBIT(val, 46, 18)
04259 /*0x00d88*/     u64     rtdma_rd_optimization_ctrl;
04260 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT  vxge_mBIT(3)
04261 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vxge_vBIT(val, 6, 2)
04262 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vxge_vBIT(val, 8, 8)
04263 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE    vxge_mBIT(19)
04264 #define VXGE_HW_PCI_EXP_DEVCTL_READRQ   0x7000  /* Max_Read_Request_Size */
04265 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val) \
04266                                                         vxge_vBIT(val, 21, 3)
04267 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN    vxge_mBIT(28)
04268 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val) \
04269                                                         vxge_vBIT(val, 29, 3)
04270 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN      vxge_mBIT(35)
04271 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) \
04272                                                         vxge_vBIT(val, 37, 3)
04273 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE   vxge_mBIT(43)
04274 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val) \
04275                                                         vxge_vBIT(val, 51, 5)
04276 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN     vxge_mBIT(59)
04277 #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) \
04278                                                         vxge_vBIT(val, 61, 3)
04279 /*0x00d90*/     u64     pda_pcc_job_monitor;
04280 #define VXGE_HW_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS  vxge_mBIT(7)
04281 /*0x00d98*/     u64     tx_protocol_assist_cfg;
04282 #define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN vxge_mBIT(6)
04283 #define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING      vxge_mBIT(7)
04284         u8      unused01000[0x01000-0x00da0];
04285 
04286 /*0x01000*/     u64     tim_cfg1_int_num[4];
04287 #define VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vxge_vBIT(val, 6, 26)
04288 #define VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN       vxge_mBIT(35)
04289 #define VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN   vxge_mBIT(36)
04290 #define VXGE_HW_TIM_CFG1_INT_NUM_TXD_CNT_EN     vxge_mBIT(37)
04291 #define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC       vxge_mBIT(38)
04292 #define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI       vxge_mBIT(39)
04293 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(val) vxge_vBIT(val, 41, 7)
04294 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(val) vxge_vBIT(val, 49, 7)
04295 #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(val) vxge_vBIT(val, 57, 7)
04296 /*0x01020*/     u64     tim_cfg2_int_num[4];
04297 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(val) vxge_vBIT(val, 0, 16)
04298 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val) vxge_vBIT(val, 16, 16)
04299 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val) vxge_vBIT(val, 32, 16)
04300 #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(val) vxge_vBIT(val, 48, 16)
04301 /*0x01040*/     u64     tim_cfg3_int_num[4];
04302 #define VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI       vxge_mBIT(0)
04303 #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vxge_vBIT(val, 1, 4)
04304 #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vxge_vBIT(val, 6, 26)
04305 #define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val) vxge_vBIT(val, 32, 6)
04306 #define VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vxge_vBIT(val, 38, 26)
04307 /*0x01060*/     u64     tim_wrkld_clc;
04308 #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vxge_vBIT(val, 0, 32)
04309 #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vxge_vBIT(val, 35, 5)
04310 #define VXGE_HW_TIM_WRKLD_CLC_CNT_FRM_BYTE      vxge_mBIT(40)
04311 #define VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(val) vxge_vBIT(val, 41, 2)
04312 #define VXGE_HW_TIM_WRKLD_CLC_CNT_LNK_EN        vxge_mBIT(43)
04313 #define VXGE_HW_TIM_WRKLD_CLC_HOST_UTIL(val) vxge_vBIT(val, 57, 7)
04314 /*0x01068*/     u64     tim_bitmap;
04315 #define VXGE_HW_TIM_BITMAP_MASK(val) vxge_vBIT(val, 0, 32)
04316 #define VXGE_HW_TIM_BITMAP_LLROOT_RXD_EN        vxge_mBIT(32)
04317 #define VXGE_HW_TIM_BITMAP_LLROOT_TXD_EN        vxge_mBIT(33)
04318 /*0x01070*/     u64     tim_ring_assn;
04319 #define VXGE_HW_TIM_RING_ASSN_INT_NUM(val) vxge_vBIT(val, 6, 2)
04320 /*0x01078*/     u64     tim_remap;
04321 #define VXGE_HW_TIM_REMAP_TX_EN vxge_mBIT(5)
04322 #define VXGE_HW_TIM_REMAP_RX_EN vxge_mBIT(6)
04323 #define VXGE_HW_TIM_REMAP_OFFLOAD_EN    vxge_mBIT(7)
04324 #define VXGE_HW_TIM_REMAP_TO_VPATH_NUM(val) vxge_vBIT(val, 11, 5)
04325 /*0x01080*/     u64     tim_vpath_map;
04326 #define VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT(val) vxge_vBIT(val, 0, 32)
04327 /*0x01088*/     u64     tim_pci_cfg;
04328 #define VXGE_HW_TIM_PCI_CFG_ADD_PAD     vxge_mBIT(7)
04329 #define VXGE_HW_TIM_PCI_CFG_NO_SNOOP    vxge_mBIT(15)
04330 #define VXGE_HW_TIM_PCI_CFG_RELAXED     vxge_mBIT(23)
04331 #define VXGE_HW_TIM_PCI_CFG_CTL_STR     vxge_mBIT(31)
04332         u8      unused01100[0x01100-0x01090];
04333 
04334 /*0x01100*/     u64     sgrp_assign;
04335 #define VXGE_HW_SGRP_ASSIGN_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 64)
04336 /*0x01108*/     u64     sgrp_aoa_and_result;
04337 #define VXGE_HW_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val) \
04338                                                         vxge_vBIT(val, 0, 64)
04339 /*0x01110*/     u64     rpe_pci_cfg;
04340 #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE vxge_mBIT(7)
04341 #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE  vxge_mBIT(8)
04342 #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE  vxge_mBIT(9)
04343 #define VXGE_HW_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE        vxge_mBIT(10)
04344 #define VXGE_HW_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE      vxge_mBIT(11)
04345 #define VXGE_HW_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE     vxge_mBIT(12)
04346 #define VXGE_HW_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE  vxge_mBIT(13)
04347 #define VXGE_HW_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE  vxge_mBIT(14)
04348 #define VXGE_HW_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE  vxge_mBIT(15)
04349 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_DATA        vxge_mBIT(18)
04350 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_NONLL_CQE   vxge_mBIT(19)
04351 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_LL_CQE      vxge_mBIT(20)
04352 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRQ_IR     vxge_mBIT(21)
04353 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQSQ_IR     vxge_mBIT(22)
04354 #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRR_IR     vxge_mBIT(23)
04355 #define VXGE_HW_RPE_PCI_CFG_RELAXED_DATA        vxge_mBIT(26)
04356 #define VXGE_HW_RPE_PCI_CFG_RELAXED_NONLL_CQE   vxge_mBIT(27)
04357 #define VXGE_HW_RPE_PCI_CFG_RELAXED_LL_CQE      vxge_mBIT(28)
04358 #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRQ_IR     vxge_mBIT(29)
04359 #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQSQ_IR     vxge_mBIT(30)
04360 #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRR_IR     vxge_mBIT(31)
04361 /*0x01118*/     u64     rpe_lro_cfg;
04362 #define VXGE_HW_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR       vxge_mBIT(7)
04363 #define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG        vxge_mBIT(11)
04364 #define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG  vxge_mBIT(15)
04365 #define VXGE_HW_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE vxge_mBIT(23)
04366 /*0x01120*/     u64     pe_mr2vp_ack_blk_limit;
04367 #define VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vxge_vBIT(val, 32, 32)
04368 /*0x01128*/     u64     pe_mr2vp_rirr_lirr_blk_limit;
04369 #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val) \
04370                                                         vxge_vBIT(val, 0, 32)
04371 #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val) \
04372                                                         vxge_vBIT(val, 32, 32)
04373 /*0x01130*/     u64     txpe_pci_nce_cfg;
04374 #define VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vxge_vBIT(val, 0, 32)
04375 #define VXGE_HW_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE        vxge_mBIT(55)
04376 #define VXGE_HW_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI   vxge_mBIT(63)
04377         u8      unused01180[0x01180-0x01138];
04378 
04379 /*0x01180*/     u64     msg_qpad_en_cfg;
04380 #define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_BWR_READ    vxge_mBIT(3)
04381 #define VXGE_HW_MSG_QPAD_EN_CFG_DMQ_BWR_READ    vxge_mBIT(7)
04382 #define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_READ vxge_mBIT(11)
04383 #define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_READ vxge_mBIT(15)
04384 #define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE   vxge_mBIT(19)
04385 #define VXGE_HW_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE vxge_mBIT(23)
04386 #define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE        vxge_mBIT(27)
04387 #define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE        vxge_mBIT(31)
04388 /*0x01188*/     u64     msg_pci_cfg;
04389 #define VXGE_HW_MSG_PCI_CFG_GENDMA_NO_SNOOP     vxge_mBIT(3)
04390 #define VXGE_HW_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP  vxge_mBIT(7)
04391 #define VXGE_HW_MSG_PCI_CFG_UMQ_NO_SNOOP        vxge_mBIT(11)
04392 #define VXGE_HW_MSG_PCI_CFG_DMQ_NO_SNOOP        vxge_mBIT(15)
04393 /*0x01190*/     u64     umqdmq_ir_init;
04394 #define VXGE_HW_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vxge_vBIT(val, 0, 64)
04395 /*0x01198*/     u64     dmq_ir_int;
04396 #define VXGE_HW_DMQ_IR_INT_IMMED_ENABLE vxge_mBIT(6)
04397 #define VXGE_HW_DMQ_IR_INT_EVENT_ENABLE vxge_mBIT(7)
04398 #define VXGE_HW_DMQ_IR_INT_NUMBER(val) vxge_vBIT(val, 9, 7)
04399 #define VXGE_HW_DMQ_IR_INT_BITMAP(val) vxge_vBIT(val, 16, 16)
04400 /*0x011a0*/     u64     dmq_bwr_init_add;
04401 #define VXGE_HW_DMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64)
04402 /*0x011a8*/     u64     dmq_bwr_init_byte;
04403 #define VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
04404 /*0x011b0*/     u64     dmq_ir;
04405 #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8)
04406 /*0x011b8*/     u64     umq_int;
04407 #define VXGE_HW_UMQ_INT_IMMED_ENABLE    vxge_mBIT(6)
04408 #define VXGE_HW_UMQ_INT_EVENT_ENABLE    vxge_mBIT(7)
04409 #define VXGE_HW_UMQ_INT_NUMBER(val) vxge_vBIT(val, 9, 7)
04410 #define VXGE_HW_UMQ_INT_BITMAP(val) vxge_vBIT(val, 16, 16)
04411 /*0x011c0*/     u64     umq_mr2vp_bwr_pfch_init;
04412 #define VXGE_HW_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vxge_vBIT(val, 0, 8)
04413 /*0x011c8*/     u64     umq_bwr_pfch_ctrl;
04414 #define VXGE_HW_UMQ_BWR_PFCH_CTRL_POLL_EN       vxge_mBIT(3)
04415 /*0x011d0*/     u64     umq_mr2vp_bwr_eol;
04416 #define VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vxge_vBIT(val, 32, 32)
04417 /*0x011d8*/     u64     umq_bwr_init_add;
04418 #define VXGE_HW_UMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64)
04419 /*0x011e0*/     u64     umq_bwr_init_byte;
04420 #define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
04421 /*0x011e8*/     u64     gendma_int;
04422 /*0x011f0*/     u64     umqdmq_ir_init_notify;
04423 #define VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE     vxge_mBIT(3)
04424 /*0x011f8*/     u64     dmq_init_notify;
04425 #define VXGE_HW_DMQ_INIT_NOTIFY_PULSE   vxge_mBIT(3)
04426 /*0x01200*/     u64     umq_init_notify;
04427 #define VXGE_HW_UMQ_INIT_NOTIFY_PULSE   vxge_mBIT(3)
04428         u8      unused01380[0x01380-0x01208];
04429 
04430 /*0x01380*/     u64     tpa_cfg;
04431 #define VXGE_HW_TPA_CFG_IGNORE_FRAME_ERR        vxge_mBIT(3)
04432 #define VXGE_HW_TPA_CFG_IPV6_STOP_SEARCHING     vxge_mBIT(7)
04433 #define VXGE_HW_TPA_CFG_L4_PSHDR_PRESENT        vxge_mBIT(11)
04434 #define VXGE_HW_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS        vxge_mBIT(15)
04435         u8      unused01400[0x01400-0x01388];
04436 
04437 /*0x01400*/     u64     tx_vp_reset_discarded_frms;
04438 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val) \
04439                                                         vxge_vBIT(val, 48, 16)
04440         u8      unused01480[0x01480-0x01408];
04441 
04442 /*0x01480*/     u64     fau_rpa_vcfg;
04443 #define VXGE_HW_FAU_RPA_VCFG_L4_COMP_CSUM       vxge_mBIT(7)
04444 #define VXGE_HW_FAU_RPA_VCFG_L3_INCL_CF vxge_mBIT(11)
04445 #define VXGE_HW_FAU_RPA_VCFG_L3_COMP_CSUM       vxge_mBIT(15)
04446         u8      unused014d0[0x014d0-0x01488];
04447 
04448 /*0x014d0*/     u64     dbg_stats_rx_mpa;
04449 #define VXGE_HW_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vxge_vBIT(val, 0, 16)
04450 #define VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vxge_vBIT(val, 16, 16)
04451 #define VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vxge_vBIT(val, 32, 16)
04452 /*0x014d8*/     u64     dbg_stats_rx_fau;
04453 #define VXGE_HW_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vxge_vBIT(val, 0, 16)
04454 #define VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val) \
04455                                                         vxge_vBIT(val, 16, 16)
04456 #define VXGE_HW_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) \
04457                                                         vxge_vBIT(val, 32, 32)
04458         u8      unused014f0[0x014f0-0x014e0];
04459 
04460 /*0x014f0*/     u64     fbmc_vp_rdy;
04461 #define VXGE_HW_FBMC_VP_RDY_QUEUE_SPAV_FM       vxge_mBIT(0)
04462         u8      unused01e00[0x01e00-0x014f8];
04463 
04464 /*0x01e00*/     u64     vpath_pcipif_int_status;
04465 #define \
04466 VXGE_HW_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_SRPCIM_MSG_TO_VPATH_INT \
04467                                                                 vxge_mBIT(3)
04468 #define VXGE_HW_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_VPATH_SPARE_R1_INT \
04469                                                                 vxge_mBIT(7)
04470 /*0x01e08*/     u64     vpath_pcipif_int_mask;
04471         u8      unused01e20[0x01e20-0x01e10];
04472 
04473 /*0x01e20*/     u64     srpcim_msg_to_vpath_reg;
04474 #define VXGE_HW_SRPCIM_MSG_TO_VPATH_REG_SWIF_SRPCIM_TO_VPATH_RMSG_INT \
04475                                                                 vxge_mBIT(3)
04476 /*0x01e28*/     u64     srpcim_msg_to_vpath_mask;
04477 /*0x01e30*/     u64     srpcim_msg_to_vpath_alarm;
04478         u8      unused01ea0[0x01ea0-0x01e38];
04479 
04480 /*0x01ea0*/     u64     vpath_to_srpcim_wmsg;
04481 #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_VPATH_TO_SRPCIM_WMSG(val) \
04482                                                         vxge_vBIT(val, 0, 64)
04483 /*0x01ea8*/     u64     vpath_to_srpcim_wmsg_trig;
04484 #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_TRIG_VPATH_TO_SRPCIM_WMSG_TRIG \
04485                                                         vxge_mBIT(0)
04486         u8      unused02000[0x02000-0x01eb0];
04487 
04488 /*0x02000*/     u64     vpath_general_int_status;
04489 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT        vxge_mBIT(3)
04490 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT        vxge_mBIT(7)
04491 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT      vxge_mBIT(15)
04492 #define VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT       vxge_mBIT(19)
04493 /*0x02008*/     u64     vpath_general_int_mask;
04494 #define VXGE_HW_VPATH_GENERAL_INT_MASK_PIC_INT  vxge_mBIT(3)
04495 #define VXGE_HW_VPATH_GENERAL_INT_MASK_PCI_INT  vxge_mBIT(7)
04496 #define VXGE_HW_VPATH_GENERAL_INT_MASK_WRDMA_INT        vxge_mBIT(15)
04497 #define VXGE_HW_VPATH_GENERAL_INT_MASK_XMAC_INT vxge_mBIT(19)
04498 /*0x02010*/     u64     vpath_ppif_int_status;
04499 #define VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT \
04500                                                         vxge_mBIT(3)
04501 #define VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT \
04502                                                         vxge_mBIT(7)
04503 #define VXGE_HW_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_PCI_CONFIG_INT \
04504                                                         vxge_mBIT(11)
04505 #define \
04506 VXGE_HW_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_MRPCIM_TO_VPATH_ALARM_INT \
04507                                                         vxge_mBIT(15)
04508 #define \
04509 VXGE_HW_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_SRPCIM_TO_VPATH_ALARM_INT \
04510                                                         vxge_mBIT(19)
04511 /*0x02018*/     u64     vpath_ppif_int_mask;
04512 /*0x02020*/     u64     kdfcctl_errors_reg;
04513 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR  vxge_mBIT(3)
04514 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR  vxge_mBIT(7)
04515 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR  vxge_mBIT(11)
04516 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON vxge_mBIT(15)
04517 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON vxge_mBIT(19)
04518 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON vxge_mBIT(23)
04519 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR        vxge_mBIT(31)
04520 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR        vxge_mBIT(35)
04521 #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR        vxge_mBIT(39)
04522 /*0x02028*/     u64     kdfcctl_errors_mask;
04523 /*0x02030*/     u64     kdfcctl_errors_alarm;
04524         u8      unused02040[0x02040-0x02038];
04525 
04526 /*0x02040*/     u64     general_errors_reg;
04527 #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW vxge_mBIT(3)
04528 #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW vxge_mBIT(7)
04529 #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW vxge_mBIT(11)
04530 #define VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR vxge_mBIT(15)
04531 #define VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ      vxge_mBIT(19)
04532 #define VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS   vxge_mBIT(27)
04533 #define VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET vxge_mBIT(31)
04534 /*0x02048*/     u64     general_errors_mask;
04535 /*0x02050*/     u64     general_errors_alarm;
04536 /*0x02058*/     u64     pci_config_errors_reg;
04537 #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_STATUS_ERR      vxge_mBIT(3)
04538 #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_UNCOR_ERR       vxge_mBIT(7)
04539 #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_COR_ERR vxge_mBIT(11)
04540 /*0x02060*/     u64     pci_config_errors_mask;
04541 /*0x02068*/     u64     pci_config_errors_alarm;
04542 /*0x02070*/     u64     mrpcim_to_vpath_alarm_reg;
04543 #define VXGE_HW_MRPCIM_TO_VPATH_ALARM_REG_PPIF_MRPCIM_TO_VPATH_ALARM \
04544                                                                 vxge_mBIT(3)
04545 /*0x02078*/     u64     mrpcim_to_vpath_alarm_mask;
04546 /*0x02080*/     u64     mrpcim_to_vpath_alarm_alarm;
04547 /*0x02088*/     u64     srpcim_to_vpath_alarm_reg;
04548 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_PPIF_SRPCIM_TO_VPATH_ALARM(val) \
04549                                                         vxge_vBIT(val, 0, 17)
04550 /*0x02090*/     u64     srpcim_to_vpath_alarm_mask;
04551 /*0x02098*/     u64     srpcim_to_vpath_alarm_alarm;
04552         u8      unused02108[0x02108-0x020a0];
04553 
04554 /*0x02108*/     u64     kdfcctl_status;
04555 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vxge_vBIT(val, 0, 8)
04556 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vxge_vBIT(val, 8, 8)
04557 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vxge_vBIT(val, 16, 8)
04558 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vxge_vBIT(val, 24, 8)
04559 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vxge_vBIT(val, 32, 8)
04560 #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vxge_vBIT(val, 40, 8)
04561 /*0x02110*/     u64     rsthdlr_status;
04562 #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET    vxge_mBIT(3)
04563 #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vxge_vBIT(val, 6, 2)
04564 /*0x02118*/     u64     fifo0_status;
04565 #define VXGE_HW_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vxge_vBIT(val, 0, 12)
04566 /*0x02120*/     u64     fifo1_status;
04567 #define VXGE_HW_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vxge_vBIT(val, 0, 12)
04568 /*0x02128*/     u64     fifo2_status;
04569 #define VXGE_HW_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vxge_vBIT(val, 0, 12)
04570         u8      unused02158[0x02158-0x02130];
04571 
04572 /*0x02158*/     u64     tgt_illegal_access;
04573 #define VXGE_HW_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7)
04574         u8      unused02200[0x02200-0x02160];
04575 
04576 /*0x02200*/     u64     vpath_general_cfg1;
04577 #define VXGE_HW_VPATH_GENERAL_CFG1_TC_VALUE(val) vxge_vBIT(val, 1, 3)
04578 #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN     vxge_mBIT(7)
04579 #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_FLIPEN  vxge_mBIT(11)
04580 #define VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN      vxge_mBIT(15)
04581 #define VXGE_HW_VPATH_GENERAL_CFG1_CTL_FLIPEN   vxge_mBIT(23)
04582 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN     vxge_mBIT(51)
04583 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN     vxge_mBIT(55)
04584 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN     vxge_mBIT(59)
04585 #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN     vxge_mBIT(63)
04586 /*0x02208*/     u64     vpath_general_cfg2;
04587 #define VXGE_HW_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vxge_vBIT(val, 1, 3)
04588 /*0x02210*/     u64     vpath_general_cfg3;
04589 #define VXGE_HW_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA    vxge_mBIT(3)
04590         u8      unused02220[0x02220-0x02218];
04591 
04592 /*0x02220*/     u64     kdfcctl_cfg0;
04593 #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0  vxge_mBIT(1)
04594 #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1  vxge_mBIT(2)
04595 #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2  vxge_mBIT(3)
04596 #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0   vxge_mBIT(5)
04597 #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1   vxge_mBIT(6)
04598 #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2   vxge_mBIT(7)
04599 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0      vxge_mBIT(9)
04600 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1      vxge_mBIT(10)
04601 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2      vxge_mBIT(11)
04602 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0      vxge_mBIT(13)
04603 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1      vxge_mBIT(14)
04604 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2      vxge_mBIT(15)
04605 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0      vxge_mBIT(17)
04606 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1      vxge_mBIT(18)
04607 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2      vxge_mBIT(19)
04608 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0      vxge_mBIT(21)
04609 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1      vxge_mBIT(22)
04610 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2      vxge_mBIT(23)
04611 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0      vxge_mBIT(25)
04612 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1      vxge_mBIT(26)
04613 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2      vxge_mBIT(27)
04614 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0      vxge_mBIT(29)
04615 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1      vxge_mBIT(30)
04616 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2      vxge_mBIT(31)
04617 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0      vxge_mBIT(33)
04618 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1      vxge_mBIT(34)
04619 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2      vxge_mBIT(35)
04620 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0      vxge_mBIT(37)
04621 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1      vxge_mBIT(38)
04622 #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2      vxge_mBIT(39)
04623 
04624         u8      unused02268[0x02268-0x02228];
04625 
04626 /*0x02268*/     u64     stats_cfg;
04627 #define VXGE_HW_STATS_CFG_START_HOST_ADDR(val) vxge_vBIT(val, 0, 57)
04628 /*0x02270*/     u64     interrupt_cfg0;
04629 #define VXGE_HW_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vxge_vBIT(val, 1, 7)
04630 #define VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vxge_vBIT(val, 9, 7)
04631 #define VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vxge_vBIT(val, 17, 7)
04632 #define VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vxge_vBIT(val, 25, 7)
04633 #define VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vxge_vBIT(val, 33, 7)
04634         u8      unused02280[0x02280-0x02278];
04635 
04636 /*0x02280*/     u64     interrupt_cfg2;
04637 #define VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7)
04638 /*0x02288*/     u64     one_shot_vect0_en;
04639 #define VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN     vxge_mBIT(3)
04640 /*0x02290*/     u64     one_shot_vect1_en;
04641 #define VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN     vxge_mBIT(3)
04642 /*0x02298*/     u64     one_shot_vect2_en;
04643 #define VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN     vxge_mBIT(3)
04644 /*0x022a0*/     u64     one_shot_vect3_en;
04645 #define VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN     vxge_mBIT(3)
04646         u8      unused022b0[0x022b0-0x022a8];
04647 
04648 /*0x022b0*/     u64     pci_config_access_cfg1;
04649 #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vxge_vBIT(val, 0, 12)
04650 #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0        vxge_mBIT(15)
04651 /*0x022b8*/     u64     pci_config_access_cfg2;
04652 #define VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ      vxge_mBIT(0)
04653 /*0x022c0*/     u64     pci_config_access_status;
04654 #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR     vxge_mBIT(0)
04655 #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA(val) vxge_vBIT(val, 32, 32)
04656         u8      unused02300[0x02300-0x022c8];
04657 
04658 /*0x02300*/     u64     vpath_debug_stats0;
04659 #define VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vxge_vBIT(val, 0, 32)
04660 /*0x02308*/     u64     vpath_debug_stats1;
04661 #define VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vxge_vBIT(val, 0, 32)
04662 /*0x02310*/     u64     vpath_debug_stats2;
04663 #define VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vxge_vBIT(val, 0, 32)
04664 /*0x02318*/     u64     vpath_debug_stats3;
04665 #define VXGE_HW_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) \
04666                                                         vxge_vBIT(val, 0, 64)
04667 /*0x02320*/     u64     vpath_debug_stats4;
04668 #define VXGE_HW_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) \
04669                                                         vxge_vBIT(val, 0, 64)
04670 /*0x02328*/     u64     vpath_debug_stats5;
04671 #define VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32)
04672 /*0x02330*/     u64     vpath_debug_stats6;
04673 #define VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32)
04674 /*0x02338*/     u64     vpath_genstats_count01;
04675 #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val) \
04676                                                         vxge_vBIT(val, 0, 32)
04677 #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val) \
04678                                                         vxge_vBIT(val, 32, 32)
04679 /*0x02340*/     u64     vpath_genstats_count23;
04680 #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val) \
04681                                                         vxge_vBIT(val, 0, 32)
04682 #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val) \
04683                                                         vxge_vBIT(val, 32, 32)
04684 /*0x02348*/     u64     vpath_genstats_count4;
04685 #define VXGE_HW_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val) \
04686                                                         vxge_vBIT(val, 32, 32)
04687 /*0x02350*/     u64     vpath_genstats_count5;
04688 #define VXGE_HW_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val) \
04689                                                         vxge_vBIT(val, 32, 32)
04690         u8      unused02648[0x02648-0x02358];
04691 } __attribute((packed));
04692 
04693 #define VXGE_HW_EEPROM_SIZE     (0x01 << 11)
04694 
04695 /* Capability lists */
04696 #define  VXGE_HW_PCI_EXP_LNKCAP_LNK_SPEED    0xf  /* Supported Link speeds */
04697 #define  VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH    0x3f0 /* Supported Link speeds. */
04698 #define  VXGE_HW_PCI_EXP_LNKCAP_LW_RES       0x0  /* Reserved. */
04699 
04700 #endif