iPXE
vxge_traffic.h
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00001 /*
00002  * vxge-traffic.h: iPXE driver for Neterion Inc's X3100 Series 10GbE
00003  *              PCIe I/O Virtualized Server Adapter.
00004  *
00005  * Copyright(c) 2002-2010 Neterion Inc.
00006  *
00007  * This software may be used and distributed according to the terms of
00008  * the GNU General Public License (GPL), incorporated herein by
00009  * reference.  Drivers based on or derived from this code fall under
00010  * the GPL and must retain the authorship, copyright and license
00011  * notice.
00012  *
00013  */
00014 
00015 FILE_LICENCE(GPL2_ONLY);
00016 
00017 #ifndef VXGE_TRAFFIC_H
00018 #define VXGE_TRAFFIC_H
00019 
00020 #include <stdint.h>
00021 #include <ipxe/if_ether.h>
00022 #include <ipxe/iobuf.h>
00023 
00024 #include "vxge_reg.h"
00025 #include "vxge_version.h"
00026 
00027 #define VXGE_HW_DTR_MAX_T_CODE          16
00028 #define VXGE_HW_ALL_FOXES               0xFFFFFFFFFFFFFFFFULL
00029 #define VXGE_HW_INTR_MASK_ALL           0xFFFFFFFFFFFFFFFFULL
00030 #define VXGE_HW_MAX_VIRTUAL_PATHS       17
00031 
00032 #define VXGE_HW_MAX_VIRTUAL_FUNCTIONS   8
00033 
00034 #define VXGE_HW_MAC_MAX_MAC_PORT_ID     3
00035 
00036 #define VXGE_HW_DEFAULT_32              0xffffffff
00037 /* frames sizes */
00038 #define VXGE_HW_HEADER_802_2_SIZE       3
00039 #define VXGE_HW_HEADER_SNAP_SIZE        5
00040 #define VXGE_HW_HEADER_VLAN_SIZE        4
00041 #define VXGE_HW_MAC_HEADER_MAX_SIZE \
00042                         (ETH_HLEN + \
00043                         VXGE_HW_HEADER_802_2_SIZE + \
00044                         VXGE_HW_HEADER_VLAN_SIZE + \
00045                         VXGE_HW_HEADER_SNAP_SIZE)
00046 
00047 /* 32bit alignments */
00048 
00049 /* A receive data corruption can occur resulting in either a single-bit or
00050 double-bit ECC error being flagged in the ASIC if the starting offset of a
00051 buffer in single buffer mode is 0x2 to 0xa. The single bit ECC error will not
00052 lock up the card but can hide the data corruption while the double-bit ECC
00053 error will lock up the card. Limiting the starting offset of the buffers to
00054 0x0, 0x1 or to a value greater than 0xF will workaround this issue.
00055 VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN of 2 causes the starting offset of
00056 buffer to be 0x2, 0x12 and so on, to have the start of the ip header dword
00057 aligned. The start of buffer of 0x2 will cause this problem to occur. To
00058 avoid this problem in all cases, add 0x10 to 0x2, to ensure that the start of
00059 buffer is outside of the problem causing offsets.
00060 */
00061 #define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN          0x12
00062 #define VXGE_HW_HEADER_802_2_SNAP_ALIGN                 2
00063 #define VXGE_HW_HEADER_802_2_ALIGN                      3
00064 #define VXGE_HW_HEADER_SNAP_ALIGN                       1
00065 
00066 #define VXGE_HW_L3_CKSUM_OK                             0xFFFF
00067 #define VXGE_HW_L4_CKSUM_OK                             0xFFFF
00068 
00069 /* Forward declarations */
00070 struct __vxge_hw_device;
00071 struct __vxge_hw_virtualpath;
00072 struct __vxge_hw_fifo;
00073 struct __vxge_hw_ring;
00074 struct vxge_hw_ring_rxd_1;
00075 struct vxge_hw_fifo_txd;
00076 
00077 #ifndef TRUE
00078 #define TRUE 1
00079 #endif
00080 
00081 #ifndef FALSE
00082 #define FALSE 0
00083 #endif
00084 
00085 /*VXGE_HW_STATUS_H*/
00086 #define VXGE_HW_EVENT_BASE                      0
00087 #define VXGE_LL_EVENT_BASE                      100
00088 
00089 /**
00090  * enum vxge_hw_event- Enumerates slow-path HW events.
00091  * @VXGE_HW_EVENT_UNKNOWN: Unknown (and invalid) event.
00092  * @VXGE_HW_EVENT_SERR: Serious vpath hardware error event.
00093  * @VXGE_HW_EVENT_ECCERR: vpath ECC error event.
00094  * @VXGE_HW_EVENT_VPATH_ERR: Error local to the respective vpath
00095  * @VXGE_HW_EVENT_FIFO_ERR: FIFO Doorbell fifo error.
00096  * @VXGE_HW_EVENT_SRPCIM_SERR: srpcim hardware error event.
00097  * @VXGE_HW_EVENT_MRPCIM_SERR: mrpcim hardware error event.
00098  * @VXGE_HW_EVENT_MRPCIM_ECCERR: mrpcim ecc error event.
00099  * @VXGE_HW_EVENT_RESET_START: Privileged entity is starting device reset
00100  * @VXGE_HW_EVENT_RESET_COMPLETE: Device reset has been completed
00101  * @VXGE_HW_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish
00102  * slot-freeze from the rest critical events (e.g. ECC) when it is
00103  * impossible to PIO read "through" the bus, i.e. when getting all-foxes.
00104  *
00105  * enum vxge_hw_event enumerates slow-path HW eventis.
00106  *
00107  * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{},
00108  * vxge_uld_link_down_f{}.
00109  */
00110 enum vxge_hw_event {
00111         VXGE_HW_EVENT_UNKNOWN           = 0,
00112         /* HW events */
00113         VXGE_HW_EVENT_RESET_START       = VXGE_HW_EVENT_BASE + 1,
00114         VXGE_HW_EVENT_RESET_COMPLETE    = VXGE_HW_EVENT_BASE + 2,
00115         VXGE_HW_EVENT_LINK_DOWN         = VXGE_HW_EVENT_BASE + 3,
00116         VXGE_HW_EVENT_LINK_UP           = VXGE_HW_EVENT_BASE + 4,
00117         VXGE_HW_EVENT_ALARM_CLEARED     = VXGE_HW_EVENT_BASE + 5,
00118         VXGE_HW_EVENT_ECCERR            = VXGE_HW_EVENT_BASE + 6,
00119         VXGE_HW_EVENT_MRPCIM_ECCERR     = VXGE_HW_EVENT_BASE + 7,
00120         VXGE_HW_EVENT_FIFO_ERR          = VXGE_HW_EVENT_BASE + 8,
00121         VXGE_HW_EVENT_VPATH_ERR         = VXGE_HW_EVENT_BASE + 9,
00122         VXGE_HW_EVENT_CRITICAL_ERR      = VXGE_HW_EVENT_BASE + 10,
00123         VXGE_HW_EVENT_SERR              = VXGE_HW_EVENT_BASE + 11,
00124         VXGE_HW_EVENT_SRPCIM_SERR       = VXGE_HW_EVENT_BASE + 12,
00125         VXGE_HW_EVENT_MRPCIM_SERR       = VXGE_HW_EVENT_BASE + 13,
00126         VXGE_HW_EVENT_SLOT_FREEZE       = VXGE_HW_EVENT_BASE + 14,
00127 };
00128 
00129 #define VXGE_HW_MAX_INTR_PER_VP        4
00130 #define VXGE_HW_VPATH_INTR_TX          0
00131 #define VXGE_HW_VPATH_INTR_RX          1
00132 #define VXGE_HW_VPATH_INTR_EINTA       2
00133 #define VXGE_HW_VPATH_INTR_BMAP        3
00134 
00135 #define VXGE_HW_BLOCK_SIZE             4096
00136 
00137 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL         17
00138 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL         18
00139 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL  19
00140 #define VXGE_HW_TIM_UTIL_SEL_PER_VPATH                  63
00141 
00142 /**
00143  * enum vxge_hw_ring_tcode - Transfer codes returned by adapter
00144  * @VXGE_HW_RING_T_CODE_OK: Transfer ok.
00145  * @VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation
00146  *              configuration mismatch.
00147  * @VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation
00148  *              configuration mismatch.
00149  * @VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum
00150  *              presentation configuration mismatch.
00151  * @VXGE_HW_RING_T_CODE_L3_PKT_ERR: Layer 3 error unparseable packet,
00152  *              such as unknown IPv6 header.
00153  * @VXGE_HW_RING_T_CODE_L2_FRM_ERR: Layer 2 error frame integrity
00154  *              error, such as FCS or ECC).
00155  * @VXGE_HW_RING_T_CODE_BUF_SIZE_ERR: Buffer size error the RxD buffer(
00156  *              s) were not appropriately sized and data loss occurred.
00157  * @VXGE_HW_RING_T_CODE_INT_ECC_ERR: Internal ECC error RxD corrupted.
00158  * @VXGE_HW_RING_T_CODE_BENIGN_OVFLOW: Benign overflow the contents of
00159  *              Segment1 exceeded the capacity of Buffer1 and the remainder
00160  *              was placed in Buffer2. Segment2 now starts in Buffer3.
00161  *              No data loss or errors occurred.
00162  * @VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0 one of the RxDs
00163  *              assigned buffers has a size of 0 bytes.
00164  * @VXGE_HW_RING_T_CODE_FRM_DROP: Frame dropped either due to
00165  *              VPath Reset or because of a VPIN mismatch.
00166  * @VXGE_HW_RING_T_CODE_UNUSED: Unused
00167  * @VXGE_HW_RING_T_CODE_MULTI_ERR: Multiple errors more than one
00168  *              transfer code condition occurred.
00169  *
00170  * Transfer codes returned by adapter.
00171  */
00172 enum vxge_hw_ring_tcode {
00173         VXGE_HW_RING_T_CODE_OK                          = 0x0,
00174         VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH           = 0x1,
00175         VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH           = 0x2,
00176         VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH        = 0x3,
00177         VXGE_HW_RING_T_CODE_L3_PKT_ERR                  = 0x5,
00178         VXGE_HW_RING_T_CODE_L2_FRM_ERR                  = 0x6,
00179         VXGE_HW_RING_T_CODE_BUF_SIZE_ERR                = 0x7,
00180         VXGE_HW_RING_T_CODE_INT_ECC_ERR                 = 0x8,
00181         VXGE_HW_RING_T_CODE_BENIGN_OVFLOW               = 0x9,
00182         VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF               = 0xA,
00183         VXGE_HW_RING_T_CODE_FRM_DROP                    = 0xC,
00184         VXGE_HW_RING_T_CODE_UNUSED                      = 0xE,
00185         VXGE_HW_RING_T_CODE_MULTI_ERR                   = 0xF
00186 };
00187 
00188 
00189 /**
00190  * enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD
00191  * @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL
00192  * @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL
00193  * @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL
00194  * @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL.
00195  *
00196  * These gather codes are used to indicate the position of a TxD in a TxD list
00197  */
00198 enum vxge_hw_fifo_gather_code {
00199         VXGE_HW_FIFO_GATHER_CODE_FIRST          = 0x2,
00200         VXGE_HW_FIFO_GATHER_CODE_MIDDLE         = 0x0,
00201         VXGE_HW_FIFO_GATHER_CODE_LAST           = 0x1,
00202         VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST     = 0x3
00203 };
00204 
00205 /**
00206  * enum enum vxge_hw_fifo_tcode - tcodes used in fifo
00207  * @VXGE_HW_FIFO_T_CODE_OK: Transfer OK
00208  * @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or
00209  *             frame data) returned with corrupt data.
00210  * @VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned
00211  *             with no data.
00212  * @VXGE_HW_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a
00213  *             frame or LSO MSS that was too long (>9800B).
00214  * @VXGE_HW_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send
00215         *              Offload operation, due to improper header template,
00216         *              unsupported protocol, etc.
00217  * @VXGE_HW_FIFO_T_CODE_UNUSED: Unused
00218  * @VXGE_HW_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple
00219  *             data buffer transfer errors are encountered (see below).
00220  *             Otherwise it is set to 0.
00221  *
00222  * These tcodes are returned in various API for TxD status
00223  */
00224 enum vxge_hw_fifo_tcode {
00225         VXGE_HW_FIFO_T_CODE_OK                  = 0x0,
00226         VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT    = 0x1,
00227         VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL       = 0x2,
00228         VXGE_HW_FIFO_T_CODE_INVALID_MSS         = 0x3,
00229         VXGE_HW_FIFO_T_CODE_LSO_ERROR           = 0x4,
00230         VXGE_HW_FIFO_T_CODE_UNUSED              = 0x7,
00231         VXGE_HW_FIFO_T_CODE_MULTI_ERROR         = 0x8
00232 };
00233 
00234 enum vxge_hw_status
00235 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring);
00236 
00237 void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring_handle,
00238                 struct vxge_hw_ring_rxd_1 *rxdp);
00239 
00240 void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo,
00241                 struct vxge_hw_fifo_txd *txdp,
00242                 struct io_buffer *iob);
00243 
00244 void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo,
00245                 struct vxge_hw_fifo_txd *txdp);
00246 
00247 enum vxge_hw_status __vxge_hw_ring_create(
00248         struct __vxge_hw_virtualpath *vpath,
00249         struct __vxge_hw_ring *ring);
00250 
00251 enum vxge_hw_status __vxge_hw_ring_delete(
00252         struct __vxge_hw_ring *ringh);
00253 
00254 enum vxge_hw_status __vxge_hw_fifo_create(
00255         struct __vxge_hw_virtualpath *vpath,
00256         struct __vxge_hw_fifo *fifo);
00257 
00258 enum vxge_hw_status
00259 __vxge_hw_fifo_delete(struct __vxge_hw_fifo *fifo);
00260 
00261 enum vxge_hw_status __vxge_hw_vpath_reset(
00262         struct __vxge_hw_device *devh, u32 vp_id);
00263 
00264 enum vxge_hw_status
00265 __vxge_hw_vpath_enable(struct __vxge_hw_device *devh, u32 vp_id);
00266 
00267 void
00268 __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev);
00269 
00270 enum vxge_hw_status
00271 __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *devh, u32 vp_id);
00272 
00273 enum vxge_hw_status
00274 __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *devh);
00275 
00276 enum vxge_hw_status
00277 __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *devh, u32 vp_id);
00278 
00279 enum vxge_hw_status
00280 __vxge_hw_vpath_initialize(struct __vxge_hw_device *devh, u32 vp_id);
00281 
00282 enum vxge_hw_status __vxge_hw_vp_initialize(
00283         struct __vxge_hw_device *hldev, u32 vp_id,
00284         struct __vxge_hw_virtualpath *vpath);
00285 
00286 void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev,
00287                         struct __vxge_hw_virtualpath *vpath);
00288 
00289 enum vxge_hw_status
00290 vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev);
00291 
00292 void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev);
00293 
00294 void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev);
00295 
00296 void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev);
00297 
00298 void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev);
00299 
00300 void vxge_hw_vpath_doorbell_rx(struct __vxge_hw_ring *ringh);
00301 
00302 enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ringh);
00303 
00304 enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo);
00305 
00306 struct vxge_hw_fifo_txd *
00307 vxge_hw_fifo_free_txdl_get(struct __vxge_hw_fifo *fifo);
00308 
00309 #endif